1 /* CPU family header for lm32bf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996-2005 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 1
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 1
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* General purpose registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* Control and status registers */
49 #define GET_H_CSR(a1) CPU (h_csr)[a1]
50 #define SET_H_CSR(a1, x) (CPU (h_csr)[a1] = (x))
52 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
55 /* Cover fns for register access. */
56 USI
lm32bf_h_pc_get (SIM_CPU
*);
57 void lm32bf_h_pc_set (SIM_CPU
*, USI
);
58 SI
lm32bf_h_gr_get (SIM_CPU
*, UINT
);
59 void lm32bf_h_gr_set (SIM_CPU
*, UINT
, SI
);
60 SI
lm32bf_h_csr_get (SIM_CPU
*, UINT
);
61 void lm32bf_h_csr_set (SIM_CPU
*, UINT
, SI
);
63 /* These must be hand-written. */
64 extern CPUREG_FETCH_FN lm32bf_fetch_register
;
65 extern CPUREG_STORE_FN lm32bf_store_register
;
71 /* Instruction argument buffer. */
74 struct { /* no operands */
110 /* Writeback handler. */
112 /* Pointer to argbuf entry for insn whose results need writing back. */
113 const struct argbuf
*abuf
;
115 /* x-before handler */
117 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
120 /* x-after handler */
124 /* This entry is used to terminate each pbb. */
126 /* Number of insns in pbb. */
128 /* Next pbb to execute. */
130 SCACHE
*branch_target
;
135 /* The ARGBUF struct. */
137 /* These are the baseclass definitions. */
142 /* ??? Temporary hack for skip insns. */
145 /* cpu specific data follows */
148 union sem_fields fields
;
153 ??? SCACHE used to contain more than just argbuf. We could delete the
154 type entirely and always just use ARGBUF, but for future concerns and as
155 a level of abstraction it is left in. */
158 struct argbuf argbuf
;
161 /* Macros to simplify extraction, reading and semantic code.
162 These define and assign the local vars that contain the insn's fields. */
164 #define EXTRACT_IFMT_EMPTY_VARS \
166 #define EXTRACT_IFMT_EMPTY_CODE \
169 #define EXTRACT_IFMT_ADD_VARS \
176 #define EXTRACT_IFMT_ADD_CODE \
178 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
179 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
180 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
181 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
182 f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
184 #define EXTRACT_IFMT_ADDI_VARS \
190 #define EXTRACT_IFMT_ADDI_CODE \
192 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
193 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
194 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
195 f_imm = EXTRACT_LSB0_INT (insn, 32, 15, 16); \
197 #define EXTRACT_IFMT_ANDI_VARS \
203 #define EXTRACT_IFMT_ANDI_CODE \
205 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
206 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
207 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
208 f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
210 #define EXTRACT_IFMT_ANDHII_VARS \
216 #define EXTRACT_IFMT_ANDHII_CODE \
218 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
219 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
220 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
221 f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
223 #define EXTRACT_IFMT_B_VARS \
230 #define EXTRACT_IFMT_B_CODE \
232 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
233 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
234 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
235 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
236 f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
238 #define EXTRACT_IFMT_BI_VARS \
242 #define EXTRACT_IFMT_BI_CODE \
244 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
245 f_call = ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 25, 26)) << (6))) >> (4)))); \
247 #define EXTRACT_IFMT_BE_VARS \
253 #define EXTRACT_IFMT_BE_CODE \
255 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
256 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
257 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
258 f_branch = ((pc) + (((int) (((EXTRACT_LSB0_INT (insn, 32, 15, 16)) << (16))) >> (14)))); \
260 #define EXTRACT_IFMT_ORI_VARS \
266 #define EXTRACT_IFMT_ORI_CODE \
268 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
269 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
270 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
271 f_uimm = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
273 #define EXTRACT_IFMT_RCSR_VARS \
280 #define EXTRACT_IFMT_RCSR_CODE \
282 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
283 f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
284 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
285 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
286 f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
288 #define EXTRACT_IFMT_SEXTB_VARS \
295 #define EXTRACT_IFMT_SEXTB_CODE \
297 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
298 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
299 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
300 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
301 f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
303 #define EXTRACT_IFMT_USER_VARS \
310 #define EXTRACT_IFMT_USER_CODE \
312 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
313 f_r0 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
314 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
315 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
316 f_user = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
318 #define EXTRACT_IFMT_WCSR_VARS \
325 #define EXTRACT_IFMT_WCSR_CODE \
327 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
328 f_csr = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
329 f_r1 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
330 f_r2 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
331 f_resv0 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
333 #define EXTRACT_IFMT_BREAK_VARS \
337 #define EXTRACT_IFMT_BREAK_CODE \
339 f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
340 f_exception = EXTRACT_LSB0_UINT (insn, 32, 25, 26); \
342 /* Collection of various things for the trace handler to use. */
344 typedef struct trace_record
{
349 #endif /* CPU_LM32BF_H */