1 /* Lattice Mico32 exception and system call support.
2 Contributed by Jon Beniston <jon@beniston.com>
4 Copyright (C) 2009, 2010 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #define WANT_CPU lm32bf
22 #define WANT_CPU_LM32BF
26 #include "targ-vals.h"
28 /* Read memory function for system call interface. */
31 syscall_read_mem (host_callback
* cb
, struct cb_syscall
*sc
,
32 unsigned long taddr
, char *buf
, int bytes
)
34 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
35 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
37 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
40 /* Write memory function for system call interface. */
43 syscall_write_mem (host_callback
* cb
, struct cb_syscall
*sc
,
44 unsigned long taddr
, const char *buf
, int bytes
)
46 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
47 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
49 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
52 /* Handle invalid instructions. */
55 sim_engine_invalid_insn (SIM_CPU
* current_cpu
, IADDR cia
, SEM_PC pc
)
57 SIM_DESC sd
= CPU_STATE (current_cpu
);
59 sim_engine_halt (sd
, current_cpu
, NULL
, cia
, sim_stopped
, SIM_SIGILL
);
64 /* Handle divide instructions. */
67 lm32bf_divu_insn (SIM_CPU
* current_cpu
, IADDR pc
, USI r0
, USI r1
, USI r2
)
69 SIM_DESC sd
= CPU_STATE (current_cpu
);
70 host_callback
*cb
= STATE_CALLBACK (sd
);
72 /* Check for divide by zero */
73 if (GET_H_GR (r1
) == 0)
75 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
76 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGFPE
);
79 /* Save PC in exception address register. */
81 /* Save and clear interrupt enable. */
82 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
83 /* Branch to divide by zero exception handler. */
84 return GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DIVIDE_BY_ZERO
* 32;
89 SET_H_GR (r2
, (USI
) GET_H_GR (r0
) / (USI
) GET_H_GR (r1
));
95 lm32bf_modu_insn (SIM_CPU
* current_cpu
, IADDR pc
, USI r0
, USI r1
, USI r2
)
97 SIM_DESC sd
= CPU_STATE (current_cpu
);
98 host_callback
*cb
= STATE_CALLBACK (sd
);
100 /* Check for divide by zero. */
101 if (GET_H_GR (r1
) == 0)
103 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
104 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGFPE
);
107 /* Save PC in exception address register. */
109 /* Save and clear interrupt enable. */
110 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
111 /* Branch to divide by zero exception handler. */
112 return GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DIVIDE_BY_ZERO
* 32;
117 SET_H_GR (r2
, (USI
) GET_H_GR (r0
) % (USI
) GET_H_GR (r1
));
122 /* Handle break instructions. */
125 lm32bf_break_insn (SIM_CPU
* current_cpu
, IADDR pc
)
127 SIM_DESC sd
= CPU_STATE (current_cpu
);
128 host_callback
*cb
= STATE_CALLBACK (sd
);
130 if (STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
132 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_stopped
, SIM_SIGTRAP
);
137 /* Save PC in breakpoint address register. */
139 /* Save and clear interrupt enable. */
140 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 2);
141 /* Branch to breakpoint exception handler. */
142 return GET_H_CSR (LM32_CSR_DEBA
) + LM32_EID_BREAKPOINT
* 32;
146 /* Handle scall instructions. */
149 lm32bf_scall_insn (SIM_CPU
* current_cpu
, IADDR pc
)
151 SIM_DESC sd
= CPU_STATE (current_cpu
);
152 host_callback
*cb
= STATE_CALLBACK (sd
);
154 if ((STATE_ENVIRONMENT (sd
) != OPERATING_ENVIRONMENT
)
155 || (GET_H_GR (8) == TARGET_SYS_exit
))
157 /* Delegate system call to host O/S. */
159 CB_SYSCALL_INIT (&s
);
161 s
.p2
= (PTR
) current_cpu
;
162 s
.read_mem
= syscall_read_mem
;
163 s
.write_mem
= syscall_write_mem
;
164 /* Extract parameters. */
165 s
.func
= GET_H_GR (8);
166 s
.arg1
= GET_H_GR (1);
167 s
.arg2
= GET_H_GR (2);
168 s
.arg3
= GET_H_GR (3);
169 /* Halt the simulator if the requested system call is _exit. */
170 if (s
.func
== TARGET_SYS_exit
)
171 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
172 /* Perform the system call. */
174 /* Store the return value in the CPU's registers. */
175 SET_H_GR (1, s
.result
);
176 SET_H_GR (2, s
.result2
);
177 SET_H_GR (3, s
.errcode
);
178 /* Skip over scall instruction. */
183 /* Save PC in exception address register. */
185 /* Save and clear interrupt enable */
186 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
187 /* Branch to system call exception handler. */
188 return GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_SYSTEM_CALL
* 32;
192 /* Handle b instructions. */
195 lm32bf_b_insn (SIM_CPU
* current_cpu
, USI r0
, USI f_r0
)
197 SIM_DESC sd
= CPU_STATE (current_cpu
);
198 host_callback
*cb
= STATE_CALLBACK (sd
);
200 /* Restore interrupt enable. */
202 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 2) >> 1);
204 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 4) >> 2);
208 /* Handle wcsr instructions. */
211 lm32bf_wcsr_insn (SIM_CPU
* current_cpu
, USI f_csr
, USI r1
)
213 SIM_DESC sd
= CPU_STATE (current_cpu
);
214 host_callback
*cb
= STATE_CALLBACK (sd
);
216 /* Writing a 1 to IP CSR clears a bit, writing 0 has no effect. */
217 if (f_csr
== LM32_CSR_IP
)
218 SET_H_CSR (f_csr
, GET_H_CSR (f_csr
) & ~r1
);
220 SET_H_CSR (f_csr
, r1
);
223 /* Handle signals. */
226 lm32_core_signal (SIM_DESC sd
,
232 transfer_type transfer
, sim_core_signals sig
)
234 const char *copy
= (transfer
== read_transfer
? "read" : "write");
235 address_word ip
= CIA_ADDR (cia
);
236 SIM_CPU
*current_cpu
= cpu
;
240 case sim_core_unmapped_signal
:
242 "core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
243 nr_bytes
, copy
, (unsigned long) addr
,
246 /* Save and clear interrupt enable. */
247 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
248 CIA_SET (cpu
, GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DATA_BUS_ERROR
* 32);
249 sim_engine_halt (sd
, cpu
, NULL
, LM32_EID_DATA_BUS_ERROR
* 32,
250 sim_stopped
, SIM_SIGSEGV
);
252 case sim_core_unaligned_signal
:
254 "core: %d byte misaligned %s to address 0x%lx at 0x%lx\n",
255 nr_bytes
, copy
, (unsigned long) addr
,
258 /* Save and clear interrupt enable. */
259 SET_H_CSR (LM32_CSR_IE
, (GET_H_CSR (LM32_CSR_IE
) & 1) << 1);
260 CIA_SET (cpu
, GET_H_CSR (LM32_CSR_EBA
) + LM32_EID_DATA_BUS_ERROR
* 32);
261 sim_engine_halt (sd
, cpu
, NULL
, LM32_EID_DATA_BUS_ERROR
* 32,
262 sim_stopped
, SIM_SIGBUS
);
265 sim_engine_abort (sd
, cpu
, cia
,
266 "sim_core_signal - internal error - bad switch");