1 /* gdb.c --- sim interface to GDB.
3 Copyright (C) 2005-2017 Free Software Foundation, Inc.
4 Contributed by Red Hat, Inc.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "gdb/callback.h"
31 #include "gdb/remote-sim.h"
32 #include "gdb/signals.h"
33 #include "gdb/sim-m32c.h"
43 /* I don't want to wrap up all the minisim's data structures in an
44 object and pass that around. That'd be a big change, and neither
45 GDB nor run needs that ability.
47 So we just have one instance, that lives in global variables, and
48 each time we open it, we re-initialize it. */
54 static struct sim_state the_minisim
= {
55 "This is the sole m32c minisim instance. See libsim.a's global variables."
61 sim_open (SIM_OPEN_KIND kind
,
62 struct host_callback_struct
*callback
,
63 struct bfd
*abfd
, char * const *argv
)
67 fprintf (stderr
, "m32c minisim: re-opened sim\n");
69 /* The 'run' interface doesn't use this function, so we don't care
70 about KIND; it's always SIM_OPEN_DEBUG. */
71 if (kind
!= SIM_OPEN_DEBUG
)
72 fprintf (stderr
, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n",
76 m32c_set_mach (bfd_get_mach (abfd
));
78 /* We can use ABFD, if non-NULL to select the appropriate
79 architecture. But we only support the r8c right now. */
81 set_callbacks (callback
);
83 /* We don't expect any command-line arguments. */
93 check_desc (SIM_DESC sd
)
95 if (sd
!= &the_minisim
)
96 fprintf (stderr
, "m32c minisim: desc != &the_minisim\n");
100 sim_close (SIM_DESC sd
, int quitting
)
104 /* Not much to do. At least free up our memory. */
111 open_objfile (const char *filename
)
113 bfd
*prog
= bfd_openr (filename
, 0);
117 fprintf (stderr
, "Can't read %s\n", filename
);
121 if (!bfd_check_format (prog
, bfd_object
))
123 fprintf (stderr
, "%s not a m32c program\n", filename
);
132 sim_load (SIM_DESC sd
, const char *prog
, struct bfd
* abfd
, int from_tty
)
137 abfd
= open_objfile (prog
);
147 sim_create_inferior (SIM_DESC sd
, struct bfd
* abfd
,
148 char * const *argv
, char * const *env
)
159 sim_read (SIM_DESC sd
, SIM_ADDR mem
, unsigned char *buf
, int length
)
166 mem_get_blk ((int) mem
, buf
, length
);
172 sim_write (SIM_DESC sd
, SIM_ADDR mem
, const unsigned char *buf
, int length
)
176 mem_put_blk ((int) mem
, buf
, length
);
182 /* Read the LENGTH bytes at BUF as an little-endian value. */
184 get_le (unsigned char *buf
, int length
)
187 while (--length
>= 0)
188 acc
= (acc
<< 8) + buf
[length
];
193 /* Store VAL as a little-endian value in the LENGTH bytes at BUF. */
195 put_le (unsigned char *buf
, int length
, DI val
)
199 for (i
= 0; i
< length
; i
++)
207 check_regno (enum m32c_sim_reg regno
)
209 return 0 <= regno
&& regno
< m32c_sim_reg_num_regs
;
213 mask_size (int addr_mask
)
224 "m32c minisim: addr_mask_size: unexpected mask 0x%x\n",
226 return sizeof (addr_mask
);
231 reg_size (enum m32c_sim_reg regno
)
235 case m32c_sim_reg_r0_bank0
:
236 case m32c_sim_reg_r1_bank0
:
237 case m32c_sim_reg_r2_bank0
:
238 case m32c_sim_reg_r3_bank0
:
239 case m32c_sim_reg_r0_bank1
:
240 case m32c_sim_reg_r1_bank1
:
241 case m32c_sim_reg_r2_bank1
:
242 case m32c_sim_reg_r3_bank1
:
243 case m32c_sim_reg_flg
:
244 case m32c_sim_reg_svf
:
247 case m32c_sim_reg_a0_bank0
:
248 case m32c_sim_reg_a1_bank0
:
249 case m32c_sim_reg_fb_bank0
:
250 case m32c_sim_reg_sb_bank0
:
251 case m32c_sim_reg_a0_bank1
:
252 case m32c_sim_reg_a1_bank1
:
253 case m32c_sim_reg_fb_bank1
:
254 case m32c_sim_reg_sb_bank1
:
255 case m32c_sim_reg_usp
:
256 case m32c_sim_reg_isp
:
257 return mask_size (addr_mask
);
259 case m32c_sim_reg_pc
:
260 case m32c_sim_reg_intb
:
261 case m32c_sim_reg_svp
:
262 case m32c_sim_reg_vct
:
263 return mask_size (membus_mask
);
265 case m32c_sim_reg_dmd0
:
266 case m32c_sim_reg_dmd1
:
269 case m32c_sim_reg_dct0
:
270 case m32c_sim_reg_dct1
:
271 case m32c_sim_reg_drc0
:
272 case m32c_sim_reg_drc1
:
275 case m32c_sim_reg_dma0
:
276 case m32c_sim_reg_dma1
:
277 case m32c_sim_reg_dsa0
:
278 case m32c_sim_reg_dsa1
:
279 case m32c_sim_reg_dra0
:
280 case m32c_sim_reg_dra1
:
284 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
291 sim_fetch_register (SIM_DESC sd
, int regno
, unsigned char *buf
, int length
)
297 if (!check_regno (regno
))
300 size
= reg_size (regno
);
307 case m32c_sim_reg_r0_bank0
:
308 val
= regs
.r
[0].r_r0
;
310 case m32c_sim_reg_r1_bank0
:
311 val
= regs
.r
[0].r_r1
;
313 case m32c_sim_reg_r2_bank0
:
314 val
= regs
.r
[0].r_r2
;
316 case m32c_sim_reg_r3_bank0
:
317 val
= regs
.r
[0].r_r3
;
319 case m32c_sim_reg_a0_bank0
:
320 val
= regs
.r
[0].r_a0
;
322 case m32c_sim_reg_a1_bank0
:
323 val
= regs
.r
[0].r_a1
;
325 case m32c_sim_reg_fb_bank0
:
326 val
= regs
.r
[0].r_fb
;
328 case m32c_sim_reg_sb_bank0
:
329 val
= regs
.r
[0].r_sb
;
331 case m32c_sim_reg_r0_bank1
:
332 val
= regs
.r
[1].r_r0
;
334 case m32c_sim_reg_r1_bank1
:
335 val
= regs
.r
[1].r_r1
;
337 case m32c_sim_reg_r2_bank1
:
338 val
= regs
.r
[1].r_r2
;
340 case m32c_sim_reg_r3_bank1
:
341 val
= regs
.r
[1].r_r3
;
343 case m32c_sim_reg_a0_bank1
:
344 val
= regs
.r
[1].r_a0
;
346 case m32c_sim_reg_a1_bank1
:
347 val
= regs
.r
[1].r_a1
;
349 case m32c_sim_reg_fb_bank1
:
350 val
= regs
.r
[1].r_fb
;
352 case m32c_sim_reg_sb_bank1
:
353 val
= regs
.r
[1].r_sb
;
356 case m32c_sim_reg_usp
:
359 case m32c_sim_reg_isp
:
362 case m32c_sim_reg_pc
:
365 case m32c_sim_reg_intb
:
366 val
= regs
.r_intbl
* 65536 + regs
.r_intbl
;
368 case m32c_sim_reg_flg
:
372 /* These registers aren't implemented by the minisim. */
373 case m32c_sim_reg_svf
:
374 case m32c_sim_reg_svp
:
375 case m32c_sim_reg_vct
:
376 case m32c_sim_reg_dmd0
:
377 case m32c_sim_reg_dmd1
:
378 case m32c_sim_reg_dct0
:
379 case m32c_sim_reg_dct1
:
380 case m32c_sim_reg_drc0
:
381 case m32c_sim_reg_drc1
:
382 case m32c_sim_reg_dma0
:
383 case m32c_sim_reg_dma1
:
384 case m32c_sim_reg_dsa0
:
385 case m32c_sim_reg_dsa1
:
386 case m32c_sim_reg_dra0
:
387 case m32c_sim_reg_dra1
:
391 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
396 put_le (buf
, length
, val
);
403 sim_store_register (SIM_DESC sd
, int regno
, unsigned char *buf
, int length
)
409 if (!check_regno (regno
))
412 size
= reg_size (regno
);
416 DI val
= get_le (buf
, length
);
420 case m32c_sim_reg_r0_bank0
:
421 regs
.r
[0].r_r0
= val
& 0xffff;
423 case m32c_sim_reg_r1_bank0
:
424 regs
.r
[0].r_r1
= val
& 0xffff;
426 case m32c_sim_reg_r2_bank0
:
427 regs
.r
[0].r_r2
= val
& 0xffff;
429 case m32c_sim_reg_r3_bank0
:
430 regs
.r
[0].r_r3
= val
& 0xffff;
432 case m32c_sim_reg_a0_bank0
:
433 regs
.r
[0].r_a0
= val
& addr_mask
;
435 case m32c_sim_reg_a1_bank0
:
436 regs
.r
[0].r_a1
= val
& addr_mask
;
438 case m32c_sim_reg_fb_bank0
:
439 regs
.r
[0].r_fb
= val
& addr_mask
;
441 case m32c_sim_reg_sb_bank0
:
442 regs
.r
[0].r_sb
= val
& addr_mask
;
444 case m32c_sim_reg_r0_bank1
:
445 regs
.r
[1].r_r0
= val
& 0xffff;
447 case m32c_sim_reg_r1_bank1
:
448 regs
.r
[1].r_r1
= val
& 0xffff;
450 case m32c_sim_reg_r2_bank1
:
451 regs
.r
[1].r_r2
= val
& 0xffff;
453 case m32c_sim_reg_r3_bank1
:
454 regs
.r
[1].r_r3
= val
& 0xffff;
456 case m32c_sim_reg_a0_bank1
:
457 regs
.r
[1].r_a0
= val
& addr_mask
;
459 case m32c_sim_reg_a1_bank1
:
460 regs
.r
[1].r_a1
= val
& addr_mask
;
462 case m32c_sim_reg_fb_bank1
:
463 regs
.r
[1].r_fb
= val
& addr_mask
;
465 case m32c_sim_reg_sb_bank1
:
466 regs
.r
[1].r_sb
= val
& addr_mask
;
469 case m32c_sim_reg_usp
:
470 regs
.r_usp
= val
& addr_mask
;
472 case m32c_sim_reg_isp
:
473 regs
.r_isp
= val
& addr_mask
;
475 case m32c_sim_reg_pc
:
476 regs
.r_pc
= val
& membus_mask
;
478 case m32c_sim_reg_intb
:
479 regs
.r_intbl
= (val
& membus_mask
) & 0xffff;
480 regs
.r_intbh
= (val
& membus_mask
) >> 16;
482 case m32c_sim_reg_flg
:
483 regs
.r_flags
= val
& 0xffff;
486 /* These registers aren't implemented by the minisim. */
487 case m32c_sim_reg_svf
:
488 case m32c_sim_reg_svp
:
489 case m32c_sim_reg_vct
:
490 case m32c_sim_reg_dmd0
:
491 case m32c_sim_reg_dmd1
:
492 case m32c_sim_reg_dct0
:
493 case m32c_sim_reg_dct1
:
494 case m32c_sim_reg_drc0
:
495 case m32c_sim_reg_drc1
:
496 case m32c_sim_reg_dma0
:
497 case m32c_sim_reg_dma1
:
498 case m32c_sim_reg_dsa0
:
499 case m32c_sim_reg_dsa1
:
500 case m32c_sim_reg_dra0
:
501 case m32c_sim_reg_dra1
:
505 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
514 static volatile int stop
;
515 static enum sim_stop reason
;
519 /* Given a signal number used by the M32C bsp (that is, newlib),
520 return a target signal number used by GDB. */
522 m32c_signal_to_target (int m32c
)
527 return GDB_SIGNAL_ILL
;
530 return GDB_SIGNAL_TRAP
;
533 return GDB_SIGNAL_BUS
;
536 return GDB_SIGNAL_SEGV
;
539 return GDB_SIGNAL_XCPU
;
542 return GDB_SIGNAL_INT
;
545 return GDB_SIGNAL_FPE
;
548 return GDB_SIGNAL_ABRT
;
555 /* Take a step return code RC and set up the variables consulted by
556 sim_stop_reason appropriately. */
560 if (M32C_STEPPED (rc
) || M32C_HIT_BREAK (rc
))
562 reason
= sim_stopped
;
563 siggnal
= GDB_SIGNAL_TRAP
;
565 else if (M32C_STOPPED (rc
))
567 reason
= sim_stopped
;
568 siggnal
= m32c_signal_to_target (M32C_STOP_SIG (rc
));
572 assert (M32C_EXITED (rc
));
574 siggnal
= M32C_EXIT_STATUS (rc
);
580 sim_resume (SIM_DESC sd
, int step
, int sig_to_deliver
)
584 if (sig_to_deliver
!= 0)
587 "Warning: the m32c minisim does not implement "
588 "signal delivery yet.\n" "Resuming with no signal.\n");
593 handle_step (decode_opcode ());
600 /* We don't clear 'stop' here, because then we would miss
601 interrupts that arrived on the way here. Instead, we clear
602 the flag in sim_stop_reason, after GDB has disabled the
603 interrupt signal handler. */
611 reason
= sim_stopped
;
612 siggnal
= GDB_SIGNAL_INT
;
616 rc
= decode_opcode ();
621 if (!M32C_STEPPED (rc
))
628 m32c_sim_restore_console ();
632 sim_stop (SIM_DESC sd
)
640 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason_p
, int *sigrc_p
)
649 sim_do_command (SIM_DESC sd
, const char *cmd
)
652 char *p
= strdup (cmd
);
656 /* Skip leading whitespace. */
660 /* Find the extent of the command word. */
661 for (p
= cmd
; *p
; p
++)
665 /* Null-terminate the command word, and record the start of any
666 further arguments. */
671 while (isspace (*args
))
677 if (strcmp (cmd
, "trace") == 0)
679 if (strcmp (args
, "on") == 0)
681 else if (strcmp (args
, "off") == 0)
684 printf ("The 'sim trace' command expects 'on' or 'off' "
685 "as an argument.\n");
687 else if (strcmp (cmd
, "verbose") == 0)
689 if (strcmp (args
, "on") == 0)
691 else if (strcmp (args
, "off") == 0)
694 printf ("The 'sim verbose' command expects 'on' or 'off'"
695 " as an argument.\n");
698 printf ("The 'sim' command expects either 'trace' or 'verbose'"
699 " as a subcommand.\n");
705 sim_complete_command (SIM_DESC sd
, const char *text
, const char *word
)
711 sim_info (SIM_DESC sd
, int verbose
)
713 printf ("The m32c minisim doesn't collect any statistics.\n");
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