1 /* gdb.c --- sim interface to GDB.
3 Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
4 Contributed by Red Hat, Inc.
6 This file is part of the GNU simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "gdb/callback.h"
30 #include "gdb/remote-sim.h"
31 #include "gdb/signals.h"
32 #include "gdb/sim-m32c.h"
39 /* I don't want to wrap up all the minisim's data structures in an
40 object and pass that around. That'd be a big change, and neither
41 GDB nor run needs that ability.
43 So we just have one instance, that lives in global variables, and
44 each time we open it, we re-initialize it. */
50 static struct sim_state the_minisim
= {
51 "This is the sole m32c minisim instance. See libsim.a's global variables."
57 sim_open (SIM_OPEN_KIND kind
,
58 struct host_callback_struct
*callback
,
59 struct bfd
*abfd
, char **argv
)
62 fprintf (stderr
, "m32c minisim: re-opened sim\n");
64 /* The 'run' interface doesn't use this function, so we don't care
65 about KIND; it's always SIM_OPEN_DEBUG. */
66 if (kind
!= SIM_OPEN_DEBUG
)
67 fprintf (stderr
, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n",
71 m32c_set_mach (bfd_get_mach (abfd
));
73 /* We can use ABFD, if non-NULL to select the appropriate
74 architecture. But we only support the r8c right now. */
76 set_callbacks (callback
);
78 /* We don't expect any command-line arguments. */
88 check_desc (SIM_DESC sd
)
90 if (sd
!= &the_minisim
)
91 fprintf (stderr
, "m32c minisim: desc != &the_minisim\n");
95 sim_close (SIM_DESC sd
, int quitting
)
99 /* Not much to do. At least free up our memory. */
106 open_objfile (const char *filename
)
108 bfd
*prog
= bfd_openr (filename
, 0);
112 fprintf (stderr
, "Can't read %s\n", filename
);
116 if (!bfd_check_format (prog
, bfd_object
))
118 fprintf (stderr
, "%s not a m32c program\n", filename
);
127 sim_load (SIM_DESC sd
, char *prog
, struct bfd
*abfd
, int from_tty
)
132 abfd
= open_objfile (prog
);
142 sim_create_inferior (SIM_DESC sd
, struct bfd
*abfd
, char **argv
, char **env
)
153 sim_read (SIM_DESC sd
, SIM_ADDR mem
, unsigned char *buf
, int length
)
160 mem_get_blk ((int) mem
, buf
, length
);
166 sim_write (SIM_DESC sd
, SIM_ADDR mem
, unsigned char *buf
, int length
)
170 mem_put_blk ((int) mem
, buf
, length
);
176 /* Read the LENGTH bytes at BUF as an little-endian value. */
178 get_le (unsigned char *buf
, int length
)
181 while (--length
>= 0)
182 acc
= (acc
<< 8) + buf
[length
];
187 /* Store VAL as a little-endian value in the LENGTH bytes at BUF. */
189 put_le (unsigned char *buf
, int length
, DI val
)
193 for (i
= 0; i
< length
; i
++)
201 check_regno (enum m32c_sim_reg regno
)
203 return 0 <= regno
&& regno
< m32c_sim_reg_num_regs
;
207 mask_size (int addr_mask
)
218 "m32c minisim: addr_mask_size: unexpected mask 0x%x\n",
220 return sizeof (addr_mask
);
225 reg_size (enum m32c_sim_reg regno
)
229 case m32c_sim_reg_r0_bank0
:
230 case m32c_sim_reg_r1_bank0
:
231 case m32c_sim_reg_r2_bank0
:
232 case m32c_sim_reg_r3_bank0
:
233 case m32c_sim_reg_r0_bank1
:
234 case m32c_sim_reg_r1_bank1
:
235 case m32c_sim_reg_r2_bank1
:
236 case m32c_sim_reg_r3_bank1
:
237 case m32c_sim_reg_flg
:
238 case m32c_sim_reg_svf
:
241 case m32c_sim_reg_a0_bank0
:
242 case m32c_sim_reg_a1_bank0
:
243 case m32c_sim_reg_fb_bank0
:
244 case m32c_sim_reg_sb_bank0
:
245 case m32c_sim_reg_a0_bank1
:
246 case m32c_sim_reg_a1_bank1
:
247 case m32c_sim_reg_fb_bank1
:
248 case m32c_sim_reg_sb_bank1
:
249 case m32c_sim_reg_usp
:
250 case m32c_sim_reg_isp
:
251 return mask_size (addr_mask
);
253 case m32c_sim_reg_pc
:
254 case m32c_sim_reg_intb
:
255 case m32c_sim_reg_svp
:
256 case m32c_sim_reg_vct
:
257 return mask_size (membus_mask
);
259 case m32c_sim_reg_dmd0
:
260 case m32c_sim_reg_dmd1
:
263 case m32c_sim_reg_dct0
:
264 case m32c_sim_reg_dct1
:
265 case m32c_sim_reg_drc0
:
266 case m32c_sim_reg_drc1
:
269 case m32c_sim_reg_dma0
:
270 case m32c_sim_reg_dma1
:
271 case m32c_sim_reg_dsa0
:
272 case m32c_sim_reg_dsa1
:
273 case m32c_sim_reg_dra0
:
274 case m32c_sim_reg_dra1
:
278 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
285 sim_fetch_register (SIM_DESC sd
, int regno
, unsigned char *buf
, int length
)
291 if (!check_regno (regno
))
294 size
= reg_size (regno
);
301 case m32c_sim_reg_r0_bank0
:
302 val
= regs
.r
[0].r_r0
;
304 case m32c_sim_reg_r1_bank0
:
305 val
= regs
.r
[0].r_r1
;
307 case m32c_sim_reg_r2_bank0
:
308 val
= regs
.r
[0].r_r2
;
310 case m32c_sim_reg_r3_bank0
:
311 val
= regs
.r
[0].r_r3
;
313 case m32c_sim_reg_a0_bank0
:
314 val
= regs
.r
[0].r_a0
;
316 case m32c_sim_reg_a1_bank0
:
317 val
= regs
.r
[0].r_a1
;
319 case m32c_sim_reg_fb_bank0
:
320 val
= regs
.r
[0].r_fb
;
322 case m32c_sim_reg_sb_bank0
:
323 val
= regs
.r
[0].r_sb
;
325 case m32c_sim_reg_r0_bank1
:
326 val
= regs
.r
[1].r_r0
;
328 case m32c_sim_reg_r1_bank1
:
329 val
= regs
.r
[1].r_r1
;
331 case m32c_sim_reg_r2_bank1
:
332 val
= regs
.r
[1].r_r2
;
334 case m32c_sim_reg_r3_bank1
:
335 val
= regs
.r
[1].r_r3
;
337 case m32c_sim_reg_a0_bank1
:
338 val
= regs
.r
[1].r_a0
;
340 case m32c_sim_reg_a1_bank1
:
341 val
= regs
.r
[1].r_a1
;
343 case m32c_sim_reg_fb_bank1
:
344 val
= regs
.r
[1].r_fb
;
346 case m32c_sim_reg_sb_bank1
:
347 val
= regs
.r
[1].r_sb
;
350 case m32c_sim_reg_usp
:
353 case m32c_sim_reg_isp
:
356 case m32c_sim_reg_pc
:
359 case m32c_sim_reg_intb
:
360 val
= regs
.r_intbl
* 65536 + regs
.r_intbl
;
362 case m32c_sim_reg_flg
:
366 /* These registers aren't implemented by the minisim. */
367 case m32c_sim_reg_svf
:
368 case m32c_sim_reg_svp
:
369 case m32c_sim_reg_vct
:
370 case m32c_sim_reg_dmd0
:
371 case m32c_sim_reg_dmd1
:
372 case m32c_sim_reg_dct0
:
373 case m32c_sim_reg_dct1
:
374 case m32c_sim_reg_drc0
:
375 case m32c_sim_reg_drc1
:
376 case m32c_sim_reg_dma0
:
377 case m32c_sim_reg_dma1
:
378 case m32c_sim_reg_dsa0
:
379 case m32c_sim_reg_dsa1
:
380 case m32c_sim_reg_dra0
:
381 case m32c_sim_reg_dra1
:
385 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
390 put_le (buf
, length
, val
);
397 sim_store_register (SIM_DESC sd
, int regno
, unsigned char *buf
, int length
)
403 if (!check_regno (regno
))
406 size
= reg_size (regno
);
410 DI val
= get_le (buf
, length
);
414 case m32c_sim_reg_r0_bank0
:
415 regs
.r
[0].r_r0
= val
& 0xffff;
417 case m32c_sim_reg_r1_bank0
:
418 regs
.r
[0].r_r1
= val
& 0xffff;
420 case m32c_sim_reg_r2_bank0
:
421 regs
.r
[0].r_r2
= val
& 0xffff;
423 case m32c_sim_reg_r3_bank0
:
424 regs
.r
[0].r_r3
= val
& 0xffff;
426 case m32c_sim_reg_a0_bank0
:
427 regs
.r
[0].r_a0
= val
& addr_mask
;
429 case m32c_sim_reg_a1_bank0
:
430 regs
.r
[0].r_a1
= val
& addr_mask
;
432 case m32c_sim_reg_fb_bank0
:
433 regs
.r
[0].r_fb
= val
& addr_mask
;
435 case m32c_sim_reg_sb_bank0
:
436 regs
.r
[0].r_sb
= val
& addr_mask
;
438 case m32c_sim_reg_r0_bank1
:
439 regs
.r
[1].r_r0
= val
& 0xffff;
441 case m32c_sim_reg_r1_bank1
:
442 regs
.r
[1].r_r1
= val
& 0xffff;
444 case m32c_sim_reg_r2_bank1
:
445 regs
.r
[1].r_r2
= val
& 0xffff;
447 case m32c_sim_reg_r3_bank1
:
448 regs
.r
[1].r_r3
= val
& 0xffff;
450 case m32c_sim_reg_a0_bank1
:
451 regs
.r
[1].r_a0
= val
& addr_mask
;
453 case m32c_sim_reg_a1_bank1
:
454 regs
.r
[1].r_a1
= val
& addr_mask
;
456 case m32c_sim_reg_fb_bank1
:
457 regs
.r
[1].r_fb
= val
& addr_mask
;
459 case m32c_sim_reg_sb_bank1
:
460 regs
.r
[1].r_sb
= val
& addr_mask
;
463 case m32c_sim_reg_usp
:
464 regs
.r_usp
= val
& addr_mask
;
466 case m32c_sim_reg_isp
:
467 regs
.r_isp
= val
& addr_mask
;
469 case m32c_sim_reg_pc
:
470 regs
.r_pc
= val
& membus_mask
;
472 case m32c_sim_reg_intb
:
473 regs
.r_intbl
= (val
& membus_mask
) & 0xffff;
474 regs
.r_intbh
= (val
& membus_mask
) >> 16;
476 case m32c_sim_reg_flg
:
477 regs
.r_flags
= val
& 0xffff;
480 /* These registers aren't implemented by the minisim. */
481 case m32c_sim_reg_svf
:
482 case m32c_sim_reg_svp
:
483 case m32c_sim_reg_vct
:
484 case m32c_sim_reg_dmd0
:
485 case m32c_sim_reg_dmd1
:
486 case m32c_sim_reg_dct0
:
487 case m32c_sim_reg_dct1
:
488 case m32c_sim_reg_drc0
:
489 case m32c_sim_reg_drc1
:
490 case m32c_sim_reg_dma0
:
491 case m32c_sim_reg_dma1
:
492 case m32c_sim_reg_dsa0
:
493 case m32c_sim_reg_dsa1
:
494 case m32c_sim_reg_dra0
:
495 case m32c_sim_reg_dra1
:
499 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
509 sim_info (SIM_DESC sd
, int verbose
)
513 printf ("The m32c minisim doesn't collect any statistics.\n");
516 static volatile int stop
;
517 static enum sim_stop reason
;
521 /* Given a signal number used by the M32C bsp (that is, newlib),
522 return a host signal number. (Oddly, the gdb/sim interface uses
523 host signal numbers...) */
525 m32c_signal_to_host (int m32c
)
574 /* Take a step return code RC and set up the variables consulted by
575 sim_stop_reason appropriately. */
579 if (M32C_STEPPED (rc
) || M32C_HIT_BREAK (rc
))
581 reason
= sim_stopped
;
582 siggnal
= TARGET_SIGNAL_TRAP
;
584 else if (M32C_STOPPED (rc
))
586 reason
= sim_stopped
;
587 siggnal
= m32c_signal_to_host (M32C_STOP_SIG (rc
));
591 assert (M32C_EXITED (rc
));
593 siggnal
= M32C_EXIT_STATUS (rc
);
599 sim_resume (SIM_DESC sd
, int step
, int sig_to_deliver
)
603 if (sig_to_deliver
!= 0)
606 "Warning: the m32c minisim does not implement "
607 "signal delivery yet.\n" "Resuming with no signal.\n");
611 handle_step (decode_opcode ());
614 /* We don't clear 'stop' here, because then we would miss
615 interrupts that arrived on the way here. Instead, we clear
616 the flag in sim_stop_reason, after GDB has disabled the
617 interrupt signal handler. */
623 reason
= sim_stopped
;
624 siggnal
= TARGET_SIGNAL_INT
;
628 int rc
= decode_opcode ();
630 if (!M32C_STEPPED (rc
))
640 sim_stop (SIM_DESC sd
)
648 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason_p
, int *sigrc_p
)
657 sim_do_command (SIM_DESC sd
, char *cmd
)
663 /* Skip leading whitespace. */
667 /* Find the extent of the command word. */
668 for (p
= cmd
; *p
; p
++)
672 /* Null-terminate the command word, and record the start of any
673 further arguments. */
679 while (isspace (*args
))
685 if (strcmp (cmd
, "trace") == 0)
687 if (strcmp (args
, "on") == 0)
689 else if (strcmp (args
, "off") == 0)
692 printf ("The 'sim trace' command expects 'on' or 'off' "
693 "as an argument.\n");
695 else if (strcmp (cmd
, "verbose") == 0)
697 if (strcmp (args
, "on") == 0)
699 else if (strcmp (args
, "off") == 0)
702 printf ("The 'sim verbose' command expects 'on' or 'off'"
703 " as an argument.\n");
706 printf ("The 'sim' command expects either 'trace' or 'verbose'"
707 " as a subcommand.\n");
This page took 0.047808 seconds and 4 git commands to generate.