1 /* gdb.c --- sim interface to GDB.
3 Copyright (C) 2005, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Red Hat, Inc.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "gdb/callback.h"
31 #include "gdb/remote-sim.h"
32 #include "gdb/signals.h"
33 #include "gdb/sim-m32c.h"
43 /* I don't want to wrap up all the minisim's data structures in an
44 object and pass that around. That'd be a big change, and neither
45 GDB nor run needs that ability.
47 So we just have one instance, that lives in global variables, and
48 each time we open it, we re-initialize it. */
54 static struct sim_state the_minisim
= {
55 "This is the sole m32c minisim instance. See libsim.a's global variables."
61 sim_open (SIM_OPEN_KIND kind
,
62 struct host_callback_struct
*callback
,
63 struct bfd
*abfd
, char **argv
)
67 fprintf (stderr
, "m32c minisim: re-opened sim\n");
69 /* The 'run' interface doesn't use this function, so we don't care
70 about KIND; it's always SIM_OPEN_DEBUG. */
71 if (kind
!= SIM_OPEN_DEBUG
)
72 fprintf (stderr
, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n",
76 m32c_set_mach (bfd_get_mach (abfd
));
78 /* We can use ABFD, if non-NULL to select the appropriate
79 architecture. But we only support the r8c right now. */
81 set_callbacks (callback
);
83 /* We don't expect any command-line arguments. */
93 check_desc (SIM_DESC sd
)
95 if (sd
!= &the_minisim
)
96 fprintf (stderr
, "m32c minisim: desc != &the_minisim\n");
100 sim_close (SIM_DESC sd
, int quitting
)
104 /* Not much to do. At least free up our memory. */
111 open_objfile (const char *filename
)
113 bfd
*prog
= bfd_openr (filename
, 0);
117 fprintf (stderr
, "Can't read %s\n", filename
);
121 if (!bfd_check_format (prog
, bfd_object
))
123 fprintf (stderr
, "%s not a m32c program\n", filename
);
132 sim_load (SIM_DESC sd
, char *prog
, struct bfd
* abfd
, int from_tty
)
137 abfd
= open_objfile (prog
);
147 sim_create_inferior (SIM_DESC sd
, struct bfd
* abfd
, char **argv
, char **env
)
158 sim_read (SIM_DESC sd
, SIM_ADDR mem
, unsigned char *buf
, int length
)
165 mem_get_blk ((int) mem
, buf
, length
);
171 sim_write (SIM_DESC sd
, SIM_ADDR mem
, const unsigned char *buf
, int length
)
175 mem_put_blk ((int) mem
, buf
, length
);
181 /* Read the LENGTH bytes at BUF as an little-endian value. */
183 get_le (unsigned char *buf
, int length
)
186 while (--length
>= 0)
187 acc
= (acc
<< 8) + buf
[length
];
192 /* Store VAL as a little-endian value in the LENGTH bytes at BUF. */
194 put_le (unsigned char *buf
, int length
, DI val
)
198 for (i
= 0; i
< length
; i
++)
206 check_regno (enum m32c_sim_reg regno
)
208 return 0 <= regno
&& regno
< m32c_sim_reg_num_regs
;
212 mask_size (int addr_mask
)
223 "m32c minisim: addr_mask_size: unexpected mask 0x%x\n",
225 return sizeof (addr_mask
);
230 reg_size (enum m32c_sim_reg regno
)
234 case m32c_sim_reg_r0_bank0
:
235 case m32c_sim_reg_r1_bank0
:
236 case m32c_sim_reg_r2_bank0
:
237 case m32c_sim_reg_r3_bank0
:
238 case m32c_sim_reg_r0_bank1
:
239 case m32c_sim_reg_r1_bank1
:
240 case m32c_sim_reg_r2_bank1
:
241 case m32c_sim_reg_r3_bank1
:
242 case m32c_sim_reg_flg
:
243 case m32c_sim_reg_svf
:
246 case m32c_sim_reg_a0_bank0
:
247 case m32c_sim_reg_a1_bank0
:
248 case m32c_sim_reg_fb_bank0
:
249 case m32c_sim_reg_sb_bank0
:
250 case m32c_sim_reg_a0_bank1
:
251 case m32c_sim_reg_a1_bank1
:
252 case m32c_sim_reg_fb_bank1
:
253 case m32c_sim_reg_sb_bank1
:
254 case m32c_sim_reg_usp
:
255 case m32c_sim_reg_isp
:
256 return mask_size (addr_mask
);
258 case m32c_sim_reg_pc
:
259 case m32c_sim_reg_intb
:
260 case m32c_sim_reg_svp
:
261 case m32c_sim_reg_vct
:
262 return mask_size (membus_mask
);
264 case m32c_sim_reg_dmd0
:
265 case m32c_sim_reg_dmd1
:
268 case m32c_sim_reg_dct0
:
269 case m32c_sim_reg_dct1
:
270 case m32c_sim_reg_drc0
:
271 case m32c_sim_reg_drc1
:
274 case m32c_sim_reg_dma0
:
275 case m32c_sim_reg_dma1
:
276 case m32c_sim_reg_dsa0
:
277 case m32c_sim_reg_dsa1
:
278 case m32c_sim_reg_dra0
:
279 case m32c_sim_reg_dra1
:
283 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
290 sim_fetch_register (SIM_DESC sd
, int regno
, unsigned char *buf
, int length
)
296 if (!check_regno (regno
))
299 size
= reg_size (regno
);
306 case m32c_sim_reg_r0_bank0
:
307 val
= regs
.r
[0].r_r0
;
309 case m32c_sim_reg_r1_bank0
:
310 val
= regs
.r
[0].r_r1
;
312 case m32c_sim_reg_r2_bank0
:
313 val
= regs
.r
[0].r_r2
;
315 case m32c_sim_reg_r3_bank0
:
316 val
= regs
.r
[0].r_r3
;
318 case m32c_sim_reg_a0_bank0
:
319 val
= regs
.r
[0].r_a0
;
321 case m32c_sim_reg_a1_bank0
:
322 val
= regs
.r
[0].r_a1
;
324 case m32c_sim_reg_fb_bank0
:
325 val
= regs
.r
[0].r_fb
;
327 case m32c_sim_reg_sb_bank0
:
328 val
= regs
.r
[0].r_sb
;
330 case m32c_sim_reg_r0_bank1
:
331 val
= regs
.r
[1].r_r0
;
333 case m32c_sim_reg_r1_bank1
:
334 val
= regs
.r
[1].r_r1
;
336 case m32c_sim_reg_r2_bank1
:
337 val
= regs
.r
[1].r_r2
;
339 case m32c_sim_reg_r3_bank1
:
340 val
= regs
.r
[1].r_r3
;
342 case m32c_sim_reg_a0_bank1
:
343 val
= regs
.r
[1].r_a0
;
345 case m32c_sim_reg_a1_bank1
:
346 val
= regs
.r
[1].r_a1
;
348 case m32c_sim_reg_fb_bank1
:
349 val
= regs
.r
[1].r_fb
;
351 case m32c_sim_reg_sb_bank1
:
352 val
= regs
.r
[1].r_sb
;
355 case m32c_sim_reg_usp
:
358 case m32c_sim_reg_isp
:
361 case m32c_sim_reg_pc
:
364 case m32c_sim_reg_intb
:
365 val
= regs
.r_intbl
* 65536 + regs
.r_intbl
;
367 case m32c_sim_reg_flg
:
371 /* These registers aren't implemented by the minisim. */
372 case m32c_sim_reg_svf
:
373 case m32c_sim_reg_svp
:
374 case m32c_sim_reg_vct
:
375 case m32c_sim_reg_dmd0
:
376 case m32c_sim_reg_dmd1
:
377 case m32c_sim_reg_dct0
:
378 case m32c_sim_reg_dct1
:
379 case m32c_sim_reg_drc0
:
380 case m32c_sim_reg_drc1
:
381 case m32c_sim_reg_dma0
:
382 case m32c_sim_reg_dma1
:
383 case m32c_sim_reg_dsa0
:
384 case m32c_sim_reg_dsa1
:
385 case m32c_sim_reg_dra0
:
386 case m32c_sim_reg_dra1
:
390 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
395 put_le (buf
, length
, val
);
402 sim_store_register (SIM_DESC sd
, int regno
, unsigned char *buf
, int length
)
408 if (!check_regno (regno
))
411 size
= reg_size (regno
);
415 DI val
= get_le (buf
, length
);
419 case m32c_sim_reg_r0_bank0
:
420 regs
.r
[0].r_r0
= val
& 0xffff;
422 case m32c_sim_reg_r1_bank0
:
423 regs
.r
[0].r_r1
= val
& 0xffff;
425 case m32c_sim_reg_r2_bank0
:
426 regs
.r
[0].r_r2
= val
& 0xffff;
428 case m32c_sim_reg_r3_bank0
:
429 regs
.r
[0].r_r3
= val
& 0xffff;
431 case m32c_sim_reg_a0_bank0
:
432 regs
.r
[0].r_a0
= val
& addr_mask
;
434 case m32c_sim_reg_a1_bank0
:
435 regs
.r
[0].r_a1
= val
& addr_mask
;
437 case m32c_sim_reg_fb_bank0
:
438 regs
.r
[0].r_fb
= val
& addr_mask
;
440 case m32c_sim_reg_sb_bank0
:
441 regs
.r
[0].r_sb
= val
& addr_mask
;
443 case m32c_sim_reg_r0_bank1
:
444 regs
.r
[1].r_r0
= val
& 0xffff;
446 case m32c_sim_reg_r1_bank1
:
447 regs
.r
[1].r_r1
= val
& 0xffff;
449 case m32c_sim_reg_r2_bank1
:
450 regs
.r
[1].r_r2
= val
& 0xffff;
452 case m32c_sim_reg_r3_bank1
:
453 regs
.r
[1].r_r3
= val
& 0xffff;
455 case m32c_sim_reg_a0_bank1
:
456 regs
.r
[1].r_a0
= val
& addr_mask
;
458 case m32c_sim_reg_a1_bank1
:
459 regs
.r
[1].r_a1
= val
& addr_mask
;
461 case m32c_sim_reg_fb_bank1
:
462 regs
.r
[1].r_fb
= val
& addr_mask
;
464 case m32c_sim_reg_sb_bank1
:
465 regs
.r
[1].r_sb
= val
& addr_mask
;
468 case m32c_sim_reg_usp
:
469 regs
.r_usp
= val
& addr_mask
;
471 case m32c_sim_reg_isp
:
472 regs
.r_isp
= val
& addr_mask
;
474 case m32c_sim_reg_pc
:
475 regs
.r_pc
= val
& membus_mask
;
477 case m32c_sim_reg_intb
:
478 regs
.r_intbl
= (val
& membus_mask
) & 0xffff;
479 regs
.r_intbh
= (val
& membus_mask
) >> 16;
481 case m32c_sim_reg_flg
:
482 regs
.r_flags
= val
& 0xffff;
485 /* These registers aren't implemented by the minisim. */
486 case m32c_sim_reg_svf
:
487 case m32c_sim_reg_svp
:
488 case m32c_sim_reg_vct
:
489 case m32c_sim_reg_dmd0
:
490 case m32c_sim_reg_dmd1
:
491 case m32c_sim_reg_dct0
:
492 case m32c_sim_reg_dct1
:
493 case m32c_sim_reg_drc0
:
494 case m32c_sim_reg_drc1
:
495 case m32c_sim_reg_dma0
:
496 case m32c_sim_reg_dma1
:
497 case m32c_sim_reg_dsa0
:
498 case m32c_sim_reg_dsa1
:
499 case m32c_sim_reg_dra0
:
500 case m32c_sim_reg_dra1
:
504 fprintf (stderr
, "m32c minisim: unrecognized register number: %d\n",
514 sim_info (SIM_DESC sd
, int verbose
)
518 printf ("The m32c minisim doesn't collect any statistics.\n");
521 static volatile int stop
;
522 static enum sim_stop reason
;
526 /* Given a signal number used by the M32C bsp (that is, newlib),
527 return a target signal number used by GDB. */
529 m32c_signal_to_target (int m32c
)
534 return TARGET_SIGNAL_ILL
;
537 return TARGET_SIGNAL_TRAP
;
540 return TARGET_SIGNAL_BUS
;
543 return TARGET_SIGNAL_SEGV
;
546 return TARGET_SIGNAL_XCPU
;
549 return TARGET_SIGNAL_INT
;
552 return TARGET_SIGNAL_FPE
;
555 return TARGET_SIGNAL_ABRT
;
562 /* Take a step return code RC and set up the variables consulted by
563 sim_stop_reason appropriately. */
567 if (M32C_STEPPED (rc
) || M32C_HIT_BREAK (rc
))
569 reason
= sim_stopped
;
570 siggnal
= TARGET_SIGNAL_TRAP
;
572 else if (M32C_STOPPED (rc
))
574 reason
= sim_stopped
;
575 siggnal
= m32c_signal_to_target (M32C_STOP_SIG (rc
));
579 assert (M32C_EXITED (rc
));
581 siggnal
= M32C_EXIT_STATUS (rc
);
587 sim_resume (SIM_DESC sd
, int step
, int sig_to_deliver
)
591 if (sig_to_deliver
!= 0)
594 "Warning: the m32c minisim does not implement "
595 "signal delivery yet.\n" "Resuming with no signal.\n");
600 handle_step (decode_opcode ());
607 /* We don't clear 'stop' here, because then we would miss
608 interrupts that arrived on the way here. Instead, we clear
609 the flag in sim_stop_reason, after GDB has disabled the
610 interrupt signal handler. */
616 reason
= sim_stopped
;
617 siggnal
= TARGET_SIGNAL_INT
;
621 int rc
= decode_opcode ();
626 if (!M32C_STEPPED (rc
))
633 m32c_sim_restore_console ();
637 sim_stop (SIM_DESC sd
)
645 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason_p
, int *sigrc_p
)
654 sim_do_command (SIM_DESC sd
, char *cmd
)
660 /* Skip leading whitespace. */
664 /* Find the extent of the command word. */
665 for (p
= cmd
; *p
; p
++)
669 /* Null-terminate the command word, and record the start of any
670 further arguments. */
676 while (isspace (*args
))
682 if (strcmp (cmd
, "trace") == 0)
684 if (strcmp (args
, "on") == 0)
686 else if (strcmp (args
, "off") == 0)
689 printf ("The 'sim trace' command expects 'on' or 'off' "
690 "as an argument.\n");
692 else if (strcmp (cmd
, "verbose") == 0)
694 if (strcmp (args
, "on") == 0)
696 else if (strcmp (args
, "off") == 0)
699 printf ("The 'sim verbose' command expects 'on' or 'off'"
700 " as an argument.\n");
703 printf ("The 'sim' command expects either 'trace' or 'verbose'"
704 " as a subcommand.\n");
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