sim/m32c/gdb-if.c

   1 /* gdb.c --- sim interface to GDB.
   2
   3 Copyright (C) 2005, 2007, 2008 Free Software Foundation, Inc.
   4 Contributed by Red Hat, Inc.
   5
   6 This file is part of the GNU simulators.
   7
   8 This program is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3 of the License, or
  11 (at your option) any later version.
  12
  13 This program is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #include <stdio.h>
  23 #include <assert.h>
  24 #include <signal.h>
  25 #include <string.h>
  26 #include <ctype.h>
  27
  28 #include "ansidecl.h"
  29 #include "gdb/callback.h"
  30 #include "gdb/remote-sim.h"
  31 #include "gdb/signals.h"
  32 #include "gdb/sim-m32c.h"
  33
  34 #include "cpu.h"
  35 #include "mem.h"
  36 #include "load.h"
  37 #include "syscalls.h"
  38
  39 /* I don't want to wrap up all the minisim's data structures in an
  40    object and pass that around.  That'd be a big change, and neither
  41    GDB nor run needs that ability.
  42
  43    So we just have one instance, that lives in global variables, and
  44    each time we open it, we re-initialize it.  */
  45 struct sim_state
  46 {
  47   const char *message;
  48 };
  49
  50 static struct sim_state the_minisim = {
  51   "This is the sole m32c minisim instance.  See libsim.a's global variables."
  52 };
  53
  54 static int open;
  55
  56 SIM_DESC
  57 sim_open (SIM_OPEN_KIND kind,
  58           struct host_callback_struct *callback,
  59           struct bfd *abfd, char **argv)
  60 {
  61   setbuf (stdout, 0);
  62   if (open)
  63     fprintf (stderr, "m32c minisim: re-opened sim\n");
  64
  65   /* The 'run' interface doesn't use this function, so we don't care
  66      about KIND; it's always SIM_OPEN_DEBUG.  */
  67   if (kind != SIM_OPEN_DEBUG)
  68     fprintf (stderr, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n",
  69              kind);
  70
  71   if (abfd)
  72     m32c_set_mach (bfd_get_mach (abfd));
  73
  74   /* We can use ABFD, if non-NULL to select the appropriate
  75      architecture.  But we only support the r8c right now.  */
  76
  77   set_callbacks (callback);
  78
  79   /* We don't expect any command-line arguments.  */
  80
  81   init_mem ();
  82   init_regs ();
  83
  84   open = 1;
  85   return &the_minisim;
  86 }
  87
  88 static void
  89 check_desc (SIM_DESC sd)
  90 {
  91   if (sd != &the_minisim)
  92     fprintf (stderr, "m32c minisim: desc != &the_minisim\n");
  93 }
  94
  95 void
  96 sim_close (SIM_DESC sd, int quitting)
  97 {
  98   check_desc (sd);
  99
 100   /* Not much to do.  At least free up our memory.  */
 101   init_mem ();
 102
 103   open = 0;
 104 }
 105
 106 static bfd *
 107 open_objfile (const char *filename)
 108 {
 109   bfd *prog = bfd_openr (filename, 0);
 110
 111   if (!prog)
 112     {
 113       fprintf (stderr, "Can't read %s\n", filename);
 114       return 0;
 115     }
 116
 117   if (!bfd_check_format (prog, bfd_object))
 118     {
 119       fprintf (stderr, "%s not a m32c program\n", filename);
 120       return 0;
 121     }
 122
 123   return prog;
 124 }
 125
 126
 127 SIM_RC
 128 sim_load (SIM_DESC sd, char *prog, struct bfd * abfd, int from_tty)
 129 {
 130   check_desc (sd);
 131
 132   if (!abfd)
 133     abfd = open_objfile (prog);
 134   if (!abfd)
 135     return SIM_RC_FAIL;
 136
 137   m32c_load (abfd);
 138
 139   return SIM_RC_OK;
 140 }
 141
 142 SIM_RC
 143 sim_create_inferior (SIM_DESC sd, struct bfd * abfd, char **argv, char **env)
 144 {
 145   check_desc (sd);
 146
 147   if (abfd)
 148     m32c_load (abfd);
 149
 150   return SIM_RC_OK;
 151 }
 152
 153 int
 154 sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
 155 {
 156   check_desc (sd);
 157
 158   if (mem == 0)
 159     return 0;
 160
 161   mem_get_blk ((int) mem, buf, length);
 162
 163   return length;
 164 }
 165
 166 int
 167 sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
 168 {
 169   check_desc (sd);
 170
 171   mem_put_blk ((int) mem, buf, length);
 172
 173   return length;
 174 }
 175
 176
 177 /* Read the LENGTH bytes at BUF as an little-endian value.  */
 178 static DI
 179 get_le (unsigned char *buf, int length)
 180 {
 181   DI acc = 0;
 182   while (--length >= 0)
 183     acc = (acc << 8) + buf[length];
 184
 185   return acc;
 186 }
 187
 188 /* Store VAL as a little-endian value in the LENGTH bytes at BUF.  */
 189 static void
 190 put_le (unsigned char *buf, int length, DI val)
 191 {
 192   int i;
 193
 194   for (i = 0; i < length; i++)
 195     {
 196       buf[i] = val & 0xff;
 197       val >>= 8;
 198     }
 199 }
 200
 201 static int
 202 check_regno (enum m32c_sim_reg regno)
 203 {
 204   return 0 <= regno && regno < m32c_sim_reg_num_regs;
 205 }
 206
 207 static size_t
 208 mask_size (int addr_mask)
 209 {
 210   switch (addr_mask)
 211     {
 212     case 0xffff:
 213       return 2;
 214     case 0xfffff:
 215     case 0xffffff:
 216       return 3;
 217     default:
 218       fprintf (stderr,
 219                "m32c minisim: addr_mask_size: unexpected mask 0x%x\n",
 220                addr_mask);
 221       return sizeof (addr_mask);
 222     }
 223 }
 224
 225 static size_t
 226 reg_size (enum m32c_sim_reg regno)
 227 {
 228   switch (regno)
 229     {
 230     case m32c_sim_reg_r0_bank0:
 231     case m32c_sim_reg_r1_bank0:
 232     case m32c_sim_reg_r2_bank0:
 233     case m32c_sim_reg_r3_bank0:
 234     case m32c_sim_reg_r0_bank1:
 235     case m32c_sim_reg_r1_bank1:
 236     case m32c_sim_reg_r2_bank1:
 237     case m32c_sim_reg_r3_bank1:
 238     case m32c_sim_reg_flg:
 239     case m32c_sim_reg_svf:
 240       return 2;
 241
 242     case m32c_sim_reg_a0_bank0:
 243     case m32c_sim_reg_a1_bank0:
 244     case m32c_sim_reg_fb_bank0:
 245     case m32c_sim_reg_sb_bank0:
 246     case m32c_sim_reg_a0_bank1:
 247     case m32c_sim_reg_a1_bank1:
 248     case m32c_sim_reg_fb_bank1:
 249     case m32c_sim_reg_sb_bank1:
 250     case m32c_sim_reg_usp:
 251     case m32c_sim_reg_isp:
 252       return mask_size (addr_mask);
 253
 254     case m32c_sim_reg_pc:
 255     case m32c_sim_reg_intb:
 256     case m32c_sim_reg_svp:
 257     case m32c_sim_reg_vct:
 258       return mask_size (membus_mask);
 259
 260     case m32c_sim_reg_dmd0:
 261     case m32c_sim_reg_dmd1:
 262       return 1;
 263
 264     case m32c_sim_reg_dct0:
 265     case m32c_sim_reg_dct1:
 266     case m32c_sim_reg_drc0:
 267     case m32c_sim_reg_drc1:
 268       return 2;
 269
 270     case m32c_sim_reg_dma0:
 271     case m32c_sim_reg_dma1:
 272     case m32c_sim_reg_dsa0:
 273     case m32c_sim_reg_dsa1:
 274     case m32c_sim_reg_dra0:
 275     case m32c_sim_reg_dra1:
 276       return 3;
 277
 278     default:
 279       fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
 280                regno);
 281       return -1;
 282     }
 283 }
 284
 285 int
 286 sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
 287 {
 288   size_t size;
 289
 290   check_desc (sd);
 291
 292   if (!check_regno (regno))
 293     return 0;
 294
 295   size = reg_size (regno);
 296   if (length == size)
 297     {
 298       DI val;
 299
 300       switch (regno)
 301         {
 302         case m32c_sim_reg_r0_bank0:
 303           val = regs.r[0].r_r0;
 304           break;
 305         case m32c_sim_reg_r1_bank0:
 306           val = regs.r[0].r_r1;
 307           break;
 308         case m32c_sim_reg_r2_bank0:
 309           val = regs.r[0].r_r2;
 310           break;
 311         case m32c_sim_reg_r3_bank0:
 312           val = regs.r[0].r_r3;
 313           break;
 314         case m32c_sim_reg_a0_bank0:
 315           val = regs.r[0].r_a0;
 316           break;
 317         case m32c_sim_reg_a1_bank0:
 318           val = regs.r[0].r_a1;
 319           break;
 320         case m32c_sim_reg_fb_bank0:
 321           val = regs.r[0].r_fb;
 322           break;
 323         case m32c_sim_reg_sb_bank0:
 324           val = regs.r[0].r_sb;
 325           break;
 326         case m32c_sim_reg_r0_bank1:
 327           val = regs.r[1].r_r0;
 328           break;
 329         case m32c_sim_reg_r1_bank1:
 330           val = regs.r[1].r_r1;
 331           break;
 332         case m32c_sim_reg_r2_bank1:
 333           val = regs.r[1].r_r2;
 334           break;
 335         case m32c_sim_reg_r3_bank1:
 336           val = regs.r[1].r_r3;
 337           break;
 338         case m32c_sim_reg_a0_bank1:
 339           val = regs.r[1].r_a0;
 340           break;
 341         case m32c_sim_reg_a1_bank1:
 342           val = regs.r[1].r_a1;
 343           break;
 344         case m32c_sim_reg_fb_bank1:
 345           val = regs.r[1].r_fb;
 346           break;
 347         case m32c_sim_reg_sb_bank1:
 348           val = regs.r[1].r_sb;
 349           break;
 350
 351         case m32c_sim_reg_usp:
 352           val = regs.r_usp;
 353           break;
 354         case m32c_sim_reg_isp:
 355           val = regs.r_isp;
 356           break;
 357         case m32c_sim_reg_pc:
 358           val = regs.r_pc;
 359           break;
 360         case m32c_sim_reg_intb:
 361           val = regs.r_intbl * 65536 + regs.r_intbl;
 362           break;
 363         case m32c_sim_reg_flg:
 364           val = regs.r_flags;
 365           break;
 366
 367           /* These registers aren't implemented by the minisim.  */
 368         case m32c_sim_reg_svf:
 369         case m32c_sim_reg_svp:
 370         case m32c_sim_reg_vct:
 371         case m32c_sim_reg_dmd0:
 372         case m32c_sim_reg_dmd1:
 373         case m32c_sim_reg_dct0:
 374         case m32c_sim_reg_dct1:
 375         case m32c_sim_reg_drc0:
 376         case m32c_sim_reg_drc1:
 377         case m32c_sim_reg_dma0:
 378         case m32c_sim_reg_dma1:
 379         case m32c_sim_reg_dsa0:
 380         case m32c_sim_reg_dsa1:
 381         case m32c_sim_reg_dra0:
 382         case m32c_sim_reg_dra1:
 383           return 0;
 384
 385         default:
 386           fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
 387                    regno);
 388           return -1;
 389         }
 390
 391       put_le (buf, length, val);
 392     }
 393
 394   return size;
 395 }
 396
 397 int
 398 sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
 399 {
 400   size_t size;
 401
 402   check_desc (sd);
 403
 404   if (!check_regno (regno))
 405     return 0;
 406
 407   size = reg_size (regno);
 408
 409   if (length == size)
 410     {
 411       DI val = get_le (buf, length);
 412
 413       switch (regno)
 414         {
 415         case m32c_sim_reg_r0_bank0:
 416           regs.r[0].r_r0 = val & 0xffff;
 417           break;
 418         case m32c_sim_reg_r1_bank0:
 419           regs.r[0].r_r1 = val & 0xffff;
 420           break;
 421         case m32c_sim_reg_r2_bank0:
 422           regs.r[0].r_r2 = val & 0xffff;
 423           break;
 424         case m32c_sim_reg_r3_bank0:
 425           regs.r[0].r_r3 = val & 0xffff;
 426           break;
 427         case m32c_sim_reg_a0_bank0:
 428           regs.r[0].r_a0 = val & addr_mask;
 429           break;
 430         case m32c_sim_reg_a1_bank0:
 431           regs.r[0].r_a1 = val & addr_mask;
 432           break;
 433         case m32c_sim_reg_fb_bank0:
 434           regs.r[0].r_fb = val & addr_mask;
 435           break;
 436         case m32c_sim_reg_sb_bank0:
 437           regs.r[0].r_sb = val & addr_mask;
 438           break;
 439         case m32c_sim_reg_r0_bank1:
 440           regs.r[1].r_r0 = val & 0xffff;
 441           break;
 442         case m32c_sim_reg_r1_bank1:
 443           regs.r[1].r_r1 = val & 0xffff;
 444           break;
 445         case m32c_sim_reg_r2_bank1:
 446           regs.r[1].r_r2 = val & 0xffff;
 447           break;
 448         case m32c_sim_reg_r3_bank1:
 449           regs.r[1].r_r3 = val & 0xffff;
 450           break;
 451         case m32c_sim_reg_a0_bank1:
 452           regs.r[1].r_a0 = val & addr_mask;
 453           break;
 454         case m32c_sim_reg_a1_bank1:
 455           regs.r[1].r_a1 = val & addr_mask;
 456           break;
 457         case m32c_sim_reg_fb_bank1:
 458           regs.r[1].r_fb = val & addr_mask;
 459           break;
 460         case m32c_sim_reg_sb_bank1:
 461           regs.r[1].r_sb = val & addr_mask;
 462           break;
 463
 464         case m32c_sim_reg_usp:
 465           regs.r_usp = val & addr_mask;
 466           break;
 467         case m32c_sim_reg_isp:
 468           regs.r_isp = val & addr_mask;
 469           break;
 470         case m32c_sim_reg_pc:
 471           regs.r_pc = val & membus_mask;
 472           break;
 473         case m32c_sim_reg_intb:
 474           regs.r_intbl = (val & membus_mask) & 0xffff;
 475           regs.r_intbh = (val & membus_mask) >> 16;
 476           break;
 477         case m32c_sim_reg_flg:
 478           regs.r_flags = val & 0xffff;
 479           break;
 480
 481           /* These registers aren't implemented by the minisim.  */
 482         case m32c_sim_reg_svf:
 483         case m32c_sim_reg_svp:
 484         case m32c_sim_reg_vct:
 485         case m32c_sim_reg_dmd0:
 486         case m32c_sim_reg_dmd1:
 487         case m32c_sim_reg_dct0:
 488         case m32c_sim_reg_dct1:
 489         case m32c_sim_reg_drc0:
 490         case m32c_sim_reg_drc1:
 491         case m32c_sim_reg_dma0:
 492         case m32c_sim_reg_dma1:
 493         case m32c_sim_reg_dsa0:
 494         case m32c_sim_reg_dsa1:
 495         case m32c_sim_reg_dra0:
 496         case m32c_sim_reg_dra1:
 497           return 0;
 498
 499         default:
 500           fprintf (stderr, "m32c minisim: unrecognized register number: %d\n",
 501                    regno);
 502           return -1;
 503         }
 504     }
 505
 506   return size;
 507 }
 508
 509 void
 510 sim_info (SIM_DESC sd, int verbose)
 511 {
 512   check_desc (sd);
 513
 514   printf ("The m32c minisim doesn't collect any statistics.\n");
 515 }
 516
 517 static volatile int stop;
 518 static enum sim_stop reason;
 519 int siggnal;
 520
 521
 522 /* Given a signal number used by the M32C bsp (that is, newlib),
 523    return a host signal number.  (Oddly, the gdb/sim interface uses
 524    host signal numbers...)  */
 525 int
 526 m32c_signal_to_host (int m32c)
 527 {
 528   switch (m32c)
 529     {
 530     case 4:
 531 #ifdef SIGILL
 532       return SIGILL;
 533 #else
 534       return SIGSEGV;
 535 #endif
 536
 537     case 5:
 538       return SIGTRAP;
 539
 540     case 10:
 541 #ifdef SIGBUS
 542       return SIGBUS;
 543 #else
 544       return SIGSEGV;
 545 #endif
 546
 547     case 11:
 548       return SIGSEGV;
 549
 550     case 24:
 551 #ifdef SIGXCPU
 552       return SIGXCPU;
 553 #else
 554       break;
 555 #endif
 556
 557     case 2:
 558       return SIGINT;
 559
 560     case 8:
 561 #ifdef SIGFPE
 562       return SIGFPE;
 563 #else
 564       break;
 565 #endif
 566
 567     case 6:
 568       return SIGABRT;
 569     }
 570
 571   return 0;
 572 }
 573
 574
 575 /* Take a step return code RC and set up the variables consulted by
 576    sim_stop_reason appropriately.  */
 577 void
 578 handle_step (int rc)
 579 {
 580   if (M32C_STEPPED (rc) || M32C_HIT_BREAK (rc))
 581     {
 582       reason = sim_stopped;
 583       siggnal = TARGET_SIGNAL_TRAP;
 584     }
 585   else if (M32C_STOPPED (rc))
 586     {
 587       reason = sim_stopped;
 588       siggnal = m32c_signal_to_host (M32C_STOP_SIG (rc));
 589     }
 590   else
 591     {
 592       assert (M32C_EXITED (rc));
 593       reason = sim_exited;
 594       siggnal = M32C_EXIT_STATUS (rc);
 595     }
 596 }
 597
 598
 599 void
 600 sim_resume (SIM_DESC sd, int step, int sig_to_deliver)
 601 {
 602   check_desc (sd);
 603
 604   if (sig_to_deliver != 0)
 605     {
 606       fprintf (stderr,
 607                "Warning: the m32c minisim does not implement "
 608                "signal delivery yet.\n" "Resuming with no signal.\n");
 609     }
 610
 611   if (step)
 612     {
 613       handle_step (decode_opcode ());
 614 #ifdef TIMER_A
 615       update_timer_a ();
 616 #endif
 617     }
 618   else
 619     {
 620       /* We don't clear 'stop' here, because then we would miss
 621          interrupts that arrived on the way here.  Instead, we clear
 622          the flag in sim_stop_reason, after GDB has disabled the
 623          interrupt signal handler.  */
 624       for (;;)
 625         {
 626           if (stop)
 627             {
 628               stop = 0;
 629               reason = sim_stopped;
 630               siggnal = TARGET_SIGNAL_INT;
 631               break;
 632             }
 633
 634           int rc = decode_opcode ();
 635 #ifdef TIMER_A
 636           update_timer_a ();
 637 #endif
 638
 639           if (!M32C_STEPPED (rc))
 640             {
 641               handle_step (rc);
 642               break;
 643             }
 644         }
 645     }
 646   m32c_sim_restore_console ();
 647 }
 648
 649 int
 650 sim_stop (SIM_DESC sd)
 651 {
 652   stop = 1;
 653
 654   return 1;
 655 }
 656
 657 void
 658 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p)
 659 {
 660   check_desc (sd);
 661
 662   *reason_p = reason;
 663   *sigrc_p = siggnal;
 664 }
 665
 666 void
 667 sim_do_command (SIM_DESC sd, char *cmd)
 668 {
 669   check_desc (sd);
 670
 671   char *p = cmd;
 672
 673   /* Skip leading whitespace.  */
 674   while (isspace (*p))
 675     p++;
 676
 677   /* Find the extent of the command word.  */
 678   for (p = cmd; *p; p++)
 679     if (isspace (*p))
 680       break;
 681
 682   /* Null-terminate the command word, and record the start of any
 683      further arguments.  */
 684   char *args;
 685   if (*p)
 686     {
 687       *p = '\0';
 688       args = p + 1;
 689       while (isspace (*args))
 690         args++;
 691     }
 692   else
 693     args = p;
 694
 695   if (strcmp (cmd, "trace") == 0)
 696     {
 697       if (strcmp (args, "on") == 0)
 698         trace = 1;
 699       else if (strcmp (args, "off") == 0)
 700         trace = 0;
 701       else
 702         printf ("The 'sim trace' command expects 'on' or 'off' "
 703                 "as an argument.\n");
 704     }
 705   else if (strcmp (cmd, "verbose") == 0)
 706     {
 707       if (strcmp (args, "on") == 0)
 708         verbose = 1;
 709       else if (strcmp (args, "off") == 0)
 710         verbose = 0;
 711       else
 712         printf ("The 'sim verbose' command expects 'on' or 'off'"
 713                 " as an argument.\n");
 714     }
 715   else
 716     printf ("The 'sim' command expects either 'trace' or 'verbose'"
 717             " as a subcommand.\n");
 718 }