sim/m32r/cpu.h

   1 /* CPU family header for m32r.
   2
   3 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   4
   5 This file is part of the GNU Simulators.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  20
  21 */
  22
  23 #ifndef CPU_M32R_H
  24 #define CPU_M32R_H
  25
  26 /* Maximum number of instructions that are fetched at a time.
  27    This is for LIW type instructions sets (e.g. m32r).  */
  28 #define MAX_LIW_INSNS 2
  29
  30 /* Maximum number of instructions that can be executed in parallel.  */
  31 #define MAX_PARALLEL_INSNS 1
  32
  33 /* CPU state information.  */
  34 typedef struct {
  35   /* Hardware elements.  */
  36   struct {
  37   /* program counter */
  38   USI h_pc;
  39 #define GET_H_PC() CPU (h_pc)
  40 #define SET_H_PC(x) (CPU (h_pc) = (x))
  41   /* general registers */
  42   SI h_gr[16];
  43 #define GET_H_GR(a1) CPU (h_gr)[a1]
  44 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  45   /* control registers */
  46   SI h_cr[7];
  47 #define GET_H_CR(a1) CPU (h_cr)[a1]
  48 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
  49   /* accumulator */
  50   DI h_accum;
  51 #define GET_H_ACCUM() CPU (h_accum)
  52 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
  53   /* condition bit */
  54   UBI h_cond;
  55 #define GET_H_COND() CPU (h_cond)
  56 #define SET_H_COND(x) (CPU (h_cond) = (x))
  57   /* sm */
  58   UBI h_sm;
  59 #define GET_H_SM() CPU (h_sm)
  60 #define SET_H_SM(x) (CPU (h_sm) = (x))
  61   /* bsm */
  62   UBI h_bsm;
  63 #define GET_H_BSM() CPU (h_bsm)
  64 #define SET_H_BSM(x) (CPU (h_bsm) = (x))
  65   /* ie */
  66   UBI h_ie;
  67 #define GET_H_IE() CPU (h_ie)
  68 #define SET_H_IE(x) (CPU (h_ie) = (x))
  69   /* bie */
  70   UBI h_bie;
  71 #define GET_H_BIE() CPU (h_bie)
  72 #define SET_H_BIE(x) (CPU (h_bie) = (x))
  73   /* bcond */
  74   UBI h_bcond;
  75 #define GET_H_BCOND() CPU (h_bcond)
  76 #define SET_H_BCOND(x) (CPU (h_bcond) = (x))
  77   /* bpc */
  78   SI h_bpc;
  79 #define GET_H_BPC() CPU (h_bpc)
  80 #define SET_H_BPC(x) (CPU (h_bpc) = (x))
  81   } hardware;
  82 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  83   /* CPU profiling state information.  */
  84   struct {
  85   /* general registers */
  86   unsigned long h_gr;
  87   } profile;
  88 #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
  89 } M32R_CPU_DATA;
  90
  91 /* FIXME: length parm to decode() is currently unneeded.  */
  92 extern DECODE *m32r_decode (SIM_CPU *, insn_t /*, int*/);
  93
  94 /* The ARGBUF struct.  */
  95 struct argbuf {
  96   /* These are the baseclass definitions.  */
  97   unsigned int length;
  98   PCADDR addr;
  99   const struct cgen_insn *opcode;
 100   /* unsigned long insn; - no longer needed */
 101   /* cpu specific data follows */
 102   union {
 103     struct { /* e.g. add $dr,$sr */
 104       SI * f_r1;
 105       SI * f_r2;
 106     } fmt_0_add;
 107     struct { /* e.g. add3 $dr,$sr,$slo16 */
 108       SI * f_r1;
 109       SI * f_r2;
 110       HI f_simm16;
 111     } fmt_1_add3;
 112     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 113       SI * f_r1;
 114       SI * f_r2;
 115       USI f_uimm16;
 116     } fmt_2_and3;
 117     struct { /* e.g. or3 $dr,$sr,$ulo16 */
 118       SI * f_r1;
 119       SI * f_r2;
 120       UHI f_uimm16;
 121     } fmt_3_or3;
 122     struct { /* e.g. addi $dr,$simm8 */
 123       SI * f_r1;
 124       SI f_simm8;
 125     } fmt_4_addi;
 126     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 127       SI * f_r1;
 128       SI * f_r2;
 129       SI f_simm16;
 130     } fmt_5_addv3;
 131     struct { /* e.g. addx $dr,$sr */
 132       SI * f_r1;
 133       SI * f_r2;
 134     } fmt_6_addx;
 135     struct { /* e.g. bc $disp8 */
 136       IADDR f_disp8;
 137     } fmt_7_bc8;
 138     struct { /* e.g. bc $disp24 */
 139       IADDR f_disp24;
 140     } fmt_8_bc24;
 141     struct { /* e.g. beq $src1,$src2,$disp16 */
 142       SI * f_r1;
 143       SI * f_r2;
 144       IADDR f_disp16;
 145     } fmt_9_beq;
 146     struct { /* e.g. beqz $src2,$disp16 */
 147       SI * f_r2;
 148       IADDR f_disp16;
 149     } fmt_10_beqz;
 150     struct { /* e.g. bl $disp8 */
 151       IADDR f_disp8;
 152     } fmt_11_bl8;
 153     struct { /* e.g. bl $disp24 */
 154       IADDR f_disp24;
 155     } fmt_12_bl24;
 156     struct { /* e.g. bra $disp8 */
 157       IADDR f_disp8;
 158     } fmt_13_bra8;
 159     struct { /* e.g. bra $disp24 */
 160       IADDR f_disp24;
 161     } fmt_14_bra24;
 162     struct { /* e.g. cmp $src1,$src2 */
 163       SI * f_r1;
 164       SI * f_r2;
 165     } fmt_15_cmp;
 166     struct { /* e.g. cmpi $src2,$simm16 */
 167       SI * f_r2;
 168       SI f_simm16;
 169     } fmt_16_cmpi;
 170     struct { /* e.g. cmpui $src2,$uimm16 */
 171       SI * f_r2;
 172       USI f_uimm16;
 173     } fmt_17_cmpui;
 174     struct { /* e.g. div $dr,$sr */
 175       SI * f_r1;
 176       SI * f_r2;
 177     } fmt_18_div;
 178     struct { /* e.g. jl $sr */
 179       SI * f_r2;
 180     } fmt_19_jl;
 181     struct { /* e.g. jmp $sr */
 182       SI * f_r2;
 183     } fmt_20_jmp;
 184     struct { /* e.g. ld $dr,@$sr */
 185       SI * f_r1;
 186       SI * f_r2;
 187     } fmt_21_ld;
 188     struct { /* e.g. ld $dr,@($slo16,$sr) */
 189       SI * f_r1;
 190       SI * f_r2;
 191       HI f_simm16;
 192     } fmt_22_ld_d;
 193     struct { /* e.g. ldb $dr,@$sr */
 194       SI * f_r1;
 195       SI * f_r2;
 196     } fmt_23_ldb;
 197     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 198       SI * f_r1;
 199       SI * f_r2;
 200       HI f_simm16;
 201     } fmt_24_ldb_d;
 202     struct { /* e.g. ldh $dr,@$sr */
 203       SI * f_r1;
 204       SI * f_r2;
 205     } fmt_25_ldh;
 206     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 207       SI * f_r1;
 208       SI * f_r2;
 209       HI f_simm16;
 210     } fmt_26_ldh_d;
 211     struct { /* e.g. ld24 $dr,$uimm24 */
 212       SI * f_r1;
 213       ADDR f_uimm24;
 214     } fmt_27_ld24;
 215     struct { /* e.g. ldi $dr,$simm8 */
 216       SI * f_r1;
 217       SI f_simm8;
 218     } fmt_28_ldi8;
 219     struct { /* e.g. ldi $dr,$slo16 */
 220       SI * f_r1;
 221       HI f_simm16;
 222     } fmt_29_ldi16;
 223     struct { /* e.g. machi $src1,$src2 */
 224       SI * f_r1;
 225       SI * f_r2;
 226     } fmt_30_machi;
 227     struct { /* e.g. mv $dr,$sr */
 228       SI * f_r1;
 229       SI * f_r2;
 230     } fmt_31_mv;
 231     struct { /* e.g. mvfachi $dr */
 232       SI * f_r1;
 233     } fmt_32_mvfachi;
 234     struct { /* e.g. mvfc $dr,$scr */
 235       SI * f_r1;
 236       UINT f_r2;
 237     } fmt_33_mvfc;
 238     struct { /* e.g. mvtachi $src1 */
 239       SI * f_r1;
 240     } fmt_34_mvtachi;
 241     struct { /* e.g. mvtc $sr,$dcr */
 242       UINT f_r1;
 243       SI * f_r2;
 244     } fmt_35_mvtc;
 245     struct { /* e.g. nop */
 246       int empty;
 247     } fmt_36_nop;
 248     struct { /* e.g. rac */
 249       int empty;
 250     } fmt_37_rac;
 251     struct { /* e.g. seth $dr,$hi16 */
 252       SI * f_r1;
 253       UHI f_hi16;
 254     } fmt_38_seth;
 255     struct { /* e.g. slli $dr,$uimm5 */
 256       SI * f_r1;
 257       USI f_uimm5;
 258     } fmt_39_slli;
 259     struct { /* e.g. st $src1,@($slo16,$src2) */
 260       SI * f_r1;
 261       SI * f_r2;
 262       HI f_simm16;
 263     } fmt_40_st_d;
 264     struct { /* e.g. trap $uimm4 */
 265       USI f_uimm4;
 266     } fmt_41_trap;
 267   } fields;
 268 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
 269   unsigned long h_gr_get;
 270   unsigned long h_gr_set;
 271 #endif
 272 };
 273
 274 /* A cached insn.
 275    This is also used in the non-scache case.  In this situation we assume
 276    the cache size is 1, and do a few things a little differently.  */
 277
 278 struct scache {
 279   IADDR next;
 280   union {
 281 #if ! WITH_SEM_SWITCH_FULL
 282     SEMANTIC_FN *sem_fn;
 283 #endif
 284 #if ! WITH_SEM_SWITCH_FAST
 285 #if WITH_SCACHE
 286     SEMANTIC_CACHE_FN *sem_fast_fn;
 287 #else
 288     SEMANTIC_FN *sem_fast_fn;
 289 #endif
 290 #endif
 291 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
 292 #ifdef __GNUC__
 293     void *sem_case;
 294 #else
 295     int sem_case;
 296 #endif
 297 #endif
 298   } semantic;
 299   struct argbuf argbuf;
 300 };
 301
 302 /* Macros to simplify extraction, reading and semantic code.
 303    These define and assign the local vars that contain the insn's fields.  */
 304
 305 #define EXTRACT_FMT_0_ADD_VARS \
 306   /* Instruction fields.  */ \
 307   UINT f_op1; \
 308   UINT f_r1; \
 309   UINT f_op2; \
 310   UINT f_r2; \
 311   unsigned int length;
 312 #define EXTRACT_FMT_0_ADD_CODE \
 313   length = 2; \
 314   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 315   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 316   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 317   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 318
 319 #define EXTRACT_FMT_1_ADD3_VARS \
 320   /* Instruction fields.  */ \
 321   UINT f_op1; \
 322   UINT f_r1; \
 323   UINT f_op2; \
 324   UINT f_r2; \
 325   int f_simm16; \
 326   unsigned int length;
 327 #define EXTRACT_FMT_1_ADD3_CODE \
 328   length = 4; \
 329   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 330   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 331   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 332   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 333   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 334
 335 #define EXTRACT_FMT_2_AND3_VARS \
 336   /* Instruction fields.  */ \
 337   UINT f_op1; \
 338   UINT f_r1; \
 339   UINT f_op2; \
 340   UINT f_r2; \
 341   UINT f_uimm16; \
 342   unsigned int length;
 343 #define EXTRACT_FMT_2_AND3_CODE \
 344   length = 4; \
 345   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 346   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 347   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 348   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 349   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 350
 351 #define EXTRACT_FMT_3_OR3_VARS \
 352   /* Instruction fields.  */ \
 353   UINT f_op1; \
 354   UINT f_r1; \
 355   UINT f_op2; \
 356   UINT f_r2; \
 357   UINT f_uimm16; \
 358   unsigned int length;
 359 #define EXTRACT_FMT_3_OR3_CODE \
 360   length = 4; \
 361   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 362   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 363   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 364   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 365   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 366
 367 #define EXTRACT_FMT_4_ADDI_VARS \
 368   /* Instruction fields.  */ \
 369   UINT f_op1; \
 370   UINT f_r1; \
 371   int f_simm8; \
 372   unsigned int length;
 373 #define EXTRACT_FMT_4_ADDI_CODE \
 374   length = 2; \
 375   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 376   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 377   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 378
 379 #define EXTRACT_FMT_5_ADDV3_VARS \
 380   /* Instruction fields.  */ \
 381   UINT f_op1; \
 382   UINT f_r1; \
 383   UINT f_op2; \
 384   UINT f_r2; \
 385   int f_simm16; \
 386   unsigned int length;
 387 #define EXTRACT_FMT_5_ADDV3_CODE \
 388   length = 4; \
 389   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 390   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 391   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 392   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 393   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 394
 395 #define EXTRACT_FMT_6_ADDX_VARS \
 396   /* Instruction fields.  */ \
 397   UINT f_op1; \
 398   UINT f_r1; \
 399   UINT f_op2; \
 400   UINT f_r2; \
 401   unsigned int length;
 402 #define EXTRACT_FMT_6_ADDX_CODE \
 403   length = 2; \
 404   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 405   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 406   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 407   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 408
 409 #define EXTRACT_FMT_7_BC8_VARS \
 410   /* Instruction fields.  */ \
 411   UINT f_op1; \
 412   UINT f_r1; \
 413   int f_disp8; \
 414   unsigned int length;
 415 #define EXTRACT_FMT_7_BC8_CODE \
 416   length = 2; \
 417   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 418   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 419   f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
 420
 421 #define EXTRACT_FMT_8_BC24_VARS \
 422   /* Instruction fields.  */ \
 423   UINT f_op1; \
 424   UINT f_r1; \
 425   int f_disp24; \
 426   unsigned int length;
 427 #define EXTRACT_FMT_8_BC24_CODE \
 428   length = 4; \
 429   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 430   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 431   f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
 432
 433 #define EXTRACT_FMT_9_BEQ_VARS \
 434   /* Instruction fields.  */ \
 435   UINT f_op1; \
 436   UINT f_r1; \
 437   UINT f_op2; \
 438   UINT f_r2; \
 439   int f_disp16; \
 440   unsigned int length;
 441 #define EXTRACT_FMT_9_BEQ_CODE \
 442   length = 4; \
 443   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 444   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 445   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 446   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 447   f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
 448
 449 #define EXTRACT_FMT_10_BEQZ_VARS \
 450   /* Instruction fields.  */ \
 451   UINT f_op1; \
 452   UINT f_r1; \
 453   UINT f_op2; \
 454   UINT f_r2; \
 455   int f_disp16; \
 456   unsigned int length;
 457 #define EXTRACT_FMT_10_BEQZ_CODE \
 458   length = 4; \
 459   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 460   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 461   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 462   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 463   f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
 464
 465 #define EXTRACT_FMT_11_BL8_VARS \
 466   /* Instruction fields.  */ \
 467   UINT f_op1; \
 468   UINT f_r1; \
 469   int f_disp8; \
 470   unsigned int length;
 471 #define EXTRACT_FMT_11_BL8_CODE \
 472   length = 2; \
 473   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 474   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 475   f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
 476
 477 #define EXTRACT_FMT_12_BL24_VARS \
 478   /* Instruction fields.  */ \
 479   UINT f_op1; \
 480   UINT f_r1; \
 481   int f_disp24; \
 482   unsigned int length;
 483 #define EXTRACT_FMT_12_BL24_CODE \
 484   length = 4; \
 485   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 486   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 487   f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
 488
 489 #define EXTRACT_FMT_13_BRA8_VARS \
 490   /* Instruction fields.  */ \
 491   UINT f_op1; \
 492   UINT f_r1; \
 493   int f_disp8; \
 494   unsigned int length;
 495 #define EXTRACT_FMT_13_BRA8_CODE \
 496   length = 2; \
 497   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 498   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 499   f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
 500
 501 #define EXTRACT_FMT_14_BRA24_VARS \
 502   /* Instruction fields.  */ \
 503   UINT f_op1; \
 504   UINT f_r1; \
 505   int f_disp24; \
 506   unsigned int length;
 507 #define EXTRACT_FMT_14_BRA24_CODE \
 508   length = 4; \
 509   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 510   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 511   f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
 512
 513 #define EXTRACT_FMT_15_CMP_VARS \
 514   /* Instruction fields.  */ \
 515   UINT f_op1; \
 516   UINT f_r1; \
 517   UINT f_op2; \
 518   UINT f_r2; \
 519   unsigned int length;
 520 #define EXTRACT_FMT_15_CMP_CODE \
 521   length = 2; \
 522   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 523   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 524   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 525   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 526
 527 #define EXTRACT_FMT_16_CMPI_VARS \
 528   /* Instruction fields.  */ \
 529   UINT f_op1; \
 530   UINT f_r1; \
 531   UINT f_op2; \
 532   UINT f_r2; \
 533   int f_simm16; \
 534   unsigned int length;
 535 #define EXTRACT_FMT_16_CMPI_CODE \
 536   length = 4; \
 537   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 538   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 539   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 540   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 541   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 542
 543 #define EXTRACT_FMT_17_CMPUI_VARS \
 544   /* Instruction fields.  */ \
 545   UINT f_op1; \
 546   UINT f_r1; \
 547   UINT f_op2; \
 548   UINT f_r2; \
 549   UINT f_uimm16; \
 550   unsigned int length;
 551 #define EXTRACT_FMT_17_CMPUI_CODE \
 552   length = 4; \
 553   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 554   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 555   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 556   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 557   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 558
 559 #define EXTRACT_FMT_18_DIV_VARS \
 560   /* Instruction fields.  */ \
 561   UINT f_op1; \
 562   UINT f_r1; \
 563   UINT f_op2; \
 564   UINT f_r2; \
 565   int f_simm16; \
 566   unsigned int length;
 567 #define EXTRACT_FMT_18_DIV_CODE \
 568   length = 4; \
 569   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 570   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 571   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 572   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 573   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 574
 575 #define EXTRACT_FMT_19_JL_VARS \
 576   /* Instruction fields.  */ \
 577   UINT f_op1; \
 578   UINT f_r1; \
 579   UINT f_op2; \
 580   UINT f_r2; \
 581   unsigned int length;
 582 #define EXTRACT_FMT_19_JL_CODE \
 583   length = 2; \
 584   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 585   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 586   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 587   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 588
 589 #define EXTRACT_FMT_20_JMP_VARS \
 590   /* Instruction fields.  */ \
 591   UINT f_op1; \
 592   UINT f_r1; \
 593   UINT f_op2; \
 594   UINT f_r2; \
 595   unsigned int length;
 596 #define EXTRACT_FMT_20_JMP_CODE \
 597   length = 2; \
 598   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 599   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 600   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 601   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 602
 603 #define EXTRACT_FMT_21_LD_VARS \
 604   /* Instruction fields.  */ \
 605   UINT f_op1; \
 606   UINT f_r1; \
 607   UINT f_op2; \
 608   UINT f_r2; \
 609   unsigned int length;
 610 #define EXTRACT_FMT_21_LD_CODE \
 611   length = 2; \
 612   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 613   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 614   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 615   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 616
 617 #define EXTRACT_FMT_22_LD_D_VARS \
 618   /* Instruction fields.  */ \
 619   UINT f_op1; \
 620   UINT f_r1; \
 621   UINT f_op2; \
 622   UINT f_r2; \
 623   int f_simm16; \
 624   unsigned int length;
 625 #define EXTRACT_FMT_22_LD_D_CODE \
 626   length = 4; \
 627   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 628   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 629   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 630   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 631   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 632
 633 #define EXTRACT_FMT_23_LDB_VARS \
 634   /* Instruction fields.  */ \
 635   UINT f_op1; \
 636   UINT f_r1; \
 637   UINT f_op2; \
 638   UINT f_r2; \
 639   unsigned int length;
 640 #define EXTRACT_FMT_23_LDB_CODE \
 641   length = 2; \
 642   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 643   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 644   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 645   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 646
 647 #define EXTRACT_FMT_24_LDB_D_VARS \
 648   /* Instruction fields.  */ \
 649   UINT f_op1; \
 650   UINT f_r1; \
 651   UINT f_op2; \
 652   UINT f_r2; \
 653   int f_simm16; \
 654   unsigned int length;
 655 #define EXTRACT_FMT_24_LDB_D_CODE \
 656   length = 4; \
 657   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 658   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 659   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 660   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 661   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 662
 663 #define EXTRACT_FMT_25_LDH_VARS \
 664   /* Instruction fields.  */ \
 665   UINT f_op1; \
 666   UINT f_r1; \
 667   UINT f_op2; \
 668   UINT f_r2; \
 669   unsigned int length;
 670 #define EXTRACT_FMT_25_LDH_CODE \
 671   length = 2; \
 672   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 673   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 674   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 675   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 676
 677 #define EXTRACT_FMT_26_LDH_D_VARS \
 678   /* Instruction fields.  */ \
 679   UINT f_op1; \
 680   UINT f_r1; \
 681   UINT f_op2; \
 682   UINT f_r2; \
 683   int f_simm16; \
 684   unsigned int length;
 685 #define EXTRACT_FMT_26_LDH_D_CODE \
 686   length = 4; \
 687   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 688   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 689   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 690   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 691   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 692
 693 #define EXTRACT_FMT_27_LD24_VARS \
 694   /* Instruction fields.  */ \
 695   UINT f_op1; \
 696   UINT f_r1; \
 697   UINT f_uimm24; \
 698   unsigned int length;
 699 #define EXTRACT_FMT_27_LD24_CODE \
 700   length = 4; \
 701   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 702   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 703   f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
 704
 705 #define EXTRACT_FMT_28_LDI8_VARS \
 706   /* Instruction fields.  */ \
 707   UINT f_op1; \
 708   UINT f_r1; \
 709   int f_simm8; \
 710   unsigned int length;
 711 #define EXTRACT_FMT_28_LDI8_CODE \
 712   length = 2; \
 713   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 714   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 715   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 716
 717 #define EXTRACT_FMT_29_LDI16_VARS \
 718   /* Instruction fields.  */ \
 719   UINT f_op1; \
 720   UINT f_r1; \
 721   UINT f_op2; \
 722   UINT f_r2; \
 723   int f_simm16; \
 724   unsigned int length;
 725 #define EXTRACT_FMT_29_LDI16_CODE \
 726   length = 4; \
 727   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 728   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 729   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 730   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 731   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 732
 733 #define EXTRACT_FMT_30_MACHI_VARS \
 734   /* Instruction fields.  */ \
 735   UINT f_op1; \
 736   UINT f_r1; \
 737   UINT f_op2; \
 738   UINT f_r2; \
 739   unsigned int length;
 740 #define EXTRACT_FMT_30_MACHI_CODE \
 741   length = 2; \
 742   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 743   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 744   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 745   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 746
 747 #define EXTRACT_FMT_31_MV_VARS \
 748   /* Instruction fields.  */ \
 749   UINT f_op1; \
 750   UINT f_r1; \
 751   UINT f_op2; \
 752   UINT f_r2; \
 753   unsigned int length;
 754 #define EXTRACT_FMT_31_MV_CODE \
 755   length = 2; \
 756   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 757   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 758   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 759   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 760
 761 #define EXTRACT_FMT_32_MVFACHI_VARS \
 762   /* Instruction fields.  */ \
 763   UINT f_op1; \
 764   UINT f_r1; \
 765   UINT f_op2; \
 766   UINT f_r2; \
 767   unsigned int length;
 768 #define EXTRACT_FMT_32_MVFACHI_CODE \
 769   length = 2; \
 770   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 771   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 772   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 773   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 774
 775 #define EXTRACT_FMT_33_MVFC_VARS \
 776   /* Instruction fields.  */ \
 777   UINT f_op1; \
 778   UINT f_r1; \
 779   UINT f_op2; \
 780   UINT f_r2; \
 781   unsigned int length;
 782 #define EXTRACT_FMT_33_MVFC_CODE \
 783   length = 2; \
 784   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 785   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 786   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 787   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 788
 789 #define EXTRACT_FMT_34_MVTACHI_VARS \
 790   /* Instruction fields.  */ \
 791   UINT f_op1; \
 792   UINT f_r1; \
 793   UINT f_op2; \
 794   UINT f_r2; \
 795   unsigned int length;
 796 #define EXTRACT_FMT_34_MVTACHI_CODE \
 797   length = 2; \
 798   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 799   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 800   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 801   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 802
 803 #define EXTRACT_FMT_35_MVTC_VARS \
 804   /* Instruction fields.  */ \
 805   UINT f_op1; \
 806   UINT f_r1; \
 807   UINT f_op2; \
 808   UINT f_r2; \
 809   unsigned int length;
 810 #define EXTRACT_FMT_35_MVTC_CODE \
 811   length = 2; \
 812   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 813   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 814   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 815   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 816
 817 #define EXTRACT_FMT_36_NOP_VARS \
 818   /* Instruction fields.  */ \
 819   UINT f_op1; \
 820   UINT f_r1; \
 821   UINT f_op2; \
 822   UINT f_r2; \
 823   unsigned int length;
 824 #define EXTRACT_FMT_36_NOP_CODE \
 825   length = 2; \
 826   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 827   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 828   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 829   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 830
 831 #define EXTRACT_FMT_37_RAC_VARS \
 832   /* Instruction fields.  */ \
 833   UINT f_op1; \
 834   UINT f_r1; \
 835   UINT f_op2; \
 836   UINT f_r2; \
 837   unsigned int length;
 838 #define EXTRACT_FMT_37_RAC_CODE \
 839   length = 2; \
 840   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 841   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 842   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 843   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 844
 845 #define EXTRACT_FMT_38_SETH_VARS \
 846   /* Instruction fields.  */ \
 847   UINT f_op1; \
 848   UINT f_r1; \
 849   UINT f_op2; \
 850   UINT f_r2; \
 851   UINT f_hi16; \
 852   unsigned int length;
 853 #define EXTRACT_FMT_38_SETH_CODE \
 854   length = 4; \
 855   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 856   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 857   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 858   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 859   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 860
 861 #define EXTRACT_FMT_39_SLLI_VARS \
 862   /* Instruction fields.  */ \
 863   UINT f_op1; \
 864   UINT f_r1; \
 865   UINT f_shift_op2; \
 866   UINT f_uimm5; \
 867   unsigned int length;
 868 #define EXTRACT_FMT_39_SLLI_CODE \
 869   length = 2; \
 870   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 871   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 872   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
 873   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
 874
 875 #define EXTRACT_FMT_40_ST_D_VARS \
 876   /* Instruction fields.  */ \
 877   UINT f_op1; \
 878   UINT f_r1; \
 879   UINT f_op2; \
 880   UINT f_r2; \
 881   int f_simm16; \
 882   unsigned int length;
 883 #define EXTRACT_FMT_40_ST_D_CODE \
 884   length = 4; \
 885   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 886   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 887   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 888   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 889   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 890
 891 #define EXTRACT_FMT_41_TRAP_VARS \
 892   /* Instruction fields.  */ \
 893   UINT f_op1; \
 894   UINT f_r1; \
 895   UINT f_op2; \
 896   UINT f_uimm4; \
 897   unsigned int length;
 898 #define EXTRACT_FMT_41_TRAP_CODE \
 899   length = 2; \
 900   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 901   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 902   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 903   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 904
 905 #endif /* CPU_M32R_H */