1 /* CPU family header for m32rbf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 1
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 #define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
50 #define SET_H_CR(index, x) \
52 m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
56 #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
57 #define SET_H_ACCUM(x) \
59 m32rbf_h_accum_set_handler (current_cpu, (x));\
63 #define GET_H_COND() CPU (h_cond)
64 #define SET_H_COND(x) (CPU (h_cond) = (x))
67 #define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
68 #define SET_H_PSW(x) \
70 m32rbf_h_psw_set_handler (current_cpu, (x));\
74 #define GET_H_BPSW() CPU (h_bpsw)
75 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
78 #define GET_H_BBPSW() CPU (h_bbpsw)
79 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
82 #define GET_H_LOCK() CPU (h_lock)
83 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
85 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
88 /* Cover fns for register access. */
89 USI
m32rbf_h_pc_get (SIM_CPU
*);
90 void m32rbf_h_pc_set (SIM_CPU
*, USI
);
91 SI
m32rbf_h_gr_get (SIM_CPU
*, UINT
);
92 void m32rbf_h_gr_set (SIM_CPU
*, UINT
, SI
);
93 USI
m32rbf_h_cr_get (SIM_CPU
*, UINT
);
94 void m32rbf_h_cr_set (SIM_CPU
*, UINT
, USI
);
95 DI
m32rbf_h_accum_get (SIM_CPU
*);
96 void m32rbf_h_accum_set (SIM_CPU
*, DI
);
97 BI
m32rbf_h_cond_get (SIM_CPU
*);
98 void m32rbf_h_cond_set (SIM_CPU
*, BI
);
99 UQI
m32rbf_h_psw_get (SIM_CPU
*);
100 void m32rbf_h_psw_set (SIM_CPU
*, UQI
);
101 UQI
m32rbf_h_bpsw_get (SIM_CPU
*);
102 void m32rbf_h_bpsw_set (SIM_CPU
*, UQI
);
103 UQI
m32rbf_h_bbpsw_get (SIM_CPU
*);
104 void m32rbf_h_bbpsw_set (SIM_CPU
*, UQI
);
105 BI
m32rbf_h_lock_get (SIM_CPU
*);
106 void m32rbf_h_lock_set (SIM_CPU
*, BI
);
108 /* These must be hand-written. */
109 extern CPUREG_FETCH_FN m32rbf_fetch_register
;
110 extern CPUREG_STORE_FN m32rbf_store_register
;
121 struct { /* empty sformat for unspecified field list */
124 struct { /* e.g. add $dr,$sr */
129 unsigned char out_dr
;
131 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
136 unsigned char out_dr
;
138 struct { /* e.g. and3 $dr,$sr,$uimm16 */
143 unsigned char out_dr
;
145 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
150 unsigned char out_dr
;
152 struct { /* e.g. addi $dr,$simm8 */
156 unsigned char out_dr
;
158 struct { /* e.g. addv $dr,$sr */
163 unsigned char out_dr
;
165 struct { /* e.g. addv3 $dr,$sr,$simm16 */
170 unsigned char out_dr
;
172 struct { /* e.g. addx $dr,$sr */
177 unsigned char out_dr
;
179 struct { /* e.g. cmp $src1,$src2 */
182 unsigned char in_src1
;
183 unsigned char in_src2
;
185 struct { /* e.g. cmpi $src2,$simm16 */
188 unsigned char in_src2
;
190 struct { /* e.g. div $dr,$sr */
195 unsigned char out_dr
;
197 struct { /* e.g. ld $dr,@$sr */
201 unsigned char out_dr
;
203 struct { /* e.g. ld $dr,@($slo16,$sr) */
208 unsigned char out_dr
;
210 struct { /* e.g. ldb $dr,@$sr */
214 unsigned char out_dr
;
216 struct { /* e.g. ldb $dr,@($slo16,$sr) */
221 unsigned char out_dr
;
223 struct { /* e.g. ldh $dr,@$sr */
227 unsigned char out_dr
;
229 struct { /* e.g. ldh $dr,@($slo16,$sr) */
234 unsigned char out_dr
;
236 struct { /* e.g. ld $dr,@$sr+ */
240 unsigned char out_dr
;
241 unsigned char out_sr
;
243 struct { /* e.g. ld24 $dr,$uimm24 */
246 unsigned char out_dr
;
248 struct { /* e.g. ldi8 $dr,$simm8 */
251 unsigned char out_dr
;
253 struct { /* e.g. ldi16 $dr,$hash$slo16 */
256 unsigned char out_dr
;
258 struct { /* e.g. lock $dr,@$sr */
262 unsigned char out_dr
;
264 struct { /* e.g. machi $src1,$src2 */
267 unsigned char in_src1
;
268 unsigned char in_src2
;
270 struct { /* e.g. mulhi $src1,$src2 */
273 unsigned char in_src1
;
274 unsigned char in_src2
;
276 struct { /* e.g. mv $dr,$sr */
280 unsigned char out_dr
;
282 struct { /* e.g. mvfachi $dr */
284 unsigned char out_dr
;
286 struct { /* e.g. mvfc $dr,$scr */
289 unsigned char out_dr
;
291 struct { /* e.g. mvtachi $src1 */
293 unsigned char in_src1
;
295 struct { /* e.g. mvtc $sr,$dcr */
300 struct { /* e.g. nop */
303 struct { /* e.g. rac */
306 struct { /* e.g. seth $dr,$hash$hi16 */
309 unsigned char out_dr
;
311 struct { /* e.g. sll3 $dr,$sr,$simm16 */
316 unsigned char out_dr
;
318 struct { /* e.g. slli $dr,$uimm5 */
322 unsigned char out_dr
;
324 struct { /* e.g. st $src1,@$src2 */
327 unsigned char in_src1
;
328 unsigned char in_src2
;
330 struct { /* e.g. st $src1,@($slo16,$src2) */
334 unsigned char in_src1
;
335 unsigned char in_src2
;
337 struct { /* e.g. stb $src1,@$src2 */
340 unsigned char in_src1
;
341 unsigned char in_src2
;
343 struct { /* e.g. stb $src1,@($slo16,$src2) */
347 unsigned char in_src1
;
348 unsigned char in_src2
;
350 struct { /* e.g. sth $src1,@$src2 */
353 unsigned char in_src1
;
354 unsigned char in_src2
;
356 struct { /* e.g. sth $src1,@($slo16,$src2) */
360 unsigned char in_src1
;
361 unsigned char in_src2
;
363 struct { /* e.g. st $src1,@+$src2 */
366 unsigned char in_src1
;
367 unsigned char in_src2
;
368 unsigned char out_src2
;
370 struct { /* e.g. unlock $src1,@$src2 */
373 unsigned char in_src1
;
374 unsigned char in_src2
;
376 /* cti insns, kept separately so addr_cache is in fixed place */
379 struct { /* e.g. bc.s $disp8 */
382 struct { /* e.g. bc.l $disp24 */
385 struct { /* e.g. beq $src1,$src2,$disp16 */
389 unsigned char in_src1
;
390 unsigned char in_src2
;
392 struct { /* e.g. beqz $src2,$disp16 */
395 unsigned char in_src2
;
397 struct { /* e.g. bl.s $disp8 */
399 unsigned char out_h_gr_14
;
401 struct { /* e.g. bl.l $disp24 */
403 unsigned char out_h_gr_14
;
405 struct { /* e.g. bra.s $disp8 */
408 struct { /* e.g. bra.l $disp24 */
411 struct { /* e.g. jl $sr */
414 unsigned char out_h_gr_14
;
416 struct { /* e.g. jmp $sr */
420 struct { /* e.g. rte */
423 struct { /* e.g. trap $uimm4 */
432 /* Writeback handler. */
434 /* Pointer to argbuf entry for insn whose results need writing back. */
435 const struct argbuf
*abuf
;
437 /* x-before handler */
439 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
442 /* x-after handler */
446 /* This entry is used to terminate each pbb. */
448 /* Number of insns in pbb. */
450 /* Next pbb to execute. */
456 /* The ARGBUF struct. */
458 /* These are the baseclass definitions. */
463 /* cpu specific data follows */
466 union sem_fields fields
;
471 ??? SCACHE used to contain more than just argbuf. We could delete the
472 type entirely and always just use ARGBUF, but for future concerns and as
473 a level of abstraction it is left in. */
476 struct argbuf argbuf
;
479 /* Macros to simplify extraction, reading and semantic code.
480 These define and assign the local vars that contain the insn's fields. */
482 #define EXTRACT_IFMT_EMPTY_VARS \
483 /* Instruction fields. */ \
485 #define EXTRACT_IFMT_EMPTY_CODE \
488 #define EXTRACT_IFMT_ADD_VARS \
489 /* Instruction fields. */ \
495 #define EXTRACT_IFMT_ADD_CODE \
497 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
498 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
499 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
500 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
502 #define EXTRACT_IFMT_ADD3_VARS \
503 /* Instruction fields. */ \
510 #define EXTRACT_IFMT_ADD3_CODE \
512 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
513 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
514 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
515 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
516 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
518 #define EXTRACT_IFMT_AND3_VARS \
519 /* Instruction fields. */ \
526 #define EXTRACT_IFMT_AND3_CODE \
528 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
529 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
530 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
531 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
532 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
534 #define EXTRACT_IFMT_OR3_VARS \
535 /* Instruction fields. */ \
542 #define EXTRACT_IFMT_OR3_CODE \
544 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
545 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
546 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
547 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
548 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
550 #define EXTRACT_IFMT_ADDI_VARS \
551 /* Instruction fields. */ \
556 #define EXTRACT_IFMT_ADDI_CODE \
558 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
559 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
560 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
562 #define EXTRACT_IFMT_ADDV3_VARS \
563 /* Instruction fields. */ \
570 #define EXTRACT_IFMT_ADDV3_CODE \
572 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
573 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
574 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
575 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
576 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
578 #define EXTRACT_IFMT_BC8_VARS \
579 /* Instruction fields. */ \
584 #define EXTRACT_IFMT_BC8_CODE \
586 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
587 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
588 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
590 #define EXTRACT_IFMT_BC24_VARS \
591 /* Instruction fields. */ \
596 #define EXTRACT_IFMT_BC24_CODE \
598 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
599 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
600 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
602 #define EXTRACT_IFMT_BEQ_VARS \
603 /* Instruction fields. */ \
610 #define EXTRACT_IFMT_BEQ_CODE \
612 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
613 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
614 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
615 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
616 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
618 #define EXTRACT_IFMT_BEQZ_VARS \
619 /* Instruction fields. */ \
626 #define EXTRACT_IFMT_BEQZ_CODE \
628 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
629 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
630 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
631 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
632 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
634 #define EXTRACT_IFMT_CMP_VARS \
635 /* Instruction fields. */ \
641 #define EXTRACT_IFMT_CMP_CODE \
643 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
644 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
645 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
646 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
648 #define EXTRACT_IFMT_CMPI_VARS \
649 /* Instruction fields. */ \
656 #define EXTRACT_IFMT_CMPI_CODE \
658 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
659 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
660 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
661 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
662 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
664 #define EXTRACT_IFMT_DIV_VARS \
665 /* Instruction fields. */ \
672 #define EXTRACT_IFMT_DIV_CODE \
674 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
675 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
676 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
677 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
678 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
680 #define EXTRACT_IFMT_JL_VARS \
681 /* Instruction fields. */ \
687 #define EXTRACT_IFMT_JL_CODE \
689 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
690 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
691 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
692 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
694 #define EXTRACT_IFMT_LD24_VARS \
695 /* Instruction fields. */ \
700 #define EXTRACT_IFMT_LD24_CODE \
702 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
703 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
704 f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
706 #define EXTRACT_IFMT_LDI16_VARS \
707 /* Instruction fields. */ \
714 #define EXTRACT_IFMT_LDI16_CODE \
716 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
717 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
718 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
719 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
720 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
722 #define EXTRACT_IFMT_MVFACHI_VARS \
723 /* Instruction fields. */ \
729 #define EXTRACT_IFMT_MVFACHI_CODE \
731 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
732 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
733 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
734 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
736 #define EXTRACT_IFMT_MVFC_VARS \
737 /* Instruction fields. */ \
743 #define EXTRACT_IFMT_MVFC_CODE \
745 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
746 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
747 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
748 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
750 #define EXTRACT_IFMT_MVTACHI_VARS \
751 /* Instruction fields. */ \
757 #define EXTRACT_IFMT_MVTACHI_CODE \
759 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
760 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
761 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
762 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
764 #define EXTRACT_IFMT_MVTC_VARS \
765 /* Instruction fields. */ \
771 #define EXTRACT_IFMT_MVTC_CODE \
773 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
774 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
775 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
776 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
778 #define EXTRACT_IFMT_NOP_VARS \
779 /* Instruction fields. */ \
785 #define EXTRACT_IFMT_NOP_CODE \
787 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
788 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
789 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
790 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
792 #define EXTRACT_IFMT_SETH_VARS \
793 /* Instruction fields. */ \
800 #define EXTRACT_IFMT_SETH_CODE \
802 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
803 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
804 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
805 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
806 f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
808 #define EXTRACT_IFMT_SLLI_VARS \
809 /* Instruction fields. */ \
815 #define EXTRACT_IFMT_SLLI_CODE \
817 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
818 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
819 f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
820 f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
822 #define EXTRACT_IFMT_ST_D_VARS \
823 /* Instruction fields. */ \
830 #define EXTRACT_IFMT_ST_D_CODE \
832 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
833 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
834 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
835 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
836 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
838 #define EXTRACT_IFMT_TRAP_VARS \
839 /* Instruction fields. */ \
845 #define EXTRACT_IFMT_TRAP_CODE \
847 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
848 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
849 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
850 f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
852 /* Collection of various things for the trace handler to use. */
854 typedef struct trace_record
{
859 #endif /* CPU_M32RBF_H */