sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 #define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
  50 #define SET_H_CR(index, x) \
  51 do { \
  52 m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
  53 ;} while (0)
  54   /* accumulator */
  55   DI h_accum;
  56 #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
  57 #define SET_H_ACCUM(x) \
  58 do { \
  59 m32rbf_h_accum_set_handler (current_cpu, (x));\
  60 ;} while (0)
  61   /* condition bit */
  62   BI h_cond;
  63 #define GET_H_COND() CPU (h_cond)
  64 #define SET_H_COND(x) (CPU (h_cond) = (x))
  65   /* psw part of psw */
  66   UQI h_psw;
  67 #define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
  68 #define SET_H_PSW(x) \
  69 do { \
  70 m32rbf_h_psw_set_handler (current_cpu, (x));\
  71 ;} while (0)
  72   /* backup psw */
  73   UQI h_bpsw;
  74 #define GET_H_BPSW() CPU (h_bpsw)
  75 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  76   /* backup bpsw */
  77   UQI h_bbpsw;
  78 #define GET_H_BBPSW() CPU (h_bbpsw)
  79 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  80   /* lock */
  81   BI h_lock;
  82 #define GET_H_LOCK() CPU (h_lock)
  83 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  84   } hardware;
  85 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  86 } M32RBF_CPU_DATA;
  87
  88 /* Cover fns for register access.  */
  89 USI m32rbf_h_pc_get (SIM_CPU *);
  90 void m32rbf_h_pc_set (SIM_CPU *, USI);
  91 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  92 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  93 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  94 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  95 DI m32rbf_h_accum_get (SIM_CPU *);
  96 void m32rbf_h_accum_set (SIM_CPU *, DI);
  97 BI m32rbf_h_cond_get (SIM_CPU *);
  98 void m32rbf_h_cond_set (SIM_CPU *, BI);
  99 UQI m32rbf_h_psw_get (SIM_CPU *);
 100 void m32rbf_h_psw_set (SIM_CPU *, UQI);
 101 UQI m32rbf_h_bpsw_get (SIM_CPU *);
 102 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
 103 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
 104 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
 105 BI m32rbf_h_lock_get (SIM_CPU *);
 106 void m32rbf_h_lock_set (SIM_CPU *, BI);
 107
 108 /* These must be hand-written.  */
 109 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 110 extern CPUREG_STORE_FN m32rbf_store_register;
 111
 112 typedef struct {
 113   UINT h_gr;
 114 } MODEL_M32R_D_DATA;
 115
 116 typedef struct {
 117   int empty;
 118 } MODEL_TEST_DATA;
 119
 120 /* Instruction argument buffer.  */
 121
 122 union sem_fields {
 123   struct { /* no operands */
 124     int empty;
 125   } fmt_empty;
 126   struct { /*  */
 127     UINT f_uimm8;
 128   } sfmt_clrpsw;
 129   struct { /*  */
 130     UINT f_uimm4;
 131   } sfmt_trap;
 132   struct { /*  */
 133     IADDR i_disp24;
 134     unsigned char out_h_gr_SI_14;
 135   } sfmt_bl24;
 136   struct { /*  */
 137     IADDR i_disp8;
 138     unsigned char out_h_gr_SI_14;
 139   } sfmt_bl8;
 140   struct { /*  */
 141     SI* i_dr;
 142     UINT f_hi16;
 143     UINT f_r1;
 144     unsigned char out_dr;
 145   } sfmt_seth;
 146   struct { /*  */
 147     ADDR i_uimm24;
 148     SI* i_dr;
 149     UINT f_r1;
 150     unsigned char out_dr;
 151   } sfmt_ld24;
 152   struct { /*  */
 153     SI* i_sr;
 154     UINT f_r2;
 155     unsigned char in_sr;
 156     unsigned char out_h_gr_SI_14;
 157   } sfmt_jl;
 158   struct { /*  */
 159     SI* i_sr;
 160     INT f_simm16;
 161     UINT f_r2;
 162     UINT f_uimm3;
 163     unsigned char in_sr;
 164   } sfmt_bset;
 165   struct { /*  */
 166     SI* i_dr;
 167     UINT f_r1;
 168     UINT f_uimm5;
 169     unsigned char in_dr;
 170     unsigned char out_dr;
 171   } sfmt_slli;
 172   struct { /*  */
 173     SI* i_dr;
 174     INT f_simm8;
 175     UINT f_r1;
 176     unsigned char in_dr;
 177     unsigned char out_dr;
 178   } sfmt_addi;
 179   struct { /*  */
 180     SI* i_src1;
 181     SI* i_src2;
 182     UINT f_r1;
 183     UINT f_r2;
 184     unsigned char in_src1;
 185     unsigned char in_src2;
 186     unsigned char out_src2;
 187   } sfmt_st_plus;
 188   struct { /*  */
 189     SI* i_src1;
 190     SI* i_src2;
 191     INT f_simm16;
 192     UINT f_r1;
 193     UINT f_r2;
 194     unsigned char in_src1;
 195     unsigned char in_src2;
 196   } sfmt_st_d;
 197   struct { /*  */
 198     SI* i_dr;
 199     SI* i_sr;
 200     UINT f_r1;
 201     UINT f_r2;
 202     unsigned char in_sr;
 203     unsigned char out_dr;
 204     unsigned char out_sr;
 205   } sfmt_ld_plus;
 206   struct { /*  */
 207     IADDR i_disp16;
 208     SI* i_src1;
 209     SI* i_src2;
 210     UINT f_r1;
 211     UINT f_r2;
 212     unsigned char in_src1;
 213     unsigned char in_src2;
 214   } sfmt_beq;
 215   struct { /*  */
 216     SI* i_dr;
 217     SI* i_sr;
 218     UINT f_r1;
 219     UINT f_r2;
 220     UINT f_uimm16;
 221     unsigned char in_sr;
 222     unsigned char out_dr;
 223   } sfmt_and3;
 224   struct { /*  */
 225     SI* i_dr;
 226     SI* i_sr;
 227     INT f_simm16;
 228     UINT f_r1;
 229     UINT f_r2;
 230     unsigned char in_sr;
 231     unsigned char out_dr;
 232   } sfmt_add3;
 233   struct { /*  */
 234     SI* i_dr;
 235     SI* i_sr;
 236     UINT f_r1;
 237     UINT f_r2;
 238     unsigned char in_dr;
 239     unsigned char in_sr;
 240     unsigned char out_dr;
 241   } sfmt_add;
 242 #if WITH_SCACHE_PBB
 243   /* Writeback handler.  */
 244   struct {
 245     /* Pointer to argbuf entry for insn whose results need writing back.  */
 246     const struct argbuf *abuf;
 247   } write;
 248   /* x-before handler */
 249   struct {
 250     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 251     int first_p;
 252   } before;
 253   /* x-after handler */
 254   struct {
 255     int empty;
 256   } after;
 257   /* This entry is used to terminate each pbb.  */
 258   struct {
 259     /* Number of insns in pbb.  */
 260     int insn_count;
 261     /* Next pbb to execute.  */
 262     SCACHE *next;
 263     SCACHE *branch_target;
 264   } chain;
 265 #endif
 266 };
 267
 268 /* The ARGBUF struct.  */
 269 struct argbuf {
 270   /* These are the baseclass definitions.  */
 271   IADDR addr;
 272   const IDESC *idesc;
 273   char trace_p;
 274   char profile_p;
 275   /* ??? Temporary hack for skip insns.  */
 276   char skip_count;
 277   char unused;
 278   /* cpu specific data follows */
 279   union sem semantic;
 280   int written;
 281   union sem_fields fields;
 282 };
 283
 284 /* A cached insn.
 285
 286    ??? SCACHE used to contain more than just argbuf.  We could delete the
 287    type entirely and always just use ARGBUF, but for future concerns and as
 288    a level of abstraction it is left in.  */
 289
 290 struct scache {
 291   struct argbuf argbuf;
 292 };
 293
 294 /* Macros to simplify extraction, reading and semantic code.
 295    These define and assign the local vars that contain the insn's fields.  */
 296
 297 #define EXTRACT_IFMT_EMPTY_VARS \
 298   unsigned int length;
 299 #define EXTRACT_IFMT_EMPTY_CODE \
 300   length = 0; \
 301
 302 #define EXTRACT_IFMT_ADD_VARS \
 303   UINT f_op1; \
 304   UINT f_r1; \
 305   UINT f_op2; \
 306   UINT f_r2; \
 307   unsigned int length;
 308 #define EXTRACT_IFMT_ADD_CODE \
 309   length = 2; \
 310   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 311   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 312   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 313   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 314
 315 #define EXTRACT_IFMT_ADD3_VARS \
 316   UINT f_op1; \
 317   UINT f_r1; \
 318   UINT f_op2; \
 319   UINT f_r2; \
 320   INT f_simm16; \
 321   unsigned int length;
 322 #define EXTRACT_IFMT_ADD3_CODE \
 323   length = 4; \
 324   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 325   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 326   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 327   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 328   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 329
 330 #define EXTRACT_IFMT_AND3_VARS \
 331   UINT f_op1; \
 332   UINT f_r1; \
 333   UINT f_op2; \
 334   UINT f_r2; \
 335   UINT f_uimm16; \
 336   unsigned int length;
 337 #define EXTRACT_IFMT_AND3_CODE \
 338   length = 4; \
 339   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 340   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 341   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 342   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 343   f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 344
 345 #define EXTRACT_IFMT_OR3_VARS \
 346   UINT f_op1; \
 347   UINT f_r1; \
 348   UINT f_op2; \
 349   UINT f_r2; \
 350   UINT f_uimm16; \
 351   unsigned int length;
 352 #define EXTRACT_IFMT_OR3_CODE \
 353   length = 4; \
 354   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 355   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 356   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 357   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 358   f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 359
 360 #define EXTRACT_IFMT_ADDI_VARS \
 361   UINT f_op1; \
 362   UINT f_r1; \
 363   INT f_simm8; \
 364   unsigned int length;
 365 #define EXTRACT_IFMT_ADDI_CODE \
 366   length = 2; \
 367   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 368   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 369   f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
 370
 371 #define EXTRACT_IFMT_ADDV3_VARS \
 372   UINT f_op1; \
 373   UINT f_r1; \
 374   UINT f_op2; \
 375   UINT f_r2; \
 376   INT f_simm16; \
 377   unsigned int length;
 378 #define EXTRACT_IFMT_ADDV3_CODE \
 379   length = 4; \
 380   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 381   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 382   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 383   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 384   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 385
 386 #define EXTRACT_IFMT_BC8_VARS \
 387   UINT f_op1; \
 388   UINT f_r1; \
 389   SI f_disp8; \
 390   unsigned int length;
 391 #define EXTRACT_IFMT_BC8_CODE \
 392   length = 2; \
 393   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 394   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 395   f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 396
 397 #define EXTRACT_IFMT_BC24_VARS \
 398   UINT f_op1; \
 399   UINT f_r1; \
 400   SI f_disp24; \
 401   unsigned int length;
 402 #define EXTRACT_IFMT_BC24_CODE \
 403   length = 4; \
 404   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 405   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 406   f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 407
 408 #define EXTRACT_IFMT_BEQ_VARS \
 409   UINT f_op1; \
 410   UINT f_r1; \
 411   UINT f_op2; \
 412   UINT f_r2; \
 413   SI f_disp16; \
 414   unsigned int length;
 415 #define EXTRACT_IFMT_BEQ_CODE \
 416   length = 4; \
 417   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 418   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 419   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 420   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 421   f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 422
 423 #define EXTRACT_IFMT_BEQZ_VARS \
 424   UINT f_op1; \
 425   UINT f_r1; \
 426   UINT f_op2; \
 427   UINT f_r2; \
 428   SI f_disp16; \
 429   unsigned int length;
 430 #define EXTRACT_IFMT_BEQZ_CODE \
 431   length = 4; \
 432   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 433   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 434   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 435   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 436   f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 437
 438 #define EXTRACT_IFMT_CMP_VARS \
 439   UINT f_op1; \
 440   UINT f_r1; \
 441   UINT f_op2; \
 442   UINT f_r2; \
 443   unsigned int length;
 444 #define EXTRACT_IFMT_CMP_CODE \
 445   length = 2; \
 446   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 447   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 448   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 449   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 450
 451 #define EXTRACT_IFMT_CMPI_VARS \
 452   UINT f_op1; \
 453   UINT f_r1; \
 454   UINT f_op2; \
 455   UINT f_r2; \
 456   INT f_simm16; \
 457   unsigned int length;
 458 #define EXTRACT_IFMT_CMPI_CODE \
 459   length = 4; \
 460   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 461   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 462   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 463   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 464   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 465
 466 #define EXTRACT_IFMT_DIV_VARS \
 467   UINT f_op1; \
 468   UINT f_r1; \
 469   UINT f_op2; \
 470   UINT f_r2; \
 471   INT f_simm16; \
 472   unsigned int length;
 473 #define EXTRACT_IFMT_DIV_CODE \
 474   length = 4; \
 475   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 476   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 477   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 478   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 479   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 480
 481 #define EXTRACT_IFMT_JL_VARS \
 482   UINT f_op1; \
 483   UINT f_r1; \
 484   UINT f_op2; \
 485   UINT f_r2; \
 486   unsigned int length;
 487 #define EXTRACT_IFMT_JL_CODE \
 488   length = 2; \
 489   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 490   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 491   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 492   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 493
 494 #define EXTRACT_IFMT_LD24_VARS \
 495   UINT f_op1; \
 496   UINT f_r1; \
 497   UINT f_uimm24; \
 498   unsigned int length;
 499 #define EXTRACT_IFMT_LD24_CODE \
 500   length = 4; \
 501   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 502   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 503   f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
 504
 505 #define EXTRACT_IFMT_LDI16_VARS \
 506   UINT f_op1; \
 507   UINT f_r1; \
 508   UINT f_op2; \
 509   UINT f_r2; \
 510   INT f_simm16; \
 511   unsigned int length;
 512 #define EXTRACT_IFMT_LDI16_CODE \
 513   length = 4; \
 514   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 515   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 516   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 517   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 518   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 519
 520 #define EXTRACT_IFMT_MVFACHI_VARS \
 521   UINT f_op1; \
 522   UINT f_r1; \
 523   UINT f_op2; \
 524   UINT f_r2; \
 525   unsigned int length;
 526 #define EXTRACT_IFMT_MVFACHI_CODE \
 527   length = 2; \
 528   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 529   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 530   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 531   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 532
 533 #define EXTRACT_IFMT_MVFC_VARS \
 534   UINT f_op1; \
 535   UINT f_r1; \
 536   UINT f_op2; \
 537   UINT f_r2; \
 538   unsigned int length;
 539 #define EXTRACT_IFMT_MVFC_CODE \
 540   length = 2; \
 541   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 542   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 543   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 544   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 545
 546 #define EXTRACT_IFMT_MVTACHI_VARS \
 547   UINT f_op1; \
 548   UINT f_r1; \
 549   UINT f_op2; \
 550   UINT f_r2; \
 551   unsigned int length;
 552 #define EXTRACT_IFMT_MVTACHI_CODE \
 553   length = 2; \
 554   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 555   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 556   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 557   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 558
 559 #define EXTRACT_IFMT_MVTC_VARS \
 560   UINT f_op1; \
 561   UINT f_r1; \
 562   UINT f_op2; \
 563   UINT f_r2; \
 564   unsigned int length;
 565 #define EXTRACT_IFMT_MVTC_CODE \
 566   length = 2; \
 567   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 568   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 569   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 570   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 571
 572 #define EXTRACT_IFMT_NOP_VARS \
 573   UINT f_op1; \
 574   UINT f_r1; \
 575   UINT f_op2; \
 576   UINT f_r2; \
 577   unsigned int length;
 578 #define EXTRACT_IFMT_NOP_CODE \
 579   length = 2; \
 580   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 581   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 582   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 583   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 584
 585 #define EXTRACT_IFMT_SETH_VARS \
 586   UINT f_op1; \
 587   UINT f_r1; \
 588   UINT f_op2; \
 589   UINT f_r2; \
 590   UINT f_hi16; \
 591   unsigned int length;
 592 #define EXTRACT_IFMT_SETH_CODE \
 593   length = 4; \
 594   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 595   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 596   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 597   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 598   f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
 599
 600 #define EXTRACT_IFMT_SLLI_VARS \
 601   UINT f_op1; \
 602   UINT f_r1; \
 603   UINT f_shift_op2; \
 604   UINT f_uimm5; \
 605   unsigned int length;
 606 #define EXTRACT_IFMT_SLLI_CODE \
 607   length = 2; \
 608   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 609   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 610   f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
 611   f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
 612
 613 #define EXTRACT_IFMT_ST_D_VARS \
 614   UINT f_op1; \
 615   UINT f_r1; \
 616   UINT f_op2; \
 617   UINT f_r2; \
 618   INT f_simm16; \
 619   unsigned int length;
 620 #define EXTRACT_IFMT_ST_D_CODE \
 621   length = 4; \
 622   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 623   f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
 624   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 625   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 626   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 627
 628 #define EXTRACT_IFMT_TRAP_VARS \
 629   UINT f_op1; \
 630   UINT f_r1; \
 631   UINT f_op2; \
 632   UINT f_uimm4; \
 633   unsigned int length;
 634 #define EXTRACT_IFMT_TRAP_CODE \
 635   length = 2; \
 636   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 637   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 638   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 639   f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 640
 641 #define EXTRACT_IFMT_CLRPSW_VARS \
 642   UINT f_op1; \
 643   UINT f_r1; \
 644   UINT f_uimm8; \
 645   unsigned int length;
 646 #define EXTRACT_IFMT_CLRPSW_CODE \
 647   length = 2; \
 648   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 649   f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
 650   f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
 651
 652 #define EXTRACT_IFMT_BSET_VARS \
 653   UINT f_op1; \
 654   UINT f_bit4; \
 655   UINT f_uimm3; \
 656   UINT f_op2; \
 657   UINT f_r2; \
 658   INT f_simm16; \
 659   unsigned int length;
 660 #define EXTRACT_IFMT_BSET_CODE \
 661   length = 4; \
 662   f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
 663   f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
 664   f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
 665   f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
 666   f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
 667   f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
 668
 669 #define EXTRACT_IFMT_BTST_VARS \
 670   UINT f_op1; \
 671   UINT f_bit4; \
 672   UINT f_uimm3; \
 673   UINT f_op2; \
 674   UINT f_r2; \
 675   unsigned int length;
 676 #define EXTRACT_IFMT_BTST_CODE \
 677   length = 2; \
 678   f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
 679   f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
 680   f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
 681   f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
 682   f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
 683
 684 /* Collection of various things for the trace handler to use.  */
 685
 686 typedef struct trace_record {
 687   IADDR pc;
 688   /* FIXME:wip */
 689 } TRACE_RECORD;
 690
 691 #endif /* CPU_M32RBF_H */