1 /* CPU family header for m32rbf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 1
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 /* GET_H_CR macro user-written */
50 /* SET_H_CR macro user-written */
53 /* GET_H_ACCUM macro user-written */
54 /* SET_H_ACCUM macro user-written */
57 #define GET_H_COND() CPU (h_cond)
58 #define SET_H_COND(x) (CPU (h_cond) = (x))
61 /* GET_H_PSW macro user-written */
62 /* SET_H_PSW macro user-written */
65 #define GET_H_BPSW() CPU (h_bpsw)
66 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
69 #define GET_H_BBPSW() CPU (h_bbpsw)
70 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
73 #define GET_H_LOCK() CPU (h_lock)
74 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
76 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
79 /* Cover fns for register access. */
80 USI
m32rbf_h_pc_get (SIM_CPU
*);
81 void m32rbf_h_pc_set (SIM_CPU
*, USI
);
82 SI
m32rbf_h_gr_get (SIM_CPU
*, UINT
);
83 void m32rbf_h_gr_set (SIM_CPU
*, UINT
, SI
);
84 USI
m32rbf_h_cr_get (SIM_CPU
*, UINT
);
85 void m32rbf_h_cr_set (SIM_CPU
*, UINT
, USI
);
86 DI
m32rbf_h_accum_get (SIM_CPU
*);
87 void m32rbf_h_accum_set (SIM_CPU
*, DI
);
88 DI
m32rbf_h_accums_get (SIM_CPU
*, UINT
);
89 void m32rbf_h_accums_set (SIM_CPU
*, UINT
, DI
);
90 BI
m32rbf_h_cond_get (SIM_CPU
*);
91 void m32rbf_h_cond_set (SIM_CPU
*, BI
);
92 UQI
m32rbf_h_psw_get (SIM_CPU
*);
93 void m32rbf_h_psw_set (SIM_CPU
*, UQI
);
94 UQI
m32rbf_h_bpsw_get (SIM_CPU
*);
95 void m32rbf_h_bpsw_set (SIM_CPU
*, UQI
);
96 UQI
m32rbf_h_bbpsw_get (SIM_CPU
*);
97 void m32rbf_h_bbpsw_set (SIM_CPU
*, UQI
);
98 BI
m32rbf_h_lock_get (SIM_CPU
*);
99 void m32rbf_h_lock_set (SIM_CPU
*, BI
);
101 /* These must be hand-written. */
102 extern CPUREG_FETCH_FN m32rbf_fetch_register
;
103 extern CPUREG_STORE_FN m32rbf_store_register
;
114 struct { /* empty sformat for unspecified field list */
117 struct { /* e.g. add $dr,$sr */
122 unsigned char out_dr
;
124 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
129 unsigned char out_dr
;
131 struct { /* e.g. and3 $dr,$sr,$uimm16 */
136 unsigned char out_dr
;
138 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
143 unsigned char out_dr
;
145 struct { /* e.g. addi $dr,$simm8 */
149 unsigned char out_dr
;
151 struct { /* e.g. addv $dr,$sr */
156 unsigned char out_dr
;
158 struct { /* e.g. addv3 $dr,$sr,$simm16 */
163 unsigned char out_dr
;
165 struct { /* e.g. addx $dr,$sr */
170 unsigned char out_dr
;
172 struct { /* e.g. cmp $src1,$src2 */
175 unsigned char in_src1
;
176 unsigned char in_src2
;
178 struct { /* e.g. cmpi $src2,$simm16 */
181 unsigned char in_src2
;
183 struct { /* e.g. div $dr,$sr */
188 unsigned char out_dr
;
190 struct { /* e.g. ld $dr,@$sr */
194 unsigned char out_dr
;
196 struct { /* e.g. ld $dr,@($slo16,$sr) */
201 unsigned char out_dr
;
203 struct { /* e.g. ldb $dr,@$sr */
207 unsigned char out_dr
;
209 struct { /* e.g. ldb $dr,@($slo16,$sr) */
214 unsigned char out_dr
;
216 struct { /* e.g. ldh $dr,@$sr */
220 unsigned char out_dr
;
222 struct { /* e.g. ldh $dr,@($slo16,$sr) */
227 unsigned char out_dr
;
229 struct { /* e.g. ld $dr,@$sr+ */
233 unsigned char out_dr
;
234 unsigned char out_sr
;
236 struct { /* e.g. ld24 $dr,$uimm24 */
239 unsigned char out_dr
;
241 struct { /* e.g. ldi8 $dr,$simm8 */
244 unsigned char out_dr
;
246 struct { /* e.g. ldi16 $dr,$hash$slo16 */
249 unsigned char out_dr
;
251 struct { /* e.g. lock $dr,@$sr */
255 unsigned char out_dr
;
257 struct { /* e.g. machi $src1,$src2 */
260 unsigned char in_src1
;
261 unsigned char in_src2
;
263 struct { /* e.g. mulhi $src1,$src2 */
266 unsigned char in_src1
;
267 unsigned char in_src2
;
269 struct { /* e.g. mv $dr,$sr */
273 unsigned char out_dr
;
275 struct { /* e.g. mvfachi $dr */
277 unsigned char out_dr
;
279 struct { /* e.g. mvfc $dr,$scr */
282 unsigned char out_dr
;
284 struct { /* e.g. mvtachi $src1 */
286 unsigned char in_src1
;
288 struct { /* e.g. mvtc $sr,$dcr */
293 struct { /* e.g. nop */
296 struct { /* e.g. rac */
299 struct { /* e.g. seth $dr,$hash$hi16 */
302 unsigned char out_dr
;
304 struct { /* e.g. sll3 $dr,$sr,$simm16 */
309 unsigned char out_dr
;
311 struct { /* e.g. slli $dr,$uimm5 */
315 unsigned char out_dr
;
317 struct { /* e.g. st $src1,@$src2 */
320 unsigned char in_src1
;
321 unsigned char in_src2
;
323 struct { /* e.g. st $src1,@($slo16,$src2) */
327 unsigned char in_src1
;
328 unsigned char in_src2
;
330 struct { /* e.g. stb $src1,@$src2 */
333 unsigned char in_src1
;
334 unsigned char in_src2
;
336 struct { /* e.g. stb $src1,@($slo16,$src2) */
340 unsigned char in_src1
;
341 unsigned char in_src2
;
343 struct { /* e.g. sth $src1,@$src2 */
346 unsigned char in_src1
;
347 unsigned char in_src2
;
349 struct { /* e.g. sth $src1,@($slo16,$src2) */
353 unsigned char in_src1
;
354 unsigned char in_src2
;
356 struct { /* e.g. st $src1,@+$src2 */
359 unsigned char in_src1
;
360 unsigned char in_src2
;
361 unsigned char out_src2
;
363 struct { /* e.g. unlock $src1,@$src2 */
366 unsigned char in_src1
;
367 unsigned char in_src2
;
369 /* cti insns, kept separately so addr_cache is in fixed place */
372 struct { /* e.g. bc.s $disp8 */
375 struct { /* e.g. bc.l $disp24 */
378 struct { /* e.g. beq $src1,$src2,$disp16 */
382 unsigned char in_src1
;
383 unsigned char in_src2
;
385 struct { /* e.g. beqz $src2,$disp16 */
388 unsigned char in_src2
;
390 struct { /* e.g. bl.s $disp8 */
392 unsigned char out_h_gr_14
;
394 struct { /* e.g. bl.l $disp24 */
396 unsigned char out_h_gr_14
;
398 struct { /* e.g. bra.s $disp8 */
401 struct { /* e.g. bra.l $disp24 */
404 struct { /* e.g. jl $sr */
407 unsigned char out_h_gr_14
;
409 struct { /* e.g. jmp $sr */
413 struct { /* e.g. rte */
416 struct { /* e.g. trap $uimm4 */
425 /* Writeback handler. */
427 /* Pointer to argbuf entry for insn whose results need writing back. */
428 const struct argbuf
*abuf
;
430 /* x-before handler */
432 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
435 /* x-after handler */
439 /* This entry is used to terminate each pbb. */
441 /* Number of insns in pbb. */
443 /* Next pbb to execute. */
449 /* The ARGBUF struct. */
451 /* These are the baseclass definitions. */
456 /* cpu specific data follows */
459 union sem_fields fields
;
464 ??? SCACHE used to contain more than just argbuf. We could delete the
465 type entirely and always just use ARGBUF, but for future concerns and as
466 a level of abstraction it is left in. */
469 struct argbuf argbuf
;
472 /* Macros to simplify extraction, reading and semantic code.
473 These define and assign the local vars that contain the insn's fields. */
475 #define EXTRACT_IFMT_EMPTY_VARS \
476 /* Instruction fields. */ \
478 #define EXTRACT_IFMT_EMPTY_CODE \
481 #define EXTRACT_IFMT_ADD_VARS \
482 /* Instruction fields. */ \
488 #define EXTRACT_IFMT_ADD_CODE \
490 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
491 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
492 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
493 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
495 #define EXTRACT_IFMT_ADD3_VARS \
496 /* Instruction fields. */ \
503 #define EXTRACT_IFMT_ADD3_CODE \
505 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
506 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
507 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
508 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
509 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
511 #define EXTRACT_IFMT_AND3_VARS \
512 /* Instruction fields. */ \
519 #define EXTRACT_IFMT_AND3_CODE \
521 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
522 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
523 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
524 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
525 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
527 #define EXTRACT_IFMT_OR3_VARS \
528 /* Instruction fields. */ \
535 #define EXTRACT_IFMT_OR3_CODE \
537 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
538 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
539 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
540 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
541 f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
543 #define EXTRACT_IFMT_ADDI_VARS \
544 /* Instruction fields. */ \
549 #define EXTRACT_IFMT_ADDI_CODE \
551 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
552 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
553 f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
555 #define EXTRACT_IFMT_ADDV3_VARS \
556 /* Instruction fields. */ \
563 #define EXTRACT_IFMT_ADDV3_CODE \
565 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
566 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
567 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
568 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
569 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
571 #define EXTRACT_IFMT_BC8_VARS \
572 /* Instruction fields. */ \
577 #define EXTRACT_IFMT_BC8_CODE \
579 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
580 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
581 f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
583 #define EXTRACT_IFMT_BC24_VARS \
584 /* Instruction fields. */ \
589 #define EXTRACT_IFMT_BC24_CODE \
591 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
592 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
593 f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
595 #define EXTRACT_IFMT_BEQ_VARS \
596 /* Instruction fields. */ \
603 #define EXTRACT_IFMT_BEQ_CODE \
605 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
606 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
607 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
608 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
609 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
611 #define EXTRACT_IFMT_BEQZ_VARS \
612 /* Instruction fields. */ \
619 #define EXTRACT_IFMT_BEQZ_CODE \
621 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
622 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
623 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
624 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
625 f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
627 #define EXTRACT_IFMT_CMP_VARS \
628 /* Instruction fields. */ \
634 #define EXTRACT_IFMT_CMP_CODE \
636 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
637 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
638 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
639 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
641 #define EXTRACT_IFMT_CMPI_VARS \
642 /* Instruction fields. */ \
649 #define EXTRACT_IFMT_CMPI_CODE \
651 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
652 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
653 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
654 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
655 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
657 #define EXTRACT_IFMT_DIV_VARS \
658 /* Instruction fields. */ \
665 #define EXTRACT_IFMT_DIV_CODE \
667 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
668 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
669 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
670 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
671 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
673 #define EXTRACT_IFMT_JL_VARS \
674 /* Instruction fields. */ \
680 #define EXTRACT_IFMT_JL_CODE \
682 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
683 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
684 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
685 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
687 #define EXTRACT_IFMT_LD24_VARS \
688 /* Instruction fields. */ \
693 #define EXTRACT_IFMT_LD24_CODE \
695 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
696 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
697 f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
699 #define EXTRACT_IFMT_LDI16_VARS \
700 /* Instruction fields. */ \
707 #define EXTRACT_IFMT_LDI16_CODE \
709 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
710 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
711 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
712 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
713 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
715 #define EXTRACT_IFMT_MVFACHI_VARS \
716 /* Instruction fields. */ \
722 #define EXTRACT_IFMT_MVFACHI_CODE \
724 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
725 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
726 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
727 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
729 #define EXTRACT_IFMT_MVFC_VARS \
730 /* Instruction fields. */ \
736 #define EXTRACT_IFMT_MVFC_CODE \
738 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
739 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
740 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
741 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
743 #define EXTRACT_IFMT_MVTACHI_VARS \
744 /* Instruction fields. */ \
750 #define EXTRACT_IFMT_MVTACHI_CODE \
752 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
753 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
754 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
755 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
757 #define EXTRACT_IFMT_MVTC_VARS \
758 /* Instruction fields. */ \
764 #define EXTRACT_IFMT_MVTC_CODE \
766 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
767 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
768 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
769 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
771 #define EXTRACT_IFMT_NOP_VARS \
772 /* Instruction fields. */ \
778 #define EXTRACT_IFMT_NOP_CODE \
780 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
781 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
782 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
783 f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
785 #define EXTRACT_IFMT_SETH_VARS \
786 /* Instruction fields. */ \
793 #define EXTRACT_IFMT_SETH_CODE \
795 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
796 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
797 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
798 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
799 f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
801 #define EXTRACT_IFMT_SLLI_VARS \
802 /* Instruction fields. */ \
808 #define EXTRACT_IFMT_SLLI_CODE \
810 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
811 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
812 f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
813 f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
815 #define EXTRACT_IFMT_ST_D_VARS \
816 /* Instruction fields. */ \
823 #define EXTRACT_IFMT_ST_D_CODE \
825 f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
826 f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
827 f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
828 f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
829 f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
831 #define EXTRACT_IFMT_TRAP_VARS \
832 /* Instruction fields. */ \
838 #define EXTRACT_IFMT_TRAP_CODE \
840 f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
841 f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
842 f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
843 f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
845 /* Collection of various things for the trace handler to use. */
847 typedef struct trace_record
{
852 #endif /* CPU_M32RBF_H */