1 /* CPU family header for m32rbf.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
7 This file is part of the GNU Simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 1
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 #define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
50 #define SET_H_CR(index, x) \
52 m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
56 #define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
57 #define SET_H_ACCUM(x) \
59 m32rbf_h_accum_set_handler (current_cpu, (x));\
63 #define GET_H_COND() CPU (h_cond)
64 #define SET_H_COND(x) (CPU (h_cond) = (x))
67 #define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
68 #define SET_H_PSW(x) \
70 m32rbf_h_psw_set_handler (current_cpu, (x));\
74 #define GET_H_BPSW() CPU (h_bpsw)
75 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
78 #define GET_H_BBPSW() CPU (h_bbpsw)
79 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
82 #define GET_H_LOCK() CPU (h_lock)
83 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
85 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
88 /* Cover fns for register access. */
89 USI
m32rbf_h_pc_get (SIM_CPU
*);
90 void m32rbf_h_pc_set (SIM_CPU
*, USI
);
91 SI
m32rbf_h_gr_get (SIM_CPU
*, UINT
);
92 void m32rbf_h_gr_set (SIM_CPU
*, UINT
, SI
);
93 USI
m32rbf_h_cr_get (SIM_CPU
*, UINT
);
94 void m32rbf_h_cr_set (SIM_CPU
*, UINT
, USI
);
95 DI
m32rbf_h_accum_get (SIM_CPU
*);
96 void m32rbf_h_accum_set (SIM_CPU
*, DI
);
97 BI
m32rbf_h_cond_get (SIM_CPU
*);
98 void m32rbf_h_cond_set (SIM_CPU
*, BI
);
99 UQI
m32rbf_h_psw_get (SIM_CPU
*);
100 void m32rbf_h_psw_set (SIM_CPU
*, UQI
);
101 UQI
m32rbf_h_bpsw_get (SIM_CPU
*);
102 void m32rbf_h_bpsw_set (SIM_CPU
*, UQI
);
103 UQI
m32rbf_h_bbpsw_get (SIM_CPU
*);
104 void m32rbf_h_bbpsw_set (SIM_CPU
*, UQI
);
105 BI
m32rbf_h_lock_get (SIM_CPU
*);
106 void m32rbf_h_lock_set (SIM_CPU
*, BI
);
108 /* These must be hand-written. */
109 extern CPUREG_FETCH_FN m32rbf_fetch_register
;
110 extern CPUREG_STORE_FN m32rbf_store_register
;
120 /* Instruction argument buffer. */
123 struct { /* no operands */
131 unsigned char out_h_gr_14
;
135 unsigned char out_h_gr_14
;
141 unsigned char out_dr
;
147 unsigned char out_dr
;
153 unsigned char out_h_gr_14
;
160 unsigned char out_dr
;
167 unsigned char out_dr
;
174 unsigned char in_src1
;
175 unsigned char in_src2
;
176 unsigned char out_src2
;
184 unsigned char in_src1
;
185 unsigned char in_src2
;
193 unsigned char out_dr
;
194 unsigned char out_sr
;
202 unsigned char in_src1
;
203 unsigned char in_src2
;
212 unsigned char out_dr
;
221 unsigned char out_dr
;
230 unsigned char out_dr
;
233 /* Writeback handler. */
235 /* Pointer to argbuf entry for insn whose results need writing back. */
236 const struct argbuf
*abuf
;
238 /* x-before handler */
240 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
243 /* x-after handler */
247 /* This entry is used to terminate each pbb. */
249 /* Number of insns in pbb. */
251 /* Next pbb to execute. */
253 SCACHE
*branch_target
;
258 /* The ARGBUF struct. */
260 /* These are the baseclass definitions. */
265 /* ??? Temporary hack for skip insns. */
268 /* cpu specific data follows */
271 union sem_fields fields
;
276 ??? SCACHE used to contain more than just argbuf. We could delete the
277 type entirely and always just use ARGBUF, but for future concerns and as
278 a level of abstraction it is left in. */
281 struct argbuf argbuf
;
284 /* Macros to simplify extraction, reading and semantic code.
285 These define and assign the local vars that contain the insn's fields. */
287 #define EXTRACT_IFMT_EMPTY_VARS \
289 #define EXTRACT_IFMT_EMPTY_CODE \
292 #define EXTRACT_IFMT_ADD_VARS \
298 #define EXTRACT_IFMT_ADD_CODE \
300 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
301 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
302 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
303 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
305 #define EXTRACT_IFMT_ADD3_VARS \
312 #define EXTRACT_IFMT_ADD3_CODE \
314 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
315 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
316 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
317 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
318 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
320 #define EXTRACT_IFMT_AND3_VARS \
327 #define EXTRACT_IFMT_AND3_CODE \
329 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
330 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
331 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
332 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
333 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
335 #define EXTRACT_IFMT_OR3_VARS \
342 #define EXTRACT_IFMT_OR3_CODE \
344 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
345 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
346 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
347 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
348 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
350 #define EXTRACT_IFMT_ADDI_VARS \
355 #define EXTRACT_IFMT_ADDI_CODE \
357 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
358 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
359 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
361 #define EXTRACT_IFMT_ADDV3_VARS \
368 #define EXTRACT_IFMT_ADDV3_CODE \
370 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
371 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
372 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
373 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
374 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
376 #define EXTRACT_IFMT_BC8_VARS \
381 #define EXTRACT_IFMT_BC8_CODE \
383 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
384 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
385 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
387 #define EXTRACT_IFMT_BC24_VARS \
392 #define EXTRACT_IFMT_BC24_CODE \
394 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
395 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
396 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
398 #define EXTRACT_IFMT_BEQ_VARS \
405 #define EXTRACT_IFMT_BEQ_CODE \
407 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
408 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
409 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
410 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
411 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
413 #define EXTRACT_IFMT_BEQZ_VARS \
420 #define EXTRACT_IFMT_BEQZ_CODE \
422 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
423 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
424 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
425 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
426 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
428 #define EXTRACT_IFMT_CMP_VARS \
434 #define EXTRACT_IFMT_CMP_CODE \
436 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
437 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
438 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
439 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
441 #define EXTRACT_IFMT_CMPI_VARS \
448 #define EXTRACT_IFMT_CMPI_CODE \
450 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
451 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
452 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
453 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
454 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
456 #define EXTRACT_IFMT_DIV_VARS \
463 #define EXTRACT_IFMT_DIV_CODE \
465 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
466 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
467 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
468 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
469 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
471 #define EXTRACT_IFMT_JL_VARS \
477 #define EXTRACT_IFMT_JL_CODE \
479 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
480 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
481 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
482 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
484 #define EXTRACT_IFMT_LD24_VARS \
489 #define EXTRACT_IFMT_LD24_CODE \
491 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
492 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
493 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
495 #define EXTRACT_IFMT_LDI16_VARS \
502 #define EXTRACT_IFMT_LDI16_CODE \
504 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
505 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
506 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
507 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
508 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
510 #define EXTRACT_IFMT_MVFACHI_VARS \
516 #define EXTRACT_IFMT_MVFACHI_CODE \
518 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
519 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
520 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
521 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
523 #define EXTRACT_IFMT_MVFC_VARS \
529 #define EXTRACT_IFMT_MVFC_CODE \
531 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
532 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
533 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
534 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
536 #define EXTRACT_IFMT_MVTACHI_VARS \
542 #define EXTRACT_IFMT_MVTACHI_CODE \
544 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
545 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
546 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
547 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
549 #define EXTRACT_IFMT_MVTC_VARS \
555 #define EXTRACT_IFMT_MVTC_CODE \
557 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
558 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
559 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
560 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
562 #define EXTRACT_IFMT_NOP_VARS \
568 #define EXTRACT_IFMT_NOP_CODE \
570 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
571 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
572 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
573 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
575 #define EXTRACT_IFMT_SETH_VARS \
582 #define EXTRACT_IFMT_SETH_CODE \
584 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
585 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
586 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
587 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
588 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
590 #define EXTRACT_IFMT_SLLI_VARS \
596 #define EXTRACT_IFMT_SLLI_CODE \
598 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
599 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
600 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
601 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
603 #define EXTRACT_IFMT_ST_D_VARS \
610 #define EXTRACT_IFMT_ST_D_CODE \
612 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
613 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
614 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
615 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
616 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
618 #define EXTRACT_IFMT_TRAP_VARS \
624 #define EXTRACT_IFMT_TRAP_CODE \
626 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
627 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
628 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
629 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
631 /* Collection of various things for the trace handler to use. */
633 typedef struct trace_record
{
638 #endif /* CPU_M32RBF_H */