1 /* CPU family header for m32r2f.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
7 This file is part of the GNU simulators.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
28 /* Maximum number of instructions that are fetched at a time.
29 This is for LIW type instructions sets (e.g. m32r). */
30 #define MAX_LIW_INSNS 2
32 /* Maximum number of instructions that can be executed in parallel. */
33 #define MAX_PARALLEL_INSNS 2
35 /* CPU state information. */
37 /* Hardware elements. */
41 #define GET_H_PC() CPU (h_pc)
42 #define SET_H_PC(x) (CPU (h_pc) = (x))
43 /* general registers */
45 #define GET_H_GR(a1) CPU (h_gr)[a1]
46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
47 /* control registers */
49 #define GET_H_CR(index) m32r2f_h_cr_get_handler (current_cpu, index)
50 #define SET_H_CR(index, x) \
52 m32r2f_h_cr_set_handler (current_cpu, (index), (x));\
56 #define GET_H_ACCUM() m32r2f_h_accum_get_handler (current_cpu)
57 #define SET_H_ACCUM(x) \
59 m32r2f_h_accum_set_handler (current_cpu, (x));\
63 #define GET_H_ACCUMS(index) m32r2f_h_accums_get_handler (current_cpu, index)
64 #define SET_H_ACCUMS(index, x) \
66 m32r2f_h_accums_set_handler (current_cpu, (index), (x));\
70 #define GET_H_COND() CPU (h_cond)
71 #define SET_H_COND(x) (CPU (h_cond) = (x))
74 #define GET_H_PSW() m32r2f_h_psw_get_handler (current_cpu)
75 #define SET_H_PSW(x) \
77 m32r2f_h_psw_set_handler (current_cpu, (x));\
81 #define GET_H_BPSW() CPU (h_bpsw)
82 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
85 #define GET_H_BBPSW() CPU (h_bbpsw)
86 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
89 #define GET_H_LOCK() CPU (h_lock)
90 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
92 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
95 /* Cover fns for register access. */
96 USI
m32r2f_h_pc_get (SIM_CPU
*);
97 void m32r2f_h_pc_set (SIM_CPU
*, USI
);
98 SI
m32r2f_h_gr_get (SIM_CPU
*, UINT
);
99 void m32r2f_h_gr_set (SIM_CPU
*, UINT
, SI
);
100 USI
m32r2f_h_cr_get (SIM_CPU
*, UINT
);
101 void m32r2f_h_cr_set (SIM_CPU
*, UINT
, USI
);
102 DI
m32r2f_h_accum_get (SIM_CPU
*);
103 void m32r2f_h_accum_set (SIM_CPU
*, DI
);
104 DI
m32r2f_h_accums_get (SIM_CPU
*, UINT
);
105 void m32r2f_h_accums_set (SIM_CPU
*, UINT
, DI
);
106 BI
m32r2f_h_cond_get (SIM_CPU
*);
107 void m32r2f_h_cond_set (SIM_CPU
*, BI
);
108 UQI
m32r2f_h_psw_get (SIM_CPU
*);
109 void m32r2f_h_psw_set (SIM_CPU
*, UQI
);
110 UQI
m32r2f_h_bpsw_get (SIM_CPU
*);
111 void m32r2f_h_bpsw_set (SIM_CPU
*, UQI
);
112 UQI
m32r2f_h_bbpsw_get (SIM_CPU
*);
113 void m32r2f_h_bbpsw_set (SIM_CPU
*, UQI
);
114 BI
m32r2f_h_lock_get (SIM_CPU
*);
115 void m32r2f_h_lock_set (SIM_CPU
*, BI
);
117 /* These must be hand-written. */
118 extern CPUREG_FETCH_FN m32r2f_fetch_register
;
119 extern CPUREG_STORE_FN m32r2f_store_register
;
125 /* Instruction argument buffer. */
128 struct { /* no operands */
139 unsigned char out_h_gr_SI_14
;
143 unsigned char out_h_gr_SI_14
;
154 unsigned char out_dr
;
160 unsigned char in_src1
;
166 unsigned char out_dr
;
172 unsigned char out_dr
;
178 unsigned char out_h_gr_SI_14
;
192 unsigned char out_dr
;
199 unsigned char out_dr
;
206 unsigned char in_src1
;
207 unsigned char in_src2
;
208 unsigned char out_src2
;
216 unsigned char in_src1
;
217 unsigned char in_src2
;
225 unsigned char in_src1
;
226 unsigned char in_src2
;
234 unsigned char out_dr
;
235 unsigned char out_sr
;
243 unsigned char in_src1
;
244 unsigned char in_src2
;
253 unsigned char out_dr
;
262 unsigned char out_dr
;
271 unsigned char out_dr
;
274 /* Writeback handler. */
276 /* Pointer to argbuf entry for insn whose results need writing back. */
277 const struct argbuf
*abuf
;
279 /* x-before handler */
281 /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
284 /* x-after handler */
288 /* This entry is used to terminate each pbb. */
290 /* Number of insns in pbb. */
292 /* Next pbb to execute. */
294 SCACHE
*branch_target
;
299 /* The ARGBUF struct. */
301 /* These are the baseclass definitions. */
306 /* ??? Temporary hack for skip insns. */
309 /* cpu specific data follows */
312 union sem_fields fields
;
317 ??? SCACHE used to contain more than just argbuf. We could delete the
318 type entirely and always just use ARGBUF, but for future concerns and as
319 a level of abstraction it is left in. */
322 struct argbuf argbuf
;
325 /* Macros to simplify extraction, reading and semantic code.
326 These define and assign the local vars that contain the insn's fields. */
328 #define EXTRACT_IFMT_EMPTY_VARS \
330 #define EXTRACT_IFMT_EMPTY_CODE \
333 #define EXTRACT_IFMT_ADD_VARS \
339 #define EXTRACT_IFMT_ADD_CODE \
341 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
342 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
343 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
344 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
346 #define EXTRACT_IFMT_ADD3_VARS \
353 #define EXTRACT_IFMT_ADD3_CODE \
355 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
356 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
357 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
358 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
359 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
361 #define EXTRACT_IFMT_AND3_VARS \
368 #define EXTRACT_IFMT_AND3_CODE \
370 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
371 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
372 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
373 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
374 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
376 #define EXTRACT_IFMT_OR3_VARS \
383 #define EXTRACT_IFMT_OR3_CODE \
385 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
386 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
387 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
388 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
389 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
391 #define EXTRACT_IFMT_ADDI_VARS \
396 #define EXTRACT_IFMT_ADDI_CODE \
398 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
399 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
400 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8); \
402 #define EXTRACT_IFMT_ADDV3_VARS \
409 #define EXTRACT_IFMT_ADDV3_CODE \
411 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
412 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
413 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
414 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
415 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
417 #define EXTRACT_IFMT_BC8_VARS \
422 #define EXTRACT_IFMT_BC8_CODE \
424 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
425 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
426 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
428 #define EXTRACT_IFMT_BC24_VARS \
433 #define EXTRACT_IFMT_BC24_CODE \
435 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
436 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
437 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
439 #define EXTRACT_IFMT_BEQ_VARS \
446 #define EXTRACT_IFMT_BEQ_CODE \
448 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
449 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
450 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
451 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
452 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
454 #define EXTRACT_IFMT_BEQZ_VARS \
461 #define EXTRACT_IFMT_BEQZ_CODE \
463 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
464 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
465 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
466 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
467 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
469 #define EXTRACT_IFMT_CMP_VARS \
475 #define EXTRACT_IFMT_CMP_CODE \
477 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
478 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
479 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
480 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
482 #define EXTRACT_IFMT_CMPI_VARS \
489 #define EXTRACT_IFMT_CMPI_CODE \
491 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
492 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
493 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
494 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
495 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
497 #define EXTRACT_IFMT_CMPZ_VARS \
503 #define EXTRACT_IFMT_CMPZ_CODE \
505 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
506 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
507 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
508 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
510 #define EXTRACT_IFMT_DIV_VARS \
517 #define EXTRACT_IFMT_DIV_CODE \
519 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
520 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
521 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
522 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
523 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
525 #define EXTRACT_IFMT_JC_VARS \
531 #define EXTRACT_IFMT_JC_CODE \
533 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
534 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
535 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
536 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
538 #define EXTRACT_IFMT_LD24_VARS \
543 #define EXTRACT_IFMT_LD24_CODE \
545 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
546 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
547 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
549 #define EXTRACT_IFMT_LDI16_VARS \
556 #define EXTRACT_IFMT_LDI16_CODE \
558 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
559 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
560 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
561 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
562 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
564 #define EXTRACT_IFMT_MACHI_A_VARS \
571 #define EXTRACT_IFMT_MACHI_A_CODE \
573 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
574 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
575 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
576 f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
577 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
579 #define EXTRACT_IFMT_MVFACHI_A_VARS \
586 #define EXTRACT_IFMT_MVFACHI_A_CODE \
588 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
589 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
590 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
591 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
592 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
594 #define EXTRACT_IFMT_MVFC_VARS \
600 #define EXTRACT_IFMT_MVFC_CODE \
602 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
603 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
604 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
605 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
607 #define EXTRACT_IFMT_MVTACHI_A_VARS \
614 #define EXTRACT_IFMT_MVTACHI_A_CODE \
616 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
617 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
618 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
619 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
620 f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
622 #define EXTRACT_IFMT_MVTC_VARS \
628 #define EXTRACT_IFMT_MVTC_CODE \
630 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
631 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
632 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
633 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
635 #define EXTRACT_IFMT_NOP_VARS \
641 #define EXTRACT_IFMT_NOP_CODE \
643 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
644 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
645 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
646 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
648 #define EXTRACT_IFMT_RAC_DSI_VARS \
657 #define EXTRACT_IFMT_RAC_DSI_CODE \
659 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
660 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
661 f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
662 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
663 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
664 f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
665 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
667 #define EXTRACT_IFMT_SETH_VARS \
674 #define EXTRACT_IFMT_SETH_CODE \
676 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
677 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
678 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
679 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
680 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
682 #define EXTRACT_IFMT_SLLI_VARS \
688 #define EXTRACT_IFMT_SLLI_CODE \
690 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
691 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
692 f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
693 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
695 #define EXTRACT_IFMT_ST_D_VARS \
702 #define EXTRACT_IFMT_ST_D_CODE \
704 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
705 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
706 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
707 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
708 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
710 #define EXTRACT_IFMT_TRAP_VARS \
716 #define EXTRACT_IFMT_TRAP_CODE \
718 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
719 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
720 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
721 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
723 #define EXTRACT_IFMT_SATB_VARS \
730 #define EXTRACT_IFMT_SATB_CODE \
732 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
733 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
734 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
735 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
736 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
738 #define EXTRACT_IFMT_CLRPSW_VARS \
743 #define EXTRACT_IFMT_CLRPSW_CODE \
745 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
746 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
747 f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
749 #define EXTRACT_IFMT_BSET_VARS \
757 #define EXTRACT_IFMT_BSET_CODE \
759 f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
760 f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
761 f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
762 f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
763 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
764 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16); \
766 #define EXTRACT_IFMT_BTST_VARS \
773 #define EXTRACT_IFMT_BTST_CODE \
775 f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
776 f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
777 f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
778 f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
779 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
781 /* Queued output values of an instruction. */
785 struct { /* empty sformat for unspecified field list */
788 struct { /* e.g. add $dr,$sr */
791 struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
794 struct { /* e.g. and3 $dr,$sr,$uimm16 */
797 struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
800 struct { /* e.g. addi $dr,$simm8 */
803 struct { /* e.g. addv $dr,$sr */
807 struct { /* e.g. addv3 $dr,$sr,$simm16 */
811 struct { /* e.g. addx $dr,$sr */
815 struct { /* e.g. bc.s $disp8 */
818 struct { /* e.g. bc.l $disp24 */
821 struct { /* e.g. beq $src1,$src2,$disp16 */
824 struct { /* e.g. beqz $src2,$disp16 */
827 struct { /* e.g. bl.s $disp8 */
831 struct { /* e.g. bl.l $disp24 */
835 struct { /* e.g. bcl.s $disp8 */
839 struct { /* e.g. bcl.l $disp24 */
843 struct { /* e.g. bra.s $disp8 */
846 struct { /* e.g. bra.l $disp24 */
849 struct { /* e.g. cmp $src1,$src2 */
852 struct { /* e.g. cmpi $src2,$simm16 */
855 struct { /* e.g. cmpz $src2 */
858 struct { /* e.g. div $dr,$sr */
861 struct { /* e.g. jc $sr */
864 struct { /* e.g. jl $sr */
868 struct { /* e.g. jmp $sr */
871 struct { /* e.g. ld $dr,@$sr */
874 struct { /* e.g. ld $dr,@($slo16,$sr) */
877 struct { /* e.g. ldb $dr,@$sr */
880 struct { /* e.g. ldb $dr,@($slo16,$sr) */
883 struct { /* e.g. ldh $dr,@$sr */
886 struct { /* e.g. ldh $dr,@($slo16,$sr) */
889 struct { /* e.g. ld $dr,@$sr+ */
893 struct { /* e.g. ld24 $dr,$uimm24 */
896 struct { /* e.g. ldi8 $dr,$simm8 */
899 struct { /* e.g. ldi16 $dr,$hash$slo16 */
902 struct { /* e.g. lock $dr,@$sr */
906 struct { /* e.g. machi $src1,$src2,$acc */
909 struct { /* e.g. mulhi $src1,$src2,$acc */
912 struct { /* e.g. mv $dr,$sr */
915 struct { /* e.g. mvfachi $dr,$accs */
918 struct { /* e.g. mvfc $dr,$scr */
921 struct { /* e.g. mvtachi $src1,$accs */
924 struct { /* e.g. mvtc $sr,$dcr */
927 struct { /* e.g. nop */
930 struct { /* e.g. rac $accd,$accs,$imm1 */
933 struct { /* e.g. rte */
939 struct { /* e.g. seth $dr,$hash$hi16 */
942 struct { /* e.g. sll3 $dr,$sr,$simm16 */
945 struct { /* e.g. slli $dr,$uimm5 */
948 struct { /* e.g. st $src1,@$src2 */
950 USI h_memory_SI_src2_idx
;
952 struct { /* e.g. st $src1,@($slo16,$src2) */
953 SI h_memory_SI_add__DFLT_src2_slo16
;
954 USI h_memory_SI_add__DFLT_src2_slo16_idx
;
956 struct { /* e.g. stb $src1,@$src2 */
958 USI h_memory_QI_src2_idx
;
960 struct { /* e.g. stb $src1,@($slo16,$src2) */
961 QI h_memory_QI_add__DFLT_src2_slo16
;
962 USI h_memory_QI_add__DFLT_src2_slo16_idx
;
964 struct { /* e.g. sth $src1,@$src2 */
966 USI h_memory_HI_src2_idx
;
968 struct { /* e.g. sth $src1,@($slo16,$src2) */
969 HI h_memory_HI_add__DFLT_src2_slo16
;
970 USI h_memory_HI_add__DFLT_src2_slo16_idx
;
972 struct { /* e.g. st $src1,@+$src2 */
973 SI h_memory_SI_new_src2
;
974 USI h_memory_SI_new_src2_idx
;
977 struct { /* e.g. sth $src1,@$src2+ */
978 HI h_memory_HI_new_src2
;
979 USI h_memory_HI_new_src2_idx
;
982 struct { /* e.g. stb $src1,@$src2+ */
983 QI h_memory_QI_new_src2
;
984 USI h_memory_QI_new_src2_idx
;
987 struct { /* e.g. trap $uimm4 */
995 struct { /* e.g. unlock $src1,@$src2 */
998 USI h_memory_SI_src2_idx
;
1000 struct { /* e.g. satb $dr,$sr */
1003 struct { /* e.g. sat $dr,$sr */
1006 struct { /* e.g. sadd */
1009 struct { /* e.g. macwu1 $src1,$src2 */
1012 struct { /* e.g. msblo $src1,$src2 */
1015 struct { /* e.g. mulwu1 $src1,$src2 */
1018 struct { /* e.g. sc */
1021 struct { /* e.g. clrpsw $uimm8 */
1024 struct { /* e.g. setpsw $uimm8 */
1027 struct { /* e.g. bset $uimm3,@($slo16,$sr) */
1028 QI h_memory_QI_add__DFLT_sr_slo16
;
1029 USI h_memory_QI_add__DFLT_sr_slo16_idx
;
1031 struct { /* e.g. btst $uimm3,$sr */
1035 /* For conditionally written operands, bitmask of which ones were. */
1039 /* Collection of various things for the trace handler to use. */
1041 typedef struct trace_record
{
1046 #endif /* CPU_M32R2F_H */