sim/m32r/cpux.h

   1 /* CPU family header for m32rx.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RX_H
  26 #define CPU_M32RX_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 2
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 #define GET_H_CR(a1) CPU (h_cr)[a1]
  50 #define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
  51   /* accumulator */
  52   DI h_accum;
  53 #define GET_H_ACCUM() CPU (h_accum)
  54 #define SET_H_ACCUM(x) (CPU (h_accum) = (x))
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 #define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
  60 #define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
  61   /* condition bit */
  62   UBI h_cond;
  63 #define GET_H_COND() CPU (h_cond)
  64 #define SET_H_COND(x) (CPU (h_cond) = (x))
  65   /* sm */
  66   UBI h_sm;
  67 #define GET_H_SM() CPU (h_sm)
  68 #define SET_H_SM(x) (CPU (h_sm) = (x))
  69   /* bsm */
  70   UBI h_bsm;
  71 #define GET_H_BSM() CPU (h_bsm)
  72 #define SET_H_BSM(x) (CPU (h_bsm) = (x))
  73   /* ie */
  74   UBI h_ie;
  75 #define GET_H_IE() CPU (h_ie)
  76 #define SET_H_IE(x) (CPU (h_ie) = (x))
  77   /* bie */
  78   UBI h_bie;
  79 #define GET_H_BIE() CPU (h_bie)
  80 #define SET_H_BIE(x) (CPU (h_bie) = (x))
  81   /* bcond */
  82   UBI h_bcond;
  83 #define GET_H_BCOND() CPU (h_bcond)
  84 #define SET_H_BCOND(x) (CPU (h_bcond) = (x))
  85   /* bpc */
  86   SI h_bpc;
  87 #define GET_H_BPC() CPU (h_bpc)
  88 #define SET_H_BPC(x) (CPU (h_bpc) = (x))
  89   /* lock */
  90   UBI h_lock;
  91 #define GET_H_LOCK() CPU (h_lock)
  92 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  93   } hardware;
  94 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  95   /* CPU profiling state information.  */
  96   struct {
  97   /* general registers */
  98   unsigned long h_gr;
  99   } profile;
 100 #define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
 101 } M32RX_CPU_DATA;
 102
 103 /* Cover fns for register access.  */
 104 USI m32rx_h_pc_get (SIM_CPU *);
 105 void m32rx_h_pc_set (SIM_CPU *, USI);
 106 SI m32rx_h_gr_get (SIM_CPU *, UINT);
 107 void m32rx_h_gr_set (SIM_CPU *, UINT, SI);
 108 USI m32rx_h_cr_get (SIM_CPU *, UINT);
 109 void m32rx_h_cr_set (SIM_CPU *, UINT, USI);
 110 DI m32rx_h_accum_get (SIM_CPU *);
 111 void m32rx_h_accum_set (SIM_CPU *, DI);
 112 DI m32rx_h_accums_get (SIM_CPU *, UINT);
 113 void m32rx_h_accums_set (SIM_CPU *, UINT, DI);
 114 UBI m32rx_h_cond_get (SIM_CPU *);
 115 void m32rx_h_cond_set (SIM_CPU *, UBI);
 116 UBI m32rx_h_sm_get (SIM_CPU *);
 117 void m32rx_h_sm_set (SIM_CPU *, UBI);
 118 UBI m32rx_h_bsm_get (SIM_CPU *);
 119 void m32rx_h_bsm_set (SIM_CPU *, UBI);
 120 UBI m32rx_h_ie_get (SIM_CPU *);
 121 void m32rx_h_ie_set (SIM_CPU *, UBI);
 122 UBI m32rx_h_bie_get (SIM_CPU *);
 123 void m32rx_h_bie_set (SIM_CPU *, UBI);
 124 UBI m32rx_h_bcond_get (SIM_CPU *);
 125 void m32rx_h_bcond_set (SIM_CPU *, UBI);
 126 SI m32rx_h_bpc_get (SIM_CPU *);
 127 void m32rx_h_bpc_set (SIM_CPU *, SI);
 128 UBI m32rx_h_lock_get (SIM_CPU *);
 129 void m32rx_h_lock_set (SIM_CPU *, UBI);
 130
 131 /* These must be hand-written.  */
 132 extern CPUREG_FETCH_FN m32rx_fetch_register;
 133 extern CPUREG_STORE_FN m32rx_store_register;
 134
 135 /* The ARGBUF struct.  */
 136 struct argbuf {
 137   /* These are the baseclass definitions.  */
 138   unsigned int length;
 139   PCADDR addr;
 140   const IDESC *idesc;
 141   /* cpu specific data follows */
 142   insn_t insn;
 143   union {
 144     struct { /* e.g. add $dr,$sr */
 145       UINT f_r1;
 146       UINT f_r2;
 147     } fmt_add;
 148     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 149       UINT f_r1;
 150       UINT f_r2;
 151       HI f_simm16;
 152     } fmt_add3;
 153     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 154       UINT f_r1;
 155       UINT f_r2;
 156       USI f_uimm16;
 157     } fmt_and3;
 158     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 159       UINT f_r1;
 160       UINT f_r2;
 161       UHI f_uimm16;
 162     } fmt_or3;
 163     struct { /* e.g. addi $dr,$simm8 */
 164       UINT f_r1;
 165       SI f_simm8;
 166     } fmt_addi;
 167     struct { /* e.g. addv $dr,$sr */
 168       UINT f_r1;
 169       UINT f_r2;
 170     } fmt_addv;
 171     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 172       UINT f_r1;
 173       UINT f_r2;
 174       SI f_simm16;
 175     } fmt_addv3;
 176     struct { /* e.g. addx $dr,$sr */
 177       UINT f_r1;
 178       UINT f_r2;
 179     } fmt_addx;
 180     struct { /* e.g. bc.s $disp8 */
 181       IADDR f_disp8;
 182     } fmt_bc8;
 183     struct { /* e.g. bc.l $disp24 */
 184       IADDR f_disp24;
 185     } fmt_bc24;
 186     struct { /* e.g. beq $src1,$src2,$disp16 */
 187       UINT f_r1;
 188       UINT f_r2;
 189       IADDR f_disp16;
 190     } fmt_beq;
 191     struct { /* e.g. beqz $src2,$disp16 */
 192       UINT f_r2;
 193       IADDR f_disp16;
 194     } fmt_beqz;
 195     struct { /* e.g. bl.s $disp8 */
 196       IADDR f_disp8;
 197     } fmt_bl8;
 198     struct { /* e.g. bl.l $disp24 */
 199       IADDR f_disp24;
 200     } fmt_bl24;
 201     struct { /* e.g. bcl.s $disp8 */
 202       IADDR f_disp8;
 203     } fmt_bcl8;
 204     struct { /* e.g. bcl.l $disp24 */
 205       IADDR f_disp24;
 206     } fmt_bcl24;
 207     struct { /* e.g. bra.s $disp8 */
 208       IADDR f_disp8;
 209     } fmt_bra8;
 210     struct { /* e.g. bra.l $disp24 */
 211       IADDR f_disp24;
 212     } fmt_bra24;
 213     struct { /* e.g. cmp $src1,$src2 */
 214       UINT f_r1;
 215       UINT f_r2;
 216     } fmt_cmp;
 217     struct { /* e.g. cmpi $src2,$simm16 */
 218       UINT f_r2;
 219       SI f_simm16;
 220     } fmt_cmpi;
 221     struct { /* e.g. cmpz $src2 */
 222       UINT f_r2;
 223     } fmt_cmpz;
 224     struct { /* e.g. div $dr,$sr */
 225       UINT f_r1;
 226       UINT f_r2;
 227     } fmt_div;
 228     struct { /* e.g. jc $sr */
 229       UINT f_r2;
 230     } fmt_jc;
 231     struct { /* e.g. jl $sr */
 232       UINT f_r2;
 233     } fmt_jl;
 234     struct { /* e.g. jmp $sr */
 235       UINT f_r2;
 236     } fmt_jmp;
 237     struct { /* e.g. ld $dr,@$sr */
 238       UINT f_r1;
 239       UINT f_r2;
 240     } fmt_ld;
 241     struct { /* e.g. ld $dr,@($slo16,$sr) */
 242       UINT f_r1;
 243       UINT f_r2;
 244       HI f_simm16;
 245     } fmt_ld_d;
 246     struct { /* e.g. ldb $dr,@$sr */
 247       UINT f_r1;
 248       UINT f_r2;
 249     } fmt_ldb;
 250     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 251       UINT f_r1;
 252       UINT f_r2;
 253       HI f_simm16;
 254     } fmt_ldb_d;
 255     struct { /* e.g. ldh $dr,@$sr */
 256       UINT f_r1;
 257       UINT f_r2;
 258     } fmt_ldh;
 259     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 260       UINT f_r1;
 261       UINT f_r2;
 262       HI f_simm16;
 263     } fmt_ldh_d;
 264     struct { /* e.g. ld $dr,@$sr+ */
 265       UINT f_r1;
 266       UINT f_r2;
 267     } fmt_ld_plus;
 268     struct { /* e.g. ld24 $dr,$uimm24 */
 269       UINT f_r1;
 270       ADDR f_uimm24;
 271     } fmt_ld24;
 272     struct { /* e.g. ldi8 $dr,$simm8 */
 273       UINT f_r1;
 274       SI f_simm8;
 275     } fmt_ldi8;
 276     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 277       UINT f_r1;
 278       HI f_simm16;
 279     } fmt_ldi16;
 280     struct { /* e.g. lock $dr,@$sr */
 281       UINT f_r1;
 282       UINT f_r2;
 283     } fmt_lock;
 284     struct { /* e.g. machi $src1,$src2,$acc */
 285       UINT f_r1;
 286       UINT f_acc;
 287       UINT f_r2;
 288     } fmt_machi_a;
 289     struct { /* e.g. mulhi $src1,$src2,$acc */
 290       UINT f_r1;
 291       UINT f_acc;
 292       UINT f_r2;
 293     } fmt_mulhi_a;
 294     struct { /* e.g. mv $dr,$sr */
 295       UINT f_r1;
 296       UINT f_r2;
 297     } fmt_mv;
 298     struct { /* e.g. mvfachi $dr,$accs */
 299       UINT f_r1;
 300       UINT f_accs;
 301     } fmt_mvfachi_a;
 302     struct { /* e.g. mvfc $dr,$scr */
 303       UINT f_r1;
 304       UINT f_r2;
 305     } fmt_mvfc;
 306     struct { /* e.g. mvtachi $src1,$accs */
 307       UINT f_r1;
 308       UINT f_accs;
 309     } fmt_mvtachi_a;
 310     struct { /* e.g. mvtc $sr,$dcr */
 311       UINT f_r1;
 312       UINT f_r2;
 313     } fmt_mvtc;
 314     struct { /* e.g. nop */
 315       int empty;
 316     } fmt_nop;
 317     struct { /* e.g. rac $accd,$accs,$imm1 */
 318       UINT f_accd;
 319       UINT f_accs;
 320       USI f_imm1;
 321     } fmt_rac_dsi;
 322     struct { /* e.g. rte */
 323       int empty;
 324     } fmt_rte;
 325     struct { /* e.g. seth $dr,$hash$hi16 */
 326       UINT f_r1;
 327       UHI f_hi16;
 328     } fmt_seth;
 329     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 330       UINT f_r1;
 331       UINT f_r2;
 332       SI f_simm16;
 333     } fmt_sll3;
 334     struct { /* e.g. slli $dr,$uimm5 */
 335       UINT f_r1;
 336       USI f_uimm5;
 337     } fmt_slli;
 338     struct { /* e.g. st $src1,@$src2 */
 339       UINT f_r1;
 340       UINT f_r2;
 341     } fmt_st;
 342     struct { /* e.g. st $src1,@($slo16,$src2) */
 343       UINT f_r1;
 344       UINT f_r2;
 345       HI f_simm16;
 346     } fmt_st_d;
 347     struct { /* e.g. stb $src1,@$src2 */
 348       UINT f_r1;
 349       UINT f_r2;
 350     } fmt_stb;
 351     struct { /* e.g. stb $src1,@($slo16,$src2) */
 352       UINT f_r1;
 353       UINT f_r2;
 354       HI f_simm16;
 355     } fmt_stb_d;
 356     struct { /* e.g. sth $src1,@$src2 */
 357       UINT f_r1;
 358       UINT f_r2;
 359     } fmt_sth;
 360     struct { /* e.g. sth $src1,@($slo16,$src2) */
 361       UINT f_r1;
 362       UINT f_r2;
 363       HI f_simm16;
 364     } fmt_sth_d;
 365     struct { /* e.g. st $src1,@+$src2 */
 366       UINT f_r1;
 367       UINT f_r2;
 368     } fmt_st_plus;
 369     struct { /* e.g. trap $uimm4 */
 370       USI f_uimm4;
 371     } fmt_trap;
 372     struct { /* e.g. unlock $src1,@$src2 */
 373       UINT f_r1;
 374       UINT f_r2;
 375     } fmt_unlock;
 376     struct { /* e.g. satb $dr,$sr */
 377       UINT f_r1;
 378       UINT f_r2;
 379     } fmt_satb;
 380     struct { /* e.g. sat $dr,$sr */
 381       UINT f_r1;
 382       UINT f_r2;
 383     } fmt_sat;
 384     struct { /* e.g. sadd */
 385       int empty;
 386     } fmt_sadd;
 387     struct { /* e.g. macwu1 $src1,$src2 */
 388       UINT f_r1;
 389       UINT f_r2;
 390     } fmt_macwu1;
 391     struct { /* e.g. msblo $src1,$src2 */
 392       UINT f_r1;
 393       UINT f_r2;
 394     } fmt_msblo;
 395     struct { /* e.g. mulwu1 $src1,$src2 */
 396       UINT f_r1;
 397       UINT f_r2;
 398     } fmt_mulwu1;
 399     struct { /* e.g. sc */
 400       int empty;
 401     } fmt_sc;
 402   } fields;
 403 #if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
 404   unsigned long h_gr_get;
 405   unsigned long h_gr_set;
 406 #endif
 407 };
 408
 409 /* A cached insn.
 410    This is currently also used in the non-scache case.  In this situation we
 411    assume the cache size is 1, and do a few things a little differently.  */
 412 /* FIXME: non-scache version to be redone.  */
 413
 414 struct scache {
 415   IADDR next;
 416   union {
 417 #if ! WITH_SEM_SWITCH_FULL
 418     SEMANTIC_FN *sem_full;
 419 #endif
 420 #if ! WITH_SEM_SWITCH_FAST
 421     SEMANTIC_FN *sem_fast;
 422 #endif
 423 #if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
 424 #ifdef __GNUC__
 425     void *sem_case;
 426 #else
 427     int sem_case;
 428 #endif
 429 #endif
 430   } semantic;
 431   struct argbuf argbuf;
 432 };
 433
 434 /* Macros to simplify extraction, reading and semantic code.
 435    These define and assign the local vars that contain the insn's fields.  */
 436
 437 #define EXTRACT_FMT_ADD_VARS \
 438   /* Instruction fields.  */ \
 439   UINT f_op1; \
 440   UINT f_r1; \
 441   UINT f_op2; \
 442   UINT f_r2; \
 443   unsigned int length;
 444 #define EXTRACT_FMT_ADD_CODE \
 445   length = 2; \
 446   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 447   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 448   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 449   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 450
 451 #define EXTRACT_FMT_ADD3_VARS \
 452   /* Instruction fields.  */ \
 453   UINT f_op1; \
 454   UINT f_r1; \
 455   UINT f_op2; \
 456   UINT f_r2; \
 457   int f_simm16; \
 458   unsigned int length;
 459 #define EXTRACT_FMT_ADD3_CODE \
 460   length = 4; \
 461   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 462   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 463   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 464   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 465   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 466
 467 #define EXTRACT_FMT_AND3_VARS \
 468   /* Instruction fields.  */ \
 469   UINT f_op1; \
 470   UINT f_r1; \
 471   UINT f_op2; \
 472   UINT f_r2; \
 473   UINT f_uimm16; \
 474   unsigned int length;
 475 #define EXTRACT_FMT_AND3_CODE \
 476   length = 4; \
 477   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 478   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 479   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 480   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 481   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 482
 483 #define EXTRACT_FMT_OR3_VARS \
 484   /* Instruction fields.  */ \
 485   UINT f_op1; \
 486   UINT f_r1; \
 487   UINT f_op2; \
 488   UINT f_r2; \
 489   UINT f_uimm16; \
 490   unsigned int length;
 491 #define EXTRACT_FMT_OR3_CODE \
 492   length = 4; \
 493   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 494   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 495   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 496   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 497   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
 498
 499 #define EXTRACT_FMT_ADDI_VARS \
 500   /* Instruction fields.  */ \
 501   UINT f_op1; \
 502   UINT f_r1; \
 503   int f_simm8; \
 504   unsigned int length;
 505 #define EXTRACT_FMT_ADDI_CODE \
 506   length = 2; \
 507   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 508   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 509   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 510
 511 #define EXTRACT_FMT_ADDV_VARS \
 512   /* Instruction fields.  */ \
 513   UINT f_op1; \
 514   UINT f_r1; \
 515   UINT f_op2; \
 516   UINT f_r2; \
 517   unsigned int length;
 518 #define EXTRACT_FMT_ADDV_CODE \
 519   length = 2; \
 520   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 521   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 522   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 523   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 524
 525 #define EXTRACT_FMT_ADDV3_VARS \
 526   /* Instruction fields.  */ \
 527   UINT f_op1; \
 528   UINT f_r1; \
 529   UINT f_op2; \
 530   UINT f_r2; \
 531   int f_simm16; \
 532   unsigned int length;
 533 #define EXTRACT_FMT_ADDV3_CODE \
 534   length = 4; \
 535   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 536   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 537   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 538   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 539   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 540
 541 #define EXTRACT_FMT_ADDX_VARS \
 542   /* Instruction fields.  */ \
 543   UINT f_op1; \
 544   UINT f_r1; \
 545   UINT f_op2; \
 546   UINT f_r2; \
 547   unsigned int length;
 548 #define EXTRACT_FMT_ADDX_CODE \
 549   length = 2; \
 550   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 551   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 552   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 553   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 554
 555 #define EXTRACT_FMT_BC8_VARS \
 556   /* Instruction fields.  */ \
 557   UINT f_op1; \
 558   UINT f_r1; \
 559   int f_disp8; \
 560   unsigned int length;
 561 #define EXTRACT_FMT_BC8_CODE \
 562   length = 2; \
 563   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 564   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 565   f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 566
 567 #define EXTRACT_FMT_BC24_VARS \
 568   /* Instruction fields.  */ \
 569   UINT f_op1; \
 570   UINT f_r1; \
 571   int f_disp24; \
 572   unsigned int length;
 573 #define EXTRACT_FMT_BC24_CODE \
 574   length = 4; \
 575   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 576   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 577   f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
 578
 579 #define EXTRACT_FMT_BEQ_VARS \
 580   /* Instruction fields.  */ \
 581   UINT f_op1; \
 582   UINT f_r1; \
 583   UINT f_op2; \
 584   UINT f_r2; \
 585   int f_disp16; \
 586   unsigned int length;
 587 #define EXTRACT_FMT_BEQ_CODE \
 588   length = 4; \
 589   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 590   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 591   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 592   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 593   f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
 594
 595 #define EXTRACT_FMT_BEQZ_VARS \
 596   /* Instruction fields.  */ \
 597   UINT f_op1; \
 598   UINT f_r1; \
 599   UINT f_op2; \
 600   UINT f_r2; \
 601   int f_disp16; \
 602   unsigned int length;
 603 #define EXTRACT_FMT_BEQZ_CODE \
 604   length = 4; \
 605   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 606   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 607   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 608   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 609   f_disp16 = ((((EXTRACT_SIGNED (insn, 32, 16, 16)) << (2))) + (pc)); \
 610
 611 #define EXTRACT_FMT_BL8_VARS \
 612   /* Instruction fields.  */ \
 613   UINT f_op1; \
 614   UINT f_r1; \
 615   int f_disp8; \
 616   unsigned int length;
 617 #define EXTRACT_FMT_BL8_CODE \
 618   length = 2; \
 619   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 620   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 621   f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 622
 623 #define EXTRACT_FMT_BL24_VARS \
 624   /* Instruction fields.  */ \
 625   UINT f_op1; \
 626   UINT f_r1; \
 627   int f_disp24; \
 628   unsigned int length;
 629 #define EXTRACT_FMT_BL24_CODE \
 630   length = 4; \
 631   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 632   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 633   f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
 634
 635 #define EXTRACT_FMT_BCL8_VARS \
 636   /* Instruction fields.  */ \
 637   UINT f_op1; \
 638   UINT f_r1; \
 639   int f_disp8; \
 640   unsigned int length;
 641 #define EXTRACT_FMT_BCL8_CODE \
 642   length = 2; \
 643   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 644   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 645   f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 646
 647 #define EXTRACT_FMT_BCL24_VARS \
 648   /* Instruction fields.  */ \
 649   UINT f_op1; \
 650   UINT f_r1; \
 651   int f_disp24; \
 652   unsigned int length;
 653 #define EXTRACT_FMT_BCL24_CODE \
 654   length = 4; \
 655   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 656   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 657   f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
 658
 659 #define EXTRACT_FMT_BRA8_VARS \
 660   /* Instruction fields.  */ \
 661   UINT f_op1; \
 662   UINT f_r1; \
 663   int f_disp8; \
 664   unsigned int length;
 665 #define EXTRACT_FMT_BRA8_CODE \
 666   length = 2; \
 667   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 668   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 669   f_disp8 = ((((EXTRACT_SIGNED (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 670
 671 #define EXTRACT_FMT_BRA24_VARS \
 672   /* Instruction fields.  */ \
 673   UINT f_op1; \
 674   UINT f_r1; \
 675   int f_disp24; \
 676   unsigned int length;
 677 #define EXTRACT_FMT_BRA24_CODE \
 678   length = 4; \
 679   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 680   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 681   f_disp24 = ((((EXTRACT_SIGNED (insn, 32, 8, 24)) << (2))) + (pc)); \
 682
 683 #define EXTRACT_FMT_CMP_VARS \
 684   /* Instruction fields.  */ \
 685   UINT f_op1; \
 686   UINT f_r1; \
 687   UINT f_op2; \
 688   UINT f_r2; \
 689   unsigned int length;
 690 #define EXTRACT_FMT_CMP_CODE \
 691   length = 2; \
 692   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 693   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 694   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 695   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 696
 697 #define EXTRACT_FMT_CMPI_VARS \
 698   /* Instruction fields.  */ \
 699   UINT f_op1; \
 700   UINT f_r1; \
 701   UINT f_op2; \
 702   UINT f_r2; \
 703   int f_simm16; \
 704   unsigned int length;
 705 #define EXTRACT_FMT_CMPI_CODE \
 706   length = 4; \
 707   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 708   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 709   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 710   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 711   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 712
 713 #define EXTRACT_FMT_CMPZ_VARS \
 714   /* Instruction fields.  */ \
 715   UINT f_op1; \
 716   UINT f_r1; \
 717   UINT f_op2; \
 718   UINT f_r2; \
 719   unsigned int length;
 720 #define EXTRACT_FMT_CMPZ_CODE \
 721   length = 2; \
 722   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 723   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 724   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 725   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 726
 727 #define EXTRACT_FMT_DIV_VARS \
 728   /* Instruction fields.  */ \
 729   UINT f_op1; \
 730   UINT f_r1; \
 731   UINT f_op2; \
 732   UINT f_r2; \
 733   int f_simm16; \
 734   unsigned int length;
 735 #define EXTRACT_FMT_DIV_CODE \
 736   length = 4; \
 737   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 738   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 739   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 740   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 741   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 742
 743 #define EXTRACT_FMT_JC_VARS \
 744   /* Instruction fields.  */ \
 745   UINT f_op1; \
 746   UINT f_r1; \
 747   UINT f_op2; \
 748   UINT f_r2; \
 749   unsigned int length;
 750 #define EXTRACT_FMT_JC_CODE \
 751   length = 2; \
 752   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 753   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 754   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 755   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 756
 757 #define EXTRACT_FMT_JL_VARS \
 758   /* Instruction fields.  */ \
 759   UINT f_op1; \
 760   UINT f_r1; \
 761   UINT f_op2; \
 762   UINT f_r2; \
 763   unsigned int length;
 764 #define EXTRACT_FMT_JL_CODE \
 765   length = 2; \
 766   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 767   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 768   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 769   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 770
 771 #define EXTRACT_FMT_JMP_VARS \
 772   /* Instruction fields.  */ \
 773   UINT f_op1; \
 774   UINT f_r1; \
 775   UINT f_op2; \
 776   UINT f_r2; \
 777   unsigned int length;
 778 #define EXTRACT_FMT_JMP_CODE \
 779   length = 2; \
 780   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 781   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 782   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 783   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 784
 785 #define EXTRACT_FMT_LD_VARS \
 786   /* Instruction fields.  */ \
 787   UINT f_op1; \
 788   UINT f_r1; \
 789   UINT f_op2; \
 790   UINT f_r2; \
 791   unsigned int length;
 792 #define EXTRACT_FMT_LD_CODE \
 793   length = 2; \
 794   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 795   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 796   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 797   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 798
 799 #define EXTRACT_FMT_LD_D_VARS \
 800   /* Instruction fields.  */ \
 801   UINT f_op1; \
 802   UINT f_r1; \
 803   UINT f_op2; \
 804   UINT f_r2; \
 805   int f_simm16; \
 806   unsigned int length;
 807 #define EXTRACT_FMT_LD_D_CODE \
 808   length = 4; \
 809   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 810   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 811   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 812   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 813   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 814
 815 #define EXTRACT_FMT_LDB_VARS \
 816   /* Instruction fields.  */ \
 817   UINT f_op1; \
 818   UINT f_r1; \
 819   UINT f_op2; \
 820   UINT f_r2; \
 821   unsigned int length;
 822 #define EXTRACT_FMT_LDB_CODE \
 823   length = 2; \
 824   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 825   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 826   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 827   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 828
 829 #define EXTRACT_FMT_LDB_D_VARS \
 830   /* Instruction fields.  */ \
 831   UINT f_op1; \
 832   UINT f_r1; \
 833   UINT f_op2; \
 834   UINT f_r2; \
 835   int f_simm16; \
 836   unsigned int length;
 837 #define EXTRACT_FMT_LDB_D_CODE \
 838   length = 4; \
 839   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 840   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 841   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 842   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 843   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 844
 845 #define EXTRACT_FMT_LDH_VARS \
 846   /* Instruction fields.  */ \
 847   UINT f_op1; \
 848   UINT f_r1; \
 849   UINT f_op2; \
 850   UINT f_r2; \
 851   unsigned int length;
 852 #define EXTRACT_FMT_LDH_CODE \
 853   length = 2; \
 854   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 855   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 856   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 857   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 858
 859 #define EXTRACT_FMT_LDH_D_VARS \
 860   /* Instruction fields.  */ \
 861   UINT f_op1; \
 862   UINT f_r1; \
 863   UINT f_op2; \
 864   UINT f_r2; \
 865   int f_simm16; \
 866   unsigned int length;
 867 #define EXTRACT_FMT_LDH_D_CODE \
 868   length = 4; \
 869   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 870   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 871   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 872   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 873   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 874
 875 #define EXTRACT_FMT_LD_PLUS_VARS \
 876   /* Instruction fields.  */ \
 877   UINT f_op1; \
 878   UINT f_r1; \
 879   UINT f_op2; \
 880   UINT f_r2; \
 881   unsigned int length;
 882 #define EXTRACT_FMT_LD_PLUS_CODE \
 883   length = 2; \
 884   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 885   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 886   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 887   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 888
 889 #define EXTRACT_FMT_LD24_VARS \
 890   /* Instruction fields.  */ \
 891   UINT f_op1; \
 892   UINT f_r1; \
 893   UINT f_uimm24; \
 894   unsigned int length;
 895 #define EXTRACT_FMT_LD24_CODE \
 896   length = 4; \
 897   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 898   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 899   f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
 900
 901 #define EXTRACT_FMT_LDI8_VARS \
 902   /* Instruction fields.  */ \
 903   UINT f_op1; \
 904   UINT f_r1; \
 905   int f_simm8; \
 906   unsigned int length;
 907 #define EXTRACT_FMT_LDI8_CODE \
 908   length = 2; \
 909   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 910   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 911   f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
 912
 913 #define EXTRACT_FMT_LDI16_VARS \
 914   /* Instruction fields.  */ \
 915   UINT f_op1; \
 916   UINT f_r1; \
 917   UINT f_op2; \
 918   UINT f_r2; \
 919   int f_simm16; \
 920   unsigned int length;
 921 #define EXTRACT_FMT_LDI16_CODE \
 922   length = 4; \
 923   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
 924   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
 925   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
 926   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
 927   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
 928
 929 #define EXTRACT_FMT_LOCK_VARS \
 930   /* Instruction fields.  */ \
 931   UINT f_op1; \
 932   UINT f_r1; \
 933   UINT f_op2; \
 934   UINT f_r2; \
 935   unsigned int length;
 936 #define EXTRACT_FMT_LOCK_CODE \
 937   length = 2; \
 938   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 939   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 940   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 941   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 942
 943 #define EXTRACT_FMT_MACHI_A_VARS \
 944   /* Instruction fields.  */ \
 945   UINT f_op1; \
 946   UINT f_r1; \
 947   UINT f_acc; \
 948   UINT f_op23; \
 949   UINT f_r2; \
 950   unsigned int length;
 951 #define EXTRACT_FMT_MACHI_A_CODE \
 952   length = 2; \
 953   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 954   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 955   f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
 956   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
 957   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 958
 959 #define EXTRACT_FMT_MULHI_A_VARS \
 960   /* Instruction fields.  */ \
 961   UINT f_op1; \
 962   UINT f_r1; \
 963   UINT f_acc; \
 964   UINT f_op23; \
 965   UINT f_r2; \
 966   unsigned int length;
 967 #define EXTRACT_FMT_MULHI_A_CODE \
 968   length = 2; \
 969   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 970   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 971   f_acc = EXTRACT_UNSIGNED (insn, 16, 8, 1); \
 972   f_op23 = EXTRACT_UNSIGNED (insn, 16, 9, 3); \
 973   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 974
 975 #define EXTRACT_FMT_MV_VARS \
 976   /* Instruction fields.  */ \
 977   UINT f_op1; \
 978   UINT f_r1; \
 979   UINT f_op2; \
 980   UINT f_r2; \
 981   unsigned int length;
 982 #define EXTRACT_FMT_MV_CODE \
 983   length = 2; \
 984   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
 985   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
 986   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
 987   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
 988
 989 #define EXTRACT_FMT_MVFACHI_A_VARS \
 990   /* Instruction fields.  */ \
 991   UINT f_op1; \
 992   UINT f_r1; \
 993   UINT f_op2; \
 994   UINT f_accs; \
 995   UINT f_op3; \
 996   unsigned int length;
 997 #define EXTRACT_FMT_MVFACHI_A_CODE \
 998   length = 2; \
 999   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1000   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1001   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1002   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1003   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1004
1005 #define EXTRACT_FMT_MVFC_VARS \
1006   /* Instruction fields.  */ \
1007   UINT f_op1; \
1008   UINT f_r1; \
1009   UINT f_op2; \
1010   UINT f_r2; \
1011   unsigned int length;
1012 #define EXTRACT_FMT_MVFC_CODE \
1013   length = 2; \
1014   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1015   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1016   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1017   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1018
1019 #define EXTRACT_FMT_MVTACHI_A_VARS \
1020   /* Instruction fields.  */ \
1021   UINT f_op1; \
1022   UINT f_r1; \
1023   UINT f_op2; \
1024   UINT f_accs; \
1025   UINT f_op3; \
1026   unsigned int length;
1027 #define EXTRACT_FMT_MVTACHI_A_CODE \
1028   length = 2; \
1029   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1030   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1031   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1032   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1033   f_op3 = EXTRACT_UNSIGNED (insn, 16, 14, 2); \
1034
1035 #define EXTRACT_FMT_MVTC_VARS \
1036   /* Instruction fields.  */ \
1037   UINT f_op1; \
1038   UINT f_r1; \
1039   UINT f_op2; \
1040   UINT f_r2; \
1041   unsigned int length;
1042 #define EXTRACT_FMT_MVTC_CODE \
1043   length = 2; \
1044   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1045   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1046   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1047   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1048
1049 #define EXTRACT_FMT_NOP_VARS \
1050   /* Instruction fields.  */ \
1051   UINT f_op1; \
1052   UINT f_r1; \
1053   UINT f_op2; \
1054   UINT f_r2; \
1055   unsigned int length;
1056 #define EXTRACT_FMT_NOP_CODE \
1057   length = 2; \
1058   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1059   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1060   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1061   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1062
1063 #define EXTRACT_FMT_RAC_DSI_VARS \
1064   /* Instruction fields.  */ \
1065   UINT f_op1; \
1066   UINT f_accd; \
1067   UINT f_bits67; \
1068   UINT f_op2; \
1069   UINT f_accs; \
1070   UINT f_bit14; \
1071   UINT f_imm1; \
1072   unsigned int length;
1073 #define EXTRACT_FMT_RAC_DSI_CODE \
1074   length = 2; \
1075   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1076   f_accd = EXTRACT_UNSIGNED (insn, 16, 4, 2); \
1077   f_bits67 = EXTRACT_UNSIGNED (insn, 16, 6, 2); \
1078   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1079   f_accs = EXTRACT_UNSIGNED (insn, 16, 12, 2); \
1080   f_bit14 = EXTRACT_UNSIGNED (insn, 16, 14, 1); \
1081   f_imm1 = ((EXTRACT_UNSIGNED (insn, 16, 15, 1)) + (1)); \
1082
1083 #define EXTRACT_FMT_RTE_VARS \
1084   /* Instruction fields.  */ \
1085   UINT f_op1; \
1086   UINT f_r1; \
1087   UINT f_op2; \
1088   UINT f_r2; \
1089   unsigned int length;
1090 #define EXTRACT_FMT_RTE_CODE \
1091   length = 2; \
1092   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1093   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1094   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1095   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1096
1097 #define EXTRACT_FMT_SETH_VARS \
1098   /* Instruction fields.  */ \
1099   UINT f_op1; \
1100   UINT f_r1; \
1101   UINT f_op2; \
1102   UINT f_r2; \
1103   UINT f_hi16; \
1104   unsigned int length;
1105 #define EXTRACT_FMT_SETH_CODE \
1106   length = 4; \
1107   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1108   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1109   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1110   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1111   f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1112
1113 #define EXTRACT_FMT_SLL3_VARS \
1114   /* Instruction fields.  */ \
1115   UINT f_op1; \
1116   UINT f_r1; \
1117   UINT f_op2; \
1118   UINT f_r2; \
1119   int f_simm16; \
1120   unsigned int length;
1121 #define EXTRACT_FMT_SLL3_CODE \
1122   length = 4; \
1123   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1124   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1125   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1126   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1127   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1128
1129 #define EXTRACT_FMT_SLLI_VARS \
1130   /* Instruction fields.  */ \
1131   UINT f_op1; \
1132   UINT f_r1; \
1133   UINT f_shift_op2; \
1134   UINT f_uimm5; \
1135   unsigned int length;
1136 #define EXTRACT_FMT_SLLI_CODE \
1137   length = 2; \
1138   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1139   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1140   f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
1141   f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
1142
1143 #define EXTRACT_FMT_ST_VARS \
1144   /* Instruction fields.  */ \
1145   UINT f_op1; \
1146   UINT f_r1; \
1147   UINT f_op2; \
1148   UINT f_r2; \
1149   unsigned int length;
1150 #define EXTRACT_FMT_ST_CODE \
1151   length = 2; \
1152   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1153   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1154   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1155   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1156
1157 #define EXTRACT_FMT_ST_D_VARS \
1158   /* Instruction fields.  */ \
1159   UINT f_op1; \
1160   UINT f_r1; \
1161   UINT f_op2; \
1162   UINT f_r2; \
1163   int f_simm16; \
1164   unsigned int length;
1165 #define EXTRACT_FMT_ST_D_CODE \
1166   length = 4; \
1167   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1168   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1169   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1170   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1171   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1172
1173 #define EXTRACT_FMT_STB_VARS \
1174   /* Instruction fields.  */ \
1175   UINT f_op1; \
1176   UINT f_r1; \
1177   UINT f_op2; \
1178   UINT f_r2; \
1179   unsigned int length;
1180 #define EXTRACT_FMT_STB_CODE \
1181   length = 2; \
1182   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1183   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1184   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1185   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1186
1187 #define EXTRACT_FMT_STB_D_VARS \
1188   /* Instruction fields.  */ \
1189   UINT f_op1; \
1190   UINT f_r1; \
1191   UINT f_op2; \
1192   UINT f_r2; \
1193   int f_simm16; \
1194   unsigned int length;
1195 #define EXTRACT_FMT_STB_D_CODE \
1196   length = 4; \
1197   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1198   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1199   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1200   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1201   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1202
1203 #define EXTRACT_FMT_STH_VARS \
1204   /* Instruction fields.  */ \
1205   UINT f_op1; \
1206   UINT f_r1; \
1207   UINT f_op2; \
1208   UINT f_r2; \
1209   unsigned int length;
1210 #define EXTRACT_FMT_STH_CODE \
1211   length = 2; \
1212   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1213   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1214   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1215   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1216
1217 #define EXTRACT_FMT_STH_D_VARS \
1218   /* Instruction fields.  */ \
1219   UINT f_op1; \
1220   UINT f_r1; \
1221   UINT f_op2; \
1222   UINT f_r2; \
1223   int f_simm16; \
1224   unsigned int length;
1225 #define EXTRACT_FMT_STH_D_CODE \
1226   length = 4; \
1227   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1228   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1229   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1230   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1231   f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
1232
1233 #define EXTRACT_FMT_ST_PLUS_VARS \
1234   /* Instruction fields.  */ \
1235   UINT f_op1; \
1236   UINT f_r1; \
1237   UINT f_op2; \
1238   UINT f_r2; \
1239   unsigned int length;
1240 #define EXTRACT_FMT_ST_PLUS_CODE \
1241   length = 2; \
1242   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1243   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1244   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1245   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1246
1247 #define EXTRACT_FMT_TRAP_VARS \
1248   /* Instruction fields.  */ \
1249   UINT f_op1; \
1250   UINT f_r1; \
1251   UINT f_op2; \
1252   UINT f_uimm4; \
1253   unsigned int length;
1254 #define EXTRACT_FMT_TRAP_CODE \
1255   length = 2; \
1256   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1257   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1258   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1259   f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1260
1261 #define EXTRACT_FMT_UNLOCK_VARS \
1262   /* Instruction fields.  */ \
1263   UINT f_op1; \
1264   UINT f_r1; \
1265   UINT f_op2; \
1266   UINT f_r2; \
1267   unsigned int length;
1268 #define EXTRACT_FMT_UNLOCK_CODE \
1269   length = 2; \
1270   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1271   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1272   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1273   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1274
1275 #define EXTRACT_FMT_SATB_VARS \
1276   /* Instruction fields.  */ \
1277   UINT f_op1; \
1278   UINT f_r1; \
1279   UINT f_op2; \
1280   UINT f_r2; \
1281   UINT f_uimm16; \
1282   unsigned int length;
1283 #define EXTRACT_FMT_SATB_CODE \
1284   length = 4; \
1285   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1286   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1287   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1288   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1289   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1290
1291 #define EXTRACT_FMT_SAT_VARS \
1292   /* Instruction fields.  */ \
1293   UINT f_op1; \
1294   UINT f_r1; \
1295   UINT f_op2; \
1296   UINT f_r2; \
1297   UINT f_uimm16; \
1298   unsigned int length;
1299 #define EXTRACT_FMT_SAT_CODE \
1300   length = 4; \
1301   f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
1302   f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
1303   f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
1304   f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
1305   f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
1306
1307 #define EXTRACT_FMT_SADD_VARS \
1308   /* Instruction fields.  */ \
1309   UINT f_op1; \
1310   UINT f_r1; \
1311   UINT f_op2; \
1312   UINT f_r2; \
1313   unsigned int length;
1314 #define EXTRACT_FMT_SADD_CODE \
1315   length = 2; \
1316   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1317   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1318   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1319   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1320
1321 #define EXTRACT_FMT_MACWU1_VARS \
1322   /* Instruction fields.  */ \
1323   UINT f_op1; \
1324   UINT f_r1; \
1325   UINT f_op2; \
1326   UINT f_r2; \
1327   unsigned int length;
1328 #define EXTRACT_FMT_MACWU1_CODE \
1329   length = 2; \
1330   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1331   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1332   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1333   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1334
1335 #define EXTRACT_FMT_MSBLO_VARS \
1336   /* Instruction fields.  */ \
1337   UINT f_op1; \
1338   UINT f_r1; \
1339   UINT f_op2; \
1340   UINT f_r2; \
1341   unsigned int length;
1342 #define EXTRACT_FMT_MSBLO_CODE \
1343   length = 2; \
1344   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1345   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1346   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1347   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1348
1349 #define EXTRACT_FMT_MULWU1_VARS \
1350   /* Instruction fields.  */ \
1351   UINT f_op1; \
1352   UINT f_r1; \
1353   UINT f_op2; \
1354   UINT f_r2; \
1355   unsigned int length;
1356 #define EXTRACT_FMT_MULWU1_CODE \
1357   length = 2; \
1358   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1359   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1360   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1361   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1362
1363 #define EXTRACT_FMT_SC_VARS \
1364   /* Instruction fields.  */ \
1365   UINT f_op1; \
1366   UINT f_r1; \
1367   UINT f_op2; \
1368   UINT f_r2; \
1369   unsigned int length;
1370 #define EXTRACT_FMT_SC_CODE \
1371   length = 2; \
1372   f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
1373   f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
1374   f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
1375   f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
1376
1377 /* Fetched input values of an instruction.  */
1378
1379 struct parexec {
1380   union {
1381     struct { /* e.g. add $dr,$sr */
1382       SI dr;
1383       SI sr;
1384     } fmt_add;
1385     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
1386       SI sr;
1387       HI slo16;
1388     } fmt_add3;
1389     struct { /* e.g. and3 $dr,$sr,$uimm16 */
1390       SI sr;
1391       USI uimm16;
1392     } fmt_and3;
1393     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
1394       SI sr;
1395       UHI ulo16;
1396     } fmt_or3;
1397     struct { /* e.g. addi $dr,$simm8 */
1398       SI dr;
1399       SI simm8;
1400     } fmt_addi;
1401     struct { /* e.g. addv $dr,$sr */
1402       SI dr;
1403       SI sr;
1404     } fmt_addv;
1405     struct { /* e.g. addv3 $dr,$sr,$simm16 */
1406       SI sr;
1407       SI simm16;
1408     } fmt_addv3;
1409     struct { /* e.g. addx $dr,$sr */
1410       SI dr;
1411       SI sr;
1412       UBI condbit;
1413     } fmt_addx;
1414     struct { /* e.g. bc.s $disp8 */
1415       UBI condbit;
1416       USI disp8;
1417     } fmt_bc8;
1418     struct { /* e.g. bc.l $disp24 */
1419       UBI condbit;
1420       USI disp24;
1421     } fmt_bc24;
1422     struct { /* e.g. beq $src1,$src2,$disp16 */
1423       SI src1;
1424       SI src2;
1425       USI disp16;
1426     } fmt_beq;
1427     struct { /* e.g. beqz $src2,$disp16 */
1428       SI src2;
1429       USI disp16;
1430     } fmt_beqz;
1431     struct { /* e.g. bl.s $disp8 */
1432       USI pc;
1433       USI disp8;
1434     } fmt_bl8;
1435     struct { /* e.g. bl.l $disp24 */
1436       USI pc;
1437       USI disp24;
1438     } fmt_bl24;
1439     struct { /* e.g. bcl.s $disp8 */
1440       UBI condbit;
1441       USI pc;
1442       USI disp8;
1443     } fmt_bcl8;
1444     struct { /* e.g. bcl.l $disp24 */
1445       UBI condbit;
1446       USI pc;
1447       USI disp24;
1448     } fmt_bcl24;
1449     struct { /* e.g. bra.s $disp8 */
1450       USI disp8;
1451     } fmt_bra8;
1452     struct { /* e.g. bra.l $disp24 */
1453       USI disp24;
1454     } fmt_bra24;
1455     struct { /* e.g. cmp $src1,$src2 */
1456       SI src1;
1457       SI src2;
1458     } fmt_cmp;
1459     struct { /* e.g. cmpi $src2,$simm16 */
1460       SI src2;
1461       SI simm16;
1462     } fmt_cmpi;
1463     struct { /* e.g. cmpz $src2 */
1464       SI src2;
1465     } fmt_cmpz;
1466     struct { /* e.g. div $dr,$sr */
1467       SI dr;
1468       SI sr;
1469     } fmt_div;
1470     struct { /* e.g. jc $sr */
1471       UBI condbit;
1472       SI sr;
1473     } fmt_jc;
1474     struct { /* e.g. jl $sr */
1475       USI pc;
1476       SI sr;
1477     } fmt_jl;
1478     struct { /* e.g. jmp $sr */
1479       SI sr;
1480     } fmt_jmp;
1481     struct { /* e.g. ld $dr,@$sr */
1482       SI h_memory_sr;
1483       USI sr;
1484     } fmt_ld;
1485     struct { /* e.g. ld $dr,@($slo16,$sr) */
1486       SI h_memory_add__VM_sr_slo16;
1487       SI sr;
1488       HI slo16;
1489     } fmt_ld_d;
1490     struct { /* e.g. ldb $dr,@$sr */
1491       QI h_memory_sr;
1492       USI sr;
1493     } fmt_ldb;
1494     struct { /* e.g. ldb $dr,@($slo16,$sr) */
1495       QI h_memory_add__VM_sr_slo16;
1496       SI sr;
1497       HI slo16;
1498     } fmt_ldb_d;
1499     struct { /* e.g. ldh $dr,@$sr */
1500       HI h_memory_sr;
1501       USI sr;
1502     } fmt_ldh;
1503     struct { /* e.g. ldh $dr,@($slo16,$sr) */
1504       HI h_memory_add__VM_sr_slo16;
1505       SI sr;
1506       HI slo16;
1507     } fmt_ldh_d;
1508     struct { /* e.g. ld $dr,@$sr+ */
1509       SI h_memory_sr;
1510       SI sr;
1511     } fmt_ld_plus;
1512     struct { /* e.g. ld24 $dr,$uimm24 */
1513       USI uimm24;
1514     } fmt_ld24;
1515     struct { /* e.g. ldi8 $dr,$simm8 */
1516       SI simm8;
1517     } fmt_ldi8;
1518     struct { /* e.g. ldi16 $dr,$hash$slo16 */
1519       HI slo16;
1520     } fmt_ldi16;
1521     struct { /* e.g. lock $dr,@$sr */
1522       SI h_memory_sr;
1523       USI sr;
1524     } fmt_lock;
1525     struct { /* e.g. machi $src1,$src2,$acc */
1526       DI acc;
1527       SI src1;
1528       SI src2;
1529     } fmt_machi_a;
1530     struct { /* e.g. mulhi $src1,$src2,$acc */
1531       SI src1;
1532       SI src2;
1533     } fmt_mulhi_a;
1534     struct { /* e.g. mv $dr,$sr */
1535       SI sr;
1536     } fmt_mv;
1537     struct { /* e.g. mvfachi $dr,$accs */
1538       DI accs;
1539     } fmt_mvfachi_a;
1540     struct { /* e.g. mvfc $dr,$scr */
1541       USI scr;
1542     } fmt_mvfc;
1543     struct { /* e.g. mvtachi $src1,$accs */
1544       DI accs;
1545       SI src1;
1546     } fmt_mvtachi_a;
1547     struct { /* e.g. mvtc $sr,$dcr */
1548       SI sr;
1549     } fmt_mvtc;
1550     struct { /* e.g. nop */
1551       int empty;
1552     } fmt_nop;
1553     struct { /* e.g. rac $accd,$accs,$imm1 */
1554       DI accs;
1555       USI imm1;
1556     } fmt_rac_dsi;
1557     struct { /* e.g. rte */
1558       UBI h_bsm_0;
1559       UBI h_bie_0;
1560       UBI h_bcond_0;
1561       SI h_bpc_0;
1562     } fmt_rte;
1563     struct { /* e.g. seth $dr,$hash$hi16 */
1564       SI hi16;
1565     } fmt_seth;
1566     struct { /* e.g. sll3 $dr,$sr,$simm16 */
1567       SI sr;
1568       SI simm16;
1569     } fmt_sll3;
1570     struct { /* e.g. slli $dr,$uimm5 */
1571       SI dr;
1572       USI uimm5;
1573     } fmt_slli;
1574     struct { /* e.g. st $src1,@$src2 */
1575       USI src2;
1576       SI src1;
1577     } fmt_st;
1578     struct { /* e.g. st $src1,@($slo16,$src2) */
1579       SI src2;
1580       HI slo16;
1581       SI src1;
1582     } fmt_st_d;
1583     struct { /* e.g. stb $src1,@$src2 */
1584       USI src2;
1585       QI src1;
1586     } fmt_stb;
1587     struct { /* e.g. stb $src1,@($slo16,$src2) */
1588       SI src2;
1589       HI slo16;
1590       QI src1;
1591     } fmt_stb_d;
1592     struct { /* e.g. sth $src1,@$src2 */
1593       USI src2;
1594       HI src1;
1595     } fmt_sth;
1596     struct { /* e.g. sth $src1,@($slo16,$src2) */
1597       SI src2;
1598       HI slo16;
1599       HI src1;
1600     } fmt_sth_d;
1601     struct { /* e.g. st $src1,@+$src2 */
1602       SI src2;
1603       SI src1;
1604     } fmt_st_plus;
1605     struct { /* e.g. trap $uimm4 */
1606       USI h_cr_0;
1607       SI pc;
1608       SI uimm4;
1609     } fmt_trap;
1610     struct { /* e.g. unlock $src1,@$src2 */
1611       UBI h_lock_0;
1612       USI src2;
1613       SI src1;
1614     } fmt_unlock;
1615     struct { /* e.g. satb $dr,$sr */
1616       SI sr;
1617     } fmt_satb;
1618     struct { /* e.g. sat $dr,$sr */
1619       UBI condbit;
1620       SI sr;
1621     } fmt_sat;
1622     struct { /* e.g. sadd */
1623       DI h_accums_1;
1624       DI h_accums_0;
1625     } fmt_sadd;
1626     struct { /* e.g. macwu1 $src1,$src2 */
1627       DI h_accums_1;
1628       SI src1;
1629       SI src2;
1630     } fmt_macwu1;
1631     struct { /* e.g. msblo $src1,$src2 */
1632       DI accum;
1633       SI src1;
1634       SI src2;
1635     } fmt_msblo;
1636     struct { /* e.g. mulwu1 $src1,$src2 */
1637       SI src1;
1638       SI src2;
1639     } fmt_mulwu1;
1640     struct { /* e.g. sc */
1641       UBI condbit;
1642     } fmt_sc;
1643   } operands;
1644 };
1645
1646 #endif /* CPU_M32RX_H */