sim/m32r/decode.c

   1 /* Simulator instruction decoder for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #define WANT_CPU m32rbf
  26 #define WANT_CPU_M32RBF
  27
  28 #include "sim-main.h"
  29 #include "sim-assert.h"
  30
  31 /* The instruction descriptor array.
  32    This is computed at runtime.  Space for it is not malloc'd to save a
  33    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
  34    but won't be done until necessary (we don't currently support the runtime
  35    addition of instructions nor an SMP machine with different cpus).  */
  36 static IDESC m32rbf_insn_data[M32RBF_INSN_MAX];
  37
  38 /* Commas between elements are contained in the macros.
  39    Some of these are conditionally compiled out.  */
  40
  41 static const struct insn_sem m32rbf_insn_sem[] =
  42 {
  43   { VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY },
  44   { VIRTUAL_INSN_X_AFTER, M32RBF_INSN_X_AFTER, M32RBF_SFMT_EMPTY },
  45   { VIRTUAL_INSN_X_BEFORE, M32RBF_INSN_X_BEFORE, M32RBF_SFMT_EMPTY },
  46   { VIRTUAL_INSN_X_CTI_CHAIN, M32RBF_INSN_X_CTI_CHAIN, M32RBF_SFMT_EMPTY },
  47   { VIRTUAL_INSN_X_CHAIN, M32RBF_INSN_X_CHAIN, M32RBF_SFMT_EMPTY },
  48   { VIRTUAL_INSN_X_BEGIN, M32RBF_INSN_X_BEGIN, M32RBF_SFMT_EMPTY },
  49   { M32R_INSN_ADD, M32RBF_INSN_ADD, M32RBF_SFMT_ADD },
  50   { M32R_INSN_ADD3, M32RBF_INSN_ADD3, M32RBF_SFMT_ADD3 },
  51   { M32R_INSN_AND, M32RBF_INSN_AND, M32RBF_SFMT_ADD },
  52   { M32R_INSN_AND3, M32RBF_INSN_AND3, M32RBF_SFMT_AND3 },
  53   { M32R_INSN_OR, M32RBF_INSN_OR, M32RBF_SFMT_ADD },
  54   { M32R_INSN_OR3, M32RBF_INSN_OR3, M32RBF_SFMT_OR3 },
  55   { M32R_INSN_XOR, M32RBF_INSN_XOR, M32RBF_SFMT_ADD },
  56   { M32R_INSN_XOR3, M32RBF_INSN_XOR3, M32RBF_SFMT_AND3 },
  57   { M32R_INSN_ADDI, M32RBF_INSN_ADDI, M32RBF_SFMT_ADDI },
  58   { M32R_INSN_ADDV, M32RBF_INSN_ADDV, M32RBF_SFMT_ADDV },
  59   { M32R_INSN_ADDV3, M32RBF_INSN_ADDV3, M32RBF_SFMT_ADDV3 },
  60   { M32R_INSN_ADDX, M32RBF_INSN_ADDX, M32RBF_SFMT_ADDX },
  61   { M32R_INSN_BC8, M32RBF_INSN_BC8, M32RBF_SFMT_BC8 },
  62   { M32R_INSN_BC24, M32RBF_INSN_BC24, M32RBF_SFMT_BC24 },
  63   { M32R_INSN_BEQ, M32RBF_INSN_BEQ, M32RBF_SFMT_BEQ },
  64   { M32R_INSN_BEQZ, M32RBF_INSN_BEQZ, M32RBF_SFMT_BEQZ },
  65   { M32R_INSN_BGEZ, M32RBF_INSN_BGEZ, M32RBF_SFMT_BEQZ },
  66   { M32R_INSN_BGTZ, M32RBF_INSN_BGTZ, M32RBF_SFMT_BEQZ },
  67   { M32R_INSN_BLEZ, M32RBF_INSN_BLEZ, M32RBF_SFMT_BEQZ },
  68   { M32R_INSN_BLTZ, M32RBF_INSN_BLTZ, M32RBF_SFMT_BEQZ },
  69   { M32R_INSN_BNEZ, M32RBF_INSN_BNEZ, M32RBF_SFMT_BEQZ },
  70   { M32R_INSN_BL8, M32RBF_INSN_BL8, M32RBF_SFMT_BL8 },
  71   { M32R_INSN_BL24, M32RBF_INSN_BL24, M32RBF_SFMT_BL24 },
  72   { M32R_INSN_BNC8, M32RBF_INSN_BNC8, M32RBF_SFMT_BC8 },
  73   { M32R_INSN_BNC24, M32RBF_INSN_BNC24, M32RBF_SFMT_BC24 },
  74   { M32R_INSN_BNE, M32RBF_INSN_BNE, M32RBF_SFMT_BEQ },
  75   { M32R_INSN_BRA8, M32RBF_INSN_BRA8, M32RBF_SFMT_BRA8 },
  76   { M32R_INSN_BRA24, M32RBF_INSN_BRA24, M32RBF_SFMT_BRA24 },
  77   { M32R_INSN_CMP, M32RBF_INSN_CMP, M32RBF_SFMT_CMP },
  78   { M32R_INSN_CMPI, M32RBF_INSN_CMPI, M32RBF_SFMT_CMPI },
  79   { M32R_INSN_CMPU, M32RBF_INSN_CMPU, M32RBF_SFMT_CMP },
  80   { M32R_INSN_CMPUI, M32RBF_INSN_CMPUI, M32RBF_SFMT_CMPI },
  81   { M32R_INSN_DIV, M32RBF_INSN_DIV, M32RBF_SFMT_DIV },
  82   { M32R_INSN_DIVU, M32RBF_INSN_DIVU, M32RBF_SFMT_DIV },
  83   { M32R_INSN_REM, M32RBF_INSN_REM, M32RBF_SFMT_DIV },
  84   { M32R_INSN_REMU, M32RBF_INSN_REMU, M32RBF_SFMT_DIV },
  85   { M32R_INSN_JL, M32RBF_INSN_JL, M32RBF_SFMT_JL },
  86   { M32R_INSN_JMP, M32RBF_INSN_JMP, M32RBF_SFMT_JMP },
  87   { M32R_INSN_LD, M32RBF_INSN_LD, M32RBF_SFMT_LD },
  88   { M32R_INSN_LD_D, M32RBF_INSN_LD_D, M32RBF_SFMT_LD_D },
  89   { M32R_INSN_LDB, M32RBF_INSN_LDB, M32RBF_SFMT_LD },
  90   { M32R_INSN_LDB_D, M32RBF_INSN_LDB_D, M32RBF_SFMT_LD_D },
  91   { M32R_INSN_LDH, M32RBF_INSN_LDH, M32RBF_SFMT_LD },
  92   { M32R_INSN_LDH_D, M32RBF_INSN_LDH_D, M32RBF_SFMT_LD_D },
  93   { M32R_INSN_LDUB, M32RBF_INSN_LDUB, M32RBF_SFMT_LD },
  94   { M32R_INSN_LDUB_D, M32RBF_INSN_LDUB_D, M32RBF_SFMT_LD_D },
  95   { M32R_INSN_LDUH, M32RBF_INSN_LDUH, M32RBF_SFMT_LD },
  96   { M32R_INSN_LDUH_D, M32RBF_INSN_LDUH_D, M32RBF_SFMT_LD_D },
  97   { M32R_INSN_LD_PLUS, M32RBF_INSN_LD_PLUS, M32RBF_SFMT_LD_PLUS },
  98   { M32R_INSN_LD24, M32RBF_INSN_LD24, M32RBF_SFMT_LD24 },
  99   { M32R_INSN_LDI8, M32RBF_INSN_LDI8, M32RBF_SFMT_LDI8 },
 100   { M32R_INSN_LDI16, M32RBF_INSN_LDI16, M32RBF_SFMT_LDI16 },
 101   { M32R_INSN_LOCK, M32RBF_INSN_LOCK, M32RBF_SFMT_LOCK },
 102   { M32R_INSN_MACHI, M32RBF_INSN_MACHI, M32RBF_SFMT_MACHI },
 103   { M32R_INSN_MACLO, M32RBF_INSN_MACLO, M32RBF_SFMT_MACHI },
 104   { M32R_INSN_MACWHI, M32RBF_INSN_MACWHI, M32RBF_SFMT_MACHI },
 105   { M32R_INSN_MACWLO, M32RBF_INSN_MACWLO, M32RBF_SFMT_MACHI },
 106   { M32R_INSN_MUL, M32RBF_INSN_MUL, M32RBF_SFMT_ADD },
 107   { M32R_INSN_MULHI, M32RBF_INSN_MULHI, M32RBF_SFMT_MULHI },
 108   { M32R_INSN_MULLO, M32RBF_INSN_MULLO, M32RBF_SFMT_MULHI },
 109   { M32R_INSN_MULWHI, M32RBF_INSN_MULWHI, M32RBF_SFMT_MULHI },
 110   { M32R_INSN_MULWLO, M32RBF_INSN_MULWLO, M32RBF_SFMT_MULHI },
 111   { M32R_INSN_MV, M32RBF_INSN_MV, M32RBF_SFMT_MV },
 112   { M32R_INSN_MVFACHI, M32RBF_INSN_MVFACHI, M32RBF_SFMT_MVFACHI },
 113   { M32R_INSN_MVFACLO, M32RBF_INSN_MVFACLO, M32RBF_SFMT_MVFACHI },
 114   { M32R_INSN_MVFACMI, M32RBF_INSN_MVFACMI, M32RBF_SFMT_MVFACHI },
 115   { M32R_INSN_MVFC, M32RBF_INSN_MVFC, M32RBF_SFMT_MVFC },
 116   { M32R_INSN_MVTACHI, M32RBF_INSN_MVTACHI, M32RBF_SFMT_MVTACHI },
 117   { M32R_INSN_MVTACLO, M32RBF_INSN_MVTACLO, M32RBF_SFMT_MVTACHI },
 118   { M32R_INSN_MVTC, M32RBF_INSN_MVTC, M32RBF_SFMT_MVTC },
 119   { M32R_INSN_NEG, M32RBF_INSN_NEG, M32RBF_SFMT_MV },
 120   { M32R_INSN_NOP, M32RBF_INSN_NOP, M32RBF_SFMT_NOP },
 121   { M32R_INSN_NOT, M32RBF_INSN_NOT, M32RBF_SFMT_MV },
 122   { M32R_INSN_RAC, M32RBF_INSN_RAC, M32RBF_SFMT_RAC },
 123   { M32R_INSN_RACH, M32RBF_INSN_RACH, M32RBF_SFMT_RAC },
 124   { M32R_INSN_RTE, M32RBF_INSN_RTE, M32RBF_SFMT_RTE },
 125   { M32R_INSN_SETH, M32RBF_INSN_SETH, M32RBF_SFMT_SETH },
 126   { M32R_INSN_SLL, M32RBF_INSN_SLL, M32RBF_SFMT_ADD },
 127   { M32R_INSN_SLL3, M32RBF_INSN_SLL3, M32RBF_SFMT_SLL3 },
 128   { M32R_INSN_SLLI, M32RBF_INSN_SLLI, M32RBF_SFMT_SLLI },
 129   { M32R_INSN_SRA, M32RBF_INSN_SRA, M32RBF_SFMT_ADD },
 130   { M32R_INSN_SRA3, M32RBF_INSN_SRA3, M32RBF_SFMT_SLL3 },
 131   { M32R_INSN_SRAI, M32RBF_INSN_SRAI, M32RBF_SFMT_SLLI },
 132   { M32R_INSN_SRL, M32RBF_INSN_SRL, M32RBF_SFMT_ADD },
 133   { M32R_INSN_SRL3, M32RBF_INSN_SRL3, M32RBF_SFMT_SLL3 },
 134   { M32R_INSN_SRLI, M32RBF_INSN_SRLI, M32RBF_SFMT_SLLI },
 135   { M32R_INSN_ST, M32RBF_INSN_ST, M32RBF_SFMT_ST },
 136   { M32R_INSN_ST_D, M32RBF_INSN_ST_D, M32RBF_SFMT_ST_D },
 137   { M32R_INSN_STB, M32RBF_INSN_STB, M32RBF_SFMT_STB },
 138   { M32R_INSN_STB_D, M32RBF_INSN_STB_D, M32RBF_SFMT_STB_D },
 139   { M32R_INSN_STH, M32RBF_INSN_STH, M32RBF_SFMT_STH },
 140   { M32R_INSN_STH_D, M32RBF_INSN_STH_D, M32RBF_SFMT_STH_D },
 141   { M32R_INSN_ST_PLUS, M32RBF_INSN_ST_PLUS, M32RBF_SFMT_ST_PLUS },
 142   { M32R_INSN_ST_MINUS, M32RBF_INSN_ST_MINUS, M32RBF_SFMT_ST_PLUS },
 143   { M32R_INSN_SUB, M32RBF_INSN_SUB, M32RBF_SFMT_ADD },
 144   { M32R_INSN_SUBV, M32RBF_INSN_SUBV, M32RBF_SFMT_ADDV },
 145   { M32R_INSN_SUBX, M32RBF_INSN_SUBX, M32RBF_SFMT_ADDX },
 146   { M32R_INSN_TRAP, M32RBF_INSN_TRAP, M32RBF_SFMT_TRAP },
 147   { M32R_INSN_UNLOCK, M32RBF_INSN_UNLOCK, M32RBF_SFMT_UNLOCK },
 148 };
 149
 150 static const struct insn_sem m32rbf_insn_sem_invalid = {
 151   VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY
 152 };
 153
 154 /* Initialize an IDESC from the compile-time computable parts.  */
 155
 156 static INLINE void
 157 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
 158 {
 159   const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
 160
 161   id->num = t->index;
 162   id->sfmt = t->sfmt;
 163   if ((int) t->type <= 0)
 164     id->idata = & cgen_virtual_insn_table[- (int) t->type];
 165   else
 166     id->idata = & insn_table[t->type];
 167   id->attrs = CGEN_INSN_ATTRS (id->idata);
 168   /* Oh my god, a magic number.  */
 169   id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
 170
 171 #if WITH_PROFILE_MODEL_P
 172   id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
 173   {
 174     SIM_DESC sd = CPU_STATE (cpu);
 175     SIM_ASSERT (t->index == id->timing->num);
 176   }
 177 #endif
 178
 179   /* Semantic pointers are initialized elsewhere.  */
 180 }
 181
 182 /* Initialize the instruction descriptor table.  */
 183
 184 void
 185 m32rbf_init_idesc_table (SIM_CPU *cpu)
 186 {
 187   IDESC *id,*tabend;
 188   const struct insn_sem *t,*tend;
 189   int tabsize = M32RBF_INSN_MAX;
 190   IDESC *table = m32rbf_insn_data;
 191
 192   memset (table, 0, tabsize * sizeof (IDESC));
 193
 194   /* First set all entries to the `invalid insn'.  */
 195   t = & m32rbf_insn_sem_invalid;
 196   for (id = table, tabend = table + tabsize; id < tabend; ++id)
 197     init_idesc (cpu, id, t);
 198
 199   /* Now fill in the values for the chosen cpu.  */
 200   for (t = m32rbf_insn_sem, tend = t + sizeof (m32rbf_insn_sem) / sizeof (*t);
 201        t != tend; ++t)
 202     {
 203       init_idesc (cpu, & table[t->index], t);
 204     }
 205
 206   /* Link the IDESC table into the cpu.  */
 207   CPU_IDESC (cpu) = table;
 208 }
 209
 210 /* Given an instruction, return a pointer to its IDESC entry.  */
 211
 212 const IDESC *
 213 m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
 214               CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
 215               ARGBUF *abuf)
 216 {
 217   /* Result of decoder.  */
 218   M32RBF_INSN_TYPE itype;
 219
 220   {
 221     CGEN_INSN_INT insn = base_insn;
 222
 223     {
 224       unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
 225       switch (val)
 226       {
 227       case 0 : itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv;
 228       case 1 : itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx;
 229       case 2 : itype = M32RBF_INSN_SUB; goto extract_sfmt_add;
 230       case 3 : itype = M32RBF_INSN_NEG; goto extract_sfmt_mv;
 231       case 4 : itype = M32RBF_INSN_CMP; goto extract_sfmt_cmp;
 232       case 5 : itype = M32RBF_INSN_CMPU; goto extract_sfmt_cmp;
 233       case 8 : itype = M32RBF_INSN_ADDV; goto extract_sfmt_addv;
 234       case 9 : itype = M32RBF_INSN_ADDX; goto extract_sfmt_addx;
 235       case 10 : itype = M32RBF_INSN_ADD; goto extract_sfmt_add;
 236       case 11 : itype = M32RBF_INSN_NOT; goto extract_sfmt_mv;
 237       case 12 : itype = M32RBF_INSN_AND; goto extract_sfmt_add;
 238       case 13 : itype = M32RBF_INSN_XOR; goto extract_sfmt_add;
 239       case 14 : itype = M32RBF_INSN_OR; goto extract_sfmt_add;
 240       case 16 : itype = M32RBF_INSN_SRL; goto extract_sfmt_add;
 241       case 18 : itype = M32RBF_INSN_SRA; goto extract_sfmt_add;
 242       case 20 : itype = M32RBF_INSN_SLL; goto extract_sfmt_add;
 243       case 22 : itype = M32RBF_INSN_MUL; goto extract_sfmt_add;
 244       case 24 : itype = M32RBF_INSN_MV; goto extract_sfmt_mv;
 245       case 25 : itype = M32RBF_INSN_MVFC; goto extract_sfmt_mvfc;
 246       case 26 : itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc;
 247       case 28 :
 248         {
 249           unsigned int val = (((insn >> 8) & (15 << 0)));
 250           switch (val)
 251           {
 252           case 14 : itype = M32RBF_INSN_JL; goto extract_sfmt_jl;
 253           case 15 : itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp;
 254           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 255           }
 256         }
 257       case 29 : itype = M32RBF_INSN_RTE; goto extract_sfmt_rte;
 258       case 31 : itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap;
 259       case 32 : itype = M32RBF_INSN_STB; goto extract_sfmt_stb;
 260       case 34 : itype = M32RBF_INSN_STH; goto extract_sfmt_sth;
 261       case 36 : itype = M32RBF_INSN_ST; goto extract_sfmt_st;
 262       case 37 : itype = M32RBF_INSN_UNLOCK; goto extract_sfmt_unlock;
 263       case 38 : itype = M32RBF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
 264       case 39 : itype = M32RBF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
 265       case 40 : itype = M32RBF_INSN_LDB; goto extract_sfmt_ld;
 266       case 41 : itype = M32RBF_INSN_LDUB; goto extract_sfmt_ld;
 267       case 42 : itype = M32RBF_INSN_LDH; goto extract_sfmt_ld;
 268       case 43 : itype = M32RBF_INSN_LDUH; goto extract_sfmt_ld;
 269       case 44 : itype = M32RBF_INSN_LD; goto extract_sfmt_ld;
 270       case 45 : itype = M32RBF_INSN_LOCK; goto extract_sfmt_lock;
 271       case 46 : itype = M32RBF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
 272       case 48 : itype = M32RBF_INSN_MULHI; goto extract_sfmt_mulhi;
 273       case 49 : itype = M32RBF_INSN_MULLO; goto extract_sfmt_mulhi;
 274       case 50 : itype = M32RBF_INSN_MULWHI; goto extract_sfmt_mulhi;
 275       case 51 : itype = M32RBF_INSN_MULWLO; goto extract_sfmt_mulhi;
 276       case 52 : itype = M32RBF_INSN_MACHI; goto extract_sfmt_machi;
 277       case 53 : itype = M32RBF_INSN_MACLO; goto extract_sfmt_machi;
 278       case 54 : itype = M32RBF_INSN_MACWHI; goto extract_sfmt_machi;
 279       case 55 : itype = M32RBF_INSN_MACWLO; goto extract_sfmt_machi;
 280       case 64 : /* fall through */
 281       case 65 : /* fall through */
 282       case 66 : /* fall through */
 283       case 67 : /* fall through */
 284       case 68 : /* fall through */
 285       case 69 : /* fall through */
 286       case 70 : /* fall through */
 287       case 71 : /* fall through */
 288       case 72 : /* fall through */
 289       case 73 : /* fall through */
 290       case 74 : /* fall through */
 291       case 75 : /* fall through */
 292       case 76 : /* fall through */
 293       case 77 : /* fall through */
 294       case 78 : /* fall through */
 295       case 79 : itype = M32RBF_INSN_ADDI; goto extract_sfmt_addi;
 296       case 80 : /* fall through */
 297       case 81 : itype = M32RBF_INSN_SRLI; goto extract_sfmt_slli;
 298       case 82 : /* fall through */
 299       case 83 : itype = M32RBF_INSN_SRAI; goto extract_sfmt_slli;
 300       case 84 : /* fall through */
 301       case 85 : itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli;
 302       case 87 :
 303         {
 304           unsigned int val = (((insn >> 0) & (15 << 0)));
 305           switch (val)
 306           {
 307           case 0 : itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi;
 308           case 1 : itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi;
 309           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 310           }
 311         }
 312       case 88 : itype = M32RBF_INSN_RACH; goto extract_sfmt_rac;
 313       case 89 : itype = M32RBF_INSN_RAC; goto extract_sfmt_rac;
 314       case 95 :
 315         {
 316           unsigned int val = (((insn >> 0) & (15 << 0)));
 317           switch (val)
 318           {
 319           case 0 : itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi;
 320           case 1 : itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi;
 321           case 2 : itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi;
 322           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 323           }
 324         }
 325       case 96 : /* fall through */
 326       case 97 : /* fall through */
 327       case 98 : /* fall through */
 328       case 99 : /* fall through */
 329       case 100 : /* fall through */
 330       case 101 : /* fall through */
 331       case 102 : /* fall through */
 332       case 103 : /* fall through */
 333       case 104 : /* fall through */
 334       case 105 : /* fall through */
 335       case 106 : /* fall through */
 336       case 107 : /* fall through */
 337       case 108 : /* fall through */
 338       case 109 : /* fall through */
 339       case 110 : /* fall through */
 340       case 111 : itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8;
 341       case 112 :
 342         {
 343           unsigned int val = (((insn >> 8) & (15 << 0)));
 344           switch (val)
 345           {
 346           case 0 : itype = M32RBF_INSN_NOP; goto extract_sfmt_nop;
 347           case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
 348           case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
 349           case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
 350           case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
 351           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 352           }
 353         }
 354       case 113 : /* fall through */
 355       case 114 : /* fall through */
 356       case 115 : /* fall through */
 357       case 116 : /* fall through */
 358       case 117 : /* fall through */
 359       case 118 : /* fall through */
 360       case 119 : /* fall through */
 361       case 120 : /* fall through */
 362       case 121 : /* fall through */
 363       case 122 : /* fall through */
 364       case 123 : /* fall through */
 365       case 124 : /* fall through */
 366       case 125 : /* fall through */
 367       case 126 : /* fall through */
 368       case 127 :
 369         {
 370           unsigned int val = (((insn >> 8) & (15 << 0)));
 371           switch (val)
 372           {
 373           case 12 : itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
 374           case 13 : itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
 375           case 14 : itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
 376           case 15 : itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
 377           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 378           }
 379         }
 380       case 132 : itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi;
 381       case 133 : itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi;
 382       case 136 : itype = M32RBF_INSN_ADDV3; goto extract_sfmt_addv3;
 383       case 138 : itype = M32RBF_INSN_ADD3; goto extract_sfmt_add3;
 384       case 140 : itype = M32RBF_INSN_AND3; goto extract_sfmt_and3;
 385       case 141 : itype = M32RBF_INSN_XOR3; goto extract_sfmt_and3;
 386       case 142 : itype = M32RBF_INSN_OR3; goto extract_sfmt_or3;
 387       case 144 : itype = M32RBF_INSN_DIV; goto extract_sfmt_div;
 388       case 145 : itype = M32RBF_INSN_DIVU; goto extract_sfmt_div;
 389       case 146 : itype = M32RBF_INSN_REM; goto extract_sfmt_div;
 390       case 147 : itype = M32RBF_INSN_REMU; goto extract_sfmt_div;
 391       case 152 : itype = M32RBF_INSN_SRL3; goto extract_sfmt_sll3;
 392       case 154 : itype = M32RBF_INSN_SRA3; goto extract_sfmt_sll3;
 393       case 156 : itype = M32RBF_INSN_SLL3; goto extract_sfmt_sll3;
 394       case 159 : itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16;
 395       case 160 : itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d;
 396       case 162 : itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d;
 397       case 164 : itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d;
 398       case 168 : itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ld_d;
 399       case 169 : itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ld_d;
 400       case 170 : itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ld_d;
 401       case 171 : itype = M32RBF_INSN_LDUH_D; goto extract_sfmt_ld_d;
 402       case 172 : itype = M32RBF_INSN_LD_D; goto extract_sfmt_ld_d;
 403       case 176 : itype = M32RBF_INSN_BEQ; goto extract_sfmt_beq;
 404       case 177 : itype = M32RBF_INSN_BNE; goto extract_sfmt_beq;
 405       case 184 : itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz;
 406       case 185 : itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz;
 407       case 186 : itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz;
 408       case 187 : itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz;
 409       case 188 : itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz;
 410       case 189 : itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz;
 411       case 220 : itype = M32RBF_INSN_SETH; goto extract_sfmt_seth;
 412       case 224 : /* fall through */
 413       case 225 : /* fall through */
 414       case 226 : /* fall through */
 415       case 227 : /* fall through */
 416       case 228 : /* fall through */
 417       case 229 : /* fall through */
 418       case 230 : /* fall through */
 419       case 231 : /* fall through */
 420       case 232 : /* fall through */
 421       case 233 : /* fall through */
 422       case 234 : /* fall through */
 423       case 235 : /* fall through */
 424       case 236 : /* fall through */
 425       case 237 : /* fall through */
 426       case 238 : /* fall through */
 427       case 239 : itype = M32RBF_INSN_LD24; goto extract_sfmt_ld24;
 428       case 240 : /* fall through */
 429       case 241 : /* fall through */
 430       case 242 : /* fall through */
 431       case 243 : /* fall through */
 432       case 244 : /* fall through */
 433       case 245 : /* fall through */
 434       case 246 : /* fall through */
 435       case 247 : /* fall through */
 436       case 248 : /* fall through */
 437       case 249 : /* fall through */
 438       case 250 : /* fall through */
 439       case 251 : /* fall through */
 440       case 252 : /* fall through */
 441       case 253 : /* fall through */
 442       case 254 : /* fall through */
 443       case 255 :
 444         {
 445           unsigned int val = (((insn >> 8) & (15 << 0)));
 446           switch (val)
 447           {
 448           case 12 : itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24;
 449           case 13 : itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24;
 450           case 14 : itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24;
 451           case 15 : itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24;
 452           default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 453           }
 454         }
 455       default : itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 456       }
 457     }
 458   }
 459
 460   /* The instruction has been decoded, now extract the fields.  */
 461
 462  extract_sfmt_empty:
 463   {
 464     const IDESC *idesc = &m32rbf_insn_data[itype];
 465     CGEN_INSN_INT insn = entire_insn;
 466 #define FLD(f) abuf->fields.fmt_empty.f
 467
 468
 469   /* Record the fields for the semantic handler.  */
 470   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
 471
 472 #undef FLD
 473     return idesc;
 474   }
 475
 476  extract_sfmt_add:
 477   {
 478     const IDESC *idesc = &m32rbf_insn_data[itype];
 479     CGEN_INSN_INT insn = entire_insn;
 480 #define FLD(f) abuf->fields.sfmt_add.f
 481     UINT f_r1;
 482     UINT f_r2;
 483
 484     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 485     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 486
 487   /* Record the fields for the semantic handler.  */
 488   FLD (i_dr) = & CPU (h_gr)[f_r1];
 489   FLD (i_sr) = & CPU (h_gr)[f_r2];
 490   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 491
 492 #if WITH_PROFILE_MODEL_P
 493   /* Record the fields for profiling.  */
 494   if (PROFILE_MODEL_P (current_cpu))
 495     {
 496       FLD (in_dr) = f_r1;
 497       FLD (in_sr) = f_r2;
 498       FLD (out_dr) = f_r1;
 499     }
 500 #endif
 501 #undef FLD
 502     return idesc;
 503   }
 504
 505  extract_sfmt_add3:
 506   {
 507     const IDESC *idesc = &m32rbf_insn_data[itype];
 508     CGEN_INSN_INT insn = entire_insn;
 509 #define FLD(f) abuf->fields.sfmt_add3.f
 510     UINT f_r1;
 511     UINT f_r2;
 512     INT f_simm16;
 513
 514     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 515     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 516     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 517
 518   /* Record the fields for the semantic handler.  */
 519   FLD (f_simm16) = f_simm16;
 520   FLD (i_sr) = & CPU (h_gr)[f_r2];
 521   FLD (i_dr) = & CPU (h_gr)[f_r1];
 522   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 523
 524 #if WITH_PROFILE_MODEL_P
 525   /* Record the fields for profiling.  */
 526   if (PROFILE_MODEL_P (current_cpu))
 527     {
 528       FLD (in_sr) = f_r2;
 529       FLD (out_dr) = f_r1;
 530     }
 531 #endif
 532 #undef FLD
 533     return idesc;
 534   }
 535
 536  extract_sfmt_and3:
 537   {
 538     const IDESC *idesc = &m32rbf_insn_data[itype];
 539     CGEN_INSN_INT insn = entire_insn;
 540 #define FLD(f) abuf->fields.sfmt_and3.f
 541     UINT f_r1;
 542     UINT f_r2;
 543     UINT f_uimm16;
 544
 545     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 546     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 547     f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
 548
 549   /* Record the fields for the semantic handler.  */
 550   FLD (f_uimm16) = f_uimm16;
 551   FLD (i_sr) = & CPU (h_gr)[f_r2];
 552   FLD (i_dr) = & CPU (h_gr)[f_r1];
 553   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 554
 555 #if WITH_PROFILE_MODEL_P
 556   /* Record the fields for profiling.  */
 557   if (PROFILE_MODEL_P (current_cpu))
 558     {
 559       FLD (in_sr) = f_r2;
 560       FLD (out_dr) = f_r1;
 561     }
 562 #endif
 563 #undef FLD
 564     return idesc;
 565   }
 566
 567  extract_sfmt_or3:
 568   {
 569     const IDESC *idesc = &m32rbf_insn_data[itype];
 570     CGEN_INSN_INT insn = entire_insn;
 571 #define FLD(f) abuf->fields.sfmt_and3.f
 572     UINT f_r1;
 573     UINT f_r2;
 574     UINT f_uimm16;
 575
 576     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 577     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 578     f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
 579
 580   /* Record the fields for the semantic handler.  */
 581   FLD (f_uimm16) = f_uimm16;
 582   FLD (i_sr) = & CPU (h_gr)[f_r2];
 583   FLD (i_dr) = & CPU (h_gr)[f_r1];
 584   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 585
 586 #if WITH_PROFILE_MODEL_P
 587   /* Record the fields for profiling.  */
 588   if (PROFILE_MODEL_P (current_cpu))
 589     {
 590       FLD (in_sr) = f_r2;
 591       FLD (out_dr) = f_r1;
 592     }
 593 #endif
 594 #undef FLD
 595     return idesc;
 596   }
 597
 598  extract_sfmt_addi:
 599   {
 600     const IDESC *idesc = &m32rbf_insn_data[itype];
 601     CGEN_INSN_INT insn = entire_insn;
 602 #define FLD(f) abuf->fields.sfmt_addi.f
 603     UINT f_r1;
 604     INT f_simm8;
 605
 606     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 607     f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
 608
 609   /* Record the fields for the semantic handler.  */
 610   FLD (f_simm8) = f_simm8;
 611   FLD (i_dr) = & CPU (h_gr)[f_r1];
 612   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
 613
 614 #if WITH_PROFILE_MODEL_P
 615   /* Record the fields for profiling.  */
 616   if (PROFILE_MODEL_P (current_cpu))
 617     {
 618       FLD (in_dr) = f_r1;
 619       FLD (out_dr) = f_r1;
 620     }
 621 #endif
 622 #undef FLD
 623     return idesc;
 624   }
 625
 626  extract_sfmt_addv:
 627   {
 628     const IDESC *idesc = &m32rbf_insn_data[itype];
 629     CGEN_INSN_INT insn = entire_insn;
 630 #define FLD(f) abuf->fields.sfmt_add.f
 631     UINT f_r1;
 632     UINT f_r2;
 633
 634     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 635     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 636
 637   /* Record the fields for the semantic handler.  */
 638   FLD (i_dr) = & CPU (h_gr)[f_r1];
 639   FLD (i_sr) = & CPU (h_gr)[f_r2];
 640   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 641
 642 #if WITH_PROFILE_MODEL_P
 643   /* Record the fields for profiling.  */
 644   if (PROFILE_MODEL_P (current_cpu))
 645     {
 646       FLD (in_dr) = f_r1;
 647       FLD (in_sr) = f_r2;
 648       FLD (out_dr) = f_r1;
 649     }
 650 #endif
 651 #undef FLD
 652     return idesc;
 653   }
 654
 655  extract_sfmt_addv3:
 656   {
 657     const IDESC *idesc = &m32rbf_insn_data[itype];
 658     CGEN_INSN_INT insn = entire_insn;
 659 #define FLD(f) abuf->fields.sfmt_add3.f
 660     UINT f_r1;
 661     UINT f_r2;
 662     INT f_simm16;
 663
 664     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 665     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 666     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 667
 668   /* Record the fields for the semantic handler.  */
 669   FLD (f_simm16) = f_simm16;
 670   FLD (i_sr) = & CPU (h_gr)[f_r2];
 671   FLD (i_dr) = & CPU (h_gr)[f_r1];
 672   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 673
 674 #if WITH_PROFILE_MODEL_P
 675   /* Record the fields for profiling.  */
 676   if (PROFILE_MODEL_P (current_cpu))
 677     {
 678       FLD (in_sr) = f_r2;
 679       FLD (out_dr) = f_r1;
 680     }
 681 #endif
 682 #undef FLD
 683     return idesc;
 684   }
 685
 686  extract_sfmt_addx:
 687   {
 688     const IDESC *idesc = &m32rbf_insn_data[itype];
 689     CGEN_INSN_INT insn = entire_insn;
 690 #define FLD(f) abuf->fields.sfmt_add.f
 691     UINT f_r1;
 692     UINT f_r2;
 693
 694     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 695     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 696
 697   /* Record the fields for the semantic handler.  */
 698   FLD (i_dr) = & CPU (h_gr)[f_r1];
 699   FLD (i_sr) = & CPU (h_gr)[f_r2];
 700   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 701
 702 #if WITH_PROFILE_MODEL_P
 703   /* Record the fields for profiling.  */
 704   if (PROFILE_MODEL_P (current_cpu))
 705     {
 706       FLD (in_dr) = f_r1;
 707       FLD (in_sr) = f_r2;
 708       FLD (out_dr) = f_r1;
 709     }
 710 #endif
 711 #undef FLD
 712     return idesc;
 713   }
 714
 715  extract_sfmt_bc8:
 716   {
 717     const IDESC *idesc = &m32rbf_insn_data[itype];
 718     CGEN_INSN_INT insn = entire_insn;
 719 #define FLD(f) abuf->fields.sfmt_bl8.f
 720     SI f_disp8;
 721
 722     f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 723
 724   /* Record the fields for the semantic handler.  */
 725   FLD (i_disp8) = f_disp8;
 726   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 727
 728 #if WITH_PROFILE_MODEL_P
 729   /* Record the fields for profiling.  */
 730   if (PROFILE_MODEL_P (current_cpu))
 731     {
 732     }
 733 #endif
 734 #undef FLD
 735     return idesc;
 736   }
 737
 738  extract_sfmt_bc24:
 739   {
 740     const IDESC *idesc = &m32rbf_insn_data[itype];
 741     CGEN_INSN_INT insn = entire_insn;
 742 #define FLD(f) abuf->fields.sfmt_bl24.f
 743     SI f_disp24;
 744
 745     f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
 746
 747   /* Record the fields for the semantic handler.  */
 748   FLD (i_disp24) = f_disp24;
 749   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 750
 751 #if WITH_PROFILE_MODEL_P
 752   /* Record the fields for profiling.  */
 753   if (PROFILE_MODEL_P (current_cpu))
 754     {
 755     }
 756 #endif
 757 #undef FLD
 758     return idesc;
 759   }
 760
 761  extract_sfmt_beq:
 762   {
 763     const IDESC *idesc = &m32rbf_insn_data[itype];
 764     CGEN_INSN_INT insn = entire_insn;
 765 #define FLD(f) abuf->fields.sfmt_beq.f
 766     UINT f_r1;
 767     UINT f_r2;
 768     SI f_disp16;
 769
 770     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 771     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 772     f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
 773
 774   /* Record the fields for the semantic handler.  */
 775   FLD (i_disp16) = f_disp16;
 776   FLD (i_src1) = & CPU (h_gr)[f_r1];
 777   FLD (i_src2) = & CPU (h_gr)[f_r2];
 778   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 779
 780 #if WITH_PROFILE_MODEL_P
 781   /* Record the fields for profiling.  */
 782   if (PROFILE_MODEL_P (current_cpu))
 783     {
 784       FLD (in_src1) = f_r1;
 785       FLD (in_src2) = f_r2;
 786     }
 787 #endif
 788 #undef FLD
 789     return idesc;
 790   }
 791
 792  extract_sfmt_beqz:
 793   {
 794     const IDESC *idesc = &m32rbf_insn_data[itype];
 795     CGEN_INSN_INT insn = entire_insn;
 796 #define FLD(f) abuf->fields.sfmt_beq.f
 797     UINT f_r2;
 798     SI f_disp16;
 799
 800     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 801     f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
 802
 803   /* Record the fields for the semantic handler.  */
 804   FLD (i_disp16) = f_disp16;
 805   FLD (i_src2) = & CPU (h_gr)[f_r2];
 806   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
 807
 808 #if WITH_PROFILE_MODEL_P
 809   /* Record the fields for profiling.  */
 810   if (PROFILE_MODEL_P (current_cpu))
 811     {
 812       FLD (in_src2) = f_r2;
 813     }
 814 #endif
 815 #undef FLD
 816     return idesc;
 817   }
 818
 819  extract_sfmt_bl8:
 820   {
 821     const IDESC *idesc = &m32rbf_insn_data[itype];
 822     CGEN_INSN_INT insn = entire_insn;
 823 #define FLD(f) abuf->fields.sfmt_bl8.f
 824     SI f_disp8;
 825
 826     f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 827
 828   /* Record the fields for the semantic handler.  */
 829   FLD (i_disp8) = f_disp8;
 830   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 831
 832 #if WITH_PROFILE_MODEL_P
 833   /* Record the fields for profiling.  */
 834   if (PROFILE_MODEL_P (current_cpu))
 835     {
 836       FLD (out_h_gr_14) = 14;
 837     }
 838 #endif
 839 #undef FLD
 840     return idesc;
 841   }
 842
 843  extract_sfmt_bl24:
 844   {
 845     const IDESC *idesc = &m32rbf_insn_data[itype];
 846     CGEN_INSN_INT insn = entire_insn;
 847 #define FLD(f) abuf->fields.sfmt_bl24.f
 848     SI f_disp24;
 849
 850     f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
 851
 852   /* Record the fields for the semantic handler.  */
 853   FLD (i_disp24) = f_disp24;
 854   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 855
 856 #if WITH_PROFILE_MODEL_P
 857   /* Record the fields for profiling.  */
 858   if (PROFILE_MODEL_P (current_cpu))
 859     {
 860       FLD (out_h_gr_14) = 14;
 861     }
 862 #endif
 863 #undef FLD
 864     return idesc;
 865   }
 866
 867  extract_sfmt_bra8:
 868   {
 869     const IDESC *idesc = &m32rbf_insn_data[itype];
 870     CGEN_INSN_INT insn = entire_insn;
 871 #define FLD(f) abuf->fields.sfmt_bl8.f
 872     SI f_disp8;
 873
 874     f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 875
 876   /* Record the fields for the semantic handler.  */
 877   FLD (i_disp8) = f_disp8;
 878   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 879
 880 #if WITH_PROFILE_MODEL_P
 881   /* Record the fields for profiling.  */
 882   if (PROFILE_MODEL_P (current_cpu))
 883     {
 884     }
 885 #endif
 886 #undef FLD
 887     return idesc;
 888   }
 889
 890  extract_sfmt_bra24:
 891   {
 892     const IDESC *idesc = &m32rbf_insn_data[itype];
 893     CGEN_INSN_INT insn = entire_insn;
 894 #define FLD(f) abuf->fields.sfmt_bl24.f
 895     SI f_disp24;
 896
 897     f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
 898
 899   /* Record the fields for the semantic handler.  */
 900   FLD (i_disp24) = f_disp24;
 901   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 902
 903 #if WITH_PROFILE_MODEL_P
 904   /* Record the fields for profiling.  */
 905   if (PROFILE_MODEL_P (current_cpu))
 906     {
 907     }
 908 #endif
 909 #undef FLD
 910     return idesc;
 911   }
 912
 913  extract_sfmt_cmp:
 914   {
 915     const IDESC *idesc = &m32rbf_insn_data[itype];
 916     CGEN_INSN_INT insn = entire_insn;
 917 #define FLD(f) abuf->fields.sfmt_st_plus.f
 918     UINT f_r1;
 919     UINT f_r2;
 920
 921     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 922     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 923
 924   /* Record the fields for the semantic handler.  */
 925   FLD (i_src1) = & CPU (h_gr)[f_r1];
 926   FLD (i_src2) = & CPU (h_gr)[f_r2];
 927   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 928
 929 #if WITH_PROFILE_MODEL_P
 930   /* Record the fields for profiling.  */
 931   if (PROFILE_MODEL_P (current_cpu))
 932     {
 933       FLD (in_src1) = f_r1;
 934       FLD (in_src2) = f_r2;
 935     }
 936 #endif
 937 #undef FLD
 938     return idesc;
 939   }
 940
 941  extract_sfmt_cmpi:
 942   {
 943     const IDESC *idesc = &m32rbf_insn_data[itype];
 944     CGEN_INSN_INT insn = entire_insn;
 945 #define FLD(f) abuf->fields.sfmt_st_d.f
 946     UINT f_r2;
 947     INT f_simm16;
 948
 949     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 950     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 951
 952   /* Record the fields for the semantic handler.  */
 953   FLD (f_simm16) = f_simm16;
 954   FLD (i_src2) = & CPU (h_gr)[f_r2];
 955   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
 956
 957 #if WITH_PROFILE_MODEL_P
 958   /* Record the fields for profiling.  */
 959   if (PROFILE_MODEL_P (current_cpu))
 960     {
 961       FLD (in_src2) = f_r2;
 962     }
 963 #endif
 964 #undef FLD
 965     return idesc;
 966   }
 967
 968  extract_sfmt_div:
 969   {
 970     const IDESC *idesc = &m32rbf_insn_data[itype];
 971     CGEN_INSN_INT insn = entire_insn;
 972 #define FLD(f) abuf->fields.sfmt_add.f
 973     UINT f_r1;
 974     UINT f_r2;
 975
 976     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 977     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 978
 979   /* Record the fields for the semantic handler.  */
 980   FLD (i_dr) = & CPU (h_gr)[f_r1];
 981   FLD (i_sr) = & CPU (h_gr)[f_r2];
 982   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 983
 984 #if WITH_PROFILE_MODEL_P
 985   /* Record the fields for profiling.  */
 986   if (PROFILE_MODEL_P (current_cpu))
 987     {
 988       FLD (in_dr) = f_r1;
 989       FLD (in_sr) = f_r2;
 990       FLD (out_dr) = f_r1;
 991     }
 992 #endif
 993 #undef FLD
 994     return idesc;
 995   }
 996
 997  extract_sfmt_jl:
 998   {
 999     const IDESC *idesc = &m32rbf_insn_data[itype];
1000     CGEN_INSN_INT insn = entire_insn;
1001 #define FLD(f) abuf->fields.sfmt_jl.f
1002     UINT f_r2;
1003
1004     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1005
1006   /* Record the fields for the semantic handler.  */
1007   FLD (i_sr) = & CPU (h_gr)[f_r2];
1008   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
1009
1010 #if WITH_PROFILE_MODEL_P
1011   /* Record the fields for profiling.  */
1012   if (PROFILE_MODEL_P (current_cpu))
1013     {
1014       FLD (in_sr) = f_r2;
1015       FLD (out_h_gr_14) = 14;
1016     }
1017 #endif
1018 #undef FLD
1019     return idesc;
1020   }
1021
1022  extract_sfmt_jmp:
1023   {
1024     const IDESC *idesc = &m32rbf_insn_data[itype];
1025     CGEN_INSN_INT insn = entire_insn;
1026 #define FLD(f) abuf->fields.sfmt_mvtc.f
1027     UINT f_r2;
1028
1029     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1030
1031   /* Record the fields for the semantic handler.  */
1032   FLD (i_sr) = & CPU (h_gr)[f_r2];
1033   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
1034
1035 #if WITH_PROFILE_MODEL_P
1036   /* Record the fields for profiling.  */
1037   if (PROFILE_MODEL_P (current_cpu))
1038     {
1039       FLD (in_sr) = f_r2;
1040     }
1041 #endif
1042 #undef FLD
1043     return idesc;
1044   }
1045
1046  extract_sfmt_ld:
1047   {
1048     const IDESC *idesc = &m32rbf_insn_data[itype];
1049     CGEN_INSN_INT insn = entire_insn;
1050 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1051     UINT f_r1;
1052     UINT f_r2;
1053
1054     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1055     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1056
1057   /* Record the fields for the semantic handler.  */
1058   FLD (i_sr) = & CPU (h_gr)[f_r2];
1059   FLD (i_dr) = & CPU (h_gr)[f_r1];
1060   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1061
1062 #if WITH_PROFILE_MODEL_P
1063   /* Record the fields for profiling.  */
1064   if (PROFILE_MODEL_P (current_cpu))
1065     {
1066       FLD (in_sr) = f_r2;
1067       FLD (out_dr) = f_r1;
1068     }
1069 #endif
1070 #undef FLD
1071     return idesc;
1072   }
1073
1074  extract_sfmt_ld_d:
1075   {
1076     const IDESC *idesc = &m32rbf_insn_data[itype];
1077     CGEN_INSN_INT insn = entire_insn;
1078 #define FLD(f) abuf->fields.sfmt_add3.f
1079     UINT f_r1;
1080     UINT f_r2;
1081     INT f_simm16;
1082
1083     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1084     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1085     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1086
1087   /* Record the fields for the semantic handler.  */
1088   FLD (f_simm16) = f_simm16;
1089   FLD (i_sr) = & CPU (h_gr)[f_r2];
1090   FLD (i_dr) = & CPU (h_gr)[f_r1];
1091   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1092
1093 #if WITH_PROFILE_MODEL_P
1094   /* Record the fields for profiling.  */
1095   if (PROFILE_MODEL_P (current_cpu))
1096     {
1097       FLD (in_sr) = f_r2;
1098       FLD (out_dr) = f_r1;
1099     }
1100 #endif
1101 #undef FLD
1102     return idesc;
1103   }
1104
1105  extract_sfmt_ld_plus:
1106   {
1107     const IDESC *idesc = &m32rbf_insn_data[itype];
1108     CGEN_INSN_INT insn = entire_insn;
1109 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1110     UINT f_r1;
1111     UINT f_r2;
1112
1113     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1114     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1115
1116   /* Record the fields for the semantic handler.  */
1117   FLD (i_sr) = & CPU (h_gr)[f_r2];
1118   FLD (i_dr) = & CPU (h_gr)[f_r1];
1119   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1120
1121 #if WITH_PROFILE_MODEL_P
1122   /* Record the fields for profiling.  */
1123   if (PROFILE_MODEL_P (current_cpu))
1124     {
1125       FLD (in_sr) = f_r2;
1126       FLD (out_dr) = f_r1;
1127       FLD (out_sr) = f_r2;
1128     }
1129 #endif
1130 #undef FLD
1131     return idesc;
1132   }
1133
1134  extract_sfmt_ld24:
1135   {
1136     const IDESC *idesc = &m32rbf_insn_data[itype];
1137     CGEN_INSN_INT insn = entire_insn;
1138 #define FLD(f) abuf->fields.sfmt_ld24.f
1139     UINT f_r1;
1140     UINT f_uimm24;
1141
1142     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1143     f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
1144
1145   /* Record the fields for the semantic handler.  */
1146   FLD (i_uimm24) = f_uimm24;
1147   FLD (i_dr) = & CPU (h_gr)[f_r1];
1148   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1149
1150 #if WITH_PROFILE_MODEL_P
1151   /* Record the fields for profiling.  */
1152   if (PROFILE_MODEL_P (current_cpu))
1153     {
1154       FLD (out_dr) = f_r1;
1155     }
1156 #endif
1157 #undef FLD
1158     return idesc;
1159   }
1160
1161  extract_sfmt_ldi8:
1162   {
1163     const IDESC *idesc = &m32rbf_insn_data[itype];
1164     CGEN_INSN_INT insn = entire_insn;
1165 #define FLD(f) abuf->fields.sfmt_addi.f
1166     UINT f_r1;
1167     INT f_simm8;
1168
1169     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1170     f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
1171
1172   /* Record the fields for the semantic handler.  */
1173   FLD (f_simm8) = f_simm8;
1174   FLD (i_dr) = & CPU (h_gr)[f_r1];
1175   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
1176
1177 #if WITH_PROFILE_MODEL_P
1178   /* Record the fields for profiling.  */
1179   if (PROFILE_MODEL_P (current_cpu))
1180     {
1181       FLD (out_dr) = f_r1;
1182     }
1183 #endif
1184 #undef FLD
1185     return idesc;
1186   }
1187
1188  extract_sfmt_ldi16:
1189   {
1190     const IDESC *idesc = &m32rbf_insn_data[itype];
1191     CGEN_INSN_INT insn = entire_insn;
1192 #define FLD(f) abuf->fields.sfmt_add3.f
1193     UINT f_r1;
1194     INT f_simm16;
1195
1196     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1197     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1198
1199   /* Record the fields for the semantic handler.  */
1200   FLD (f_simm16) = f_simm16;
1201   FLD (i_dr) = & CPU (h_gr)[f_r1];
1202   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
1203
1204 #if WITH_PROFILE_MODEL_P
1205   /* Record the fields for profiling.  */
1206   if (PROFILE_MODEL_P (current_cpu))
1207     {
1208       FLD (out_dr) = f_r1;
1209     }
1210 #endif
1211 #undef FLD
1212     return idesc;
1213   }
1214
1215  extract_sfmt_lock:
1216   {
1217     const IDESC *idesc = &m32rbf_insn_data[itype];
1218     CGEN_INSN_INT insn = entire_insn;
1219 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1220     UINT f_r1;
1221     UINT f_r2;
1222
1223     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1224     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1225
1226   /* Record the fields for the semantic handler.  */
1227   FLD (i_sr) = & CPU (h_gr)[f_r2];
1228   FLD (i_dr) = & CPU (h_gr)[f_r1];
1229   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1230
1231 #if WITH_PROFILE_MODEL_P
1232   /* Record the fields for profiling.  */
1233   if (PROFILE_MODEL_P (current_cpu))
1234     {
1235       FLD (in_sr) = f_r2;
1236       FLD (out_dr) = f_r1;
1237     }
1238 #endif
1239 #undef FLD
1240     return idesc;
1241   }
1242
1243  extract_sfmt_machi:
1244   {
1245     const IDESC *idesc = &m32rbf_insn_data[itype];
1246     CGEN_INSN_INT insn = entire_insn;
1247 #define FLD(f) abuf->fields.sfmt_st_plus.f
1248     UINT f_r1;
1249     UINT f_r2;
1250
1251     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1252     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1253
1254   /* Record the fields for the semantic handler.  */
1255   FLD (i_src1) = & CPU (h_gr)[f_r1];
1256   FLD (i_src2) = & CPU (h_gr)[f_r2];
1257   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1258
1259 #if WITH_PROFILE_MODEL_P
1260   /* Record the fields for profiling.  */
1261   if (PROFILE_MODEL_P (current_cpu))
1262     {
1263       FLD (in_src1) = f_r1;
1264       FLD (in_src2) = f_r2;
1265     }
1266 #endif
1267 #undef FLD
1268     return idesc;
1269   }
1270
1271  extract_sfmt_mulhi:
1272   {
1273     const IDESC *idesc = &m32rbf_insn_data[itype];
1274     CGEN_INSN_INT insn = entire_insn;
1275 #define FLD(f) abuf->fields.sfmt_st_plus.f
1276     UINT f_r1;
1277     UINT f_r2;
1278
1279     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1280     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1281
1282   /* Record the fields for the semantic handler.  */
1283   FLD (i_src1) = & CPU (h_gr)[f_r1];
1284   FLD (i_src2) = & CPU (h_gr)[f_r2];
1285   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1286
1287 #if WITH_PROFILE_MODEL_P
1288   /* Record the fields for profiling.  */
1289   if (PROFILE_MODEL_P (current_cpu))
1290     {
1291       FLD (in_src1) = f_r1;
1292       FLD (in_src2) = f_r2;
1293     }
1294 #endif
1295 #undef FLD
1296     return idesc;
1297   }
1298
1299  extract_sfmt_mv:
1300   {
1301     const IDESC *idesc = &m32rbf_insn_data[itype];
1302     CGEN_INSN_INT insn = entire_insn;
1303 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1304     UINT f_r1;
1305     UINT f_r2;
1306
1307     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1308     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1309
1310   /* Record the fields for the semantic handler.  */
1311   FLD (i_sr) = & CPU (h_gr)[f_r2];
1312   FLD (i_dr) = & CPU (h_gr)[f_r1];
1313   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1314
1315 #if WITH_PROFILE_MODEL_P
1316   /* Record the fields for profiling.  */
1317   if (PROFILE_MODEL_P (current_cpu))
1318     {
1319       FLD (in_sr) = f_r2;
1320       FLD (out_dr) = f_r1;
1321     }
1322 #endif
1323 #undef FLD
1324     return idesc;
1325   }
1326
1327  extract_sfmt_mvfachi:
1328   {
1329     const IDESC *idesc = &m32rbf_insn_data[itype];
1330     CGEN_INSN_INT insn = entire_insn;
1331 #define FLD(f) abuf->fields.sfmt_seth.f
1332     UINT f_r1;
1333
1334     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1335
1336   /* Record the fields for the semantic handler.  */
1337   FLD (i_dr) = & CPU (h_gr)[f_r1];
1338   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0));
1339
1340 #if WITH_PROFILE_MODEL_P
1341   /* Record the fields for profiling.  */
1342   if (PROFILE_MODEL_P (current_cpu))
1343     {
1344       FLD (out_dr) = f_r1;
1345     }
1346 #endif
1347 #undef FLD
1348     return idesc;
1349   }
1350
1351  extract_sfmt_mvfc:
1352   {
1353     const IDESC *idesc = &m32rbf_insn_data[itype];
1354     CGEN_INSN_INT insn = entire_insn;
1355 #define FLD(f) abuf->fields.sfmt_mvfc.f
1356     UINT f_r1;
1357     UINT f_r2;
1358
1359     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1360     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1361
1362   /* Record the fields for the semantic handler.  */
1363   FLD (f_r2) = f_r2;
1364   FLD (i_dr) = & CPU (h_gr)[f_r1];
1365   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1366
1367 #if WITH_PROFILE_MODEL_P
1368   /* Record the fields for profiling.  */
1369   if (PROFILE_MODEL_P (current_cpu))
1370     {
1371       FLD (out_dr) = f_r1;
1372     }
1373 #endif
1374 #undef FLD
1375     return idesc;
1376   }
1377
1378  extract_sfmt_mvtachi:
1379   {
1380     const IDESC *idesc = &m32rbf_insn_data[itype];
1381     CGEN_INSN_INT insn = entire_insn;
1382 #define FLD(f) abuf->fields.sfmt_st_plus.f
1383     UINT f_r1;
1384
1385     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1386
1387   /* Record the fields for the semantic handler.  */
1388   FLD (i_src1) = & CPU (h_gr)[f_r1];
1389   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0));
1390
1391 #if WITH_PROFILE_MODEL_P
1392   /* Record the fields for profiling.  */
1393   if (PROFILE_MODEL_P (current_cpu))
1394     {
1395       FLD (in_src1) = f_r1;
1396     }
1397 #endif
1398 #undef FLD
1399     return idesc;
1400   }
1401
1402  extract_sfmt_mvtc:
1403   {
1404     const IDESC *idesc = &m32rbf_insn_data[itype];
1405     CGEN_INSN_INT insn = entire_insn;
1406 #define FLD(f) abuf->fields.sfmt_mvtc.f
1407     UINT f_r1;
1408     UINT f_r2;
1409
1410     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1411     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1412
1413   /* Record the fields for the semantic handler.  */
1414   FLD (f_r1) = f_r1;
1415   FLD (i_sr) = & CPU (h_gr)[f_r2];
1416   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1417
1418 #if WITH_PROFILE_MODEL_P
1419   /* Record the fields for profiling.  */
1420   if (PROFILE_MODEL_P (current_cpu))
1421     {
1422       FLD (in_sr) = f_r2;
1423     }
1424 #endif
1425 #undef FLD
1426     return idesc;
1427   }
1428
1429  extract_sfmt_nop:
1430   {
1431     const IDESC *idesc = &m32rbf_insn_data[itype];
1432     CGEN_INSN_INT insn = entire_insn;
1433 #define FLD(f) abuf->fields.fmt_empty.f
1434
1435
1436   /* Record the fields for the semantic handler.  */
1437   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
1438
1439 #undef FLD
1440     return idesc;
1441   }
1442
1443  extract_sfmt_rac:
1444   {
1445     const IDESC *idesc = &m32rbf_insn_data[itype];
1446     CGEN_INSN_INT insn = entire_insn;
1447 #define FLD(f) abuf->fields.fmt_empty.f
1448
1449
1450   /* Record the fields for the semantic handler.  */
1451   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac", (char *) 0));
1452
1453 #undef FLD
1454     return idesc;
1455   }
1456
1457  extract_sfmt_rte:
1458   {
1459     const IDESC *idesc = &m32rbf_insn_data[itype];
1460     CGEN_INSN_INT insn = entire_insn;
1461 #define FLD(f) abuf->fields.fmt_empty.f
1462
1463
1464   /* Record the fields for the semantic handler.  */
1465   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
1466
1467 #if WITH_PROFILE_MODEL_P
1468   /* Record the fields for profiling.  */
1469   if (PROFILE_MODEL_P (current_cpu))
1470     {
1471     }
1472 #endif
1473 #undef FLD
1474     return idesc;
1475   }
1476
1477  extract_sfmt_seth:
1478   {
1479     const IDESC *idesc = &m32rbf_insn_data[itype];
1480     CGEN_INSN_INT insn = entire_insn;
1481 #define FLD(f) abuf->fields.sfmt_seth.f
1482     UINT f_r1;
1483     UINT f_hi16;
1484
1485     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1486     f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
1487
1488   /* Record the fields for the semantic handler.  */
1489   FLD (f_hi16) = f_hi16;
1490   FLD (i_dr) = & CPU (h_gr)[f_r1];
1491   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
1492
1493 #if WITH_PROFILE_MODEL_P
1494   /* Record the fields for profiling.  */
1495   if (PROFILE_MODEL_P (current_cpu))
1496     {
1497       FLD (out_dr) = f_r1;
1498     }
1499 #endif
1500 #undef FLD
1501     return idesc;
1502   }
1503
1504  extract_sfmt_sll3:
1505   {
1506     const IDESC *idesc = &m32rbf_insn_data[itype];
1507     CGEN_INSN_INT insn = entire_insn;
1508 #define FLD(f) abuf->fields.sfmt_add3.f
1509     UINT f_r1;
1510     UINT f_r2;
1511     INT f_simm16;
1512
1513     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1514     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1515     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1516
1517   /* Record the fields for the semantic handler.  */
1518   FLD (f_simm16) = f_simm16;
1519   FLD (i_sr) = & CPU (h_gr)[f_r2];
1520   FLD (i_dr) = & CPU (h_gr)[f_r1];
1521   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1522
1523 #if WITH_PROFILE_MODEL_P
1524   /* Record the fields for profiling.  */
1525   if (PROFILE_MODEL_P (current_cpu))
1526     {
1527       FLD (in_sr) = f_r2;
1528       FLD (out_dr) = f_r1;
1529     }
1530 #endif
1531 #undef FLD
1532     return idesc;
1533   }
1534
1535  extract_sfmt_slli:
1536   {
1537     const IDESC *idesc = &m32rbf_insn_data[itype];
1538     CGEN_INSN_INT insn = entire_insn;
1539 #define FLD(f) abuf->fields.sfmt_slli.f
1540     UINT f_r1;
1541     UINT f_uimm5;
1542
1543     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1544     f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
1545
1546   /* Record the fields for the semantic handler.  */
1547   FLD (f_uimm5) = f_uimm5;
1548   FLD (i_dr) = & CPU (h_gr)[f_r1];
1549   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
1550
1551 #if WITH_PROFILE_MODEL_P
1552   /* Record the fields for profiling.  */
1553   if (PROFILE_MODEL_P (current_cpu))
1554     {
1555       FLD (in_dr) = f_r1;
1556       FLD (out_dr) = f_r1;
1557     }
1558 #endif
1559 #undef FLD
1560     return idesc;
1561   }
1562
1563  extract_sfmt_st:
1564   {
1565     const IDESC *idesc = &m32rbf_insn_data[itype];
1566     CGEN_INSN_INT insn = entire_insn;
1567 #define FLD(f) abuf->fields.sfmt_st_plus.f
1568     UINT f_r1;
1569     UINT f_r2;
1570
1571     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1572     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1573
1574   /* Record the fields for the semantic handler.  */
1575   FLD (i_src1) = & CPU (h_gr)[f_r1];
1576   FLD (i_src2) = & CPU (h_gr)[f_r2];
1577   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1578
1579 #if WITH_PROFILE_MODEL_P
1580   /* Record the fields for profiling.  */
1581   if (PROFILE_MODEL_P (current_cpu))
1582     {
1583       FLD (in_src1) = f_r1;
1584       FLD (in_src2) = f_r2;
1585     }
1586 #endif
1587 #undef FLD
1588     return idesc;
1589   }
1590
1591  extract_sfmt_st_d:
1592   {
1593     const IDESC *idesc = &m32rbf_insn_data[itype];
1594     CGEN_INSN_INT insn = entire_insn;
1595 #define FLD(f) abuf->fields.sfmt_st_d.f
1596     UINT f_r1;
1597     UINT f_r2;
1598     INT f_simm16;
1599
1600     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1601     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1602     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1603
1604   /* Record the fields for the semantic handler.  */
1605   FLD (f_simm16) = f_simm16;
1606   FLD (i_src1) = & CPU (h_gr)[f_r1];
1607   FLD (i_src2) = & CPU (h_gr)[f_r2];
1608   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1609
1610 #if WITH_PROFILE_MODEL_P
1611   /* Record the fields for profiling.  */
1612   if (PROFILE_MODEL_P (current_cpu))
1613     {
1614       FLD (in_src1) = f_r1;
1615       FLD (in_src2) = f_r2;
1616     }
1617 #endif
1618 #undef FLD
1619     return idesc;
1620   }
1621
1622  extract_sfmt_stb:
1623   {
1624     const IDESC *idesc = &m32rbf_insn_data[itype];
1625     CGEN_INSN_INT insn = entire_insn;
1626 #define FLD(f) abuf->fields.sfmt_st_plus.f
1627     UINT f_r1;
1628     UINT f_r2;
1629
1630     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1631     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1632
1633   /* Record the fields for the semantic handler.  */
1634   FLD (i_src1) = & CPU (h_gr)[f_r1];
1635   FLD (i_src2) = & CPU (h_gr)[f_r2];
1636   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1637
1638 #if WITH_PROFILE_MODEL_P
1639   /* Record the fields for profiling.  */
1640   if (PROFILE_MODEL_P (current_cpu))
1641     {
1642       FLD (in_src1) = f_r1;
1643       FLD (in_src2) = f_r2;
1644     }
1645 #endif
1646 #undef FLD
1647     return idesc;
1648   }
1649
1650  extract_sfmt_stb_d:
1651   {
1652     const IDESC *idesc = &m32rbf_insn_data[itype];
1653     CGEN_INSN_INT insn = entire_insn;
1654 #define FLD(f) abuf->fields.sfmt_st_d.f
1655     UINT f_r1;
1656     UINT f_r2;
1657     INT f_simm16;
1658
1659     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1660     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1661     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1662
1663   /* Record the fields for the semantic handler.  */
1664   FLD (f_simm16) = f_simm16;
1665   FLD (i_src1) = & CPU (h_gr)[f_r1];
1666   FLD (i_src2) = & CPU (h_gr)[f_r2];
1667   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1668
1669 #if WITH_PROFILE_MODEL_P
1670   /* Record the fields for profiling.  */
1671   if (PROFILE_MODEL_P (current_cpu))
1672     {
1673       FLD (in_src1) = f_r1;
1674       FLD (in_src2) = f_r2;
1675     }
1676 #endif
1677 #undef FLD
1678     return idesc;
1679   }
1680
1681  extract_sfmt_sth:
1682   {
1683     const IDESC *idesc = &m32rbf_insn_data[itype];
1684     CGEN_INSN_INT insn = entire_insn;
1685 #define FLD(f) abuf->fields.sfmt_st_plus.f
1686     UINT f_r1;
1687     UINT f_r2;
1688
1689     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1690     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1691
1692   /* Record the fields for the semantic handler.  */
1693   FLD (i_src1) = & CPU (h_gr)[f_r1];
1694   FLD (i_src2) = & CPU (h_gr)[f_r2];
1695   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1696
1697 #if WITH_PROFILE_MODEL_P
1698   /* Record the fields for profiling.  */
1699   if (PROFILE_MODEL_P (current_cpu))
1700     {
1701       FLD (in_src1) = f_r1;
1702       FLD (in_src2) = f_r2;
1703     }
1704 #endif
1705 #undef FLD
1706     return idesc;
1707   }
1708
1709  extract_sfmt_sth_d:
1710   {
1711     const IDESC *idesc = &m32rbf_insn_data[itype];
1712     CGEN_INSN_INT insn = entire_insn;
1713 #define FLD(f) abuf->fields.sfmt_st_d.f
1714     UINT f_r1;
1715     UINT f_r2;
1716     INT f_simm16;
1717
1718     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1719     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1720     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1721
1722   /* Record the fields for the semantic handler.  */
1723   FLD (f_simm16) = f_simm16;
1724   FLD (i_src1) = & CPU (h_gr)[f_r1];
1725   FLD (i_src2) = & CPU (h_gr)[f_r2];
1726   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1727
1728 #if WITH_PROFILE_MODEL_P
1729   /* Record the fields for profiling.  */
1730   if (PROFILE_MODEL_P (current_cpu))
1731     {
1732       FLD (in_src1) = f_r1;
1733       FLD (in_src2) = f_r2;
1734     }
1735 #endif
1736 #undef FLD
1737     return idesc;
1738   }
1739
1740  extract_sfmt_st_plus:
1741   {
1742     const IDESC *idesc = &m32rbf_insn_data[itype];
1743     CGEN_INSN_INT insn = entire_insn;
1744 #define FLD(f) abuf->fields.sfmt_st_plus.f
1745     UINT f_r1;
1746     UINT f_r2;
1747
1748     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1749     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1750
1751   /* Record the fields for the semantic handler.  */
1752   FLD (i_src1) = & CPU (h_gr)[f_r1];
1753   FLD (i_src2) = & CPU (h_gr)[f_r2];
1754   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1755
1756 #if WITH_PROFILE_MODEL_P
1757   /* Record the fields for profiling.  */
1758   if (PROFILE_MODEL_P (current_cpu))
1759     {
1760       FLD (in_src1) = f_r1;
1761       FLD (in_src2) = f_r2;
1762       FLD (out_src2) = f_r2;
1763     }
1764 #endif
1765 #undef FLD
1766     return idesc;
1767   }
1768
1769  extract_sfmt_trap:
1770   {
1771     const IDESC *idesc = &m32rbf_insn_data[itype];
1772     CGEN_INSN_INT insn = entire_insn;
1773 #define FLD(f) abuf->fields.sfmt_trap.f
1774     UINT f_uimm4;
1775
1776     f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1777
1778   /* Record the fields for the semantic handler.  */
1779   FLD (f_uimm4) = f_uimm4;
1780   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
1781
1782 #if WITH_PROFILE_MODEL_P
1783   /* Record the fields for profiling.  */
1784   if (PROFILE_MODEL_P (current_cpu))
1785     {
1786     }
1787 #endif
1788 #undef FLD
1789     return idesc;
1790   }
1791
1792  extract_sfmt_unlock:
1793   {
1794     const IDESC *idesc = &m32rbf_insn_data[itype];
1795     CGEN_INSN_INT insn = entire_insn;
1796 #define FLD(f) abuf->fields.sfmt_st_plus.f
1797     UINT f_r1;
1798     UINT f_r2;
1799
1800     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1801     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1802
1803   /* Record the fields for the semantic handler.  */
1804   FLD (i_src1) = & CPU (h_gr)[f_r1];
1805   FLD (i_src2) = & CPU (h_gr)[f_r2];
1806   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1807
1808 #if WITH_PROFILE_MODEL_P
1809   /* Record the fields for profiling.  */
1810   if (PROFILE_MODEL_P (current_cpu))
1811     {
1812       FLD (in_src1) = f_r1;
1813       FLD (in_src2) = f_r2;
1814     }
1815 #endif
1816 #undef FLD
1817     return idesc;
1818   }
1819
1820 }