sim/m32r/decode.c

   1 /* Simulator instruction decoder for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #define WANT_CPU m32rbf
  26 #define WANT_CPU_M32RBF
  27
  28 #include "sim-main.h"
  29 #include "sim-assert.h"
  30
  31 /* FIXME: Need to review choices for the following.  */
  32
  33 #if WITH_SEM_SWITCH_FULL
  34 #define FULL(fn)
  35 #else
  36 #define FULL(fn) CONCAT3 (m32rbf,_sem_,fn) ,
  37 #endif
  38
  39 #if WITH_FAST
  40 #if WITH_SEM_SWITCH_FAST
  41 #define FAST(fn)
  42 #else
  43 #define FAST(fn) CONCAT3 (m32rbf,_semf_,fn) , /* f for fast */
  44 #endif
  45 #else
  46 #define FAST(fn)
  47 #endif
  48
  49 /* The instruction descriptor array.
  50    This is computed at runtime.  Space for it is not malloc'd to save a
  51    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
  52    but won't be done until necessary (we don't currently support the runtime
  53    addition of instructions nor an SMP machine with different cpus).  */
  54 static IDESC m32rbf_insn_data[M32RBF_INSN_MAX];
  55
  56 /* Instruction semantic handlers and support.
  57    This struct defines the part of an IDESC that can be computed at
  58    compile time.  */
  59
  60 struct insn_sem {
  61   /* The instruction type (a number that identifies each insn over the
  62      entire architecture).  */
  63   CGEN_INSN_TYPE type;
  64
  65   /* Index in IDESC table.  */
  66   int index;
  67
  68   /* Routines to execute the insn.
  69      The full version has all features (profiling,tracing) compiled in.
  70      The fast version has none of that.  */
  71 #if ! WITH_SEM_SWITCH_FULL
  72   SEMANTIC_FN *sem_full;
  73 #endif
  74 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
  75   SEMANTIC_FN *sem_fast;
  76 #endif
  77
  78 };
  79 /* The INSN_ prefix is not here and is instead part of the `insn' argument
  80    to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
  81 #define IDX(insn) CONCAT2 (M32RBF_,insn)
  82 #define TYPE(insn) CONCAT2 (M32R_,insn)
  83
  84 /* Commas between elements are contained in the macros.
  85    Some of these are conditionally compiled out.  */
  86
  87 static const struct insn_sem m32rbf_insn_sem[] =
  88 {
  89   { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) },
  90   { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) },
  91   { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) },
  92   { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) },
  93   { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) },
  94   { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) },
  95   { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) },
  96   { TYPE (INSN_ADD3), IDX (INSN_ADD3), FULL (add3) FAST (add3) },
  97   { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) },
  98   { TYPE (INSN_AND3), IDX (INSN_AND3), FULL (and3) FAST (and3) },
  99   { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) },
 100   { TYPE (INSN_OR3), IDX (INSN_OR3), FULL (or3) FAST (or3) },
 101   { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) },
 102   { TYPE (INSN_XOR3), IDX (INSN_XOR3), FULL (xor3) FAST (xor3) },
 103   { TYPE (INSN_ADDI), IDX (INSN_ADDI), FULL (addi) FAST (addi) },
 104   { TYPE (INSN_ADDV), IDX (INSN_ADDV), FULL (addv) FAST (addv) },
 105   { TYPE (INSN_ADDV3), IDX (INSN_ADDV3), FULL (addv3) FAST (addv3) },
 106   { TYPE (INSN_ADDX), IDX (INSN_ADDX), FULL (addx) FAST (addx) },
 107   { TYPE (INSN_BC8), IDX (INSN_BC8), FULL (bc8) FAST (bc8) },
 108   { TYPE (INSN_BC24), IDX (INSN_BC24), FULL (bc24) FAST (bc24) },
 109   { TYPE (INSN_BEQ), IDX (INSN_BEQ), FULL (beq) FAST (beq) },
 110   { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), FULL (beqz) FAST (beqz) },
 111   { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), FULL (bgez) FAST (bgez) },
 112   { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), FULL (bgtz) FAST (bgtz) },
 113   { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), FULL (blez) FAST (blez) },
 114   { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), FULL (bltz) FAST (bltz) },
 115   { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), FULL (bnez) FAST (bnez) },
 116   { TYPE (INSN_BL8), IDX (INSN_BL8), FULL (bl8) FAST (bl8) },
 117   { TYPE (INSN_BL24), IDX (INSN_BL24), FULL (bl24) FAST (bl24) },
 118   { TYPE (INSN_BNC8), IDX (INSN_BNC8), FULL (bnc8) FAST (bnc8) },
 119   { TYPE (INSN_BNC24), IDX (INSN_BNC24), FULL (bnc24) FAST (bnc24) },
 120   { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) },
 121   { TYPE (INSN_BRA8), IDX (INSN_BRA8), FULL (bra8) FAST (bra8) },
 122   { TYPE (INSN_BRA24), IDX (INSN_BRA24), FULL (bra24) FAST (bra24) },
 123   { TYPE (INSN_CMP), IDX (INSN_CMP), FULL (cmp) FAST (cmp) },
 124   { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) },
 125   { TYPE (INSN_CMPU), IDX (INSN_CMPU), FULL (cmpu) FAST (cmpu) },
 126   { TYPE (INSN_CMPUI), IDX (INSN_CMPUI), FULL (cmpui) FAST (cmpui) },
 127   { TYPE (INSN_DIV), IDX (INSN_DIV), FULL (div) FAST (div) },
 128   { TYPE (INSN_DIVU), IDX (INSN_DIVU), FULL (divu) FAST (divu) },
 129   { TYPE (INSN_REM), IDX (INSN_REM), FULL (rem) FAST (rem) },
 130   { TYPE (INSN_REMU), IDX (INSN_REMU), FULL (remu) FAST (remu) },
 131   { TYPE (INSN_JL), IDX (INSN_JL), FULL (jl) FAST (jl) },
 132   { TYPE (INSN_JMP), IDX (INSN_JMP), FULL (jmp) FAST (jmp) },
 133   { TYPE (INSN_LD), IDX (INSN_LD), FULL (ld) FAST (ld) },
 134   { TYPE (INSN_LD_D), IDX (INSN_LD_D), FULL (ld_d) FAST (ld_d) },
 135   { TYPE (INSN_LDB), IDX (INSN_LDB), FULL (ldb) FAST (ldb) },
 136   { TYPE (INSN_LDB_D), IDX (INSN_LDB_D), FULL (ldb_d) FAST (ldb_d) },
 137   { TYPE (INSN_LDH), IDX (INSN_LDH), FULL (ldh) FAST (ldh) },
 138   { TYPE (INSN_LDH_D), IDX (INSN_LDH_D), FULL (ldh_d) FAST (ldh_d) },
 139   { TYPE (INSN_LDUB), IDX (INSN_LDUB), FULL (ldub) FAST (ldub) },
 140   { TYPE (INSN_LDUB_D), IDX (INSN_LDUB_D), FULL (ldub_d) FAST (ldub_d) },
 141   { TYPE (INSN_LDUH), IDX (INSN_LDUH), FULL (lduh) FAST (lduh) },
 142   { TYPE (INSN_LDUH_D), IDX (INSN_LDUH_D), FULL (lduh_d) FAST (lduh_d) },
 143   { TYPE (INSN_LD_PLUS), IDX (INSN_LD_PLUS), FULL (ld_plus) FAST (ld_plus) },
 144   { TYPE (INSN_LD24), IDX (INSN_LD24), FULL (ld24) FAST (ld24) },
 145   { TYPE (INSN_LDI8), IDX (INSN_LDI8), FULL (ldi8) FAST (ldi8) },
 146   { TYPE (INSN_LDI16), IDX (INSN_LDI16), FULL (ldi16) FAST (ldi16) },
 147   { TYPE (INSN_LOCK), IDX (INSN_LOCK), FULL (lock) FAST (lock) },
 148   { TYPE (INSN_MACHI), IDX (INSN_MACHI), FULL (machi) FAST (machi) },
 149   { TYPE (INSN_MACLO), IDX (INSN_MACLO), FULL (maclo) FAST (maclo) },
 150   { TYPE (INSN_MACWHI), IDX (INSN_MACWHI), FULL (macwhi) FAST (macwhi) },
 151   { TYPE (INSN_MACWLO), IDX (INSN_MACWLO), FULL (macwlo) FAST (macwlo) },
 152   { TYPE (INSN_MUL), IDX (INSN_MUL), FULL (mul) FAST (mul) },
 153   { TYPE (INSN_MULHI), IDX (INSN_MULHI), FULL (mulhi) FAST (mulhi) },
 154   { TYPE (INSN_MULLO), IDX (INSN_MULLO), FULL (mullo) FAST (mullo) },
 155   { TYPE (INSN_MULWHI), IDX (INSN_MULWHI), FULL (mulwhi) FAST (mulwhi) },
 156   { TYPE (INSN_MULWLO), IDX (INSN_MULWLO), FULL (mulwlo) FAST (mulwlo) },
 157   { TYPE (INSN_MV), IDX (INSN_MV), FULL (mv) FAST (mv) },
 158   { TYPE (INSN_MVFACHI), IDX (INSN_MVFACHI), FULL (mvfachi) FAST (mvfachi) },
 159   { TYPE (INSN_MVFACLO), IDX (INSN_MVFACLO), FULL (mvfaclo) FAST (mvfaclo) },
 160   { TYPE (INSN_MVFACMI), IDX (INSN_MVFACMI), FULL (mvfacmi) FAST (mvfacmi) },
 161   { TYPE (INSN_MVFC), IDX (INSN_MVFC), FULL (mvfc) FAST (mvfc) },
 162   { TYPE (INSN_MVTACHI), IDX (INSN_MVTACHI), FULL (mvtachi) FAST (mvtachi) },
 163   { TYPE (INSN_MVTACLO), IDX (INSN_MVTACLO), FULL (mvtaclo) FAST (mvtaclo) },
 164   { TYPE (INSN_MVTC), IDX (INSN_MVTC), FULL (mvtc) FAST (mvtc) },
 165   { TYPE (INSN_NEG), IDX (INSN_NEG), FULL (neg) FAST (neg) },
 166   { TYPE (INSN_NOP), IDX (INSN_NOP), FULL (nop) FAST (nop) },
 167   { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) },
 168   { TYPE (INSN_RAC), IDX (INSN_RAC), FULL (rac) FAST (rac) },
 169   { TYPE (INSN_RACH), IDX (INSN_RACH), FULL (rach) FAST (rach) },
 170   { TYPE (INSN_RTE), IDX (INSN_RTE), FULL (rte) FAST (rte) },
 171   { TYPE (INSN_SETH), IDX (INSN_SETH), FULL (seth) FAST (seth) },
 172   { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) },
 173   { TYPE (INSN_SLL3), IDX (INSN_SLL3), FULL (sll3) FAST (sll3) },
 174   { TYPE (INSN_SLLI), IDX (INSN_SLLI), FULL (slli) FAST (slli) },
 175   { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) },
 176   { TYPE (INSN_SRA3), IDX (INSN_SRA3), FULL (sra3) FAST (sra3) },
 177   { TYPE (INSN_SRAI), IDX (INSN_SRAI), FULL (srai) FAST (srai) },
 178   { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) },
 179   { TYPE (INSN_SRL3), IDX (INSN_SRL3), FULL (srl3) FAST (srl3) },
 180   { TYPE (INSN_SRLI), IDX (INSN_SRLI), FULL (srli) FAST (srli) },
 181   { TYPE (INSN_ST), IDX (INSN_ST), FULL (st) FAST (st) },
 182   { TYPE (INSN_ST_D), IDX (INSN_ST_D), FULL (st_d) FAST (st_d) },
 183   { TYPE (INSN_STB), IDX (INSN_STB), FULL (stb) FAST (stb) },
 184   { TYPE (INSN_STB_D), IDX (INSN_STB_D), FULL (stb_d) FAST (stb_d) },
 185   { TYPE (INSN_STH), IDX (INSN_STH), FULL (sth) FAST (sth) },
 186   { TYPE (INSN_STH_D), IDX (INSN_STH_D), FULL (sth_d) FAST (sth_d) },
 187   { TYPE (INSN_ST_PLUS), IDX (INSN_ST_PLUS), FULL (st_plus) FAST (st_plus) },
 188   { TYPE (INSN_ST_MINUS), IDX (INSN_ST_MINUS), FULL (st_minus) FAST (st_minus) },
 189   { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) },
 190   { TYPE (INSN_SUBV), IDX (INSN_SUBV), FULL (subv) FAST (subv) },
 191   { TYPE (INSN_SUBX), IDX (INSN_SUBX), FULL (subx) FAST (subx) },
 192   { TYPE (INSN_TRAP), IDX (INSN_TRAP), FULL (trap) FAST (trap) },
 193   { TYPE (INSN_UNLOCK), IDX (INSN_UNLOCK), FULL (unlock) FAST (unlock) },
 194 };
 195
 196 static const struct insn_sem m32rbf_insn_sem_invalid =
 197 {
 198   VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid)
 199 };
 200
 201 #undef IDX
 202 #undef TYPE
 203
 204 /* Initialize an IDESC from the compile-time computable parts.  */
 205
 206 static INLINE void
 207 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
 208 {
 209   const CGEN_INSN *opcode_table = m32r_cgen_insn_table_entries;
 210
 211   id->num = t->index;
 212   if ((int) t->type <= 0)
 213     id->opcode = & cgen_virtual_opcode_table[- t->type];
 214   else
 215     id->opcode = & opcode_table[t->type];
 216 #if ! WITH_SEM_SWITCH_FULL
 217   id->sem_full = t->sem_full;
 218 #endif
 219 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
 220   id->sem_fast = t->sem_fast;
 221 #endif
 222 #if WITH_PROFILE_MODEL_P
 223   id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
 224   {
 225     SIM_DESC sd = CPU_STATE (cpu);
 226     SIM_ASSERT (t->index == id->timing->num);
 227   }
 228 #endif
 229 }
 230
 231 /* Initialize the instruction descriptor table.  */
 232
 233 void
 234 m32rbf_init_idesc_table (SIM_CPU *cpu)
 235 {
 236   IDESC *id,*tabend;
 237   const struct insn_sem *t,*tend;
 238   int tabsize = M32RBF_INSN_MAX;
 239   IDESC *table = m32rbf_insn_data;
 240
 241   memset (table, 0, tabsize * sizeof (IDESC));
 242
 243   /* First set all entries to the `invalid insn'.  */
 244   t = & m32rbf_insn_sem_invalid;
 245   for (id = table, tabend = table + tabsize; id < tabend; ++id)
 246     init_idesc (cpu, id, t);
 247
 248   /* Now fill in the values for the chosen cpu.  */
 249   for (t = m32rbf_insn_sem, tend = t + sizeof (m32rbf_insn_sem) / sizeof (*t);
 250        t != tend; ++t)
 251     {
 252       init_idesc (cpu, & table[t->index], t);
 253     }
 254
 255   /* Link the IDESC table into the cpu.  */
 256   CPU_IDESC (cpu) = table;
 257 }
 258
 259 /* Enum declaration for all instruction formats.  */
 260 typedef enum ifmt {
 261   FMT_EMPTY, FMT_ADD, FMT_ADD3, FMT_AND3
 262  , FMT_OR3, FMT_ADDI, FMT_ADDV, FMT_ADDV3
 263  , FMT_ADDX, FMT_BC8, FMT_BC24, FMT_BEQ
 264  , FMT_BEQZ, FMT_BL8, FMT_BL24, FMT_BRA8
 265  , FMT_BRA24, FMT_CMP, FMT_CMPI, FMT_DIV
 266  , FMT_JL, FMT_JMP, FMT_LD, FMT_LD_D
 267  , FMT_LDB, FMT_LDB_D, FMT_LDH, FMT_LDH_D
 268  , FMT_LD_PLUS, FMT_LD24, FMT_LDI8, FMT_LDI16
 269  , FMT_LOCK, FMT_MACHI, FMT_MULHI, FMT_MV
 270  , FMT_MVFACHI, FMT_MVFC, FMT_MVTACHI, FMT_MVTC
 271  , FMT_NOP, FMT_RAC, FMT_RTE, FMT_SETH
 272  , FMT_SLL3, FMT_SLLI, FMT_ST, FMT_ST_D
 273  , FMT_STB, FMT_STB_D, FMT_STH, FMT_STH_D
 274  , FMT_ST_PLUS, FMT_TRAP, FMT_UNLOCK
 275 } IFMT;
 276
 277 /* The decoder uses this to record insns and direct extraction handling.  */
 278
 279 typedef struct {
 280   const IDESC *idesc;
 281 #ifdef __GNUC__
 282   void *ifmt;
 283 #else
 284   enum ifmt ifmt;
 285 #endif
 286 } DECODE_DESC;
 287
 288 /* Macro to go from decode phase to extraction phase.  */
 289
 290 #ifdef __GNUC__
 291 #define GOTO_EXTRACT(id) goto *(id)->ifmt
 292 #else
 293 #define GOTO_EXTRACT(id) goto extract
 294 #endif
 295
 296 /* The decoder needs a slightly different computed goto switch control.  */
 297 #ifdef __GNUC__
 298 #define DECODE_SWITCH(N, X) goto *labels_##N[X];
 299 #else
 300 #define DECODE_SWITCH(N, X) switch (X)
 301 #endif
 302
 303 /* Given an instruction, return a pointer to its IDESC entry.  */
 304
 305 const IDESC *
 306 m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
 307               CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
 308               ARGBUF *abuf)
 309 {
 310   /* Result of decoder, used by extractor.  */
 311   const DECODE_DESC *idecode;
 312
 313   /* First decode the instruction.  */
 314
 315   {
 316 #define I(insn) & m32rbf_insn_data[CONCAT2 (M32RBF_,insn)]
 317 #ifdef __GNUC__
 318 #define E(fmt) && case_ex_##fmt
 319 #else
 320 #define E(fmt) fmt
 321 #endif
 322     CGEN_INSN_INT insn = base_insn;
 323     static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
 324     {
 325 #ifdef __GNUC__
 326       static const void *labels_0[256] = {
 327         && default_0, && default_0, && default_0, && default_0,
 328         && default_0, && default_0, && default_0, && default_0,
 329         && default_0, && default_0, && default_0, && default_0,
 330         && default_0, && default_0, && default_0, && default_0,
 331         && default_0, && default_0, && default_0, && default_0,
 332         && default_0, && default_0, && default_0, && default_0,
 333         && default_0, && default_0, && default_0, && default_0,
 334         && case_0_28, && default_0, && default_0, && default_0,
 335         && default_0, && default_0, && default_0, && default_0,
 336         && default_0, && default_0, && default_0, && default_0,
 337         && default_0, && default_0, && default_0, && default_0,
 338         && default_0, && default_0, && default_0, && default_0,
 339         && default_0, && default_0, && default_0, && default_0,
 340         && default_0, && default_0, && default_0, && default_0,
 341         && default_0, && default_0, && default_0, && default_0,
 342         && default_0, && default_0, && default_0, && default_0,
 343         && default_0, && default_0, && default_0, && default_0,
 344         && default_0, && default_0, && default_0, && default_0,
 345         && default_0, && default_0, && default_0, && default_0,
 346         && default_0, && default_0, && default_0, && default_0,
 347         && default_0, && default_0, && default_0, && default_0,
 348         && default_0, && default_0, && default_0, && case_0_87,
 349         && default_0, && default_0, && default_0, && default_0,
 350         && default_0, && default_0, && default_0, && case_0_95,
 351         && default_0, && default_0, && default_0, && default_0,
 352         && default_0, && default_0, && default_0, && default_0,
 353         && default_0, && default_0, && default_0, && default_0,
 354         && default_0, && default_0, && default_0, && default_0,
 355         && case_0_112, && case_0_113, && case_0_114, && case_0_115,
 356         && case_0_116, && case_0_117, && case_0_118, && case_0_119,
 357         && case_0_120, && case_0_121, && case_0_122, && case_0_123,
 358         && case_0_124, && case_0_125, && case_0_126, && case_0_127,
 359         && default_0, && default_0, && default_0, && default_0,
 360         && default_0, && default_0, && default_0, && default_0,
 361         && default_0, && default_0, && default_0, && default_0,
 362         && default_0, && default_0, && default_0, && default_0,
 363         && default_0, && default_0, && default_0, && default_0,
 364         && default_0, && default_0, && default_0, && default_0,
 365         && default_0, && default_0, && default_0, && default_0,
 366         && default_0, && default_0, && default_0, && default_0,
 367         && default_0, && default_0, && default_0, && default_0,
 368         && default_0, && default_0, && default_0, && default_0,
 369         && default_0, && default_0, && default_0, && default_0,
 370         && default_0, && default_0, && default_0, && default_0,
 371         && default_0, && default_0, && default_0, && default_0,
 372         && default_0, && default_0, && default_0, && default_0,
 373         && default_0, && default_0, && default_0, && default_0,
 374         && default_0, && default_0, && default_0, && default_0,
 375         && default_0, && default_0, && default_0, && default_0,
 376         && default_0, && default_0, && default_0, && default_0,
 377         && default_0, && default_0, && default_0, && default_0,
 378         && default_0, && default_0, && default_0, && default_0,
 379         && default_0, && default_0, && default_0, && default_0,
 380         && default_0, && default_0, && default_0, && default_0,
 381         && default_0, && default_0, && default_0, && default_0,
 382         && default_0, && default_0, && default_0, && default_0,
 383         && default_0, && default_0, && default_0, && default_0,
 384         && default_0, && default_0, && default_0, && default_0,
 385         && default_0, && default_0, && default_0, && default_0,
 386         && default_0, && default_0, && default_0, && default_0,
 387         && case_0_240, && case_0_241, && case_0_242, && case_0_243,
 388         && case_0_244, && case_0_245, && case_0_246, && case_0_247,
 389         && case_0_248, && case_0_249, && case_0_250, && case_0_251,
 390         && case_0_252, && case_0_253, && case_0_254, && case_0_255,
 391       };
 392 #endif
 393       static const DECODE_DESC insns[256] = {
 394         { I (INSN_SUBV), E (FMT_ADDV) }, { I (INSN_SUBX), E (FMT_ADDX) },
 395         { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_NEG), E (FMT_MV) },
 396         { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_CMPU), E (FMT_CMP) },
 397         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 398         { I (INSN_ADDV), E (FMT_ADDV) }, { I (INSN_ADDX), E (FMT_ADDX) },
 399         { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_NOT), E (FMT_MV) },
 400         { I (INSN_AND), E (FMT_ADD) }, { I (INSN_XOR), E (FMT_ADD) },
 401         { I (INSN_OR), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 402         { I (INSN_SRL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 403         { I (INSN_SRA), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 404         { I (INSN_SLL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 405         { I (INSN_MUL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 406         { I (INSN_MV), E (FMT_MV) }, { I (INSN_MVFC), E (FMT_MVFC) },
 407         { I (INSN_MVTC), E (FMT_MVTC) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 408         { 0 }, { I (INSN_RTE), E (FMT_RTE) },
 409         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_TRAP), E (FMT_TRAP) },
 410         { I (INSN_STB), E (FMT_STB) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 411         { I (INSN_STH), E (FMT_STH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 412         { I (INSN_ST), E (FMT_ST) }, { I (INSN_UNLOCK), E (FMT_UNLOCK) },
 413         { I (INSN_ST_PLUS), E (FMT_ST_PLUS) }, { I (INSN_ST_MINUS), E (FMT_ST_PLUS) },
 414         { I (INSN_LDB), E (FMT_LDB) }, { I (INSN_LDUB), E (FMT_LDB) },
 415         { I (INSN_LDH), E (FMT_LDH) }, { I (INSN_LDUH), E (FMT_LDH) },
 416         { I (INSN_LD), E (FMT_LD) }, { I (INSN_LOCK), E (FMT_LOCK) },
 417         { I (INSN_LD_PLUS), E (FMT_LD_PLUS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 418         { I (INSN_MULHI), E (FMT_MULHI) }, { I (INSN_MULLO), E (FMT_MULHI) },
 419         { I (INSN_MULWHI), E (FMT_MULHI) }, { I (INSN_MULWLO), E (FMT_MULHI) },
 420         { I (INSN_MACHI), E (FMT_MACHI) }, { I (INSN_MACLO), E (FMT_MACHI) },
 421         { I (INSN_MACWHI), E (FMT_MACHI) }, { I (INSN_MACWLO), E (FMT_MACHI) },
 422         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 423         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 424         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 425         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 426         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 427         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 428         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 429         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 430         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 431         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 432         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 433         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 434         { I (INSN_SRLI), E (FMT_SLLI) }, { I (INSN_SRLI), E (FMT_SLLI) },
 435         { I (INSN_SRAI), E (FMT_SLLI) }, { I (INSN_SRAI), E (FMT_SLLI) },
 436         { I (INSN_SLLI), E (FMT_SLLI) }, { I (INSN_SLLI), E (FMT_SLLI) },
 437         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
 438         { I (INSN_RACH), E (FMT_RAC) }, { I (INSN_RAC), E (FMT_RAC) },
 439         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 440         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 441         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
 442         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 443         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 444         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 445         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 446         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 447         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 448         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 449         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 450         { 0 }, { 0 },
 451         { 0 }, { 0 },
 452         { 0 }, { 0 },
 453         { 0 }, { 0 },
 454         { 0 }, { 0 },
 455         { 0 }, { 0 },
 456         { 0 }, { 0 },
 457         { 0 }, { 0 },
 458         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 459         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 460         { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMPUI), E (FMT_CMPI) },
 461         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 462         { I (INSN_ADDV3), E (FMT_ADDV3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 463         { I (INSN_ADD3), E (FMT_ADD3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 464         { I (INSN_AND3), E (FMT_AND3) }, { I (INSN_XOR3), E (FMT_AND3) },
 465         { I (INSN_OR3), E (FMT_OR3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 466         { I (INSN_DIV), E (FMT_DIV) }, { I (INSN_DIVU), E (FMT_DIV) },
 467         { I (INSN_REM), E (FMT_DIV) }, { I (INSN_REMU), E (FMT_DIV) },
 468         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 469         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 470         { I (INSN_SRL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 471         { I (INSN_SRA3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 472         { I (INSN_SLL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 473         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDI16), E (FMT_LDI16) },
 474         { I (INSN_STB_D), E (FMT_STB_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 475         { I (INSN_STH_D), E (FMT_STH_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 476         { I (INSN_ST_D), E (FMT_ST_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 477         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 478         { I (INSN_LDB_D), E (FMT_LDB_D) }, { I (INSN_LDUB_D), E (FMT_LDB_D) },
 479         { I (INSN_LDH_D), E (FMT_LDH_D) }, { I (INSN_LDUH_D), E (FMT_LDH_D) },
 480         { I (INSN_LD_D), E (FMT_LD_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 481         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 482         { I (INSN_BEQ), E (FMT_BEQ) }, { I (INSN_BNE), E (FMT_BEQ) },
 483         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 484         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 485         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 486         { I (INSN_BEQZ), E (FMT_BEQZ) }, { I (INSN_BNEZ), E (FMT_BEQZ) },
 487         { I (INSN_BLTZ), E (FMT_BEQZ) }, { I (INSN_BGEZ), E (FMT_BEQZ) },
 488         { I (INSN_BLEZ), E (FMT_BEQZ) }, { I (INSN_BGTZ), E (FMT_BEQZ) },
 489         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 490         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 491         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 492         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 493         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 494         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 495         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 496         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 497         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 498         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 499         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 500         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 501         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 502         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 503         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 504         { I (INSN_SETH), E (FMT_SETH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 505         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 506         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 507         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 508         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 509         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 510         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 511         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 512         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 513         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 514         { 0 }, { 0 },
 515         { 0 }, { 0 },
 516         { 0 }, { 0 },
 517         { 0 }, { 0 },
 518         { 0 }, { 0 },
 519         { 0 }, { 0 },
 520         { 0 }, { 0 },
 521         { 0 }, { 0 },
 522       };
 523       unsigned int val;
 524       val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
 525       DECODE_SWITCH (0, val)
 526         {
 527         CASE (0, 28) :
 528           {
 529             static const DECODE_DESC insns[16] = {
 530               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 531               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 532               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 533               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 534               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 535               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 536               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 537               { I (INSN_JL), E (FMT_JL) }, { I (INSN_JMP), E (FMT_JMP) },
 538             };
 539             unsigned int val = (((insn >> 8) & (15 << 0)));
 540             idecode = &insns[val];
 541             GOTO_EXTRACT (idecode);
 542           }
 543         CASE (0, 87) :
 544           {
 545             static const DECODE_DESC insns[16] = {
 546               { I (INSN_MVTACHI), E (FMT_MVTACHI) }, { I (INSN_MVTACLO), E (FMT_MVTACHI) },
 547               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 548               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 549               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 550               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 551               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 552               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 553               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 554             };
 555             unsigned int val = (((insn >> 0) & (15 << 0)));
 556             idecode = &insns[val];
 557             GOTO_EXTRACT (idecode);
 558           }
 559         CASE (0, 95) :
 560           {
 561             static const DECODE_DESC insns[16] = {
 562               { I (INSN_MVFACHI), E (FMT_MVFACHI) }, { I (INSN_MVFACLO), E (FMT_MVFACHI) },
 563               { I (INSN_MVFACMI), E (FMT_MVFACHI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 564               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 565               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 566               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 567               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 568               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 569               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 570             };
 571             unsigned int val = (((insn >> 0) & (15 << 0)));
 572             idecode = &insns[val];
 573             GOTO_EXTRACT (idecode);
 574           }
 575         CASE (0, 112) :
 576           {
 577             static const DECODE_DESC insns[16] = {
 578               { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 579               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 580               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 581               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 582               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 583               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 584               { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) },
 585               { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) },
 586             };
 587             unsigned int val = (((insn >> 8) & (15 << 0)));
 588             idecode = &insns[val];
 589             GOTO_EXTRACT (idecode);
 590           }
 591         CASE (0, 113) : /* fall through */
 592         CASE (0, 114) : /* fall through */
 593         CASE (0, 115) : /* fall through */
 594         CASE (0, 116) : /* fall through */
 595         CASE (0, 117) : /* fall through */
 596         CASE (0, 118) : /* fall through */
 597         CASE (0, 119) : /* fall through */
 598         CASE (0, 120) : /* fall through */
 599         CASE (0, 121) : /* fall through */
 600         CASE (0, 122) : /* fall through */
 601         CASE (0, 123) : /* fall through */
 602         CASE (0, 124) : /* fall through */
 603         CASE (0, 125) : /* fall through */
 604         CASE (0, 126) : /* fall through */
 605         CASE (0, 127) :
 606           {
 607             static const DECODE_DESC insns[16] = {
 608               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 609               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 610               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 611               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 612               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 613               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 614               { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) },
 615               { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) },
 616             };
 617             unsigned int val = (((insn >> 8) & (15 << 0)));
 618             idecode = &insns[val];
 619             GOTO_EXTRACT (idecode);
 620           }
 621         CASE (0, 240) : /* fall through */
 622         CASE (0, 241) : /* fall through */
 623         CASE (0, 242) : /* fall through */
 624         CASE (0, 243) : /* fall through */
 625         CASE (0, 244) : /* fall through */
 626         CASE (0, 245) : /* fall through */
 627         CASE (0, 246) : /* fall through */
 628         CASE (0, 247) : /* fall through */
 629         CASE (0, 248) : /* fall through */
 630         CASE (0, 249) : /* fall through */
 631         CASE (0, 250) : /* fall through */
 632         CASE (0, 251) : /* fall through */
 633         CASE (0, 252) : /* fall through */
 634         CASE (0, 253) : /* fall through */
 635         CASE (0, 254) : /* fall through */
 636         CASE (0, 255) :
 637           {
 638             static const DECODE_DESC insns[16] = {
 639               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 640               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 641               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 642               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 643               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 644               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 645               { I (INSN_BC24), E (FMT_BC24) }, { I (INSN_BNC24), E (FMT_BC24) },
 646               { I (INSN_BL24), E (FMT_BL24) }, { I (INSN_BRA24), E (FMT_BRA24) },
 647             };
 648             unsigned int val = (((insn >> 8) & (15 << 0)));
 649             idecode = &insns[val];
 650             GOTO_EXTRACT (idecode);
 651           }
 652         DEFAULT (0) :
 653           idecode = &insns[val];
 654           GOTO_EXTRACT (idecode);
 655         }
 656       ENDSWITCH (0)
 657     }
 658 #undef I
 659 #undef E
 660   }
 661
 662   /* The instruction has been decoded, now extract the fields.  */
 663
 664  extract:
 665   {
 666 #ifndef __GNUC__
 667     switch (idecode->ifmt)
 668 #endif
 669       {
 670
 671   CASE (ex, FMT_EMPTY) :
 672   {
 673     CGEN_INSN_INT insn = entire_insn;
 674 #define FLD(f) abuf->fields.fmt_empty.f
 675   EXTRACT_FMT_EMPTY_VARS /* */
 676
 677   EXTRACT_FMT_EMPTY_CODE
 678
 679   /* Record the fields for the semantic handler.  */
 680   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
 681
 682 #undef FLD
 683   BREAK (ex);
 684   }
 685
 686   CASE (ex, FMT_ADD) :
 687   {
 688     CGEN_INSN_INT insn = entire_insn;
 689 #define FLD(f) abuf->fields.fmt_add.f
 690   EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 691
 692   EXTRACT_FMT_ADD_CODE
 693
 694   /* Record the fields for the semantic handler.  */
 695   FLD (i_dr) = & CPU (h_gr)[f_r1];
 696   FLD (i_sr) = & CPU (h_gr)[f_r2];
 697   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 698
 699 #if WITH_PROFILE_MODEL_P
 700   /* Record the fields for profiling.  */
 701   if (PROFILE_MODEL_P (current_cpu))
 702     {
 703       FLD (in_dr) = f_r1;
 704       FLD (in_sr) = f_r2;
 705       FLD (out_dr) = f_r1;
 706     }
 707 #endif
 708 #undef FLD
 709   BREAK (ex);
 710   }
 711
 712   CASE (ex, FMT_ADD3) :
 713   {
 714     CGEN_INSN_INT insn = entire_insn;
 715 #define FLD(f) abuf->fields.fmt_add3.f
 716   EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 717
 718   EXTRACT_FMT_ADD3_CODE
 719
 720   /* Record the fields for the semantic handler.  */
 721   FLD (f_simm16) = f_simm16;
 722   FLD (i_sr) = & CPU (h_gr)[f_r2];
 723   FLD (i_dr) = & CPU (h_gr)[f_r1];
 724   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 725
 726 #if WITH_PROFILE_MODEL_P
 727   /* Record the fields for profiling.  */
 728   if (PROFILE_MODEL_P (current_cpu))
 729     {
 730       FLD (in_sr) = f_r2;
 731       FLD (out_dr) = f_r1;
 732     }
 733 #endif
 734 #undef FLD
 735   BREAK (ex);
 736   }
 737
 738   CASE (ex, FMT_AND3) :
 739   {
 740     CGEN_INSN_INT insn = entire_insn;
 741 #define FLD(f) abuf->fields.fmt_and3.f
 742   EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 743
 744   EXTRACT_FMT_AND3_CODE
 745
 746   /* Record the fields for the semantic handler.  */
 747   FLD (f_uimm16) = f_uimm16;
 748   FLD (i_sr) = & CPU (h_gr)[f_r2];
 749   FLD (i_dr) = & CPU (h_gr)[f_r1];
 750   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 751
 752 #if WITH_PROFILE_MODEL_P
 753   /* Record the fields for profiling.  */
 754   if (PROFILE_MODEL_P (current_cpu))
 755     {
 756       FLD (in_sr) = f_r2;
 757       FLD (out_dr) = f_r1;
 758     }
 759 #endif
 760 #undef FLD
 761   BREAK (ex);
 762   }
 763
 764   CASE (ex, FMT_OR3) :
 765   {
 766     CGEN_INSN_INT insn = entire_insn;
 767 #define FLD(f) abuf->fields.fmt_or3.f
 768   EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 769
 770   EXTRACT_FMT_OR3_CODE
 771
 772   /* Record the fields for the semantic handler.  */
 773   FLD (f_uimm16) = f_uimm16;
 774   FLD (i_sr) = & CPU (h_gr)[f_r2];
 775   FLD (i_dr) = & CPU (h_gr)[f_r1];
 776   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 777
 778 #if WITH_PROFILE_MODEL_P
 779   /* Record the fields for profiling.  */
 780   if (PROFILE_MODEL_P (current_cpu))
 781     {
 782       FLD (in_sr) = f_r2;
 783       FLD (out_dr) = f_r1;
 784     }
 785 #endif
 786 #undef FLD
 787   BREAK (ex);
 788   }
 789
 790   CASE (ex, FMT_ADDI) :
 791   {
 792     CGEN_INSN_INT insn = entire_insn;
 793 #define FLD(f) abuf->fields.fmt_addi.f
 794   EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
 795
 796   EXTRACT_FMT_ADDI_CODE
 797
 798   /* Record the fields for the semantic handler.  */
 799   FLD (f_simm8) = f_simm8;
 800   FLD (i_dr) = & CPU (h_gr)[f_r1];
 801   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
 802
 803 #if WITH_PROFILE_MODEL_P
 804   /* Record the fields for profiling.  */
 805   if (PROFILE_MODEL_P (current_cpu))
 806     {
 807       FLD (in_dr) = f_r1;
 808       FLD (out_dr) = f_r1;
 809     }
 810 #endif
 811 #undef FLD
 812   BREAK (ex);
 813   }
 814
 815   CASE (ex, FMT_ADDV) :
 816   {
 817     CGEN_INSN_INT insn = entire_insn;
 818 #define FLD(f) abuf->fields.fmt_addv.f
 819   EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
 820
 821   EXTRACT_FMT_ADDV_CODE
 822
 823   /* Record the fields for the semantic handler.  */
 824   FLD (i_dr) = & CPU (h_gr)[f_r1];
 825   FLD (i_sr) = & CPU (h_gr)[f_r2];
 826   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 827
 828 #if WITH_PROFILE_MODEL_P
 829   /* Record the fields for profiling.  */
 830   if (PROFILE_MODEL_P (current_cpu))
 831     {
 832       FLD (in_dr) = f_r1;
 833       FLD (in_sr) = f_r2;
 834       FLD (out_dr) = f_r1;
 835     }
 836 #endif
 837 #undef FLD
 838   BREAK (ex);
 839   }
 840
 841   CASE (ex, FMT_ADDV3) :
 842   {
 843     CGEN_INSN_INT insn = entire_insn;
 844 #define FLD(f) abuf->fields.fmt_addv3.f
 845   EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 846
 847   EXTRACT_FMT_ADDV3_CODE
 848
 849   /* Record the fields for the semantic handler.  */
 850   FLD (f_simm16) = f_simm16;
 851   FLD (i_sr) = & CPU (h_gr)[f_r2];
 852   FLD (i_dr) = & CPU (h_gr)[f_r1];
 853   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 854
 855 #if WITH_PROFILE_MODEL_P
 856   /* Record the fields for profiling.  */
 857   if (PROFILE_MODEL_P (current_cpu))
 858     {
 859       FLD (in_sr) = f_r2;
 860       FLD (out_dr) = f_r1;
 861     }
 862 #endif
 863 #undef FLD
 864   BREAK (ex);
 865   }
 866
 867   CASE (ex, FMT_ADDX) :
 868   {
 869     CGEN_INSN_INT insn = entire_insn;
 870 #define FLD(f) abuf->fields.fmt_addx.f
 871   EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
 872
 873   EXTRACT_FMT_ADDX_CODE
 874
 875   /* Record the fields for the semantic handler.  */
 876   FLD (i_dr) = & CPU (h_gr)[f_r1];
 877   FLD (i_sr) = & CPU (h_gr)[f_r2];
 878   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 879
 880 #if WITH_PROFILE_MODEL_P
 881   /* Record the fields for profiling.  */
 882   if (PROFILE_MODEL_P (current_cpu))
 883     {
 884       FLD (in_dr) = f_r1;
 885       FLD (in_sr) = f_r2;
 886       FLD (out_dr) = f_r1;
 887     }
 888 #endif
 889 #undef FLD
 890   BREAK (ex);
 891   }
 892
 893   CASE (ex, FMT_BC8) :
 894   {
 895     CGEN_INSN_INT insn = entire_insn;
 896 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
 897   EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
 898
 899   EXTRACT_FMT_BC8_CODE
 900
 901   /* Record the fields for the semantic handler.  */
 902   FLD (i_disp8) = f_disp8;
 903   SEM_BRANCH_INIT_EXTRACT (abuf);
 904   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 905
 906 #if WITH_PROFILE_MODEL_P
 907   /* Record the fields for profiling.  */
 908   if (PROFILE_MODEL_P (current_cpu))
 909     {
 910     }
 911 #endif
 912 #undef FLD
 913   BREAK (ex);
 914   }
 915
 916   CASE (ex, FMT_BC24) :
 917   {
 918     CGEN_INSN_INT insn = entire_insn;
 919 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
 920   EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
 921
 922   EXTRACT_FMT_BC24_CODE
 923
 924   /* Record the fields for the semantic handler.  */
 925   FLD (i_disp24) = f_disp24;
 926   SEM_BRANCH_INIT_EXTRACT (abuf);
 927   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 928
 929 #if WITH_PROFILE_MODEL_P
 930   /* Record the fields for profiling.  */
 931   if (PROFILE_MODEL_P (current_cpu))
 932     {
 933     }
 934 #endif
 935 #undef FLD
 936   BREAK (ex);
 937   }
 938
 939   CASE (ex, FMT_BEQ) :
 940   {
 941     CGEN_INSN_INT insn = entire_insn;
 942 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
 943   EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 944
 945   EXTRACT_FMT_BEQ_CODE
 946
 947   /* Record the fields for the semantic handler.  */
 948   FLD (i_src1) = & CPU (h_gr)[f_r1];
 949   FLD (i_src2) = & CPU (h_gr)[f_r2];
 950   FLD (i_disp16) = f_disp16;
 951   SEM_BRANCH_INIT_EXTRACT (abuf);
 952   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
 953
 954 #if WITH_PROFILE_MODEL_P
 955   /* Record the fields for profiling.  */
 956   if (PROFILE_MODEL_P (current_cpu))
 957     {
 958       FLD (in_src1) = f_r1;
 959       FLD (in_src2) = f_r2;
 960     }
 961 #endif
 962 #undef FLD
 963   BREAK (ex);
 964   }
 965
 966   CASE (ex, FMT_BEQZ) :
 967   {
 968     CGEN_INSN_INT insn = entire_insn;
 969 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 970   EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 971
 972   EXTRACT_FMT_BEQZ_CODE
 973
 974   /* Record the fields for the semantic handler.  */
 975   FLD (i_src2) = & CPU (h_gr)[f_r2];
 976   FLD (i_disp16) = f_disp16;
 977   SEM_BRANCH_INIT_EXTRACT (abuf);
 978   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
 979
 980 #if WITH_PROFILE_MODEL_P
 981   /* Record the fields for profiling.  */
 982   if (PROFILE_MODEL_P (current_cpu))
 983     {
 984       FLD (in_src2) = f_r2;
 985     }
 986 #endif
 987 #undef FLD
 988   BREAK (ex);
 989   }
 990
 991   CASE (ex, FMT_BL8) :
 992   {
 993     CGEN_INSN_INT insn = entire_insn;
 994 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
 995   EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */
 996
 997   EXTRACT_FMT_BL8_CODE
 998
 999   /* Record the fields for the semantic handler.  */
1000   FLD (i_disp8) = f_disp8;
1001   SEM_BRANCH_INIT_EXTRACT (abuf);
1002   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1003
1004 #if WITH_PROFILE_MODEL_P
1005   /* Record the fields for profiling.  */
1006   if (PROFILE_MODEL_P (current_cpu))
1007     {
1008       FLD (out_h_gr_14) = 14;
1009     }
1010 #endif
1011 #undef FLD
1012   BREAK (ex);
1013   }
1014
1015   CASE (ex, FMT_BL24) :
1016   {
1017     CGEN_INSN_INT insn = entire_insn;
1018 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
1019   EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */
1020
1021   EXTRACT_FMT_BL24_CODE
1022
1023   /* Record the fields for the semantic handler.  */
1024   FLD (i_disp24) = f_disp24;
1025   SEM_BRANCH_INIT_EXTRACT (abuf);
1026   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1027
1028 #if WITH_PROFILE_MODEL_P
1029   /* Record the fields for profiling.  */
1030   if (PROFILE_MODEL_P (current_cpu))
1031     {
1032       FLD (out_h_gr_14) = 14;
1033     }
1034 #endif
1035 #undef FLD
1036   BREAK (ex);
1037   }
1038
1039   CASE (ex, FMT_BRA8) :
1040   {
1041     CGEN_INSN_INT insn = entire_insn;
1042 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
1043   EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */
1044
1045   EXTRACT_FMT_BRA8_CODE
1046
1047   /* Record the fields for the semantic handler.  */
1048   FLD (i_disp8) = f_disp8;
1049   SEM_BRANCH_INIT_EXTRACT (abuf);
1050   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1051
1052 #if WITH_PROFILE_MODEL_P
1053   /* Record the fields for profiling.  */
1054   if (PROFILE_MODEL_P (current_cpu))
1055     {
1056     }
1057 #endif
1058 #undef FLD
1059   BREAK (ex);
1060   }
1061
1062   CASE (ex, FMT_BRA24) :
1063   {
1064     CGEN_INSN_INT insn = entire_insn;
1065 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
1066   EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */
1067
1068   EXTRACT_FMT_BRA24_CODE
1069
1070   /* Record the fields for the semantic handler.  */
1071   FLD (i_disp24) = f_disp24;
1072   SEM_BRANCH_INIT_EXTRACT (abuf);
1073   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1074
1075 #if WITH_PROFILE_MODEL_P
1076   /* Record the fields for profiling.  */
1077   if (PROFILE_MODEL_P (current_cpu))
1078     {
1079     }
1080 #endif
1081 #undef FLD
1082   BREAK (ex);
1083   }
1084
1085   CASE (ex, FMT_CMP) :
1086   {
1087     CGEN_INSN_INT insn = entire_insn;
1088 #define FLD(f) abuf->fields.fmt_cmp.f
1089   EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1090
1091   EXTRACT_FMT_CMP_CODE
1092
1093   /* Record the fields for the semantic handler.  */
1094   FLD (i_src1) = & CPU (h_gr)[f_r1];
1095   FLD (i_src2) = & CPU (h_gr)[f_r2];
1096   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1097
1098 #if WITH_PROFILE_MODEL_P
1099   /* Record the fields for profiling.  */
1100   if (PROFILE_MODEL_P (current_cpu))
1101     {
1102       FLD (in_src1) = f_r1;
1103       FLD (in_src2) = f_r2;
1104     }
1105 #endif
1106 #undef FLD
1107   BREAK (ex);
1108   }
1109
1110   CASE (ex, FMT_CMPI) :
1111   {
1112     CGEN_INSN_INT insn = entire_insn;
1113 #define FLD(f) abuf->fields.fmt_cmpi.f
1114   EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1115
1116   EXTRACT_FMT_CMPI_CODE
1117
1118   /* Record the fields for the semantic handler.  */
1119   FLD (f_simm16) = f_simm16;
1120   FLD (i_src2) = & CPU (h_gr)[f_r2];
1121   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
1122
1123 #if WITH_PROFILE_MODEL_P
1124   /* Record the fields for profiling.  */
1125   if (PROFILE_MODEL_P (current_cpu))
1126     {
1127       FLD (in_src2) = f_r2;
1128     }
1129 #endif
1130 #undef FLD
1131   BREAK (ex);
1132   }
1133
1134   CASE (ex, FMT_DIV) :
1135   {
1136     CGEN_INSN_INT insn = entire_insn;
1137 #define FLD(f) abuf->fields.fmt_div.f
1138   EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1139
1140   EXTRACT_FMT_DIV_CODE
1141
1142   /* Record the fields for the semantic handler.  */
1143   FLD (i_sr) = & CPU (h_gr)[f_r2];
1144   FLD (i_dr) = & CPU (h_gr)[f_r1];
1145   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1146
1147 #if WITH_PROFILE_MODEL_P
1148   /* Record the fields for profiling.  */
1149   if (PROFILE_MODEL_P (current_cpu))
1150     {
1151       FLD (in_sr) = f_r2;
1152       FLD (in_dr) = f_r1;
1153       FLD (out_dr) = f_r1;
1154     }
1155 #endif
1156 #undef FLD
1157   BREAK (ex);
1158   }
1159
1160   CASE (ex, FMT_JL) :
1161   {
1162     CGEN_INSN_INT insn = entire_insn;
1163 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
1164   EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
1165
1166   EXTRACT_FMT_JL_CODE
1167
1168   /* Record the fields for the semantic handler.  */
1169   FLD (i_sr) = & CPU (h_gr)[f_r2];
1170   SEM_BRANCH_INIT_EXTRACT (abuf);
1171   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
1172
1173 #if WITH_PROFILE_MODEL_P
1174   /* Record the fields for profiling.  */
1175   if (PROFILE_MODEL_P (current_cpu))
1176     {
1177       FLD (in_sr) = f_r2;
1178       FLD (out_h_gr_14) = 14;
1179     }
1180 #endif
1181 #undef FLD
1182   BREAK (ex);
1183   }
1184
1185   CASE (ex, FMT_JMP) :
1186   {
1187     CGEN_INSN_INT insn = entire_insn;
1188 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
1189   EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1190
1191   EXTRACT_FMT_JMP_CODE
1192
1193   /* Record the fields for the semantic handler.  */
1194   FLD (i_sr) = & CPU (h_gr)[f_r2];
1195   SEM_BRANCH_INIT_EXTRACT (abuf);
1196   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
1197
1198 #if WITH_PROFILE_MODEL_P
1199   /* Record the fields for profiling.  */
1200   if (PROFILE_MODEL_P (current_cpu))
1201     {
1202       FLD (in_sr) = f_r2;
1203     }
1204 #endif
1205 #undef FLD
1206   BREAK (ex);
1207   }
1208
1209   CASE (ex, FMT_LD) :
1210   {
1211     CGEN_INSN_INT insn = entire_insn;
1212 #define FLD(f) abuf->fields.fmt_ld.f
1213   EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1214
1215   EXTRACT_FMT_LD_CODE
1216
1217   /* Record the fields for the semantic handler.  */
1218   FLD (i_sr) = & CPU (h_gr)[f_r2];
1219   FLD (i_dr) = & CPU (h_gr)[f_r1];
1220   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1221
1222 #if WITH_PROFILE_MODEL_P
1223   /* Record the fields for profiling.  */
1224   if (PROFILE_MODEL_P (current_cpu))
1225     {
1226       FLD (in_sr) = f_r2;
1227       FLD (out_dr) = f_r1;
1228     }
1229 #endif
1230 #undef FLD
1231   BREAK (ex);
1232   }
1233
1234   CASE (ex, FMT_LD_D) :
1235   {
1236     CGEN_INSN_INT insn = entire_insn;
1237 #define FLD(f) abuf->fields.fmt_ld_d.f
1238   EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1239
1240   EXTRACT_FMT_LD_D_CODE
1241
1242   /* Record the fields for the semantic handler.  */
1243   FLD (f_simm16) = f_simm16;
1244   FLD (i_sr) = & CPU (h_gr)[f_r2];
1245   FLD (i_dr) = & CPU (h_gr)[f_r1];
1246   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1247
1248 #if WITH_PROFILE_MODEL_P
1249   /* Record the fields for profiling.  */
1250   if (PROFILE_MODEL_P (current_cpu))
1251     {
1252       FLD (in_sr) = f_r2;
1253       FLD (out_dr) = f_r1;
1254     }
1255 #endif
1256 #undef FLD
1257   BREAK (ex);
1258   }
1259
1260   CASE (ex, FMT_LDB) :
1261   {
1262     CGEN_INSN_INT insn = entire_insn;
1263 #define FLD(f) abuf->fields.fmt_ldb.f
1264   EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
1265
1266   EXTRACT_FMT_LDB_CODE
1267
1268   /* Record the fields for the semantic handler.  */
1269   FLD (i_sr) = & CPU (h_gr)[f_r2];
1270   FLD (i_dr) = & CPU (h_gr)[f_r1];
1271   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1272
1273 #if WITH_PROFILE_MODEL_P
1274   /* Record the fields for profiling.  */
1275   if (PROFILE_MODEL_P (current_cpu))
1276     {
1277       FLD (in_sr) = f_r2;
1278       FLD (out_dr) = f_r1;
1279     }
1280 #endif
1281 #undef FLD
1282   BREAK (ex);
1283   }
1284
1285   CASE (ex, FMT_LDB_D) :
1286   {
1287     CGEN_INSN_INT insn = entire_insn;
1288 #define FLD(f) abuf->fields.fmt_ldb_d.f
1289   EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1290
1291   EXTRACT_FMT_LDB_D_CODE
1292
1293   /* Record the fields for the semantic handler.  */
1294   FLD (f_simm16) = f_simm16;
1295   FLD (i_sr) = & CPU (h_gr)[f_r2];
1296   FLD (i_dr) = & CPU (h_gr)[f_r1];
1297   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1298
1299 #if WITH_PROFILE_MODEL_P
1300   /* Record the fields for profiling.  */
1301   if (PROFILE_MODEL_P (current_cpu))
1302     {
1303       FLD (in_sr) = f_r2;
1304       FLD (out_dr) = f_r1;
1305     }
1306 #endif
1307 #undef FLD
1308   BREAK (ex);
1309   }
1310
1311   CASE (ex, FMT_LDH) :
1312   {
1313     CGEN_INSN_INT insn = entire_insn;
1314 #define FLD(f) abuf->fields.fmt_ldh.f
1315   EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
1316
1317   EXTRACT_FMT_LDH_CODE
1318
1319   /* Record the fields for the semantic handler.  */
1320   FLD (i_sr) = & CPU (h_gr)[f_r2];
1321   FLD (i_dr) = & CPU (h_gr)[f_r1];
1322   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1323
1324 #if WITH_PROFILE_MODEL_P
1325   /* Record the fields for profiling.  */
1326   if (PROFILE_MODEL_P (current_cpu))
1327     {
1328       FLD (in_sr) = f_r2;
1329       FLD (out_dr) = f_r1;
1330     }
1331 #endif
1332 #undef FLD
1333   BREAK (ex);
1334   }
1335
1336   CASE (ex, FMT_LDH_D) :
1337   {
1338     CGEN_INSN_INT insn = entire_insn;
1339 #define FLD(f) abuf->fields.fmt_ldh_d.f
1340   EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1341
1342   EXTRACT_FMT_LDH_D_CODE
1343
1344   /* Record the fields for the semantic handler.  */
1345   FLD (f_simm16) = f_simm16;
1346   FLD (i_sr) = & CPU (h_gr)[f_r2];
1347   FLD (i_dr) = & CPU (h_gr)[f_r1];
1348   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1349
1350 #if WITH_PROFILE_MODEL_P
1351   /* Record the fields for profiling.  */
1352   if (PROFILE_MODEL_P (current_cpu))
1353     {
1354       FLD (in_sr) = f_r2;
1355       FLD (out_dr) = f_r1;
1356     }
1357 #endif
1358 #undef FLD
1359   BREAK (ex);
1360   }
1361
1362   CASE (ex, FMT_LD_PLUS) :
1363   {
1364     CGEN_INSN_INT insn = entire_insn;
1365 #define FLD(f) abuf->fields.fmt_ld_plus.f
1366   EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
1367
1368   EXTRACT_FMT_LD_PLUS_CODE
1369
1370   /* Record the fields for the semantic handler.  */
1371   FLD (i_sr) = & CPU (h_gr)[f_r2];
1372   FLD (i_dr) = & CPU (h_gr)[f_r1];
1373   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1374
1375 #if WITH_PROFILE_MODEL_P
1376   /* Record the fields for profiling.  */
1377   if (PROFILE_MODEL_P (current_cpu))
1378     {
1379       FLD (in_sr) = f_r2;
1380       FLD (out_dr) = f_r1;
1381       FLD (out_sr) = f_r2;
1382     }
1383 #endif
1384 #undef FLD
1385   BREAK (ex);
1386   }
1387
1388   CASE (ex, FMT_LD24) :
1389   {
1390     CGEN_INSN_INT insn = entire_insn;
1391 #define FLD(f) abuf->fields.fmt_ld24.f
1392   EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
1393
1394   EXTRACT_FMT_LD24_CODE
1395
1396   /* Record the fields for the semantic handler.  */
1397   FLD (i_uimm24) = f_uimm24;
1398   FLD (i_dr) = & CPU (h_gr)[f_r1];
1399   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1400
1401 #if WITH_PROFILE_MODEL_P
1402   /* Record the fields for profiling.  */
1403   if (PROFILE_MODEL_P (current_cpu))
1404     {
1405       FLD (out_dr) = f_r1;
1406     }
1407 #endif
1408 #undef FLD
1409   BREAK (ex);
1410   }
1411
1412   CASE (ex, FMT_LDI8) :
1413   {
1414     CGEN_INSN_INT insn = entire_insn;
1415 #define FLD(f) abuf->fields.fmt_ldi8.f
1416   EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */
1417
1418   EXTRACT_FMT_LDI8_CODE
1419
1420   /* Record the fields for the semantic handler.  */
1421   FLD (f_simm8) = f_simm8;
1422   FLD (i_dr) = & CPU (h_gr)[f_r1];
1423   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
1424
1425 #if WITH_PROFILE_MODEL_P
1426   /* Record the fields for profiling.  */
1427   if (PROFILE_MODEL_P (current_cpu))
1428     {
1429       FLD (out_dr) = f_r1;
1430     }
1431 #endif
1432 #undef FLD
1433   BREAK (ex);
1434   }
1435
1436   CASE (ex, FMT_LDI16) :
1437   {
1438     CGEN_INSN_INT insn = entire_insn;
1439 #define FLD(f) abuf->fields.fmt_ldi16.f
1440   EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1441
1442   EXTRACT_FMT_LDI16_CODE
1443
1444   /* Record the fields for the semantic handler.  */
1445   FLD (f_simm16) = f_simm16;
1446   FLD (i_dr) = & CPU (h_gr)[f_r1];
1447   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
1448
1449 #if WITH_PROFILE_MODEL_P
1450   /* Record the fields for profiling.  */
1451   if (PROFILE_MODEL_P (current_cpu))
1452     {
1453       FLD (out_dr) = f_r1;
1454     }
1455 #endif
1456 #undef FLD
1457   BREAK (ex);
1458   }
1459
1460   CASE (ex, FMT_LOCK) :
1461   {
1462     CGEN_INSN_INT insn = entire_insn;
1463 #define FLD(f) abuf->fields.fmt_lock.f
1464   EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
1465
1466   EXTRACT_FMT_LOCK_CODE
1467
1468   /* Record the fields for the semantic handler.  */
1469   FLD (i_sr) = & CPU (h_gr)[f_r2];
1470   FLD (i_dr) = & CPU (h_gr)[f_r1];
1471   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1472
1473 #if WITH_PROFILE_MODEL_P
1474   /* Record the fields for profiling.  */
1475   if (PROFILE_MODEL_P (current_cpu))
1476     {
1477       FLD (in_sr) = f_r2;
1478       FLD (out_dr) = f_r1;
1479     }
1480 #endif
1481 #undef FLD
1482   BREAK (ex);
1483   }
1484
1485   CASE (ex, FMT_MACHI) :
1486   {
1487     CGEN_INSN_INT insn = entire_insn;
1488 #define FLD(f) abuf->fields.fmt_machi.f
1489   EXTRACT_FMT_MACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
1490
1491   EXTRACT_FMT_MACHI_CODE
1492
1493   /* Record the fields for the semantic handler.  */
1494   FLD (i_src1) = & CPU (h_gr)[f_r1];
1495   FLD (i_src2) = & CPU (h_gr)[f_r2];
1496   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1497
1498 #if WITH_PROFILE_MODEL_P
1499   /* Record the fields for profiling.  */
1500   if (PROFILE_MODEL_P (current_cpu))
1501     {
1502       FLD (in_src1) = f_r1;
1503       FLD (in_src2) = f_r2;
1504     }
1505 #endif
1506 #undef FLD
1507   BREAK (ex);
1508   }
1509
1510   CASE (ex, FMT_MULHI) :
1511   {
1512     CGEN_INSN_INT insn = entire_insn;
1513 #define FLD(f) abuf->fields.fmt_mulhi.f
1514   EXTRACT_FMT_MULHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
1515
1516   EXTRACT_FMT_MULHI_CODE
1517
1518   /* Record the fields for the semantic handler.  */
1519   FLD (i_src1) = & CPU (h_gr)[f_r1];
1520   FLD (i_src2) = & CPU (h_gr)[f_r2];
1521   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1522
1523 #if WITH_PROFILE_MODEL_P
1524   /* Record the fields for profiling.  */
1525   if (PROFILE_MODEL_P (current_cpu))
1526     {
1527       FLD (in_src1) = f_r1;
1528       FLD (in_src2) = f_r2;
1529     }
1530 #endif
1531 #undef FLD
1532   BREAK (ex);
1533   }
1534
1535   CASE (ex, FMT_MV) :
1536   {
1537     CGEN_INSN_INT insn = entire_insn;
1538 #define FLD(f) abuf->fields.fmt_mv.f
1539   EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
1540
1541   EXTRACT_FMT_MV_CODE
1542
1543   /* Record the fields for the semantic handler.  */
1544   FLD (i_sr) = & CPU (h_gr)[f_r2];
1545   FLD (i_dr) = & CPU (h_gr)[f_r1];
1546   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1547
1548 #if WITH_PROFILE_MODEL_P
1549   /* Record the fields for profiling.  */
1550   if (PROFILE_MODEL_P (current_cpu))
1551     {
1552       FLD (in_sr) = f_r2;
1553       FLD (out_dr) = f_r1;
1554     }
1555 #endif
1556 #undef FLD
1557   BREAK (ex);
1558   }
1559
1560   CASE (ex, FMT_MVFACHI) :
1561   {
1562     CGEN_INSN_INT insn = entire_insn;
1563 #define FLD(f) abuf->fields.fmt_mvfachi.f
1564   EXTRACT_FMT_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
1565
1566   EXTRACT_FMT_MVFACHI_CODE
1567
1568   /* Record the fields for the semantic handler.  */
1569   FLD (i_dr) = & CPU (h_gr)[f_r1];
1570   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0));
1571
1572 #if WITH_PROFILE_MODEL_P
1573   /* Record the fields for profiling.  */
1574   if (PROFILE_MODEL_P (current_cpu))
1575     {
1576       FLD (out_dr) = f_r1;
1577     }
1578 #endif
1579 #undef FLD
1580   BREAK (ex);
1581   }
1582
1583   CASE (ex, FMT_MVFC) :
1584   {
1585     CGEN_INSN_INT insn = entire_insn;
1586 #define FLD(f) abuf->fields.fmt_mvfc.f
1587   EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1588
1589   EXTRACT_FMT_MVFC_CODE
1590
1591   /* Record the fields for the semantic handler.  */
1592   FLD (f_r2) = f_r2;
1593   FLD (i_dr) = & CPU (h_gr)[f_r1];
1594   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1595
1596 #if WITH_PROFILE_MODEL_P
1597   /* Record the fields for profiling.  */
1598   if (PROFILE_MODEL_P (current_cpu))
1599     {
1600       FLD (out_dr) = f_r1;
1601     }
1602 #endif
1603 #undef FLD
1604   BREAK (ex);
1605   }
1606
1607   CASE (ex, FMT_MVTACHI) :
1608   {
1609     CGEN_INSN_INT insn = entire_insn;
1610 #define FLD(f) abuf->fields.fmt_mvtachi.f
1611   EXTRACT_FMT_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
1612
1613   EXTRACT_FMT_MVTACHI_CODE
1614
1615   /* Record the fields for the semantic handler.  */
1616   FLD (i_src1) = & CPU (h_gr)[f_r1];
1617   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0));
1618
1619 #if WITH_PROFILE_MODEL_P
1620   /* Record the fields for profiling.  */
1621   if (PROFILE_MODEL_P (current_cpu))
1622     {
1623       FLD (in_src1) = f_r1;
1624     }
1625 #endif
1626 #undef FLD
1627   BREAK (ex);
1628   }
1629
1630   CASE (ex, FMT_MVTC) :
1631   {
1632     CGEN_INSN_INT insn = entire_insn;
1633 #define FLD(f) abuf->fields.fmt_mvtc.f
1634   EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1635
1636   EXTRACT_FMT_MVTC_CODE
1637
1638   /* Record the fields for the semantic handler.  */
1639   FLD (f_r1) = f_r1;
1640   FLD (i_sr) = & CPU (h_gr)[f_r2];
1641   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1642
1643 #if WITH_PROFILE_MODEL_P
1644   /* Record the fields for profiling.  */
1645   if (PROFILE_MODEL_P (current_cpu))
1646     {
1647       FLD (in_sr) = f_r2;
1648     }
1649 #endif
1650 #undef FLD
1651   BREAK (ex);
1652   }
1653
1654   CASE (ex, FMT_NOP) :
1655   {
1656     CGEN_INSN_INT insn = entire_insn;
1657 #define FLD(f) abuf->fields.fmt_nop.f
1658   EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1659
1660   EXTRACT_FMT_NOP_CODE
1661
1662   /* Record the fields for the semantic handler.  */
1663   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0));
1664
1665 #undef FLD
1666   BREAK (ex);
1667   }
1668
1669   CASE (ex, FMT_RAC) :
1670   {
1671     CGEN_INSN_INT insn = entire_insn;
1672 #define FLD(f) abuf->fields.fmt_rac.f
1673   EXTRACT_FMT_RAC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1674
1675   EXTRACT_FMT_RAC_CODE
1676
1677   /* Record the fields for the semantic handler.  */
1678   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac", (char *) 0));
1679
1680 #undef FLD
1681   BREAK (ex);
1682   }
1683
1684   CASE (ex, FMT_RTE) :
1685   {
1686     CGEN_INSN_INT insn = entire_insn;
1687 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1688   EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
1689
1690   EXTRACT_FMT_RTE_CODE
1691
1692   /* Record the fields for the semantic handler.  */
1693   SEM_BRANCH_INIT_EXTRACT (abuf);
1694   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rte", (char *) 0));
1695
1696 #if WITH_PROFILE_MODEL_P
1697   /* Record the fields for profiling.  */
1698   if (PROFILE_MODEL_P (current_cpu))
1699     {
1700     }
1701 #endif
1702 #undef FLD
1703   BREAK (ex);
1704   }
1705
1706   CASE (ex, FMT_SETH) :
1707   {
1708     CGEN_INSN_INT insn = entire_insn;
1709 #define FLD(f) abuf->fields.fmt_seth.f
1710   EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
1711
1712   EXTRACT_FMT_SETH_CODE
1713
1714   /* Record the fields for the semantic handler.  */
1715   FLD (f_hi16) = f_hi16;
1716   FLD (i_dr) = & CPU (h_gr)[f_r1];
1717   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
1718
1719 #if WITH_PROFILE_MODEL_P
1720   /* Record the fields for profiling.  */
1721   if (PROFILE_MODEL_P (current_cpu))
1722     {
1723       FLD (out_dr) = f_r1;
1724     }
1725 #endif
1726 #undef FLD
1727   BREAK (ex);
1728   }
1729
1730   CASE (ex, FMT_SLL3) :
1731   {
1732     CGEN_INSN_INT insn = entire_insn;
1733 #define FLD(f) abuf->fields.fmt_sll3.f
1734   EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1735
1736   EXTRACT_FMT_SLL3_CODE
1737
1738   /* Record the fields for the semantic handler.  */
1739   FLD (f_simm16) = f_simm16;
1740   FLD (i_sr) = & CPU (h_gr)[f_r2];
1741   FLD (i_dr) = & CPU (h_gr)[f_r1];
1742   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1743
1744 #if WITH_PROFILE_MODEL_P
1745   /* Record the fields for profiling.  */
1746   if (PROFILE_MODEL_P (current_cpu))
1747     {
1748       FLD (in_sr) = f_r2;
1749       FLD (out_dr) = f_r1;
1750     }
1751 #endif
1752 #undef FLD
1753   BREAK (ex);
1754   }
1755
1756   CASE (ex, FMT_SLLI) :
1757   {
1758     CGEN_INSN_INT insn = entire_insn;
1759 #define FLD(f) abuf->fields.fmt_slli.f
1760   EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
1761
1762   EXTRACT_FMT_SLLI_CODE
1763
1764   /* Record the fields for the semantic handler.  */
1765   FLD (f_uimm5) = f_uimm5;
1766   FLD (i_dr) = & CPU (h_gr)[f_r1];
1767   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
1768
1769 #if WITH_PROFILE_MODEL_P
1770   /* Record the fields for profiling.  */
1771   if (PROFILE_MODEL_P (current_cpu))
1772     {
1773       FLD (in_dr) = f_r1;
1774       FLD (out_dr) = f_r1;
1775     }
1776 #endif
1777 #undef FLD
1778   BREAK (ex);
1779   }
1780
1781   CASE (ex, FMT_ST) :
1782   {
1783     CGEN_INSN_INT insn = entire_insn;
1784 #define FLD(f) abuf->fields.fmt_st.f
1785   EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */
1786
1787   EXTRACT_FMT_ST_CODE
1788
1789   /* Record the fields for the semantic handler.  */
1790   FLD (i_src2) = & CPU (h_gr)[f_r2];
1791   FLD (i_src1) = & CPU (h_gr)[f_r1];
1792   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1793
1794 #if WITH_PROFILE_MODEL_P
1795   /* Record the fields for profiling.  */
1796   if (PROFILE_MODEL_P (current_cpu))
1797     {
1798       FLD (in_src2) = f_r2;
1799       FLD (in_src1) = f_r1;
1800     }
1801 #endif
1802 #undef FLD
1803   BREAK (ex);
1804   }
1805
1806   CASE (ex, FMT_ST_D) :
1807   {
1808     CGEN_INSN_INT insn = entire_insn;
1809 #define FLD(f) abuf->fields.fmt_st_d.f
1810   EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1811
1812   EXTRACT_FMT_ST_D_CODE
1813
1814   /* Record the fields for the semantic handler.  */
1815   FLD (f_simm16) = f_simm16;
1816   FLD (i_src2) = & CPU (h_gr)[f_r2];
1817   FLD (i_src1) = & CPU (h_gr)[f_r1];
1818   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1819
1820 #if WITH_PROFILE_MODEL_P
1821   /* Record the fields for profiling.  */
1822   if (PROFILE_MODEL_P (current_cpu))
1823     {
1824       FLD (in_src2) = f_r2;
1825       FLD (in_src1) = f_r1;
1826     }
1827 #endif
1828 #undef FLD
1829   BREAK (ex);
1830   }
1831
1832   CASE (ex, FMT_STB) :
1833   {
1834     CGEN_INSN_INT insn = entire_insn;
1835 #define FLD(f) abuf->fields.fmt_stb.f
1836   EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */
1837
1838   EXTRACT_FMT_STB_CODE
1839
1840   /* Record the fields for the semantic handler.  */
1841   FLD (i_src2) = & CPU (h_gr)[f_r2];
1842   FLD (i_src1) = & CPU (h_gr)[f_r1];
1843   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1844
1845 #if WITH_PROFILE_MODEL_P
1846   /* Record the fields for profiling.  */
1847   if (PROFILE_MODEL_P (current_cpu))
1848     {
1849       FLD (in_src2) = f_r2;
1850       FLD (in_src1) = f_r1;
1851     }
1852 #endif
1853 #undef FLD
1854   BREAK (ex);
1855   }
1856
1857   CASE (ex, FMT_STB_D) :
1858   {
1859     CGEN_INSN_INT insn = entire_insn;
1860 #define FLD(f) abuf->fields.fmt_stb_d.f
1861   EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1862
1863   EXTRACT_FMT_STB_D_CODE
1864
1865   /* Record the fields for the semantic handler.  */
1866   FLD (f_simm16) = f_simm16;
1867   FLD (i_src2) = & CPU (h_gr)[f_r2];
1868   FLD (i_src1) = & CPU (h_gr)[f_r1];
1869   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1870
1871 #if WITH_PROFILE_MODEL_P
1872   /* Record the fields for profiling.  */
1873   if (PROFILE_MODEL_P (current_cpu))
1874     {
1875       FLD (in_src2) = f_r2;
1876       FLD (in_src1) = f_r1;
1877     }
1878 #endif
1879 #undef FLD
1880   BREAK (ex);
1881   }
1882
1883   CASE (ex, FMT_STH) :
1884   {
1885     CGEN_INSN_INT insn = entire_insn;
1886 #define FLD(f) abuf->fields.fmt_sth.f
1887   EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */
1888
1889   EXTRACT_FMT_STH_CODE
1890
1891   /* Record the fields for the semantic handler.  */
1892   FLD (i_src2) = & CPU (h_gr)[f_r2];
1893   FLD (i_src1) = & CPU (h_gr)[f_r1];
1894   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1895
1896 #if WITH_PROFILE_MODEL_P
1897   /* Record the fields for profiling.  */
1898   if (PROFILE_MODEL_P (current_cpu))
1899     {
1900       FLD (in_src2) = f_r2;
1901       FLD (in_src1) = f_r1;
1902     }
1903 #endif
1904 #undef FLD
1905   BREAK (ex);
1906   }
1907
1908   CASE (ex, FMT_STH_D) :
1909   {
1910     CGEN_INSN_INT insn = entire_insn;
1911 #define FLD(f) abuf->fields.fmt_sth_d.f
1912   EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1913
1914   EXTRACT_FMT_STH_D_CODE
1915
1916   /* Record the fields for the semantic handler.  */
1917   FLD (f_simm16) = f_simm16;
1918   FLD (i_src2) = & CPU (h_gr)[f_r2];
1919   FLD (i_src1) = & CPU (h_gr)[f_r1];
1920   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1921
1922 #if WITH_PROFILE_MODEL_P
1923   /* Record the fields for profiling.  */
1924   if (PROFILE_MODEL_P (current_cpu))
1925     {
1926       FLD (in_src2) = f_r2;
1927       FLD (in_src1) = f_r1;
1928     }
1929 #endif
1930 #undef FLD
1931   BREAK (ex);
1932   }
1933
1934   CASE (ex, FMT_ST_PLUS) :
1935   {
1936     CGEN_INSN_INT insn = entire_insn;
1937 #define FLD(f) abuf->fields.fmt_st_plus.f
1938   EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
1939
1940   EXTRACT_FMT_ST_PLUS_CODE
1941
1942   /* Record the fields for the semantic handler.  */
1943   FLD (i_src2) = & CPU (h_gr)[f_r2];
1944   FLD (i_src1) = & CPU (h_gr)[f_r1];
1945   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_plus", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1946
1947 #if WITH_PROFILE_MODEL_P
1948   /* Record the fields for profiling.  */
1949   if (PROFILE_MODEL_P (current_cpu))
1950     {
1951       FLD (in_src2) = f_r2;
1952       FLD (in_src1) = f_r1;
1953       FLD (out_src2) = f_r2;
1954     }
1955 #endif
1956 #undef FLD
1957   BREAK (ex);
1958   }
1959
1960   CASE (ex, FMT_TRAP) :
1961   {
1962     CGEN_INSN_INT insn = entire_insn;
1963 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
1964   EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
1965
1966   EXTRACT_FMT_TRAP_CODE
1967
1968   /* Record the fields for the semantic handler.  */
1969   FLD (f_uimm4) = f_uimm4;
1970   SEM_BRANCH_INIT_EXTRACT (abuf);
1971   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
1972
1973 #if WITH_PROFILE_MODEL_P
1974   /* Record the fields for profiling.  */
1975   if (PROFILE_MODEL_P (current_cpu))
1976     {
1977     }
1978 #endif
1979 #undef FLD
1980   BREAK (ex);
1981   }
1982
1983   CASE (ex, FMT_UNLOCK) :
1984   {
1985     CGEN_INSN_INT insn = entire_insn;
1986 #define FLD(f) abuf->fields.fmt_unlock.f
1987   EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
1988
1989   EXTRACT_FMT_UNLOCK_CODE
1990
1991   /* Record the fields for the semantic handler.  */
1992   FLD (i_src2) = & CPU (h_gr)[f_r2];
1993   FLD (i_src1) = & CPU (h_gr)[f_r1];
1994   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_unlock", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1995
1996 #if WITH_PROFILE_MODEL_P
1997   /* Record the fields for profiling.  */
1998   if (PROFILE_MODEL_P (current_cpu))
1999     {
2000       FLD (in_src2) = f_r2;
2001       FLD (in_src1) = f_r1;
2002     }
2003 #endif
2004 #undef FLD
2005   BREAK (ex);
2006   }
2007
2008
2009       }
2010     ENDSWITCH (ex)
2011
2012   }
2013
2014   return idecode->idesc;
2015 }