sim/m32r/decode.c

   1 /* Simulator instruction decoder for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #define WANT_CPU
  26 #define WANT_CPU_M32RBF
  27
  28 #include "sim-main.h"
  29 #include "sim-assert.h"
  30
  31 /* FIXME: Need to review choices for the following.  */
  32
  33 #if WITH_SEM_SWITCH_FULL
  34 #define FULL(fn)
  35 #else
  36 #define FULL(fn) CONCAT3 (m32rbf,_sem_,fn) ,
  37 #endif
  38
  39 #if WITH_FAST
  40 #if WITH_SEM_SWITCH_FAST
  41 #define FAST(fn)
  42 #else
  43 #define FAST(fn) CONCAT3 (m32rbf,_semf_,fn) , /* f for fast */
  44 #endif
  45 #else
  46 #define FAST(fn)
  47 #endif
  48
  49 /* The instruction descriptor array.
  50    This is computed at runtime.  Space for it is not malloc'd to save a
  51    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
  52    but won't be done until necessary (we don't currently support the runtime
  53    addition of instructions nor an SMP machine with different cpus).  */
  54 static IDESC m32rbf_insn_data[M32RBF_INSN_MAX];
  55
  56 /* Instruction semantic handlers and support.
  57    This struct defines the part of an IDESC that can be computed at
  58    compile time.  */
  59
  60 struct insn_sem {
  61   /* The instruction type (a number that identifies each insn over the
  62      entire architecture).  */
  63   CGEN_INSN_TYPE type;
  64
  65   /* Index in IDESC table.  */
  66   int index;
  67
  68   /* Routines to execute the insn.
  69      The full version has all features (profiling,tracing) compiled in.
  70      The fast version has none of that.  */
  71 #if ! WITH_SEM_SWITCH_FULL
  72   SEMANTIC_FN *sem_full;
  73 #endif
  74 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
  75   SEMANTIC_FN *sem_fast;
  76 #endif
  77
  78 };
  79 /* The INSN_ prefix is not here and is instead part of the `insn' argument
  80    to avoid collisions with header files (e.g. `AND' in ansidecl.h).  */
  81 #define IDX(insn) CONCAT2 (M32RBF_,insn)
  82 #define TYPE(insn) CONCAT2 (M32R_,insn)
  83
  84 /* Commas between elements are contained in the macros.
  85    Some of these are conditionally compiled out.  */
  86
  87 static const struct insn_sem m32rbf_insn_sem[] =
  88 {
  89   { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid) },
  90   { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), FULL (x_after) FAST (x_after) },
  91   { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), FULL (x_before) FAST (x_before) },
  92   { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), FULL (x_cti_chain) FAST (x_cti_chain) },
  93   { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), FULL (x_chain) FAST (x_chain) },
  94   { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), FULL (x_begin) FAST (x_begin) },
  95   { TYPE (INSN_ADD), IDX (INSN_ADD), FULL (add) FAST (add) },
  96   { TYPE (INSN_ADD3), IDX (INSN_ADD3), FULL (add3) FAST (add3) },
  97   { TYPE (INSN_AND), IDX (INSN_AND), FULL (and) FAST (and) },
  98   { TYPE (INSN_AND3), IDX (INSN_AND3), FULL (and3) FAST (and3) },
  99   { TYPE (INSN_OR), IDX (INSN_OR), FULL (or) FAST (or) },
 100   { TYPE (INSN_OR3), IDX (INSN_OR3), FULL (or3) FAST (or3) },
 101   { TYPE (INSN_XOR), IDX (INSN_XOR), FULL (xor) FAST (xor) },
 102   { TYPE (INSN_XOR3), IDX (INSN_XOR3), FULL (xor3) FAST (xor3) },
 103   { TYPE (INSN_ADDI), IDX (INSN_ADDI), FULL (addi) FAST (addi) },
 104   { TYPE (INSN_ADDV), IDX (INSN_ADDV), FULL (addv) FAST (addv) },
 105   { TYPE (INSN_ADDV3), IDX (INSN_ADDV3), FULL (addv3) FAST (addv3) },
 106   { TYPE (INSN_ADDX), IDX (INSN_ADDX), FULL (addx) FAST (addx) },
 107   { TYPE (INSN_BC8), IDX (INSN_BC8), FULL (bc8) FAST (bc8) },
 108   { TYPE (INSN_BC24), IDX (INSN_BC24), FULL (bc24) FAST (bc24) },
 109   { TYPE (INSN_BEQ), IDX (INSN_BEQ), FULL (beq) FAST (beq) },
 110   { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), FULL (beqz) FAST (beqz) },
 111   { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), FULL (bgez) FAST (bgez) },
 112   { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), FULL (bgtz) FAST (bgtz) },
 113   { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), FULL (blez) FAST (blez) },
 114   { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), FULL (bltz) FAST (bltz) },
 115   { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), FULL (bnez) FAST (bnez) },
 116   { TYPE (INSN_BL8), IDX (INSN_BL8), FULL (bl8) FAST (bl8) },
 117   { TYPE (INSN_BL24), IDX (INSN_BL24), FULL (bl24) FAST (bl24) },
 118   { TYPE (INSN_BNC8), IDX (INSN_BNC8), FULL (bnc8) FAST (bnc8) },
 119   { TYPE (INSN_BNC24), IDX (INSN_BNC24), FULL (bnc24) FAST (bnc24) },
 120   { TYPE (INSN_BNE), IDX (INSN_BNE), FULL (bne) FAST (bne) },
 121   { TYPE (INSN_BRA8), IDX (INSN_BRA8), FULL (bra8) FAST (bra8) },
 122   { TYPE (INSN_BRA24), IDX (INSN_BRA24), FULL (bra24) FAST (bra24) },
 123   { TYPE (INSN_CMP), IDX (INSN_CMP), FULL (cmp) FAST (cmp) },
 124   { TYPE (INSN_CMPI), IDX (INSN_CMPI), FULL (cmpi) FAST (cmpi) },
 125   { TYPE (INSN_CMPU), IDX (INSN_CMPU), FULL (cmpu) FAST (cmpu) },
 126   { TYPE (INSN_CMPUI), IDX (INSN_CMPUI), FULL (cmpui) FAST (cmpui) },
 127   { TYPE (INSN_DIV), IDX (INSN_DIV), FULL (div) FAST (div) },
 128   { TYPE (INSN_DIVU), IDX (INSN_DIVU), FULL (divu) FAST (divu) },
 129   { TYPE (INSN_REM), IDX (INSN_REM), FULL (rem) FAST (rem) },
 130   { TYPE (INSN_REMU), IDX (INSN_REMU), FULL (remu) FAST (remu) },
 131   { TYPE (INSN_JL), IDX (INSN_JL), FULL (jl) FAST (jl) },
 132   { TYPE (INSN_JMP), IDX (INSN_JMP), FULL (jmp) FAST (jmp) },
 133   { TYPE (INSN_LD), IDX (INSN_LD), FULL (ld) FAST (ld) },
 134   { TYPE (INSN_LD_D), IDX (INSN_LD_D), FULL (ld_d) FAST (ld_d) },
 135   { TYPE (INSN_LDB), IDX (INSN_LDB), FULL (ldb) FAST (ldb) },
 136   { TYPE (INSN_LDB_D), IDX (INSN_LDB_D), FULL (ldb_d) FAST (ldb_d) },
 137   { TYPE (INSN_LDH), IDX (INSN_LDH), FULL (ldh) FAST (ldh) },
 138   { TYPE (INSN_LDH_D), IDX (INSN_LDH_D), FULL (ldh_d) FAST (ldh_d) },
 139   { TYPE (INSN_LDUB), IDX (INSN_LDUB), FULL (ldub) FAST (ldub) },
 140   { TYPE (INSN_LDUB_D), IDX (INSN_LDUB_D), FULL (ldub_d) FAST (ldub_d) },
 141   { TYPE (INSN_LDUH), IDX (INSN_LDUH), FULL (lduh) FAST (lduh) },
 142   { TYPE (INSN_LDUH_D), IDX (INSN_LDUH_D), FULL (lduh_d) FAST (lduh_d) },
 143   { TYPE (INSN_LD_PLUS), IDX (INSN_LD_PLUS), FULL (ld_plus) FAST (ld_plus) },
 144   { TYPE (INSN_LD24), IDX (INSN_LD24), FULL (ld24) FAST (ld24) },
 145   { TYPE (INSN_LDI8), IDX (INSN_LDI8), FULL (ldi8) FAST (ldi8) },
 146   { TYPE (INSN_LDI16), IDX (INSN_LDI16), FULL (ldi16) FAST (ldi16) },
 147   { TYPE (INSN_LOCK), IDX (INSN_LOCK), FULL (lock) FAST (lock) },
 148   { TYPE (INSN_MACHI), IDX (INSN_MACHI), FULL (machi) FAST (machi) },
 149   { TYPE (INSN_MACLO), IDX (INSN_MACLO), FULL (maclo) FAST (maclo) },
 150   { TYPE (INSN_MACWHI), IDX (INSN_MACWHI), FULL (macwhi) FAST (macwhi) },
 151   { TYPE (INSN_MACWLO), IDX (INSN_MACWLO), FULL (macwlo) FAST (macwlo) },
 152   { TYPE (INSN_MUL), IDX (INSN_MUL), FULL (mul) FAST (mul) },
 153   { TYPE (INSN_MULHI), IDX (INSN_MULHI), FULL (mulhi) FAST (mulhi) },
 154   { TYPE (INSN_MULLO), IDX (INSN_MULLO), FULL (mullo) FAST (mullo) },
 155   { TYPE (INSN_MULWHI), IDX (INSN_MULWHI), FULL (mulwhi) FAST (mulwhi) },
 156   { TYPE (INSN_MULWLO), IDX (INSN_MULWLO), FULL (mulwlo) FAST (mulwlo) },
 157   { TYPE (INSN_MV), IDX (INSN_MV), FULL (mv) FAST (mv) },
 158   { TYPE (INSN_MVFACHI), IDX (INSN_MVFACHI), FULL (mvfachi) FAST (mvfachi) },
 159   { TYPE (INSN_MVFACLO), IDX (INSN_MVFACLO), FULL (mvfaclo) FAST (mvfaclo) },
 160   { TYPE (INSN_MVFACMI), IDX (INSN_MVFACMI), FULL (mvfacmi) FAST (mvfacmi) },
 161   { TYPE (INSN_MVFC), IDX (INSN_MVFC), FULL (mvfc) FAST (mvfc) },
 162   { TYPE (INSN_MVTACHI), IDX (INSN_MVTACHI), FULL (mvtachi) FAST (mvtachi) },
 163   { TYPE (INSN_MVTACLO), IDX (INSN_MVTACLO), FULL (mvtaclo) FAST (mvtaclo) },
 164   { TYPE (INSN_MVTC), IDX (INSN_MVTC), FULL (mvtc) FAST (mvtc) },
 165   { TYPE (INSN_NEG), IDX (INSN_NEG), FULL (neg) FAST (neg) },
 166   { TYPE (INSN_NOP), IDX (INSN_NOP), FULL (nop) FAST (nop) },
 167   { TYPE (INSN_NOT), IDX (INSN_NOT), FULL (not) FAST (not) },
 168   { TYPE (INSN_RAC), IDX (INSN_RAC), FULL (rac) FAST (rac) },
 169   { TYPE (INSN_RACH), IDX (INSN_RACH), FULL (rach) FAST (rach) },
 170   { TYPE (INSN_RTE), IDX (INSN_RTE), FULL (rte) FAST (rte) },
 171   { TYPE (INSN_SETH), IDX (INSN_SETH), FULL (seth) FAST (seth) },
 172   { TYPE (INSN_SLL), IDX (INSN_SLL), FULL (sll) FAST (sll) },
 173   { TYPE (INSN_SLL3), IDX (INSN_SLL3), FULL (sll3) FAST (sll3) },
 174   { TYPE (INSN_SLLI), IDX (INSN_SLLI), FULL (slli) FAST (slli) },
 175   { TYPE (INSN_SRA), IDX (INSN_SRA), FULL (sra) FAST (sra) },
 176   { TYPE (INSN_SRA3), IDX (INSN_SRA3), FULL (sra3) FAST (sra3) },
 177   { TYPE (INSN_SRAI), IDX (INSN_SRAI), FULL (srai) FAST (srai) },
 178   { TYPE (INSN_SRL), IDX (INSN_SRL), FULL (srl) FAST (srl) },
 179   { TYPE (INSN_SRL3), IDX (INSN_SRL3), FULL (srl3) FAST (srl3) },
 180   { TYPE (INSN_SRLI), IDX (INSN_SRLI), FULL (srli) FAST (srli) },
 181   { TYPE (INSN_ST), IDX (INSN_ST), FULL (st) FAST (st) },
 182   { TYPE (INSN_ST_D), IDX (INSN_ST_D), FULL (st_d) FAST (st_d) },
 183   { TYPE (INSN_STB), IDX (INSN_STB), FULL (stb) FAST (stb) },
 184   { TYPE (INSN_STB_D), IDX (INSN_STB_D), FULL (stb_d) FAST (stb_d) },
 185   { TYPE (INSN_STH), IDX (INSN_STH), FULL (sth) FAST (sth) },
 186   { TYPE (INSN_STH_D), IDX (INSN_STH_D), FULL (sth_d) FAST (sth_d) },
 187   { TYPE (INSN_ST_PLUS), IDX (INSN_ST_PLUS), FULL (st_plus) FAST (st_plus) },
 188   { TYPE (INSN_ST_MINUS), IDX (INSN_ST_MINUS), FULL (st_minus) FAST (st_minus) },
 189   { TYPE (INSN_SUB), IDX (INSN_SUB), FULL (sub) FAST (sub) },
 190   { TYPE (INSN_SUBV), IDX (INSN_SUBV), FULL (subv) FAST (subv) },
 191   { TYPE (INSN_SUBX), IDX (INSN_SUBX), FULL (subx) FAST (subx) },
 192   { TYPE (INSN_TRAP), IDX (INSN_TRAP), FULL (trap) FAST (trap) },
 193   { TYPE (INSN_UNLOCK), IDX (INSN_UNLOCK), FULL (unlock) FAST (unlock) },
 194 };
 195
 196 static const struct insn_sem m32rbf_insn_sem_invalid =
 197 {
 198   VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), FULL (x_invalid) FAST (x_invalid)
 199 };
 200
 201 #undef IDX
 202 #undef TYPE
 203
 204 /* Initialize an IDESC from the compile-time computable parts.  */
 205
 206 static INLINE void
 207 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
 208 {
 209   const CGEN_INSN *opcode_table = m32r_cgen_insn_table_entries;
 210
 211   id->num = t->index;
 212   if ((int) t->type <= 0)
 213     id->opcode = & cgen_virtual_opcode_table[- t->type];
 214   else
 215     id->opcode = & opcode_table[t->type];
 216 #if ! WITH_SEM_SWITCH_FULL
 217   id->sem_full = t->sem_full;
 218 #endif
 219 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
 220   id->sem_fast = t->sem_fast;
 221 #endif
 222 #if WITH_PROFILE_MODEL_P
 223   id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
 224   {
 225     SIM_DESC sd = CPU_STATE (cpu);
 226     SIM_ASSERT (t->index == id->timing->num);
 227   }
 228 #endif
 229 }
 230
 231 /* Initialize the instruction descriptor table.  */
 232
 233 void
 234 m32rbf_init_idesc_table (SIM_CPU *cpu)
 235 {
 236   IDESC *id,*tabend;
 237   const struct insn_sem *t,*tend;
 238   int tabsize = M32RBF_INSN_MAX;
 239   IDESC *table = m32rbf_insn_data;
 240
 241   memset (table, 0, tabsize * sizeof (IDESC));
 242
 243   /* First set all entries to the `invalid insn'.  */
 244   t = & m32rbf_insn_sem_invalid;
 245   for (id = table, tabend = table + tabsize; id < tabend; ++id)
 246     init_idesc (cpu, id, t);
 247
 248   /* Now fill in the values for the chosen cpu.  */
 249   for (t = m32rbf_insn_sem, tend = t + sizeof (m32rbf_insn_sem) / sizeof (*t);
 250        t != tend; ++t)
 251     {
 252       init_idesc (cpu, & table[t->index], t);
 253     }
 254
 255   /* Link the IDESC table into the cpu.  */
 256   CPU_IDESC (cpu) = table;
 257 }
 258
 259 /* Enum declaration for all instruction formats.  */
 260 typedef enum ifmt {
 261   FMT_ADD, FMT_ADD3, FMT_AND3, FMT_OR3
 262  , FMT_ADDI, FMT_ADDV, FMT_ADDV3, FMT_ADDX
 263  , FMT_BC8, FMT_BC24, FMT_BEQ, FMT_BEQZ
 264  , FMT_BL8, FMT_BL24, FMT_BRA8, FMT_BRA24
 265  , FMT_CMP, FMT_CMPI, FMT_DIV, FMT_JL
 266  , FMT_JMP, FMT_LD, FMT_LD_D, FMT_LDB
 267  , FMT_LDB_D, FMT_LDH, FMT_LDH_D, FMT_LD_PLUS
 268  , FMT_LD24, FMT_LDI8, FMT_LDI16, FMT_LOCK
 269  , FMT_MACHI, FMT_MULHI, FMT_MV, FMT_MVFACHI
 270  , FMT_MVFC, FMT_MVTACHI, FMT_MVTC, FMT_NOP
 271  , FMT_RAC, FMT_RTE, FMT_SETH, FMT_SLL3
 272  , FMT_SLLI, FMT_ST, FMT_ST_D, FMT_STB
 273  , FMT_STB_D, FMT_STH, FMT_STH_D, FMT_ST_PLUS
 274  , FMT_TRAP, FMT_UNLOCK
 275 } IFMT;
 276
 277 /* The decoder uses this to record insns and direct extraction handling.  */
 278
 279 typedef struct {
 280   const IDESC *idesc;
 281 #ifdef __GNUC__
 282   void *ifmt;
 283 #else
 284   enum ifmt ifmt;
 285 #endif
 286 } DECODE_DESC;
 287
 288 /* Macro to go from decode phase to extraction phase.  */
 289
 290 #ifdef __GNUC__
 291 #define GOTO_EXTRACT(id) goto *(id)->ifmt
 292 #else
 293 #define GOTO_EXTRACT(id) goto extract
 294 #endif
 295
 296 /* The decoder needs a slightly different computed goto switch control.  */
 297 #ifdef __GNUC__
 298 #define DECODE_SWITCH(N, X) goto *labels_##N[X];
 299 #else
 300 #define DECODE_SWITCH(N, X) switch (X)
 301 #endif
 302
 303 /* Given an instruction, return a pointer to its IDESC entry.  */
 304
 305 const IDESC *
 306 m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
 307               CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
 308               ARGBUF *abuf)
 309 {
 310   /* Result of decoder, used by extractor.  */
 311   const DECODE_DESC *idecode;
 312
 313   /* First decode the instruction.  */
 314
 315   {
 316 #define I(insn) & m32rbf_insn_data[CONCAT2 (M32RBF_,insn)]
 317 #ifdef __GNUC__
 318 #define E(fmt) && case_ex_##fmt
 319 #else
 320 #define E(fmt) fmt
 321 #endif
 322     CGEN_INSN_INT insn = base_insn;
 323     static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
 324     {
 325 #ifdef __GNUC__
 326       static const void *labels_0[256] = {
 327         && default_0, && default_0, && default_0, && default_0,
 328         && default_0, && default_0, && default_0, && default_0,
 329         && default_0, && default_0, && default_0, && default_0,
 330         && default_0, && default_0, && default_0, && default_0,
 331         && default_0, && default_0, && default_0, && default_0,
 332         && default_0, && default_0, && default_0, && default_0,
 333         && default_0, && default_0, && default_0, && default_0,
 334         && case_0_28, && default_0, && default_0, && default_0,
 335         && default_0, && default_0, && default_0, && default_0,
 336         && default_0, && default_0, && default_0, && default_0,
 337         && default_0, && default_0, && default_0, && default_0,
 338         && default_0, && default_0, && default_0, && default_0,
 339         && default_0, && default_0, && default_0, && default_0,
 340         && default_0, && default_0, && default_0, && default_0,
 341         && default_0, && default_0, && default_0, && default_0,
 342         && default_0, && default_0, && default_0, && default_0,
 343         && default_0, && default_0, && default_0, && default_0,
 344         && default_0, && default_0, && default_0, && default_0,
 345         && default_0, && default_0, && default_0, && default_0,
 346         && default_0, && default_0, && default_0, && default_0,
 347         && default_0, && default_0, && default_0, && default_0,
 348         && default_0, && default_0, && default_0, && case_0_87,
 349         && default_0, && default_0, && default_0, && default_0,
 350         && default_0, && default_0, && default_0, && case_0_95,
 351         && default_0, && default_0, && default_0, && default_0,
 352         && default_0, && default_0, && default_0, && default_0,
 353         && default_0, && default_0, && default_0, && default_0,
 354         && default_0, && default_0, && default_0, && default_0,
 355         && case_0_112, && case_0_113, && case_0_114, && case_0_115,
 356         && case_0_116, && case_0_117, && case_0_118, && case_0_119,
 357         && case_0_120, && case_0_121, && case_0_122, && case_0_123,
 358         && case_0_124, && case_0_125, && case_0_126, && case_0_127,
 359         && default_0, && default_0, && default_0, && default_0,
 360         && default_0, && default_0, && default_0, && default_0,
 361         && default_0, && default_0, && default_0, && default_0,
 362         && default_0, && default_0, && default_0, && default_0,
 363         && default_0, && default_0, && default_0, && default_0,
 364         && default_0, && default_0, && default_0, && default_0,
 365         && default_0, && default_0, && default_0, && default_0,
 366         && default_0, && default_0, && default_0, && default_0,
 367         && default_0, && default_0, && default_0, && default_0,
 368         && default_0, && default_0, && default_0, && default_0,
 369         && default_0, && default_0, && default_0, && default_0,
 370         && default_0, && default_0, && default_0, && default_0,
 371         && default_0, && default_0, && default_0, && default_0,
 372         && default_0, && default_0, && default_0, && default_0,
 373         && default_0, && default_0, && default_0, && default_0,
 374         && default_0, && default_0, && default_0, && default_0,
 375         && default_0, && default_0, && default_0, && default_0,
 376         && default_0, && default_0, && default_0, && default_0,
 377         && default_0, && default_0, && default_0, && default_0,
 378         && default_0, && default_0, && default_0, && default_0,
 379         && default_0, && default_0, && default_0, && default_0,
 380         && default_0, && default_0, && default_0, && default_0,
 381         && default_0, && default_0, && default_0, && default_0,
 382         && default_0, && default_0, && default_0, && default_0,
 383         && default_0, && default_0, && default_0, && default_0,
 384         && default_0, && default_0, && default_0, && default_0,
 385         && default_0, && default_0, && default_0, && default_0,
 386         && default_0, && default_0, && default_0, && default_0,
 387         && case_0_240, && case_0_241, && case_0_242, && case_0_243,
 388         && case_0_244, && case_0_245, && case_0_246, && case_0_247,
 389         && case_0_248, && case_0_249, && case_0_250, && case_0_251,
 390         && case_0_252, && case_0_253, && case_0_254, && case_0_255,
 391       };
 392 #endif
 393       static const DECODE_DESC insns[256] = {
 394         { I (INSN_SUBV), E (FMT_ADDV) }, { I (INSN_SUBX), E (FMT_ADDX) },
 395         { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_NEG), E (FMT_MV) },
 396         { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_CMPU), E (FMT_CMP) },
 397         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 398         { I (INSN_ADDV), E (FMT_ADDV) }, { I (INSN_ADDX), E (FMT_ADDX) },
 399         { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_NOT), E (FMT_MV) },
 400         { I (INSN_AND), E (FMT_ADD) }, { I (INSN_XOR), E (FMT_ADD) },
 401         { I (INSN_OR), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 402         { I (INSN_SRL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 403         { I (INSN_SRA), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 404         { I (INSN_SLL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 405         { I (INSN_MUL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 406         { I (INSN_MV), E (FMT_MV) }, { I (INSN_MVFC), E (FMT_MVFC) },
 407         { I (INSN_MVTC), E (FMT_MVTC) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 408         { 0 }, { I (INSN_RTE), E (FMT_RTE) },
 409         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_TRAP), E (FMT_TRAP) },
 410         { I (INSN_STB), E (FMT_STB) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 411         { I (INSN_STH), E (FMT_STH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 412         { I (INSN_ST), E (FMT_ST) }, { I (INSN_UNLOCK), E (FMT_UNLOCK) },
 413         { I (INSN_ST_PLUS), E (FMT_ST_PLUS) }, { I (INSN_ST_MINUS), E (FMT_ST_PLUS) },
 414         { I (INSN_LDB), E (FMT_LDB) }, { I (INSN_LDUB), E (FMT_LDB) },
 415         { I (INSN_LDH), E (FMT_LDH) }, { I (INSN_LDUH), E (FMT_LDH) },
 416         { I (INSN_LD), E (FMT_LD) }, { I (INSN_LOCK), E (FMT_LOCK) },
 417         { I (INSN_LD_PLUS), E (FMT_LD_PLUS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 418         { I (INSN_MULHI), E (FMT_MULHI) }, { I (INSN_MULLO), E (FMT_MULHI) },
 419         { I (INSN_MULWHI), E (FMT_MULHI) }, { I (INSN_MULWLO), E (FMT_MULHI) },
 420         { I (INSN_MACHI), E (FMT_MACHI) }, { I (INSN_MACLO), E (FMT_MACHI) },
 421         { I (INSN_MACWHI), E (FMT_MACHI) }, { I (INSN_MACWLO), E (FMT_MACHI) },
 422         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 423         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 424         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 425         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 426         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 427         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 428         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 429         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 430         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 431         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 432         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 433         { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
 434         { I (INSN_SRLI), E (FMT_SLLI) }, { I (INSN_SRLI), E (FMT_SLLI) },
 435         { I (INSN_SRAI), E (FMT_SLLI) }, { I (INSN_SRAI), E (FMT_SLLI) },
 436         { I (INSN_SLLI), E (FMT_SLLI) }, { I (INSN_SLLI), E (FMT_SLLI) },
 437         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
 438         { I (INSN_RACH), E (FMT_RAC) }, { I (INSN_RAC), E (FMT_RAC) },
 439         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 440         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 441         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
 442         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 443         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 444         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 445         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 446         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 447         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 448         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 449         { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
 450         { 0 }, { 0 },
 451         { 0 }, { 0 },
 452         { 0 }, { 0 },
 453         { 0 }, { 0 },
 454         { 0 }, { 0 },
 455         { 0 }, { 0 },
 456         { 0 }, { 0 },
 457         { 0 }, { 0 },
 458         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 459         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 460         { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMPUI), E (FMT_CMPI) },
 461         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 462         { I (INSN_ADDV3), E (FMT_ADDV3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 463         { I (INSN_ADD3), E (FMT_ADD3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 464         { I (INSN_AND3), E (FMT_AND3) }, { I (INSN_XOR3), E (FMT_AND3) },
 465         { I (INSN_OR3), E (FMT_OR3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 466         { I (INSN_DIV), E (FMT_DIV) }, { I (INSN_DIVU), E (FMT_DIV) },
 467         { I (INSN_REM), E (FMT_DIV) }, { I (INSN_REMU), E (FMT_DIV) },
 468         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 469         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 470         { I (INSN_SRL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 471         { I (INSN_SRA3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 472         { I (INSN_SLL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 473         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDI16), E (FMT_LDI16) },
 474         { I (INSN_STB_D), E (FMT_STB_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 475         { I (INSN_STH_D), E (FMT_STH_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 476         { I (INSN_ST_D), E (FMT_ST_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 477         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 478         { I (INSN_LDB_D), E (FMT_LDB_D) }, { I (INSN_LDUB_D), E (FMT_LDB_D) },
 479         { I (INSN_LDH_D), E (FMT_LDH_D) }, { I (INSN_LDUH_D), E (FMT_LDH_D) },
 480         { I (INSN_LD_D), E (FMT_LD_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 481         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 482         { I (INSN_BEQ), E (FMT_BEQ) }, { I (INSN_BNE), E (FMT_BEQ) },
 483         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 484         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 485         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 486         { I (INSN_BEQZ), E (FMT_BEQZ) }, { I (INSN_BNEZ), E (FMT_BEQZ) },
 487         { I (INSN_BLTZ), E (FMT_BEQZ) }, { I (INSN_BGEZ), E (FMT_BEQZ) },
 488         { I (INSN_BLEZ), E (FMT_BEQZ) }, { I (INSN_BGTZ), E (FMT_BEQZ) },
 489         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 490         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 491         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 492         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 493         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 494         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 495         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 496         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 497         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 498         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 499         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 500         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 501         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 502         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 503         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 504         { I (INSN_SETH), E (FMT_SETH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 505         { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 506         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 507         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 508         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 509         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 510         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 511         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 512         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 513         { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
 514         { 0 }, { 0 },
 515         { 0 }, { 0 },
 516         { 0 }, { 0 },
 517         { 0 }, { 0 },
 518         { 0 }, { 0 },
 519         { 0 }, { 0 },
 520         { 0 }, { 0 },
 521         { 0 }, { 0 },
 522       };
 523       unsigned int val;
 524       val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
 525       DECODE_SWITCH (0, val)
 526         {
 527         CASE (0, 28) :
 528           {
 529             static const DECODE_DESC insns[16] = {
 530               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 531               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 532               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 533               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 534               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 535               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 536               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 537               { I (INSN_JL), E (FMT_JL) }, { I (INSN_JMP), E (FMT_JMP) },
 538             };
 539             unsigned int val = (((insn >> 8) & (15 << 0)));
 540             idecode = &insns[val];
 541             GOTO_EXTRACT (idecode);
 542           }
 543         CASE (0, 87) :
 544           {
 545             static const DECODE_DESC insns[16] = {
 546               { I (INSN_MVTACHI), E (FMT_MVTACHI) }, { I (INSN_MVTACLO), E (FMT_MVTACHI) },
 547               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 548               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 549               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 550               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 551               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 552               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 553               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 554             };
 555             unsigned int val = (((insn >> 0) & (15 << 0)));
 556             idecode = &insns[val];
 557             GOTO_EXTRACT (idecode);
 558           }
 559         CASE (0, 95) :
 560           {
 561             static const DECODE_DESC insns[16] = {
 562               { I (INSN_MVFACHI), E (FMT_MVFACHI) }, { I (INSN_MVFACLO), E (FMT_MVFACHI) },
 563               { I (INSN_MVFACMI), E (FMT_MVFACHI) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 564               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 565               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 566               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 567               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 568               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 569               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 570             };
 571             unsigned int val = (((insn >> 0) & (15 << 0)));
 572             idecode = &insns[val];
 573             GOTO_EXTRACT (idecode);
 574           }
 575         CASE (0, 112) :
 576           {
 577             static const DECODE_DESC insns[16] = {
 578               { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 579               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 580               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 581               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 582               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 583               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 584               { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) },
 585               { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) },
 586             };
 587             unsigned int val = (((insn >> 8) & (15 << 0)));
 588             idecode = &insns[val];
 589             GOTO_EXTRACT (idecode);
 590           }
 591         CASE (0, 113) : /* fall through */
 592         CASE (0, 114) : /* fall through */
 593         CASE (0, 115) : /* fall through */
 594         CASE (0, 116) : /* fall through */
 595         CASE (0, 117) : /* fall through */
 596         CASE (0, 118) : /* fall through */
 597         CASE (0, 119) : /* fall through */
 598         CASE (0, 120) : /* fall through */
 599         CASE (0, 121) : /* fall through */
 600         CASE (0, 122) : /* fall through */
 601         CASE (0, 123) : /* fall through */
 602         CASE (0, 124) : /* fall through */
 603         CASE (0, 125) : /* fall through */
 604         CASE (0, 126) : /* fall through */
 605         CASE (0, 127) :
 606           {
 607             static const DECODE_DESC insns[16] = {
 608               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 609               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 610               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 611               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 612               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 613               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 614               { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) },
 615               { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) },
 616             };
 617             unsigned int val = (((insn >> 8) & (15 << 0)));
 618             idecode = &insns[val];
 619             GOTO_EXTRACT (idecode);
 620           }
 621         CASE (0, 240) : /* fall through */
 622         CASE (0, 241) : /* fall through */
 623         CASE (0, 242) : /* fall through */
 624         CASE (0, 243) : /* fall through */
 625         CASE (0, 244) : /* fall through */
 626         CASE (0, 245) : /* fall through */
 627         CASE (0, 246) : /* fall through */
 628         CASE (0, 247) : /* fall through */
 629         CASE (0, 248) : /* fall through */
 630         CASE (0, 249) : /* fall through */
 631         CASE (0, 250) : /* fall through */
 632         CASE (0, 251) : /* fall through */
 633         CASE (0, 252) : /* fall through */
 634         CASE (0, 253) : /* fall through */
 635         CASE (0, 254) : /* fall through */
 636         CASE (0, 255) :
 637           {
 638             static const DECODE_DESC insns[16] = {
 639               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 640               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 641               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 642               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 643               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 644               { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
 645               { I (INSN_BC24), E (FMT_BC24) }, { I (INSN_BNC24), E (FMT_BC24) },
 646               { I (INSN_BL24), E (FMT_BL24) }, { I (INSN_BRA24), E (FMT_BRA24) },
 647             };
 648             unsigned int val = (((insn >> 8) & (15 << 0)));
 649             idecode = &insns[val];
 650             GOTO_EXTRACT (idecode);
 651           }
 652         DEFAULT (0) :
 653           idecode = &insns[val];
 654           GOTO_EXTRACT (idecode);
 655         }
 656       ENDSWITCH (0)
 657     }
 658 #undef I
 659 #undef E
 660   }
 661
 662   /* The instruction has been decoded, now extract the fields.  */
 663
 664  extract:
 665   {
 666 #ifndef __GNUC__
 667     switch (idecode->ifmt)
 668 #endif
 669       {
 670
 671   CASE (ex, FMT_ADD) :
 672   {
 673     CGEN_INSN_INT insn = entire_insn;
 674 #define FLD(f) abuf->fields.fmt_add.f
 675   EXTRACT_FMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 676
 677   EXTRACT_FMT_ADD_CODE
 678
 679   /* Record the fields for the semantic handler.  */
 680   FLD (i_dr) = & CPU (h_gr)[f_r1];
 681   FLD (i_sr) = & CPU (h_gr)[f_r2];
 682   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 683
 684 #if WITH_PROFILE_MODEL_P
 685   /* Record the fields for profiling.  */
 686   if (PROFILE_MODEL_P (current_cpu))
 687     {
 688       FLD (in_dr) = f_r1;
 689       FLD (in_sr) = f_r2;
 690       FLD (out_dr) = f_r1;
 691     }
 692 #endif
 693 #undef FLD
 694   BREAK (ex);
 695   }
 696
 697   CASE (ex, FMT_ADD3) :
 698   {
 699     CGEN_INSN_INT insn = entire_insn;
 700 #define FLD(f) abuf->fields.fmt_add3.f
 701   EXTRACT_FMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 702
 703   EXTRACT_FMT_ADD3_CODE
 704
 705   /* Record the fields for the semantic handler.  */
 706   FLD (i_sr) = & CPU (h_gr)[f_r2];
 707   FLD (f_simm16) = f_simm16;
 708   FLD (i_dr) = & CPU (h_gr)[f_r1];
 709   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
 710
 711 #if WITH_PROFILE_MODEL_P
 712   /* Record the fields for profiling.  */
 713   if (PROFILE_MODEL_P (current_cpu))
 714     {
 715       FLD (in_sr) = f_r2;
 716       FLD (out_dr) = f_r1;
 717     }
 718 #endif
 719 #undef FLD
 720   BREAK (ex);
 721   }
 722
 723   CASE (ex, FMT_AND3) :
 724   {
 725     CGEN_INSN_INT insn = entire_insn;
 726 #define FLD(f) abuf->fields.fmt_and3.f
 727   EXTRACT_FMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 728
 729   EXTRACT_FMT_AND3_CODE
 730
 731   /* Record the fields for the semantic handler.  */
 732   FLD (i_sr) = & CPU (h_gr)[f_r2];
 733   FLD (f_uimm16) = f_uimm16;
 734   FLD (i_dr) = & CPU (h_gr)[f_r1];
 735   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "sr 0x%x", 'x', f_r2, "uimm16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0));
 736
 737 #if WITH_PROFILE_MODEL_P
 738   /* Record the fields for profiling.  */
 739   if (PROFILE_MODEL_P (current_cpu))
 740     {
 741       FLD (in_sr) = f_r2;
 742       FLD (out_dr) = f_r1;
 743     }
 744 #endif
 745 #undef FLD
 746   BREAK (ex);
 747   }
 748
 749   CASE (ex, FMT_OR3) :
 750   {
 751     CGEN_INSN_INT insn = entire_insn;
 752 #define FLD(f) abuf->fields.fmt_or3.f
 753   EXTRACT_FMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 754
 755   EXTRACT_FMT_OR3_CODE
 756
 757   /* Record the fields for the semantic handler.  */
 758   FLD (i_sr) = & CPU (h_gr)[f_r2];
 759   FLD (f_uimm16) = f_uimm16;
 760   FLD (i_dr) = & CPU (h_gr)[f_r1];
 761   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "sr 0x%x", 'x', f_r2, "ulo16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0));
 762
 763 #if WITH_PROFILE_MODEL_P
 764   /* Record the fields for profiling.  */
 765   if (PROFILE_MODEL_P (current_cpu))
 766     {
 767       FLD (in_sr) = f_r2;
 768       FLD (out_dr) = f_r1;
 769     }
 770 #endif
 771 #undef FLD
 772   BREAK (ex);
 773   }
 774
 775   CASE (ex, FMT_ADDI) :
 776   {
 777     CGEN_INSN_INT insn = entire_insn;
 778 #define FLD(f) abuf->fields.fmt_addi.f
 779   EXTRACT_FMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
 780
 781   EXTRACT_FMT_ADDI_CODE
 782
 783   /* Record the fields for the semantic handler.  */
 784   FLD (i_dr) = & CPU (h_gr)[f_r1];
 785   FLD (f_simm8) = f_simm8;
 786   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "dr 0x%x", 'x', f_r1, "simm8 0x%x", 'x', f_simm8, (char *) 0));
 787
 788 #if WITH_PROFILE_MODEL_P
 789   /* Record the fields for profiling.  */
 790   if (PROFILE_MODEL_P (current_cpu))
 791     {
 792       FLD (in_dr) = f_r1;
 793       FLD (out_dr) = f_r1;
 794     }
 795 #endif
 796 #undef FLD
 797   BREAK (ex);
 798   }
 799
 800   CASE (ex, FMT_ADDV) :
 801   {
 802     CGEN_INSN_INT insn = entire_insn;
 803 #define FLD(f) abuf->fields.fmt_addv.f
 804   EXTRACT_FMT_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
 805
 806   EXTRACT_FMT_ADDV_CODE
 807
 808   /* Record the fields for the semantic handler.  */
 809   FLD (i_dr) = & CPU (h_gr)[f_r1];
 810   FLD (i_sr) = & CPU (h_gr)[f_r2];
 811   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 812
 813 #if WITH_PROFILE_MODEL_P
 814   /* Record the fields for profiling.  */
 815   if (PROFILE_MODEL_P (current_cpu))
 816     {
 817       FLD (in_dr) = f_r1;
 818       FLD (in_sr) = f_r2;
 819       FLD (out_dr) = f_r1;
 820     }
 821 #endif
 822 #undef FLD
 823   BREAK (ex);
 824   }
 825
 826   CASE (ex, FMT_ADDV3) :
 827   {
 828     CGEN_INSN_INT insn = entire_insn;
 829 #define FLD(f) abuf->fields.fmt_addv3.f
 830   EXTRACT_FMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 831
 832   EXTRACT_FMT_ADDV3_CODE
 833
 834   /* Record the fields for the semantic handler.  */
 835   FLD (i_sr) = & CPU (h_gr)[f_r2];
 836   FLD (f_simm16) = f_simm16;
 837   FLD (i_dr) = & CPU (h_gr)[f_r1];
 838   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
 839
 840 #if WITH_PROFILE_MODEL_P
 841   /* Record the fields for profiling.  */
 842   if (PROFILE_MODEL_P (current_cpu))
 843     {
 844       FLD (in_sr) = f_r2;
 845       FLD (out_dr) = f_r1;
 846     }
 847 #endif
 848 #undef FLD
 849   BREAK (ex);
 850   }
 851
 852   CASE (ex, FMT_ADDX) :
 853   {
 854     CGEN_INSN_INT insn = entire_insn;
 855 #define FLD(f) abuf->fields.fmt_addx.f
 856   EXTRACT_FMT_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
 857
 858   EXTRACT_FMT_ADDX_CODE
 859
 860   /* Record the fields for the semantic handler.  */
 861   FLD (i_dr) = & CPU (h_gr)[f_r1];
 862   FLD (i_sr) = & CPU (h_gr)[f_r2];
 863   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 864
 865 #if WITH_PROFILE_MODEL_P
 866   /* Record the fields for profiling.  */
 867   if (PROFILE_MODEL_P (current_cpu))
 868     {
 869       FLD (in_dr) = f_r1;
 870       FLD (in_sr) = f_r2;
 871       FLD (out_dr) = f_r1;
 872     }
 873 #endif
 874 #undef FLD
 875   BREAK (ex);
 876   }
 877
 878   CASE (ex, FMT_BC8) :
 879   {
 880     CGEN_INSN_INT insn = entire_insn;
 881 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
 882   EXTRACT_FMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
 883
 884   EXTRACT_FMT_BC8_CODE
 885
 886   /* Record the fields for the semantic handler.  */
 887   FLD (f_disp8) = f_disp8;
 888   SEM_BRANCH_INIT_EXTRACT (abuf);
 889   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 890
 891 #if WITH_PROFILE_MODEL_P
 892   /* Record the fields for profiling.  */
 893   if (PROFILE_MODEL_P (current_cpu))
 894     {
 895     }
 896 #endif
 897 #undef FLD
 898   BREAK (ex);
 899   }
 900
 901   CASE (ex, FMT_BC24) :
 902   {
 903     CGEN_INSN_INT insn = entire_insn;
 904 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
 905   EXTRACT_FMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
 906
 907   EXTRACT_FMT_BC24_CODE
 908
 909   /* Record the fields for the semantic handler.  */
 910   FLD (f_disp24) = f_disp24;
 911   SEM_BRANCH_INIT_EXTRACT (abuf);
 912   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 913
 914 #if WITH_PROFILE_MODEL_P
 915   /* Record the fields for profiling.  */
 916   if (PROFILE_MODEL_P (current_cpu))
 917     {
 918     }
 919 #endif
 920 #undef FLD
 921   BREAK (ex);
 922   }
 923
 924   CASE (ex, FMT_BEQ) :
 925   {
 926     CGEN_INSN_INT insn = entire_insn;
 927 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
 928   EXTRACT_FMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 929
 930   EXTRACT_FMT_BEQ_CODE
 931
 932   /* Record the fields for the semantic handler.  */
 933   FLD (i_src1) = & CPU (h_gr)[f_r1];
 934   FLD (i_src2) = & CPU (h_gr)[f_r2];
 935   FLD (f_disp16) = f_disp16;
 936   SEM_BRANCH_INIT_EXTRACT (abuf);
 937   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
 938
 939 #if WITH_PROFILE_MODEL_P
 940   /* Record the fields for profiling.  */
 941   if (PROFILE_MODEL_P (current_cpu))
 942     {
 943       FLD (in_src1) = f_r1;
 944       FLD (in_src2) = f_r2;
 945     }
 946 #endif
 947 #undef FLD
 948   BREAK (ex);
 949   }
 950
 951   CASE (ex, FMT_BEQZ) :
 952   {
 953     CGEN_INSN_INT insn = entire_insn;
 954 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
 955   EXTRACT_FMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 956
 957   EXTRACT_FMT_BEQZ_CODE
 958
 959   /* Record the fields for the semantic handler.  */
 960   FLD (i_src2) = & CPU (h_gr)[f_r2];
 961   FLD (f_disp16) = f_disp16;
 962   SEM_BRANCH_INIT_EXTRACT (abuf);
 963   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
 964
 965 #if WITH_PROFILE_MODEL_P
 966   /* Record the fields for profiling.  */
 967   if (PROFILE_MODEL_P (current_cpu))
 968     {
 969       FLD (in_src2) = f_r2;
 970     }
 971 #endif
 972 #undef FLD
 973   BREAK (ex);
 974   }
 975
 976   CASE (ex, FMT_BL8) :
 977   {
 978     CGEN_INSN_INT insn = entire_insn;
 979 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
 980   EXTRACT_FMT_BL8_VARS /* f-op1 f-r1 f-disp8 */
 981
 982   EXTRACT_FMT_BL8_CODE
 983
 984   /* Record the fields for the semantic handler.  */
 985   FLD (f_disp8) = f_disp8;
 986   SEM_BRANCH_INIT_EXTRACT (abuf);
 987   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 988
 989 #if WITH_PROFILE_MODEL_P
 990   /* Record the fields for profiling.  */
 991   if (PROFILE_MODEL_P (current_cpu))
 992     {
 993       FLD (out_h_gr_14) = 14;
 994     }
 995 #endif
 996 #undef FLD
 997   BREAK (ex);
 998   }
 999
1000   CASE (ex, FMT_BL24) :
1001   {
1002     CGEN_INSN_INT insn = entire_insn;
1003 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
1004   EXTRACT_FMT_BL24_VARS /* f-op1 f-r1 f-disp24 */
1005
1006   EXTRACT_FMT_BL24_CODE
1007
1008   /* Record the fields for the semantic handler.  */
1009   FLD (f_disp24) = f_disp24;
1010   SEM_BRANCH_INIT_EXTRACT (abuf);
1011   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1012
1013 #if WITH_PROFILE_MODEL_P
1014   /* Record the fields for profiling.  */
1015   if (PROFILE_MODEL_P (current_cpu))
1016     {
1017       FLD (out_h_gr_14) = 14;
1018     }
1019 #endif
1020 #undef FLD
1021   BREAK (ex);
1022   }
1023
1024   CASE (ex, FMT_BRA8) :
1025   {
1026     CGEN_INSN_INT insn = entire_insn;
1027 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
1028   EXTRACT_FMT_BRA8_VARS /* f-op1 f-r1 f-disp8 */
1029
1030   EXTRACT_FMT_BRA8_CODE
1031
1032   /* Record the fields for the semantic handler.  */
1033   FLD (f_disp8) = f_disp8;
1034   SEM_BRANCH_INIT_EXTRACT (abuf);
1035   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1036
1037 #if WITH_PROFILE_MODEL_P
1038   /* Record the fields for profiling.  */
1039   if (PROFILE_MODEL_P (current_cpu))
1040     {
1041     }
1042 #endif
1043 #undef FLD
1044   BREAK (ex);
1045   }
1046
1047   CASE (ex, FMT_BRA24) :
1048   {
1049     CGEN_INSN_INT insn = entire_insn;
1050 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
1051   EXTRACT_FMT_BRA24_VARS /* f-op1 f-r1 f-disp24 */
1052
1053   EXTRACT_FMT_BRA24_CODE
1054
1055   /* Record the fields for the semantic handler.  */
1056   FLD (f_disp24) = f_disp24;
1057   SEM_BRANCH_INIT_EXTRACT (abuf);
1058   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1059
1060 #if WITH_PROFILE_MODEL_P
1061   /* Record the fields for profiling.  */
1062   if (PROFILE_MODEL_P (current_cpu))
1063     {
1064     }
1065 #endif
1066 #undef FLD
1067   BREAK (ex);
1068   }
1069
1070   CASE (ex, FMT_CMP) :
1071   {
1072     CGEN_INSN_INT insn = entire_insn;
1073 #define FLD(f) abuf->fields.fmt_cmp.f
1074   EXTRACT_FMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1075
1076   EXTRACT_FMT_CMP_CODE
1077
1078   /* Record the fields for the semantic handler.  */
1079   FLD (i_src1) = & CPU (h_gr)[f_r1];
1080   FLD (i_src2) = & CPU (h_gr)[f_r2];
1081   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1082
1083 #if WITH_PROFILE_MODEL_P
1084   /* Record the fields for profiling.  */
1085   if (PROFILE_MODEL_P (current_cpu))
1086     {
1087       FLD (in_src1) = f_r1;
1088       FLD (in_src2) = f_r2;
1089     }
1090 #endif
1091 #undef FLD
1092   BREAK (ex);
1093   }
1094
1095   CASE (ex, FMT_CMPI) :
1096   {
1097     CGEN_INSN_INT insn = entire_insn;
1098 #define FLD(f) abuf->fields.fmt_cmpi.f
1099   EXTRACT_FMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1100
1101   EXTRACT_FMT_CMPI_CODE
1102
1103   /* Record the fields for the semantic handler.  */
1104   FLD (i_src2) = & CPU (h_gr)[f_r2];
1105   FLD (f_simm16) = f_simm16;
1106   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "src2 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0));
1107
1108 #if WITH_PROFILE_MODEL_P
1109   /* Record the fields for profiling.  */
1110   if (PROFILE_MODEL_P (current_cpu))
1111     {
1112       FLD (in_src2) = f_r2;
1113     }
1114 #endif
1115 #undef FLD
1116   BREAK (ex);
1117   }
1118
1119   CASE (ex, FMT_DIV) :
1120   {
1121     CGEN_INSN_INT insn = entire_insn;
1122 #define FLD(f) abuf->fields.fmt_div.f
1123   EXTRACT_FMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1124
1125   EXTRACT_FMT_DIV_CODE
1126
1127   /* Record the fields for the semantic handler.  */
1128   FLD (i_sr) = & CPU (h_gr)[f_r2];
1129   FLD (i_dr) = & CPU (h_gr)[f_r1];
1130   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1131
1132 #if WITH_PROFILE_MODEL_P
1133   /* Record the fields for profiling.  */
1134   if (PROFILE_MODEL_P (current_cpu))
1135     {
1136       FLD (in_sr) = f_r2;
1137       FLD (in_dr) = f_r1;
1138       FLD (out_dr) = f_r1;
1139     }
1140 #endif
1141 #undef FLD
1142   BREAK (ex);
1143   }
1144
1145   CASE (ex, FMT_JL) :
1146   {
1147     CGEN_INSN_INT insn = entire_insn;
1148 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
1149   EXTRACT_FMT_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
1150
1151   EXTRACT_FMT_JL_CODE
1152
1153   /* Record the fields for the semantic handler.  */
1154   FLD (i_sr) = & CPU (h_gr)[f_r2];
1155   SEM_BRANCH_INIT_EXTRACT (abuf);
1156   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
1157
1158 #if WITH_PROFILE_MODEL_P
1159   /* Record the fields for profiling.  */
1160   if (PROFILE_MODEL_P (current_cpu))
1161     {
1162       FLD (in_sr) = f_r2;
1163       FLD (out_h_gr_14) = 14;
1164     }
1165 #endif
1166 #undef FLD
1167   BREAK (ex);
1168   }
1169
1170   CASE (ex, FMT_JMP) :
1171   {
1172     CGEN_INSN_INT insn = entire_insn;
1173 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
1174   EXTRACT_FMT_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1175
1176   EXTRACT_FMT_JMP_CODE
1177
1178   /* Record the fields for the semantic handler.  */
1179   FLD (i_sr) = & CPU (h_gr)[f_r2];
1180   SEM_BRANCH_INIT_EXTRACT (abuf);
1181   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
1182
1183 #if WITH_PROFILE_MODEL_P
1184   /* Record the fields for profiling.  */
1185   if (PROFILE_MODEL_P (current_cpu))
1186     {
1187       FLD (in_sr) = f_r2;
1188     }
1189 #endif
1190 #undef FLD
1191   BREAK (ex);
1192   }
1193
1194   CASE (ex, FMT_LD) :
1195   {
1196     CGEN_INSN_INT insn = entire_insn;
1197 #define FLD(f) abuf->fields.fmt_ld.f
1198   EXTRACT_FMT_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1199
1200   EXTRACT_FMT_LD_CODE
1201
1202   /* Record the fields for the semantic handler.  */
1203   FLD (i_sr) = & CPU (h_gr)[f_r2];
1204   FLD (i_dr) = & CPU (h_gr)[f_r1];
1205   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1206
1207 #if WITH_PROFILE_MODEL_P
1208   /* Record the fields for profiling.  */
1209   if (PROFILE_MODEL_P (current_cpu))
1210     {
1211       FLD (in_sr) = f_r2;
1212       FLD (out_dr) = f_r1;
1213     }
1214 #endif
1215 #undef FLD
1216   BREAK (ex);
1217   }
1218
1219   CASE (ex, FMT_LD_D) :
1220   {
1221     CGEN_INSN_INT insn = entire_insn;
1222 #define FLD(f) abuf->fields.fmt_ld_d.f
1223   EXTRACT_FMT_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1224
1225   EXTRACT_FMT_LD_D_CODE
1226
1227   /* Record the fields for the semantic handler.  */
1228   FLD (i_sr) = & CPU (h_gr)[f_r2];
1229   FLD (f_simm16) = f_simm16;
1230   FLD (i_dr) = & CPU (h_gr)[f_r1];
1231   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
1232
1233 #if WITH_PROFILE_MODEL_P
1234   /* Record the fields for profiling.  */
1235   if (PROFILE_MODEL_P (current_cpu))
1236     {
1237       FLD (in_sr) = f_r2;
1238       FLD (out_dr) = f_r1;
1239     }
1240 #endif
1241 #undef FLD
1242   BREAK (ex);
1243   }
1244
1245   CASE (ex, FMT_LDB) :
1246   {
1247     CGEN_INSN_INT insn = entire_insn;
1248 #define FLD(f) abuf->fields.fmt_ldb.f
1249   EXTRACT_FMT_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
1250
1251   EXTRACT_FMT_LDB_CODE
1252
1253   /* Record the fields for the semantic handler.  */
1254   FLD (i_sr) = & CPU (h_gr)[f_r2];
1255   FLD (i_dr) = & CPU (h_gr)[f_r1];
1256   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1257
1258 #if WITH_PROFILE_MODEL_P
1259   /* Record the fields for profiling.  */
1260   if (PROFILE_MODEL_P (current_cpu))
1261     {
1262       FLD (in_sr) = f_r2;
1263       FLD (out_dr) = f_r1;
1264     }
1265 #endif
1266 #undef FLD
1267   BREAK (ex);
1268   }
1269
1270   CASE (ex, FMT_LDB_D) :
1271   {
1272     CGEN_INSN_INT insn = entire_insn;
1273 #define FLD(f) abuf->fields.fmt_ldb_d.f
1274   EXTRACT_FMT_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1275
1276   EXTRACT_FMT_LDB_D_CODE
1277
1278   /* Record the fields for the semantic handler.  */
1279   FLD (i_sr) = & CPU (h_gr)[f_r2];
1280   FLD (f_simm16) = f_simm16;
1281   FLD (i_dr) = & CPU (h_gr)[f_r1];
1282   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
1283
1284 #if WITH_PROFILE_MODEL_P
1285   /* Record the fields for profiling.  */
1286   if (PROFILE_MODEL_P (current_cpu))
1287     {
1288       FLD (in_sr) = f_r2;
1289       FLD (out_dr) = f_r1;
1290     }
1291 #endif
1292 #undef FLD
1293   BREAK (ex);
1294   }
1295
1296   CASE (ex, FMT_LDH) :
1297   {
1298     CGEN_INSN_INT insn = entire_insn;
1299 #define FLD(f) abuf->fields.fmt_ldh.f
1300   EXTRACT_FMT_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
1301
1302   EXTRACT_FMT_LDH_CODE
1303
1304   /* Record the fields for the semantic handler.  */
1305   FLD (i_sr) = & CPU (h_gr)[f_r2];
1306   FLD (i_dr) = & CPU (h_gr)[f_r1];
1307   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1308
1309 #if WITH_PROFILE_MODEL_P
1310   /* Record the fields for profiling.  */
1311   if (PROFILE_MODEL_P (current_cpu))
1312     {
1313       FLD (in_sr) = f_r2;
1314       FLD (out_dr) = f_r1;
1315     }
1316 #endif
1317 #undef FLD
1318   BREAK (ex);
1319   }
1320
1321   CASE (ex, FMT_LDH_D) :
1322   {
1323     CGEN_INSN_INT insn = entire_insn;
1324 #define FLD(f) abuf->fields.fmt_ldh_d.f
1325   EXTRACT_FMT_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1326
1327   EXTRACT_FMT_LDH_D_CODE
1328
1329   /* Record the fields for the semantic handler.  */
1330   FLD (i_sr) = & CPU (h_gr)[f_r2];
1331   FLD (f_simm16) = f_simm16;
1332   FLD (i_dr) = & CPU (h_gr)[f_r1];
1333   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
1334
1335 #if WITH_PROFILE_MODEL_P
1336   /* Record the fields for profiling.  */
1337   if (PROFILE_MODEL_P (current_cpu))
1338     {
1339       FLD (in_sr) = f_r2;
1340       FLD (out_dr) = f_r1;
1341     }
1342 #endif
1343 #undef FLD
1344   BREAK (ex);
1345   }
1346
1347   CASE (ex, FMT_LD_PLUS) :
1348   {
1349     CGEN_INSN_INT insn = entire_insn;
1350 #define FLD(f) abuf->fields.fmt_ld_plus.f
1351   EXTRACT_FMT_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
1352
1353   EXTRACT_FMT_LD_PLUS_CODE
1354
1355   /* Record the fields for the semantic handler.  */
1356   FLD (i_sr) = & CPU (h_gr)[f_r2];
1357   FLD (i_dr) = & CPU (h_gr)[f_r1];
1358   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1359
1360 #if WITH_PROFILE_MODEL_P
1361   /* Record the fields for profiling.  */
1362   if (PROFILE_MODEL_P (current_cpu))
1363     {
1364       FLD (in_sr) = f_r2;
1365       FLD (out_dr) = f_r1;
1366       FLD (out_sr) = f_r2;
1367     }
1368 #endif
1369 #undef FLD
1370   BREAK (ex);
1371   }
1372
1373   CASE (ex, FMT_LD24) :
1374   {
1375     CGEN_INSN_INT insn = entire_insn;
1376 #define FLD(f) abuf->fields.fmt_ld24.f
1377   EXTRACT_FMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
1378
1379   EXTRACT_FMT_LD24_CODE
1380
1381   /* Record the fields for the semantic handler.  */
1382   FLD (f_uimm24) = f_uimm24;
1383   FLD (i_dr) = & CPU (h_gr)[f_r1];
1384   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1385
1386 #if WITH_PROFILE_MODEL_P
1387   /* Record the fields for profiling.  */
1388   if (PROFILE_MODEL_P (current_cpu))
1389     {
1390       FLD (out_dr) = f_r1;
1391     }
1392 #endif
1393 #undef FLD
1394   BREAK (ex);
1395   }
1396
1397   CASE (ex, FMT_LDI8) :
1398   {
1399     CGEN_INSN_INT insn = entire_insn;
1400 #define FLD(f) abuf->fields.fmt_ldi8.f
1401   EXTRACT_FMT_LDI8_VARS /* f-op1 f-r1 f-simm8 */
1402
1403   EXTRACT_FMT_LDI8_CODE
1404
1405   /* Record the fields for the semantic handler.  */
1406   FLD (f_simm8) = f_simm8;
1407   FLD (i_dr) = & CPU (h_gr)[f_r1];
1408   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
1409
1410 #if WITH_PROFILE_MODEL_P
1411   /* Record the fields for profiling.  */
1412   if (PROFILE_MODEL_P (current_cpu))
1413     {
1414       FLD (out_dr) = f_r1;
1415     }
1416 #endif
1417 #undef FLD
1418   BREAK (ex);
1419   }
1420
1421   CASE (ex, FMT_LDI16) :
1422   {
1423     CGEN_INSN_INT insn = entire_insn;
1424 #define FLD(f) abuf->fields.fmt_ldi16.f
1425   EXTRACT_FMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1426
1427   EXTRACT_FMT_LDI16_CODE
1428
1429   /* Record the fields for the semantic handler.  */
1430   FLD (f_simm16) = f_simm16;
1431   FLD (i_dr) = & CPU (h_gr)[f_r1];
1432   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
1433
1434 #if WITH_PROFILE_MODEL_P
1435   /* Record the fields for profiling.  */
1436   if (PROFILE_MODEL_P (current_cpu))
1437     {
1438       FLD (out_dr) = f_r1;
1439     }
1440 #endif
1441 #undef FLD
1442   BREAK (ex);
1443   }
1444
1445   CASE (ex, FMT_LOCK) :
1446   {
1447     CGEN_INSN_INT insn = entire_insn;
1448 #define FLD(f) abuf->fields.fmt_lock.f
1449   EXTRACT_FMT_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
1450
1451   EXTRACT_FMT_LOCK_CODE
1452
1453   /* Record the fields for the semantic handler.  */
1454   FLD (i_sr) = & CPU (h_gr)[f_r2];
1455   FLD (i_dr) = & CPU (h_gr)[f_r1];
1456   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1457
1458 #if WITH_PROFILE_MODEL_P
1459   /* Record the fields for profiling.  */
1460   if (PROFILE_MODEL_P (current_cpu))
1461     {
1462       FLD (in_sr) = f_r2;
1463       FLD (out_dr) = f_r1;
1464     }
1465 #endif
1466 #undef FLD
1467   BREAK (ex);
1468   }
1469
1470   CASE (ex, FMT_MACHI) :
1471   {
1472     CGEN_INSN_INT insn = entire_insn;
1473 #define FLD(f) abuf->fields.fmt_machi.f
1474   EXTRACT_FMT_MACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
1475
1476   EXTRACT_FMT_MACHI_CODE
1477
1478   /* Record the fields for the semantic handler.  */
1479   FLD (i_src1) = & CPU (h_gr)[f_r1];
1480   FLD (i_src2) = & CPU (h_gr)[f_r2];
1481   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_machi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1482
1483 #if WITH_PROFILE_MODEL_P
1484   /* Record the fields for profiling.  */
1485   if (PROFILE_MODEL_P (current_cpu))
1486     {
1487       FLD (in_src1) = f_r1;
1488       FLD (in_src2) = f_r2;
1489     }
1490 #endif
1491 #undef FLD
1492   BREAK (ex);
1493   }
1494
1495   CASE (ex, FMT_MULHI) :
1496   {
1497     CGEN_INSN_INT insn = entire_insn;
1498 #define FLD(f) abuf->fields.fmt_mulhi.f
1499   EXTRACT_FMT_MULHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
1500
1501   EXTRACT_FMT_MULHI_CODE
1502
1503   /* Record the fields for the semantic handler.  */
1504   FLD (i_src1) = & CPU (h_gr)[f_r1];
1505   FLD (i_src2) = & CPU (h_gr)[f_r2];
1506   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulhi", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1507
1508 #if WITH_PROFILE_MODEL_P
1509   /* Record the fields for profiling.  */
1510   if (PROFILE_MODEL_P (current_cpu))
1511     {
1512       FLD (in_src1) = f_r1;
1513       FLD (in_src2) = f_r2;
1514     }
1515 #endif
1516 #undef FLD
1517   BREAK (ex);
1518   }
1519
1520   CASE (ex, FMT_MV) :
1521   {
1522     CGEN_INSN_INT insn = entire_insn;
1523 #define FLD(f) abuf->fields.fmt_mv.f
1524   EXTRACT_FMT_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
1525
1526   EXTRACT_FMT_MV_CODE
1527
1528   /* Record the fields for the semantic handler.  */
1529   FLD (i_sr) = & CPU (h_gr)[f_r2];
1530   FLD (i_dr) = & CPU (h_gr)[f_r1];
1531   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1532
1533 #if WITH_PROFILE_MODEL_P
1534   /* Record the fields for profiling.  */
1535   if (PROFILE_MODEL_P (current_cpu))
1536     {
1537       FLD (in_sr) = f_r2;
1538       FLD (out_dr) = f_r1;
1539     }
1540 #endif
1541 #undef FLD
1542   BREAK (ex);
1543   }
1544
1545   CASE (ex, FMT_MVFACHI) :
1546   {
1547     CGEN_INSN_INT insn = entire_insn;
1548 #define FLD(f) abuf->fields.fmt_mvfachi.f
1549   EXTRACT_FMT_MVFACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
1550
1551   EXTRACT_FMT_MVFACHI_CODE
1552
1553   /* Record the fields for the semantic handler.  */
1554   FLD (i_dr) = & CPU (h_gr)[f_r1];
1555   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfachi", "dr 0x%x", 'x', f_r1, (char *) 0));
1556
1557 #if WITH_PROFILE_MODEL_P
1558   /* Record the fields for profiling.  */
1559   if (PROFILE_MODEL_P (current_cpu))
1560     {
1561       FLD (out_dr) = f_r1;
1562     }
1563 #endif
1564 #undef FLD
1565   BREAK (ex);
1566   }
1567
1568   CASE (ex, FMT_MVFC) :
1569   {
1570     CGEN_INSN_INT insn = entire_insn;
1571 #define FLD(f) abuf->fields.fmt_mvfc.f
1572   EXTRACT_FMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1573
1574   EXTRACT_FMT_MVFC_CODE
1575
1576   /* Record the fields for the semantic handler.  */
1577   FLD (f_r2) = f_r2;
1578   FLD (i_dr) = & CPU (h_gr)[f_r1];
1579   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "scr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1580
1581 #if WITH_PROFILE_MODEL_P
1582   /* Record the fields for profiling.  */
1583   if (PROFILE_MODEL_P (current_cpu))
1584     {
1585       FLD (out_dr) = f_r1;
1586     }
1587 #endif
1588 #undef FLD
1589   BREAK (ex);
1590   }
1591
1592   CASE (ex, FMT_MVTACHI) :
1593   {
1594     CGEN_INSN_INT insn = entire_insn;
1595 #define FLD(f) abuf->fields.fmt_mvtachi.f
1596   EXTRACT_FMT_MVTACHI_VARS /* f-op1 f-r1 f-op2 f-r2 */
1597
1598   EXTRACT_FMT_MVTACHI_CODE
1599
1600   /* Record the fields for the semantic handler.  */
1601   FLD (i_src1) = & CPU (h_gr)[f_r1];
1602   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtachi", "src1 0x%x", 'x', f_r1, (char *) 0));
1603
1604 #if WITH_PROFILE_MODEL_P
1605   /* Record the fields for profiling.  */
1606   if (PROFILE_MODEL_P (current_cpu))
1607     {
1608       FLD (in_src1) = f_r1;
1609     }
1610 #endif
1611 #undef FLD
1612   BREAK (ex);
1613   }
1614
1615   CASE (ex, FMT_MVTC) :
1616   {
1617     CGEN_INSN_INT insn = entire_insn;
1618 #define FLD(f) abuf->fields.fmt_mvtc.f
1619   EXTRACT_FMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1620
1621   EXTRACT_FMT_MVTC_CODE
1622
1623   /* Record the fields for the semantic handler.  */
1624   FLD (i_sr) = & CPU (h_gr)[f_r2];
1625   FLD (f_r1) = f_r1;
1626   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "sr 0x%x", 'x', f_r2, "dcr 0x%x", 'x', f_r1, (char *) 0));
1627
1628 #if WITH_PROFILE_MODEL_P
1629   /* Record the fields for profiling.  */
1630   if (PROFILE_MODEL_P (current_cpu))
1631     {
1632       FLD (in_sr) = f_r2;
1633     }
1634 #endif
1635 #undef FLD
1636   BREAK (ex);
1637   }
1638
1639   CASE (ex, FMT_NOP) :
1640   {
1641     CGEN_INSN_INT insn = entire_insn;
1642 #define FLD(f) abuf->fields.fmt_nop.f
1643   EXTRACT_FMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1644
1645   EXTRACT_FMT_NOP_CODE
1646
1647   /* Record the fields for the semantic handler.  */
1648   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0));
1649
1650 #undef FLD
1651   BREAK (ex);
1652   }
1653
1654   CASE (ex, FMT_RAC) :
1655   {
1656     CGEN_INSN_INT insn = entire_insn;
1657 #define FLD(f) abuf->fields.fmt_rac.f
1658   EXTRACT_FMT_RAC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1659
1660   EXTRACT_FMT_RAC_CODE
1661
1662   /* Record the fields for the semantic handler.  */
1663   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac", (char *) 0));
1664
1665 #undef FLD
1666   BREAK (ex);
1667   }
1668
1669   CASE (ex, FMT_RTE) :
1670   {
1671     CGEN_INSN_INT insn = entire_insn;
1672 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1673   EXTRACT_FMT_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
1674
1675   EXTRACT_FMT_RTE_CODE
1676
1677   /* Record the fields for the semantic handler.  */
1678   SEM_BRANCH_INIT_EXTRACT (abuf);
1679   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rte", (char *) 0));
1680
1681 #if WITH_PROFILE_MODEL_P
1682   /* Record the fields for profiling.  */
1683   if (PROFILE_MODEL_P (current_cpu))
1684     {
1685     }
1686 #endif
1687 #undef FLD
1688   BREAK (ex);
1689   }
1690
1691   CASE (ex, FMT_SETH) :
1692   {
1693     CGEN_INSN_INT insn = entire_insn;
1694 #define FLD(f) abuf->fields.fmt_seth.f
1695   EXTRACT_FMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
1696
1697   EXTRACT_FMT_SETH_CODE
1698
1699   /* Record the fields for the semantic handler.  */
1700   FLD (f_hi16) = f_hi16;
1701   FLD (i_dr) = & CPU (h_gr)[f_r1];
1702   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
1703
1704 #if WITH_PROFILE_MODEL_P
1705   /* Record the fields for profiling.  */
1706   if (PROFILE_MODEL_P (current_cpu))
1707     {
1708       FLD (out_dr) = f_r1;
1709     }
1710 #endif
1711 #undef FLD
1712   BREAK (ex);
1713   }
1714
1715   CASE (ex, FMT_SLL3) :
1716   {
1717     CGEN_INSN_INT insn = entire_insn;
1718 #define FLD(f) abuf->fields.fmt_sll3.f
1719   EXTRACT_FMT_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1720
1721   EXTRACT_FMT_SLL3_CODE
1722
1723   /* Record the fields for the semantic handler.  */
1724   FLD (i_sr) = & CPU (h_gr)[f_r2];
1725   FLD (f_simm16) = f_simm16;
1726   FLD (i_dr) = & CPU (h_gr)[f_r1];
1727   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
1728
1729 #if WITH_PROFILE_MODEL_P
1730   /* Record the fields for profiling.  */
1731   if (PROFILE_MODEL_P (current_cpu))
1732     {
1733       FLD (in_sr) = f_r2;
1734       FLD (out_dr) = f_r1;
1735     }
1736 #endif
1737 #undef FLD
1738   BREAK (ex);
1739   }
1740
1741   CASE (ex, FMT_SLLI) :
1742   {
1743     CGEN_INSN_INT insn = entire_insn;
1744 #define FLD(f) abuf->fields.fmt_slli.f
1745   EXTRACT_FMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
1746
1747   EXTRACT_FMT_SLLI_CODE
1748
1749   /* Record the fields for the semantic handler.  */
1750   FLD (i_dr) = & CPU (h_gr)[f_r1];
1751   FLD (f_uimm5) = f_uimm5;
1752   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0));
1753
1754 #if WITH_PROFILE_MODEL_P
1755   /* Record the fields for profiling.  */
1756   if (PROFILE_MODEL_P (current_cpu))
1757     {
1758       FLD (in_dr) = f_r1;
1759       FLD (out_dr) = f_r1;
1760     }
1761 #endif
1762 #undef FLD
1763   BREAK (ex);
1764   }
1765
1766   CASE (ex, FMT_ST) :
1767   {
1768     CGEN_INSN_INT insn = entire_insn;
1769 #define FLD(f) abuf->fields.fmt_st.f
1770   EXTRACT_FMT_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */
1771
1772   EXTRACT_FMT_ST_CODE
1773
1774   /* Record the fields for the semantic handler.  */
1775   FLD (i_src2) = & CPU (h_gr)[f_r2];
1776   FLD (i_src1) = & CPU (h_gr)[f_r1];
1777   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1778
1779 #if WITH_PROFILE_MODEL_P
1780   /* Record the fields for profiling.  */
1781   if (PROFILE_MODEL_P (current_cpu))
1782     {
1783       FLD (in_src2) = f_r2;
1784       FLD (in_src1) = f_r1;
1785     }
1786 #endif
1787 #undef FLD
1788   BREAK (ex);
1789   }
1790
1791   CASE (ex, FMT_ST_D) :
1792   {
1793     CGEN_INSN_INT insn = entire_insn;
1794 #define FLD(f) abuf->fields.fmt_st_d.f
1795   EXTRACT_FMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1796
1797   EXTRACT_FMT_ST_D_CODE
1798
1799   /* Record the fields for the semantic handler.  */
1800   FLD (i_src2) = & CPU (h_gr)[f_r2];
1801   FLD (f_simm16) = f_simm16;
1802   FLD (i_src1) = & CPU (h_gr)[f_r1];
1803   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0));
1804
1805 #if WITH_PROFILE_MODEL_P
1806   /* Record the fields for profiling.  */
1807   if (PROFILE_MODEL_P (current_cpu))
1808     {
1809       FLD (in_src2) = f_r2;
1810       FLD (in_src1) = f_r1;
1811     }
1812 #endif
1813 #undef FLD
1814   BREAK (ex);
1815   }
1816
1817   CASE (ex, FMT_STB) :
1818   {
1819     CGEN_INSN_INT insn = entire_insn;
1820 #define FLD(f) abuf->fields.fmt_stb.f
1821   EXTRACT_FMT_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */
1822
1823   EXTRACT_FMT_STB_CODE
1824
1825   /* Record the fields for the semantic handler.  */
1826   FLD (i_src2) = & CPU (h_gr)[f_r2];
1827   FLD (i_src1) = & CPU (h_gr)[f_r1];
1828   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1829
1830 #if WITH_PROFILE_MODEL_P
1831   /* Record the fields for profiling.  */
1832   if (PROFILE_MODEL_P (current_cpu))
1833     {
1834       FLD (in_src2) = f_r2;
1835       FLD (in_src1) = f_r1;
1836     }
1837 #endif
1838 #undef FLD
1839   BREAK (ex);
1840   }
1841
1842   CASE (ex, FMT_STB_D) :
1843   {
1844     CGEN_INSN_INT insn = entire_insn;
1845 #define FLD(f) abuf->fields.fmt_stb_d.f
1846   EXTRACT_FMT_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1847
1848   EXTRACT_FMT_STB_D_CODE
1849
1850   /* Record the fields for the semantic handler.  */
1851   FLD (i_src2) = & CPU (h_gr)[f_r2];
1852   FLD (f_simm16) = f_simm16;
1853   FLD (i_src1) = & CPU (h_gr)[f_r1];
1854   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0));
1855
1856 #if WITH_PROFILE_MODEL_P
1857   /* Record the fields for profiling.  */
1858   if (PROFILE_MODEL_P (current_cpu))
1859     {
1860       FLD (in_src2) = f_r2;
1861       FLD (in_src1) = f_r1;
1862     }
1863 #endif
1864 #undef FLD
1865   BREAK (ex);
1866   }
1867
1868   CASE (ex, FMT_STH) :
1869   {
1870     CGEN_INSN_INT insn = entire_insn;
1871 #define FLD(f) abuf->fields.fmt_sth.f
1872   EXTRACT_FMT_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */
1873
1874   EXTRACT_FMT_STH_CODE
1875
1876   /* Record the fields for the semantic handler.  */
1877   FLD (i_src2) = & CPU (h_gr)[f_r2];
1878   FLD (i_src1) = & CPU (h_gr)[f_r1];
1879   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1880
1881 #if WITH_PROFILE_MODEL_P
1882   /* Record the fields for profiling.  */
1883   if (PROFILE_MODEL_P (current_cpu))
1884     {
1885       FLD (in_src2) = f_r2;
1886       FLD (in_src1) = f_r1;
1887     }
1888 #endif
1889 #undef FLD
1890   BREAK (ex);
1891   }
1892
1893   CASE (ex, FMT_STH_D) :
1894   {
1895     CGEN_INSN_INT insn = entire_insn;
1896 #define FLD(f) abuf->fields.fmt_sth_d.f
1897   EXTRACT_FMT_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1898
1899   EXTRACT_FMT_STH_D_CODE
1900
1901   /* Record the fields for the semantic handler.  */
1902   FLD (i_src2) = & CPU (h_gr)[f_r2];
1903   FLD (f_simm16) = f_simm16;
1904   FLD (i_src1) = & CPU (h_gr)[f_r1];
1905   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0));
1906
1907 #if WITH_PROFILE_MODEL_P
1908   /* Record the fields for profiling.  */
1909   if (PROFILE_MODEL_P (current_cpu))
1910     {
1911       FLD (in_src2) = f_r2;
1912       FLD (in_src1) = f_r1;
1913     }
1914 #endif
1915 #undef FLD
1916   BREAK (ex);
1917   }
1918
1919   CASE (ex, FMT_ST_PLUS) :
1920   {
1921     CGEN_INSN_INT insn = entire_insn;
1922 #define FLD(f) abuf->fields.fmt_st_plus.f
1923   EXTRACT_FMT_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
1924
1925   EXTRACT_FMT_ST_PLUS_CODE
1926
1927   /* Record the fields for the semantic handler.  */
1928   FLD (i_src2) = & CPU (h_gr)[f_r2];
1929   FLD (i_src1) = & CPU (h_gr)[f_r1];
1930   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_plus", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1931
1932 #if WITH_PROFILE_MODEL_P
1933   /* Record the fields for profiling.  */
1934   if (PROFILE_MODEL_P (current_cpu))
1935     {
1936       FLD (in_src2) = f_r2;
1937       FLD (in_src1) = f_r1;
1938       FLD (out_src2) = f_r2;
1939     }
1940 #endif
1941 #undef FLD
1942   BREAK (ex);
1943   }
1944
1945   CASE (ex, FMT_TRAP) :
1946   {
1947     CGEN_INSN_INT insn = entire_insn;
1948 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
1949   EXTRACT_FMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
1950
1951   EXTRACT_FMT_TRAP_CODE
1952
1953   /* Record the fields for the semantic handler.  */
1954   FLD (f_uimm4) = f_uimm4;
1955   SEM_BRANCH_INIT_EXTRACT (abuf);
1956   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0));
1957
1958 #if WITH_PROFILE_MODEL_P
1959   /* Record the fields for profiling.  */
1960   if (PROFILE_MODEL_P (current_cpu))
1961     {
1962     }
1963 #endif
1964 #undef FLD
1965   BREAK (ex);
1966   }
1967
1968   CASE (ex, FMT_UNLOCK) :
1969   {
1970     CGEN_INSN_INT insn = entire_insn;
1971 #define FLD(f) abuf->fields.fmt_unlock.f
1972   EXTRACT_FMT_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
1973
1974   EXTRACT_FMT_UNLOCK_CODE
1975
1976   /* Record the fields for the semantic handler.  */
1977   FLD (i_src2) = & CPU (h_gr)[f_r2];
1978   FLD (i_src1) = & CPU (h_gr)[f_r1];
1979   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_unlock", "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
1980
1981 #if WITH_PROFILE_MODEL_P
1982   /* Record the fields for profiling.  */
1983   if (PROFILE_MODEL_P (current_cpu))
1984     {
1985       FLD (in_src2) = f_r2;
1986       FLD (in_src1) = f_r1;
1987     }
1988 #endif
1989 #undef FLD
1990   BREAK (ex);
1991   }
1992
1993       CASE (ex, FMT_EMPTY) :
1994         BREAK (ex);
1995
1996       }
1997     ENDSWITCH (ex)
1998
1999     return idecode->idesc;
2000   }
2001 }