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2000-08-28 Dave Brolley <brolley@redhat.com>
[deliverable/binutils-gdb.git] / sim / m32r / decodex.c
1 /* Simulator instruction decoder for m32rxf.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6
7 This file is part of the GNU Simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23 */
24
25 #define WANT_CPU m32rxf
26 #define WANT_CPU_M32RXF
27
28 #include "sim-main.h"
29 #include "sim-assert.h"
30
31 /* Insn can't be executed in parallel.
32 Or is that "do NOt Pass to Air defense Radar"? :-) */
33 #define NOPAR (-1)
34
35 /* The instruction descriptor array.
36 This is computed at runtime. Space for it is not malloc'd to save a
37 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
38 but won't be done until necessary (we don't currently support the runtime
39 addition of instructions nor an SMP machine with different cpus). */
40 static IDESC m32rxf_insn_data[M32RXF_INSN_MAX];
41
42 /* Commas between elements are contained in the macros.
43 Some of these are conditionally compiled out. */
44
45 static const struct insn_sem m32rxf_insn_sem[] =
46 {
47 { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
48 { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
49 { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
50 { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
51 { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
52 { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR },
53 { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD },
54 { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR },
55 { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND },
56 { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
57 { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR },
58 { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR },
59 { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR },
60 { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR },
61 { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI },
62 { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV },
63 { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR },
64 { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX },
65 { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 },
66 { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
67 { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
68 { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
69 { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
70 { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
71 { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
72 { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
73 { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR },
74 { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 },
75 { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR },
76 { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 },
77 { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
78 { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 },
79 { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR },
80 { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR },
81 { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 },
82 { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR },
83 { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 },
84 { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR },
85 { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP },
86 { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
87 { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU },
88 { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR },
89 { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ },
90 { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ },
91 { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR },
92 { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
93 { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR },
94 { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR },
95 { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR },
96 { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC },
97 { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC },
98 { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL },
99 { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP },
100 { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD },
101 { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
102 { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB },
103 { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
104 { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH },
105 { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
106 { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB },
107 { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
108 { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH },
109 { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR },
110 { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS },
111 { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR },
112 { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 },
113 { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR },
114 { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK },
115 { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A },
116 { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A },
117 { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A },
118 { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A },
119 { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL },
120 { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A },
121 { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A },
122 { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A },
123 { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A },
124 { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV },
125 { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A },
126 { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A },
127 { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A },
128 { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC },
129 { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A },
130 { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A },
131 { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC },
132 { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG },
133 { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP },
134 { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT },
135 { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI },
136 { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI },
137 { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE },
138 { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR },
139 { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL },
140 { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
141 { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI },
142 { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA },
143 { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
144 { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI },
145 { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL },
146 { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR },
147 { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI },
148 { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST },
149 { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR },
150 { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB },
151 { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR },
152 { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH },
153 { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR },
154 { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS },
155 { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS },
156 { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB },
157 { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV },
158 { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX },
159 { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP },
160 { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK },
161 { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR },
162 { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR },
163 { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR },
164 { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ },
165 { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD },
166 { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 },
167 { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO },
168 { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 },
169 { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 },
170 { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC },
171 { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC },
172 };
173
174 static const struct insn_sem m32rxf_insn_sem_invalid = {
175 VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
176 };
177
178 /* Initialize an IDESC from the compile-time computable parts. */
179
180 static INLINE void
181 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
182 {
183 const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
184
185 id->num = t->index;
186 id->sfmt = t->sfmt;
187 if ((int) t->type <= 0)
188 id->idata = & cgen_virtual_insn_table[- (int) t->type];
189 else
190 id->idata = & insn_table[t->type];
191 id->attrs = CGEN_INSN_ATTRS (id->idata);
192 /* Oh my god, a magic number. */
193 id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
194
195 #if WITH_PROFILE_MODEL_P
196 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
197 {
198 SIM_DESC sd = CPU_STATE (cpu);
199 SIM_ASSERT (t->index == id->timing->num);
200 }
201 #endif
202
203 /* Semantic pointers are initialized elsewhere. */
204 }
205
206 /* Initialize the instruction descriptor table. */
207
208 void
209 m32rxf_init_idesc_table (SIM_CPU *cpu)
210 {
211 IDESC *id,*tabend;
212 const struct insn_sem *t,*tend;
213 int tabsize = M32RXF_INSN_MAX;
214 IDESC *table = m32rxf_insn_data;
215
216 memset (table, 0, tabsize * sizeof (IDESC));
217
218 /* First set all entries to the `invalid insn'. */
219 t = & m32rxf_insn_sem_invalid;
220 for (id = table, tabend = table + tabsize; id < tabend; ++id)
221 init_idesc (cpu, id, t);
222
223 /* Now fill in the values for the chosen cpu. */
224 for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
225 t != tend; ++t)
226 {
227 init_idesc (cpu, & table[t->index], t);
228 if (t->par_index != NOPAR)
229 {
230 init_idesc (cpu, &table[t->par_index], t);
231 table[t->index].par_idesc = &table[t->par_index];
232 }
233 if (t->par_index != NOPAR)
234 {
235 init_idesc (cpu, &table[t->write_index], t);
236 table[t->par_index].par_idesc = &table[t->write_index];
237 }
238 }
239
240 /* Link the IDESC table into the cpu. */
241 CPU_IDESC (cpu) = table;
242 }
243
244 /* Given an instruction, return a pointer to its IDESC entry. */
245
246 const IDESC *
247 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
248 CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
249 ARGBUF *abuf)
250 {
251 /* Result of decoder. */
252 M32RXF_INSN_TYPE itype;
253
254 {
255 CGEN_INSN_INT insn = base_insn;
256
257 {
258 unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
259 switch (val)
260 {
261 case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv;
262 case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx;
263 case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add;
264 case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv;
265 case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp;
266 case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp;
267 case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp;
268 case 7 :
269 {
270 unsigned int val = (((insn >> 8) & (15 << 0)));
271 switch (val)
272 {
273 case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz;
274 case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz;
275 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
276 }
277 }
278 case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv;
279 case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx;
280 case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add;
281 case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv;
282 case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;
283 case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;
284 case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;
285 case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;
286 case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;
287 case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;
288 case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add;
289 case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv;
290 case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc;
291 case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc;
292 case 28 :
293 {
294 unsigned int val = (((insn >> 8) & (15 << 0)));
295 switch (val)
296 {
297 case 12 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc;
298 case 13 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc;
299 case 14 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl;
300 case 15 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp;
301 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
302 }
303 }
304 case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte;
305 case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap;
306 case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;
307 case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;
308 case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st;
309 case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock;
310 case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
311 case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
312 case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ld;
313 case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ld;
314 case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ld;
315 case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ld;
316 case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld;
317 case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock;
318 case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
319 case 48 : /* fall through */
320 case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
321 case 49 : /* fall through */
322 case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
323 case 50 : /* fall through */
324 case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
325 case 51 : /* fall through */
326 case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
327 case 52 : /* fall through */
328 case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a;
329 case 53 : /* fall through */
330 case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a;
331 case 54 : /* fall through */
332 case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a;
333 case 55 : /* fall through */
334 case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a;
335 case 64 : /* fall through */
336 case 65 : /* fall through */
337 case 66 : /* fall through */
338 case 67 : /* fall through */
339 case 68 : /* fall through */
340 case 69 : /* fall through */
341 case 70 : /* fall through */
342 case 71 : /* fall through */
343 case 72 : /* fall through */
344 case 73 : /* fall through */
345 case 74 : /* fall through */
346 case 75 : /* fall through */
347 case 76 : /* fall through */
348 case 77 : /* fall through */
349 case 78 : /* fall through */
350 case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi;
351 case 80 : /* fall through */
352 case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli;
353 case 82 : /* fall through */
354 case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli;
355 case 84 : /* fall through */
356 case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli;
357 case 87 :
358 {
359 unsigned int val = (((insn >> 0) & (3 << 0)));
360 switch (val)
361 {
362 case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
363 case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
364 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
365 }
366 }
367 case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
368 case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
369 case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1;
370 case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1;
371 case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1;
372 case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo;
373 case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd;
374 case 95 :
375 {
376 unsigned int val = (((insn >> 0) & (3 << 0)));
377 switch (val)
378 {
379 case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
380 case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
381 case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
382 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
383 }
384 }
385 case 96 : /* fall through */
386 case 97 : /* fall through */
387 case 98 : /* fall through */
388 case 99 : /* fall through */
389 case 100 : /* fall through */
390 case 101 : /* fall through */
391 case 102 : /* fall through */
392 case 103 : /* fall through */
393 case 104 : /* fall through */
394 case 105 : /* fall through */
395 case 106 : /* fall through */
396 case 107 : /* fall through */
397 case 108 : /* fall through */
398 case 109 : /* fall through */
399 case 110 : /* fall through */
400 case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8;
401 case 112 :
402 {
403 unsigned int val = (((insn >> 8) & (15 << 0)));
404 switch (val)
405 {
406 case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop;
407 case 4 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc;
408 case 5 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc;
409 case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
410 case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
411 case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
412 case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
413 case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
414 case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
415 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
416 }
417 }
418 case 113 : /* fall through */
419 case 114 : /* fall through */
420 case 115 : /* fall through */
421 case 116 : /* fall through */
422 case 117 : /* fall through */
423 case 118 : /* fall through */
424 case 119 : /* fall through */
425 case 120 : /* fall through */
426 case 121 : /* fall through */
427 case 122 : /* fall through */
428 case 123 : /* fall through */
429 case 124 : /* fall through */
430 case 125 : /* fall through */
431 case 126 : /* fall through */
432 case 127 :
433 {
434 unsigned int val = (((insn >> 8) & (15 << 0)));
435 switch (val)
436 {
437 case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
438 case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
439 case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
440 case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
441 case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
442 case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
443 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
444 }
445 }
446 case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi;
447 case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi;
448 case 134 :
449 {
450 unsigned int val = (((insn >> -6) & (63 << 0)));
451 switch (val)
452 {
453 case 0 :
454 {
455 unsigned int val = (((insn >> -12) & (63 << 0)));
456 switch (val)
457 {
458 case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat;
459 case 32 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb;
460 case 48 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb;
461 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
462 }
463 }
464 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
465 }
466 }
467 case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3;
468 case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3;
469 case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3;
470 case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3;
471 case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
472 case 144 :
473 {
474 unsigned int val = (((insn >> -6) & (63 << 0)));
475 switch (val)
476 {
477 case 0 :
478 {
479 unsigned int val = (((insn >> -12) & (63 << 0)));
480 switch (val)
481 {
482 case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div;
483 case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div;
484 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
485 }
486 }
487 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
488 }
489 }
490 case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div;
491 case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div;
492 case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div;
493 case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3;
494 case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3;
495 case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3;
496 case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16;
497 case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;
498 case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;
499 case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;
500 case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ld_d;
501 case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ld_d;
502 case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ld_d;
503 case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ld_d;
504 case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d;
505 case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq;
506 case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq;
507 case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz;
508 case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz;
509 case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz;
510 case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz;
511 case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz;
512 case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz;
513 case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth;
514 case 224 : /* fall through */
515 case 225 : /* fall through */
516 case 226 : /* fall through */
517 case 227 : /* fall through */
518 case 228 : /* fall through */
519 case 229 : /* fall through */
520 case 230 : /* fall through */
521 case 231 : /* fall through */
522 case 232 : /* fall through */
523 case 233 : /* fall through */
524 case 234 : /* fall through */
525 case 235 : /* fall through */
526 case 236 : /* fall through */
527 case 237 : /* fall through */
528 case 238 : /* fall through */
529 case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24;
530 case 240 : /* fall through */
531 case 241 : /* fall through */
532 case 242 : /* fall through */
533 case 243 : /* fall through */
534 case 244 : /* fall through */
535 case 245 : /* fall through */
536 case 246 : /* fall through */
537 case 247 : /* fall through */
538 case 248 : /* fall through */
539 case 249 : /* fall through */
540 case 250 : /* fall through */
541 case 251 : /* fall through */
542 case 252 : /* fall through */
543 case 253 : /* fall through */
544 case 254 : /* fall through */
545 case 255 :
546 {
547 unsigned int val = (((insn >> 8) & (15 << 0)));
548 switch (val)
549 {
550 case 8 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24;
551 case 9 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24;
552 case 12 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24;
553 case 13 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24;
554 case 14 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24;
555 case 15 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24;
556 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
557 }
558 }
559 default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
560 }
561 }
562 }
563
564 /* The instruction has been decoded, now extract the fields. */
565
566 extract_sfmt_empty:
567 {
568 const IDESC *idesc = &m32rxf_insn_data[itype];
569 CGEN_INSN_INT insn = entire_insn;
570 #define FLD(f) abuf->fields.fmt_empty.f
571
572
573 /* Record the fields for the semantic handler. */
574 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
575
576 #undef FLD
577 return idesc;
578 }
579
580 extract_sfmt_add:
581 {
582 const IDESC *idesc = &m32rxf_insn_data[itype];
583 CGEN_INSN_INT insn = entire_insn;
584 #define FLD(f) abuf->fields.sfmt_add.f
585 UINT f_r1;
586 UINT f_r2;
587
588 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
589 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
590
591 /* Record the fields for the semantic handler. */
592 FLD (f_r1) = f_r1;
593 FLD (f_r2) = f_r2;
594 FLD (i_dr) = & CPU (h_gr)[f_r1];
595 FLD (i_sr) = & CPU (h_gr)[f_r2];
596 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
597
598 #if WITH_PROFILE_MODEL_P
599 /* Record the fields for profiling. */
600 if (PROFILE_MODEL_P (current_cpu))
601 {
602 FLD (in_dr) = f_r1;
603 FLD (in_sr) = f_r2;
604 FLD (out_dr) = f_r1;
605 }
606 #endif
607 #undef FLD
608 return idesc;
609 }
610
611 extract_sfmt_add3:
612 {
613 const IDESC *idesc = &m32rxf_insn_data[itype];
614 CGEN_INSN_INT insn = entire_insn;
615 #define FLD(f) abuf->fields.sfmt_add3.f
616 UINT f_r1;
617 UINT f_r2;
618 INT f_simm16;
619
620 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
621 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
622 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
623
624 /* Record the fields for the semantic handler. */
625 FLD (f_simm16) = f_simm16;
626 FLD (f_r2) = f_r2;
627 FLD (f_r1) = f_r1;
628 FLD (i_sr) = & CPU (h_gr)[f_r2];
629 FLD (i_dr) = & CPU (h_gr)[f_r1];
630 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
631
632 #if WITH_PROFILE_MODEL_P
633 /* Record the fields for profiling. */
634 if (PROFILE_MODEL_P (current_cpu))
635 {
636 FLD (in_sr) = f_r2;
637 FLD (out_dr) = f_r1;
638 }
639 #endif
640 #undef FLD
641 return idesc;
642 }
643
644 extract_sfmt_and3:
645 {
646 const IDESC *idesc = &m32rxf_insn_data[itype];
647 CGEN_INSN_INT insn = entire_insn;
648 #define FLD(f) abuf->fields.sfmt_and3.f
649 UINT f_r1;
650 UINT f_r2;
651 UINT f_uimm16;
652
653 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
654 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
655 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
656
657 /* Record the fields for the semantic handler. */
658 FLD (f_r2) = f_r2;
659 FLD (f_uimm16) = f_uimm16;
660 FLD (f_r1) = f_r1;
661 FLD (i_sr) = & CPU (h_gr)[f_r2];
662 FLD (i_dr) = & CPU (h_gr)[f_r1];
663 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
664
665 #if WITH_PROFILE_MODEL_P
666 /* Record the fields for profiling. */
667 if (PROFILE_MODEL_P (current_cpu))
668 {
669 FLD (in_sr) = f_r2;
670 FLD (out_dr) = f_r1;
671 }
672 #endif
673 #undef FLD
674 return idesc;
675 }
676
677 extract_sfmt_or3:
678 {
679 const IDESC *idesc = &m32rxf_insn_data[itype];
680 CGEN_INSN_INT insn = entire_insn;
681 #define FLD(f) abuf->fields.sfmt_and3.f
682 UINT f_r1;
683 UINT f_r2;
684 UINT f_uimm16;
685
686 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
687 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
688 f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
689
690 /* Record the fields for the semantic handler. */
691 FLD (f_r2) = f_r2;
692 FLD (f_uimm16) = f_uimm16;
693 FLD (f_r1) = f_r1;
694 FLD (i_sr) = & CPU (h_gr)[f_r2];
695 FLD (i_dr) = & CPU (h_gr)[f_r1];
696 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
697
698 #if WITH_PROFILE_MODEL_P
699 /* Record the fields for profiling. */
700 if (PROFILE_MODEL_P (current_cpu))
701 {
702 FLD (in_sr) = f_r2;
703 FLD (out_dr) = f_r1;
704 }
705 #endif
706 #undef FLD
707 return idesc;
708 }
709
710 extract_sfmt_addi:
711 {
712 const IDESC *idesc = &m32rxf_insn_data[itype];
713 CGEN_INSN_INT insn = entire_insn;
714 #define FLD(f) abuf->fields.sfmt_addi.f
715 UINT f_r1;
716 INT f_simm8;
717
718 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
719 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
720
721 /* Record the fields for the semantic handler. */
722 FLD (f_r1) = f_r1;
723 FLD (f_simm8) = f_simm8;
724 FLD (i_dr) = & CPU (h_gr)[f_r1];
725 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
726
727 #if WITH_PROFILE_MODEL_P
728 /* Record the fields for profiling. */
729 if (PROFILE_MODEL_P (current_cpu))
730 {
731 FLD (in_dr) = f_r1;
732 FLD (out_dr) = f_r1;
733 }
734 #endif
735 #undef FLD
736 return idesc;
737 }
738
739 extract_sfmt_addv:
740 {
741 const IDESC *idesc = &m32rxf_insn_data[itype];
742 CGEN_INSN_INT insn = entire_insn;
743 #define FLD(f) abuf->fields.sfmt_add.f
744 UINT f_r1;
745 UINT f_r2;
746
747 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
748 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
749
750 /* Record the fields for the semantic handler. */
751 FLD (f_r1) = f_r1;
752 FLD (f_r2) = f_r2;
753 FLD (i_dr) = & CPU (h_gr)[f_r1];
754 FLD (i_sr) = & CPU (h_gr)[f_r2];
755 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
756
757 #if WITH_PROFILE_MODEL_P
758 /* Record the fields for profiling. */
759 if (PROFILE_MODEL_P (current_cpu))
760 {
761 FLD (in_dr) = f_r1;
762 FLD (in_sr) = f_r2;
763 FLD (out_dr) = f_r1;
764 }
765 #endif
766 #undef FLD
767 return idesc;
768 }
769
770 extract_sfmt_addv3:
771 {
772 const IDESC *idesc = &m32rxf_insn_data[itype];
773 CGEN_INSN_INT insn = entire_insn;
774 #define FLD(f) abuf->fields.sfmt_add3.f
775 UINT f_r1;
776 UINT f_r2;
777 INT f_simm16;
778
779 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
780 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
781 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
782
783 /* Record the fields for the semantic handler. */
784 FLD (f_simm16) = f_simm16;
785 FLD (f_r2) = f_r2;
786 FLD (f_r1) = f_r1;
787 FLD (i_sr) = & CPU (h_gr)[f_r2];
788 FLD (i_dr) = & CPU (h_gr)[f_r1];
789 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
790
791 #if WITH_PROFILE_MODEL_P
792 /* Record the fields for profiling. */
793 if (PROFILE_MODEL_P (current_cpu))
794 {
795 FLD (in_sr) = f_r2;
796 FLD (out_dr) = f_r1;
797 }
798 #endif
799 #undef FLD
800 return idesc;
801 }
802
803 extract_sfmt_addx:
804 {
805 const IDESC *idesc = &m32rxf_insn_data[itype];
806 CGEN_INSN_INT insn = entire_insn;
807 #define FLD(f) abuf->fields.sfmt_add.f
808 UINT f_r1;
809 UINT f_r2;
810
811 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
812 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
813
814 /* Record the fields for the semantic handler. */
815 FLD (f_r1) = f_r1;
816 FLD (f_r2) = f_r2;
817 FLD (i_dr) = & CPU (h_gr)[f_r1];
818 FLD (i_sr) = & CPU (h_gr)[f_r2];
819 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
820
821 #if WITH_PROFILE_MODEL_P
822 /* Record the fields for profiling. */
823 if (PROFILE_MODEL_P (current_cpu))
824 {
825 FLD (in_dr) = f_r1;
826 FLD (in_sr) = f_r2;
827 FLD (out_dr) = f_r1;
828 }
829 #endif
830 #undef FLD
831 return idesc;
832 }
833
834 extract_sfmt_bc8:
835 {
836 const IDESC *idesc = &m32rxf_insn_data[itype];
837 CGEN_INSN_INT insn = entire_insn;
838 #define FLD(f) abuf->fields.sfmt_bl8.f
839 SI f_disp8;
840
841 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
842
843 /* Record the fields for the semantic handler. */
844 FLD (i_disp8) = f_disp8;
845 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
846
847 #if WITH_PROFILE_MODEL_P
848 /* Record the fields for profiling. */
849 if (PROFILE_MODEL_P (current_cpu))
850 {
851 }
852 #endif
853 #undef FLD
854 return idesc;
855 }
856
857 extract_sfmt_bc24:
858 {
859 const IDESC *idesc = &m32rxf_insn_data[itype];
860 CGEN_INSN_INT insn = entire_insn;
861 #define FLD(f) abuf->fields.sfmt_bl24.f
862 SI f_disp24;
863
864 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
865
866 /* Record the fields for the semantic handler. */
867 FLD (i_disp24) = f_disp24;
868 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
869
870 #if WITH_PROFILE_MODEL_P
871 /* Record the fields for profiling. */
872 if (PROFILE_MODEL_P (current_cpu))
873 {
874 }
875 #endif
876 #undef FLD
877 return idesc;
878 }
879
880 extract_sfmt_beq:
881 {
882 const IDESC *idesc = &m32rxf_insn_data[itype];
883 CGEN_INSN_INT insn = entire_insn;
884 #define FLD(f) abuf->fields.sfmt_beq.f
885 UINT f_r1;
886 UINT f_r2;
887 SI f_disp16;
888
889 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
890 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
891 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
892
893 /* Record the fields for the semantic handler. */
894 FLD (f_r1) = f_r1;
895 FLD (f_r2) = f_r2;
896 FLD (i_disp16) = f_disp16;
897 FLD (i_src1) = & CPU (h_gr)[f_r1];
898 FLD (i_src2) = & CPU (h_gr)[f_r2];
899 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
900
901 #if WITH_PROFILE_MODEL_P
902 /* Record the fields for profiling. */
903 if (PROFILE_MODEL_P (current_cpu))
904 {
905 FLD (in_src1) = f_r1;
906 FLD (in_src2) = f_r2;
907 }
908 #endif
909 #undef FLD
910 return idesc;
911 }
912
913 extract_sfmt_beqz:
914 {
915 const IDESC *idesc = &m32rxf_insn_data[itype];
916 CGEN_INSN_INT insn = entire_insn;
917 #define FLD(f) abuf->fields.sfmt_beq.f
918 UINT f_r2;
919 SI f_disp16;
920
921 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
922 f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
923
924 /* Record the fields for the semantic handler. */
925 FLD (f_r2) = f_r2;
926 FLD (i_disp16) = f_disp16;
927 FLD (i_src2) = & CPU (h_gr)[f_r2];
928 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
929
930 #if WITH_PROFILE_MODEL_P
931 /* Record the fields for profiling. */
932 if (PROFILE_MODEL_P (current_cpu))
933 {
934 FLD (in_src2) = f_r2;
935 }
936 #endif
937 #undef FLD
938 return idesc;
939 }
940
941 extract_sfmt_bl8:
942 {
943 const IDESC *idesc = &m32rxf_insn_data[itype];
944 CGEN_INSN_INT insn = entire_insn;
945 #define FLD(f) abuf->fields.sfmt_bl8.f
946 SI f_disp8;
947
948 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
949
950 /* Record the fields for the semantic handler. */
951 FLD (i_disp8) = f_disp8;
952 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
953
954 #if WITH_PROFILE_MODEL_P
955 /* Record the fields for profiling. */
956 if (PROFILE_MODEL_P (current_cpu))
957 {
958 FLD (out_h_gr_14) = 14;
959 }
960 #endif
961 #undef FLD
962 return idesc;
963 }
964
965 extract_sfmt_bl24:
966 {
967 const IDESC *idesc = &m32rxf_insn_data[itype];
968 CGEN_INSN_INT insn = entire_insn;
969 #define FLD(f) abuf->fields.sfmt_bl24.f
970 SI f_disp24;
971
972 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
973
974 /* Record the fields for the semantic handler. */
975 FLD (i_disp24) = f_disp24;
976 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
977
978 #if WITH_PROFILE_MODEL_P
979 /* Record the fields for profiling. */
980 if (PROFILE_MODEL_P (current_cpu))
981 {
982 FLD (out_h_gr_14) = 14;
983 }
984 #endif
985 #undef FLD
986 return idesc;
987 }
988
989 extract_sfmt_bcl8:
990 {
991 const IDESC *idesc = &m32rxf_insn_data[itype];
992 CGEN_INSN_INT insn = entire_insn;
993 #define FLD(f) abuf->fields.sfmt_bl8.f
994 SI f_disp8;
995
996 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
997
998 /* Record the fields for the semantic handler. */
999 FLD (i_disp8) = f_disp8;
1000 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1001
1002 #if WITH_PROFILE_MODEL_P
1003 /* Record the fields for profiling. */
1004 if (PROFILE_MODEL_P (current_cpu))
1005 {
1006 FLD (out_h_gr_14) = 14;
1007 }
1008 #endif
1009 #undef FLD
1010 return idesc;
1011 }
1012
1013 extract_sfmt_bcl24:
1014 {
1015 const IDESC *idesc = &m32rxf_insn_data[itype];
1016 CGEN_INSN_INT insn = entire_insn;
1017 #define FLD(f) abuf->fields.sfmt_bl24.f
1018 SI f_disp24;
1019
1020 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1021
1022 /* Record the fields for the semantic handler. */
1023 FLD (i_disp24) = f_disp24;
1024 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1025
1026 #if WITH_PROFILE_MODEL_P
1027 /* Record the fields for profiling. */
1028 if (PROFILE_MODEL_P (current_cpu))
1029 {
1030 FLD (out_h_gr_14) = 14;
1031 }
1032 #endif
1033 #undef FLD
1034 return idesc;
1035 }
1036
1037 extract_sfmt_bra8:
1038 {
1039 const IDESC *idesc = &m32rxf_insn_data[itype];
1040 CGEN_INSN_INT insn = entire_insn;
1041 #define FLD(f) abuf->fields.sfmt_bl8.f
1042 SI f_disp8;
1043
1044 f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1045
1046 /* Record the fields for the semantic handler. */
1047 FLD (i_disp8) = f_disp8;
1048 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1049
1050 #if WITH_PROFILE_MODEL_P
1051 /* Record the fields for profiling. */
1052 if (PROFILE_MODEL_P (current_cpu))
1053 {
1054 }
1055 #endif
1056 #undef FLD
1057 return idesc;
1058 }
1059
1060 extract_sfmt_bra24:
1061 {
1062 const IDESC *idesc = &m32rxf_insn_data[itype];
1063 CGEN_INSN_INT insn = entire_insn;
1064 #define FLD(f) abuf->fields.sfmt_bl24.f
1065 SI f_disp24;
1066
1067 f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1068
1069 /* Record the fields for the semantic handler. */
1070 FLD (i_disp24) = f_disp24;
1071 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1072
1073 #if WITH_PROFILE_MODEL_P
1074 /* Record the fields for profiling. */
1075 if (PROFILE_MODEL_P (current_cpu))
1076 {
1077 }
1078 #endif
1079 #undef FLD
1080 return idesc;
1081 }
1082
1083 extract_sfmt_cmp:
1084 {
1085 const IDESC *idesc = &m32rxf_insn_data[itype];
1086 CGEN_INSN_INT insn = entire_insn;
1087 #define FLD(f) abuf->fields.sfmt_st_plus.f
1088 UINT f_r1;
1089 UINT f_r2;
1090
1091 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1092 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1093
1094 /* Record the fields for the semantic handler. */
1095 FLD (f_r1) = f_r1;
1096 FLD (f_r2) = f_r2;
1097 FLD (i_src1) = & CPU (h_gr)[f_r1];
1098 FLD (i_src2) = & CPU (h_gr)[f_r2];
1099 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1100
1101 #if WITH_PROFILE_MODEL_P
1102 /* Record the fields for profiling. */
1103 if (PROFILE_MODEL_P (current_cpu))
1104 {
1105 FLD (in_src1) = f_r1;
1106 FLD (in_src2) = f_r2;
1107 }
1108 #endif
1109 #undef FLD
1110 return idesc;
1111 }
1112
1113 extract_sfmt_cmpi:
1114 {
1115 const IDESC *idesc = &m32rxf_insn_data[itype];
1116 CGEN_INSN_INT insn = entire_insn;
1117 #define FLD(f) abuf->fields.sfmt_st_d.f
1118 UINT f_r2;
1119 INT f_simm16;
1120
1121 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1122 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1123
1124 /* Record the fields for the semantic handler. */
1125 FLD (f_simm16) = f_simm16;
1126 FLD (f_r2) = f_r2;
1127 FLD (i_src2) = & CPU (h_gr)[f_r2];
1128 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1129
1130 #if WITH_PROFILE_MODEL_P
1131 /* Record the fields for profiling. */
1132 if (PROFILE_MODEL_P (current_cpu))
1133 {
1134 FLD (in_src2) = f_r2;
1135 }
1136 #endif
1137 #undef FLD
1138 return idesc;
1139 }
1140
1141 extract_sfmt_cmpz:
1142 {
1143 const IDESC *idesc = &m32rxf_insn_data[itype];
1144 CGEN_INSN_INT insn = entire_insn;
1145 #define FLD(f) abuf->fields.sfmt_st_plus.f
1146 UINT f_r2;
1147
1148 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1149
1150 /* Record the fields for the semantic handler. */
1151 FLD (f_r2) = f_r2;
1152 FLD (i_src2) = & CPU (h_gr)[f_r2];
1153 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1154
1155 #if WITH_PROFILE_MODEL_P
1156 /* Record the fields for profiling. */
1157 if (PROFILE_MODEL_P (current_cpu))
1158 {
1159 FLD (in_src2) = f_r2;
1160 }
1161 #endif
1162 #undef FLD
1163 return idesc;
1164 }
1165
1166 extract_sfmt_div:
1167 {
1168 const IDESC *idesc = &m32rxf_insn_data[itype];
1169 CGEN_INSN_INT insn = entire_insn;
1170 #define FLD(f) abuf->fields.sfmt_add.f
1171 UINT f_r1;
1172 UINT f_r2;
1173
1174 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1175 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1176
1177 /* Record the fields for the semantic handler. */
1178 FLD (f_r1) = f_r1;
1179 FLD (f_r2) = f_r2;
1180 FLD (i_dr) = & CPU (h_gr)[f_r1];
1181 FLD (i_sr) = & CPU (h_gr)[f_r2];
1182 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1183
1184 #if WITH_PROFILE_MODEL_P
1185 /* Record the fields for profiling. */
1186 if (PROFILE_MODEL_P (current_cpu))
1187 {
1188 FLD (in_dr) = f_r1;
1189 FLD (in_sr) = f_r2;
1190 FLD (out_dr) = f_r1;
1191 }
1192 #endif
1193 #undef FLD
1194 return idesc;
1195 }
1196
1197 extract_sfmt_jc:
1198 {
1199 const IDESC *idesc = &m32rxf_insn_data[itype];
1200 CGEN_INSN_INT insn = entire_insn;
1201 #define FLD(f) abuf->fields.sfmt_jl.f
1202 UINT f_r2;
1203
1204 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1205
1206 /* Record the fields for the semantic handler. */
1207 FLD (f_r2) = f_r2;
1208 FLD (i_sr) = & CPU (h_gr)[f_r2];
1209 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1210
1211 #if WITH_PROFILE_MODEL_P
1212 /* Record the fields for profiling. */
1213 if (PROFILE_MODEL_P (current_cpu))
1214 {
1215 FLD (in_sr) = f_r2;
1216 }
1217 #endif
1218 #undef FLD
1219 return idesc;
1220 }
1221
1222 extract_sfmt_jl:
1223 {
1224 const IDESC *idesc = &m32rxf_insn_data[itype];
1225 CGEN_INSN_INT insn = entire_insn;
1226 #define FLD(f) abuf->fields.sfmt_jl.f
1227 UINT f_r2;
1228
1229 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1230
1231 /* Record the fields for the semantic handler. */
1232 FLD (f_r2) = f_r2;
1233 FLD (i_sr) = & CPU (h_gr)[f_r2];
1234 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1235
1236 #if WITH_PROFILE_MODEL_P
1237 /* Record the fields for profiling. */
1238 if (PROFILE_MODEL_P (current_cpu))
1239 {
1240 FLD (in_sr) = f_r2;
1241 FLD (out_h_gr_14) = 14;
1242 }
1243 #endif
1244 #undef FLD
1245 return idesc;
1246 }
1247
1248 extract_sfmt_jmp:
1249 {
1250 const IDESC *idesc = &m32rxf_insn_data[itype];
1251 CGEN_INSN_INT insn = entire_insn;
1252 #define FLD(f) abuf->fields.sfmt_jl.f
1253 UINT f_r2;
1254
1255 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1256
1257 /* Record the fields for the semantic handler. */
1258 FLD (f_r2) = f_r2;
1259 FLD (i_sr) = & CPU (h_gr)[f_r2];
1260 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1261
1262 #if WITH_PROFILE_MODEL_P
1263 /* Record the fields for profiling. */
1264 if (PROFILE_MODEL_P (current_cpu))
1265 {
1266 FLD (in_sr) = f_r2;
1267 }
1268 #endif
1269 #undef FLD
1270 return idesc;
1271 }
1272
1273 extract_sfmt_ld:
1274 {
1275 const IDESC *idesc = &m32rxf_insn_data[itype];
1276 CGEN_INSN_INT insn = entire_insn;
1277 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1278 UINT f_r1;
1279 UINT f_r2;
1280
1281 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1282 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1283
1284 /* Record the fields for the semantic handler. */
1285 FLD (f_r2) = f_r2;
1286 FLD (f_r1) = f_r1;
1287 FLD (i_sr) = & CPU (h_gr)[f_r2];
1288 FLD (i_dr) = & CPU (h_gr)[f_r1];
1289 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1290
1291 #if WITH_PROFILE_MODEL_P
1292 /* Record the fields for profiling. */
1293 if (PROFILE_MODEL_P (current_cpu))
1294 {
1295 FLD (in_sr) = f_r2;
1296 FLD (out_dr) = f_r1;
1297 }
1298 #endif
1299 #undef FLD
1300 return idesc;
1301 }
1302
1303 extract_sfmt_ld_d:
1304 {
1305 const IDESC *idesc = &m32rxf_insn_data[itype];
1306 CGEN_INSN_INT insn = entire_insn;
1307 #define FLD(f) abuf->fields.sfmt_add3.f
1308 UINT f_r1;
1309 UINT f_r2;
1310 INT f_simm16;
1311
1312 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1313 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1314 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1315
1316 /* Record the fields for the semantic handler. */
1317 FLD (f_simm16) = f_simm16;
1318 FLD (f_r2) = f_r2;
1319 FLD (f_r1) = f_r1;
1320 FLD (i_sr) = & CPU (h_gr)[f_r2];
1321 FLD (i_dr) = & CPU (h_gr)[f_r1];
1322 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1323
1324 #if WITH_PROFILE_MODEL_P
1325 /* Record the fields for profiling. */
1326 if (PROFILE_MODEL_P (current_cpu))
1327 {
1328 FLD (in_sr) = f_r2;
1329 FLD (out_dr) = f_r1;
1330 }
1331 #endif
1332 #undef FLD
1333 return idesc;
1334 }
1335
1336 extract_sfmt_ld_plus:
1337 {
1338 const IDESC *idesc = &m32rxf_insn_data[itype];
1339 CGEN_INSN_INT insn = entire_insn;
1340 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1341 UINT f_r1;
1342 UINT f_r2;
1343
1344 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1345 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1346
1347 /* Record the fields for the semantic handler. */
1348 FLD (f_r2) = f_r2;
1349 FLD (f_r1) = f_r1;
1350 FLD (i_sr) = & CPU (h_gr)[f_r2];
1351 FLD (i_dr) = & CPU (h_gr)[f_r1];
1352 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1353
1354 #if WITH_PROFILE_MODEL_P
1355 /* Record the fields for profiling. */
1356 if (PROFILE_MODEL_P (current_cpu))
1357 {
1358 FLD (in_sr) = f_r2;
1359 FLD (out_dr) = f_r1;
1360 FLD (out_sr) = f_r2;
1361 }
1362 #endif
1363 #undef FLD
1364 return idesc;
1365 }
1366
1367 extract_sfmt_ld24:
1368 {
1369 const IDESC *idesc = &m32rxf_insn_data[itype];
1370 CGEN_INSN_INT insn = entire_insn;
1371 #define FLD(f) abuf->fields.sfmt_ld24.f
1372 UINT f_r1;
1373 UINT f_uimm24;
1374
1375 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1376 f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
1377
1378 /* Record the fields for the semantic handler. */
1379 FLD (f_r1) = f_r1;
1380 FLD (i_uimm24) = f_uimm24;
1381 FLD (i_dr) = & CPU (h_gr)[f_r1];
1382 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1383
1384 #if WITH_PROFILE_MODEL_P
1385 /* Record the fields for profiling. */
1386 if (PROFILE_MODEL_P (current_cpu))
1387 {
1388 FLD (out_dr) = f_r1;
1389 }
1390 #endif
1391 #undef FLD
1392 return idesc;
1393 }
1394
1395 extract_sfmt_ldi8:
1396 {
1397 const IDESC *idesc = &m32rxf_insn_data[itype];
1398 CGEN_INSN_INT insn = entire_insn;
1399 #define FLD(f) abuf->fields.sfmt_addi.f
1400 UINT f_r1;
1401 INT f_simm8;
1402
1403 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1404 f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
1405
1406 /* Record the fields for the semantic handler. */
1407 FLD (f_simm8) = f_simm8;
1408 FLD (f_r1) = f_r1;
1409 FLD (i_dr) = & CPU (h_gr)[f_r1];
1410 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1411
1412 #if WITH_PROFILE_MODEL_P
1413 /* Record the fields for profiling. */
1414 if (PROFILE_MODEL_P (current_cpu))
1415 {
1416 FLD (out_dr) = f_r1;
1417 }
1418 #endif
1419 #undef FLD
1420 return idesc;
1421 }
1422
1423 extract_sfmt_ldi16:
1424 {
1425 const IDESC *idesc = &m32rxf_insn_data[itype];
1426 CGEN_INSN_INT insn = entire_insn;
1427 #define FLD(f) abuf->fields.sfmt_add3.f
1428 UINT f_r1;
1429 INT f_simm16;
1430
1431 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1432 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1433
1434 /* Record the fields for the semantic handler. */
1435 FLD (f_simm16) = f_simm16;
1436 FLD (f_r1) = f_r1;
1437 FLD (i_dr) = & CPU (h_gr)[f_r1];
1438 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1439
1440 #if WITH_PROFILE_MODEL_P
1441 /* Record the fields for profiling. */
1442 if (PROFILE_MODEL_P (current_cpu))
1443 {
1444 FLD (out_dr) = f_r1;
1445 }
1446 #endif
1447 #undef FLD
1448 return idesc;
1449 }
1450
1451 extract_sfmt_lock:
1452 {
1453 const IDESC *idesc = &m32rxf_insn_data[itype];
1454 CGEN_INSN_INT insn = entire_insn;
1455 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1456 UINT f_r1;
1457 UINT f_r2;
1458
1459 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1460 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1461
1462 /* Record the fields for the semantic handler. */
1463 FLD (f_r2) = f_r2;
1464 FLD (f_r1) = f_r1;
1465 FLD (i_sr) = & CPU (h_gr)[f_r2];
1466 FLD (i_dr) = & CPU (h_gr)[f_r1];
1467 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1468
1469 #if WITH_PROFILE_MODEL_P
1470 /* Record the fields for profiling. */
1471 if (PROFILE_MODEL_P (current_cpu))
1472 {
1473 FLD (in_sr) = f_r2;
1474 FLD (out_dr) = f_r1;
1475 }
1476 #endif
1477 #undef FLD
1478 return idesc;
1479 }
1480
1481 extract_sfmt_machi_a:
1482 {
1483 const IDESC *idesc = &m32rxf_insn_data[itype];
1484 CGEN_INSN_INT insn = entire_insn;
1485 #define FLD(f) abuf->fields.sfmt_machi_a.f
1486 UINT f_r1;
1487 UINT f_acc;
1488 UINT f_r2;
1489
1490 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1491 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1492 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1493
1494 /* Record the fields for the semantic handler. */
1495 FLD (f_acc) = f_acc;
1496 FLD (f_r1) = f_r1;
1497 FLD (f_r2) = f_r2;
1498 FLD (i_src1) = & CPU (h_gr)[f_r1];
1499 FLD (i_src2) = & CPU (h_gr)[f_r2];
1500 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1501
1502 #if WITH_PROFILE_MODEL_P
1503 /* Record the fields for profiling. */
1504 if (PROFILE_MODEL_P (current_cpu))
1505 {
1506 FLD (in_src1) = f_r1;
1507 FLD (in_src2) = f_r2;
1508 }
1509 #endif
1510 #undef FLD
1511 return idesc;
1512 }
1513
1514 extract_sfmt_mulhi_a:
1515 {
1516 const IDESC *idesc = &m32rxf_insn_data[itype];
1517 CGEN_INSN_INT insn = entire_insn;
1518 #define FLD(f) abuf->fields.sfmt_machi_a.f
1519 UINT f_r1;
1520 UINT f_acc;
1521 UINT f_r2;
1522
1523 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1524 f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1525 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1526
1527 /* Record the fields for the semantic handler. */
1528 FLD (f_r1) = f_r1;
1529 FLD (f_r2) = f_r2;
1530 FLD (f_acc) = f_acc;
1531 FLD (i_src1) = & CPU (h_gr)[f_r1];
1532 FLD (i_src2) = & CPU (h_gr)[f_r2];
1533 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1534
1535 #if WITH_PROFILE_MODEL_P
1536 /* Record the fields for profiling. */
1537 if (PROFILE_MODEL_P (current_cpu))
1538 {
1539 FLD (in_src1) = f_r1;
1540 FLD (in_src2) = f_r2;
1541 }
1542 #endif
1543 #undef FLD
1544 return idesc;
1545 }
1546
1547 extract_sfmt_mv:
1548 {
1549 const IDESC *idesc = &m32rxf_insn_data[itype];
1550 CGEN_INSN_INT insn = entire_insn;
1551 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1552 UINT f_r1;
1553 UINT f_r2;
1554
1555 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1556 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1557
1558 /* Record the fields for the semantic handler. */
1559 FLD (f_r2) = f_r2;
1560 FLD (f_r1) = f_r1;
1561 FLD (i_sr) = & CPU (h_gr)[f_r2];
1562 FLD (i_dr) = & CPU (h_gr)[f_r1];
1563 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1564
1565 #if WITH_PROFILE_MODEL_P
1566 /* Record the fields for profiling. */
1567 if (PROFILE_MODEL_P (current_cpu))
1568 {
1569 FLD (in_sr) = f_r2;
1570 FLD (out_dr) = f_r1;
1571 }
1572 #endif
1573 #undef FLD
1574 return idesc;
1575 }
1576
1577 extract_sfmt_mvfachi_a:
1578 {
1579 const IDESC *idesc = &m32rxf_insn_data[itype];
1580 CGEN_INSN_INT insn = entire_insn;
1581 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1582 UINT f_r1;
1583 UINT f_accs;
1584
1585 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1586 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1587
1588 /* Record the fields for the semantic handler. */
1589 FLD (f_accs) = f_accs;
1590 FLD (f_r1) = f_r1;
1591 FLD (i_dr) = & CPU (h_gr)[f_r1];
1592 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1593
1594 #if WITH_PROFILE_MODEL_P
1595 /* Record the fields for profiling. */
1596 if (PROFILE_MODEL_P (current_cpu))
1597 {
1598 FLD (out_dr) = f_r1;
1599 }
1600 #endif
1601 #undef FLD
1602 return idesc;
1603 }
1604
1605 extract_sfmt_mvfc:
1606 {
1607 const IDESC *idesc = &m32rxf_insn_data[itype];
1608 CGEN_INSN_INT insn = entire_insn;
1609 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1610 UINT f_r1;
1611 UINT f_r2;
1612
1613 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1614 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1615
1616 /* Record the fields for the semantic handler. */
1617 FLD (f_r2) = f_r2;
1618 FLD (f_r1) = f_r1;
1619 FLD (i_dr) = & CPU (h_gr)[f_r1];
1620 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1621
1622 #if WITH_PROFILE_MODEL_P
1623 /* Record the fields for profiling. */
1624 if (PROFILE_MODEL_P (current_cpu))
1625 {
1626 FLD (out_dr) = f_r1;
1627 }
1628 #endif
1629 #undef FLD
1630 return idesc;
1631 }
1632
1633 extract_sfmt_mvtachi_a:
1634 {
1635 const IDESC *idesc = &m32rxf_insn_data[itype];
1636 CGEN_INSN_INT insn = entire_insn;
1637 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1638 UINT f_r1;
1639 UINT f_accs;
1640
1641 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1642 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1643
1644 /* Record the fields for the semantic handler. */
1645 FLD (f_accs) = f_accs;
1646 FLD (f_r1) = f_r1;
1647 FLD (i_src1) = & CPU (h_gr)[f_r1];
1648 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
1649
1650 #if WITH_PROFILE_MODEL_P
1651 /* Record the fields for profiling. */
1652 if (PROFILE_MODEL_P (current_cpu))
1653 {
1654 FLD (in_src1) = f_r1;
1655 }
1656 #endif
1657 #undef FLD
1658 return idesc;
1659 }
1660
1661 extract_sfmt_mvtc:
1662 {
1663 const IDESC *idesc = &m32rxf_insn_data[itype];
1664 CGEN_INSN_INT insn = entire_insn;
1665 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1666 UINT f_r1;
1667 UINT f_r2;
1668
1669 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1670 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1671
1672 /* Record the fields for the semantic handler. */
1673 FLD (f_r2) = f_r2;
1674 FLD (f_r1) = f_r1;
1675 FLD (i_sr) = & CPU (h_gr)[f_r2];
1676 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1677
1678 #if WITH_PROFILE_MODEL_P
1679 /* Record the fields for profiling. */
1680 if (PROFILE_MODEL_P (current_cpu))
1681 {
1682 FLD (in_sr) = f_r2;
1683 }
1684 #endif
1685 #undef FLD
1686 return idesc;
1687 }
1688
1689 extract_sfmt_nop:
1690 {
1691 const IDESC *idesc = &m32rxf_insn_data[itype];
1692 CGEN_INSN_INT insn = entire_insn;
1693 #define FLD(f) abuf->fields.fmt_empty.f
1694
1695
1696 /* Record the fields for the semantic handler. */
1697 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
1698
1699 #undef FLD
1700 return idesc;
1701 }
1702
1703 extract_sfmt_rac_dsi:
1704 {
1705 const IDESC *idesc = &m32rxf_insn_data[itype];
1706 CGEN_INSN_INT insn = entire_insn;
1707 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
1708 UINT f_accd;
1709 UINT f_accs;
1710 SI f_imm1;
1711
1712 f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
1713 f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1714 f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
1715
1716 /* Record the fields for the semantic handler. */
1717 FLD (f_accs) = f_accs;
1718 FLD (f_imm1) = f_imm1;
1719 FLD (f_accd) = f_accd;
1720 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
1721
1722 #undef FLD
1723 return idesc;
1724 }
1725
1726 extract_sfmt_rte:
1727 {
1728 const IDESC *idesc = &m32rxf_insn_data[itype];
1729 CGEN_INSN_INT insn = entire_insn;
1730 #define FLD(f) abuf->fields.fmt_empty.f
1731
1732
1733 /* Record the fields for the semantic handler. */
1734 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
1735
1736 #if WITH_PROFILE_MODEL_P
1737 /* Record the fields for profiling. */
1738 if (PROFILE_MODEL_P (current_cpu))
1739 {
1740 }
1741 #endif
1742 #undef FLD
1743 return idesc;
1744 }
1745
1746 extract_sfmt_seth:
1747 {
1748 const IDESC *idesc = &m32rxf_insn_data[itype];
1749 CGEN_INSN_INT insn = entire_insn;
1750 #define FLD(f) abuf->fields.sfmt_seth.f
1751 UINT f_r1;
1752 UINT f_hi16;
1753
1754 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1755 f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
1756
1757 /* Record the fields for the semantic handler. */
1758 FLD (f_hi16) = f_hi16;
1759 FLD (f_r1) = f_r1;
1760 FLD (i_dr) = & CPU (h_gr)[f_r1];
1761 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1762
1763 #if WITH_PROFILE_MODEL_P
1764 /* Record the fields for profiling. */
1765 if (PROFILE_MODEL_P (current_cpu))
1766 {
1767 FLD (out_dr) = f_r1;
1768 }
1769 #endif
1770 #undef FLD
1771 return idesc;
1772 }
1773
1774 extract_sfmt_sll3:
1775 {
1776 const IDESC *idesc = &m32rxf_insn_data[itype];
1777 CGEN_INSN_INT insn = entire_insn;
1778 #define FLD(f) abuf->fields.sfmt_add3.f
1779 UINT f_r1;
1780 UINT f_r2;
1781 INT f_simm16;
1782
1783 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1784 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1785 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1786
1787 /* Record the fields for the semantic handler. */
1788 FLD (f_simm16) = f_simm16;
1789 FLD (f_r2) = f_r2;
1790 FLD (f_r1) = f_r1;
1791 FLD (i_sr) = & CPU (h_gr)[f_r2];
1792 FLD (i_dr) = & CPU (h_gr)[f_r1];
1793 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1794
1795 #if WITH_PROFILE_MODEL_P
1796 /* Record the fields for profiling. */
1797 if (PROFILE_MODEL_P (current_cpu))
1798 {
1799 FLD (in_sr) = f_r2;
1800 FLD (out_dr) = f_r1;
1801 }
1802 #endif
1803 #undef FLD
1804 return idesc;
1805 }
1806
1807 extract_sfmt_slli:
1808 {
1809 const IDESC *idesc = &m32rxf_insn_data[itype];
1810 CGEN_INSN_INT insn = entire_insn;
1811 #define FLD(f) abuf->fields.sfmt_slli.f
1812 UINT f_r1;
1813 UINT f_uimm5;
1814
1815 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1816 f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
1817
1818 /* Record the fields for the semantic handler. */
1819 FLD (f_r1) = f_r1;
1820 FLD (f_uimm5) = f_uimm5;
1821 FLD (i_dr) = & CPU (h_gr)[f_r1];
1822 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
1823
1824 #if WITH_PROFILE_MODEL_P
1825 /* Record the fields for profiling. */
1826 if (PROFILE_MODEL_P (current_cpu))
1827 {
1828 FLD (in_dr) = f_r1;
1829 FLD (out_dr) = f_r1;
1830 }
1831 #endif
1832 #undef FLD
1833 return idesc;
1834 }
1835
1836 extract_sfmt_st:
1837 {
1838 const IDESC *idesc = &m32rxf_insn_data[itype];
1839 CGEN_INSN_INT insn = entire_insn;
1840 #define FLD(f) abuf->fields.sfmt_st_plus.f
1841 UINT f_r1;
1842 UINT f_r2;
1843
1844 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1845 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1846
1847 /* Record the fields for the semantic handler. */
1848 FLD (f_r1) = f_r1;
1849 FLD (f_r2) = f_r2;
1850 FLD (i_src1) = & CPU (h_gr)[f_r1];
1851 FLD (i_src2) = & CPU (h_gr)[f_r2];
1852 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1853
1854 #if WITH_PROFILE_MODEL_P
1855 /* Record the fields for profiling. */
1856 if (PROFILE_MODEL_P (current_cpu))
1857 {
1858 FLD (in_src1) = f_r1;
1859 FLD (in_src2) = f_r2;
1860 }
1861 #endif
1862 #undef FLD
1863 return idesc;
1864 }
1865
1866 extract_sfmt_st_d:
1867 {
1868 const IDESC *idesc = &m32rxf_insn_data[itype];
1869 CGEN_INSN_INT insn = entire_insn;
1870 #define FLD(f) abuf->fields.sfmt_st_d.f
1871 UINT f_r1;
1872 UINT f_r2;
1873 INT f_simm16;
1874
1875 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1876 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1877 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1878
1879 /* Record the fields for the semantic handler. */
1880 FLD (f_simm16) = f_simm16;
1881 FLD (f_r1) = f_r1;
1882 FLD (f_r2) = f_r2;
1883 FLD (i_src1) = & CPU (h_gr)[f_r1];
1884 FLD (i_src2) = & CPU (h_gr)[f_r2];
1885 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1886
1887 #if WITH_PROFILE_MODEL_P
1888 /* Record the fields for profiling. */
1889 if (PROFILE_MODEL_P (current_cpu))
1890 {
1891 FLD (in_src1) = f_r1;
1892 FLD (in_src2) = f_r2;
1893 }
1894 #endif
1895 #undef FLD
1896 return idesc;
1897 }
1898
1899 extract_sfmt_stb:
1900 {
1901 const IDESC *idesc = &m32rxf_insn_data[itype];
1902 CGEN_INSN_INT insn = entire_insn;
1903 #define FLD(f) abuf->fields.sfmt_st_plus.f
1904 UINT f_r1;
1905 UINT f_r2;
1906
1907 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1908 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1909
1910 /* Record the fields for the semantic handler. */
1911 FLD (f_r1) = f_r1;
1912 FLD (f_r2) = f_r2;
1913 FLD (i_src1) = & CPU (h_gr)[f_r1];
1914 FLD (i_src2) = & CPU (h_gr)[f_r2];
1915 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1916
1917 #if WITH_PROFILE_MODEL_P
1918 /* Record the fields for profiling. */
1919 if (PROFILE_MODEL_P (current_cpu))
1920 {
1921 FLD (in_src1) = f_r1;
1922 FLD (in_src2) = f_r2;
1923 }
1924 #endif
1925 #undef FLD
1926 return idesc;
1927 }
1928
1929 extract_sfmt_stb_d:
1930 {
1931 const IDESC *idesc = &m32rxf_insn_data[itype];
1932 CGEN_INSN_INT insn = entire_insn;
1933 #define FLD(f) abuf->fields.sfmt_st_d.f
1934 UINT f_r1;
1935 UINT f_r2;
1936 INT f_simm16;
1937
1938 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1939 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1940 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1941
1942 /* Record the fields for the semantic handler. */
1943 FLD (f_simm16) = f_simm16;
1944 FLD (f_r1) = f_r1;
1945 FLD (f_r2) = f_r2;
1946 FLD (i_src1) = & CPU (h_gr)[f_r1];
1947 FLD (i_src2) = & CPU (h_gr)[f_r2];
1948 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1949
1950 #if WITH_PROFILE_MODEL_P
1951 /* Record the fields for profiling. */
1952 if (PROFILE_MODEL_P (current_cpu))
1953 {
1954 FLD (in_src1) = f_r1;
1955 FLD (in_src2) = f_r2;
1956 }
1957 #endif
1958 #undef FLD
1959 return idesc;
1960 }
1961
1962 extract_sfmt_sth:
1963 {
1964 const IDESC *idesc = &m32rxf_insn_data[itype];
1965 CGEN_INSN_INT insn = entire_insn;
1966 #define FLD(f) abuf->fields.sfmt_st_plus.f
1967 UINT f_r1;
1968 UINT f_r2;
1969
1970 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1971 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1972
1973 /* Record the fields for the semantic handler. */
1974 FLD (f_r1) = f_r1;
1975 FLD (f_r2) = f_r2;
1976 FLD (i_src1) = & CPU (h_gr)[f_r1];
1977 FLD (i_src2) = & CPU (h_gr)[f_r2];
1978 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1979
1980 #if WITH_PROFILE_MODEL_P
1981 /* Record the fields for profiling. */
1982 if (PROFILE_MODEL_P (current_cpu))
1983 {
1984 FLD (in_src1) = f_r1;
1985 FLD (in_src2) = f_r2;
1986 }
1987 #endif
1988 #undef FLD
1989 return idesc;
1990 }
1991
1992 extract_sfmt_sth_d:
1993 {
1994 const IDESC *idesc = &m32rxf_insn_data[itype];
1995 CGEN_INSN_INT insn = entire_insn;
1996 #define FLD(f) abuf->fields.sfmt_st_d.f
1997 UINT f_r1;
1998 UINT f_r2;
1999 INT f_simm16;
2000
2001 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2002 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2003 f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
2004
2005 /* Record the fields for the semantic handler. */
2006 FLD (f_simm16) = f_simm16;
2007 FLD (f_r1) = f_r1;
2008 FLD (f_r2) = f_r2;
2009 FLD (i_src1) = & CPU (h_gr)[f_r1];
2010 FLD (i_src2) = & CPU (h_gr)[f_r2];
2011 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2012
2013 #if WITH_PROFILE_MODEL_P
2014 /* Record the fields for profiling. */
2015 if (PROFILE_MODEL_P (current_cpu))
2016 {
2017 FLD (in_src1) = f_r1;
2018 FLD (in_src2) = f_r2;
2019 }
2020 #endif
2021 #undef FLD
2022 return idesc;
2023 }
2024
2025 extract_sfmt_st_plus:
2026 {
2027 const IDESC *idesc = &m32rxf_insn_data[itype];
2028 CGEN_INSN_INT insn = entire_insn;
2029 #define FLD(f) abuf->fields.sfmt_st_plus.f
2030 UINT f_r1;
2031 UINT f_r2;
2032
2033 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2034 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2035
2036 /* Record the fields for the semantic handler. */
2037 FLD (f_r1) = f_r1;
2038 FLD (f_r2) = f_r2;
2039 FLD (i_src1) = & CPU (h_gr)[f_r1];
2040 FLD (i_src2) = & CPU (h_gr)[f_r2];
2041 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2042
2043 #if WITH_PROFILE_MODEL_P
2044 /* Record the fields for profiling. */
2045 if (PROFILE_MODEL_P (current_cpu))
2046 {
2047 FLD (in_src1) = f_r1;
2048 FLD (in_src2) = f_r2;
2049 FLD (out_src2) = f_r2;
2050 }
2051 #endif
2052 #undef FLD
2053 return idesc;
2054 }
2055
2056 extract_sfmt_trap:
2057 {
2058 const IDESC *idesc = &m32rxf_insn_data[itype];
2059 CGEN_INSN_INT insn = entire_insn;
2060 #define FLD(f) abuf->fields.sfmt_trap.f
2061 UINT f_uimm4;
2062
2063 f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2064
2065 /* Record the fields for the semantic handler. */
2066 FLD (f_uimm4) = f_uimm4;
2067 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
2068
2069 #if WITH_PROFILE_MODEL_P
2070 /* Record the fields for profiling. */
2071 if (PROFILE_MODEL_P (current_cpu))
2072 {
2073 }
2074 #endif
2075 #undef FLD
2076 return idesc;
2077 }
2078
2079 extract_sfmt_unlock:
2080 {
2081 const IDESC *idesc = &m32rxf_insn_data[itype];
2082 CGEN_INSN_INT insn = entire_insn;
2083 #define FLD(f) abuf->fields.sfmt_st_plus.f
2084 UINT f_r1;
2085 UINT f_r2;
2086
2087 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2088 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2089
2090 /* Record the fields for the semantic handler. */
2091 FLD (f_r1) = f_r1;
2092 FLD (f_r2) = f_r2;
2093 FLD (i_src1) = & CPU (h_gr)[f_r1];
2094 FLD (i_src2) = & CPU (h_gr)[f_r2];
2095 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2096
2097 #if WITH_PROFILE_MODEL_P
2098 /* Record the fields for profiling. */
2099 if (PROFILE_MODEL_P (current_cpu))
2100 {
2101 FLD (in_src1) = f_r1;
2102 FLD (in_src2) = f_r2;
2103 }
2104 #endif
2105 #undef FLD
2106 return idesc;
2107 }
2108
2109 extract_sfmt_satb:
2110 {
2111 const IDESC *idesc = &m32rxf_insn_data[itype];
2112 CGEN_INSN_INT insn = entire_insn;
2113 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2114 UINT f_r1;
2115 UINT f_r2;
2116
2117 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2118 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2119
2120 /* Record the fields for the semantic handler. */
2121 FLD (f_r2) = f_r2;
2122 FLD (f_r1) = f_r1;
2123 FLD (i_sr) = & CPU (h_gr)[f_r2];
2124 FLD (i_dr) = & CPU (h_gr)[f_r1];
2125 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2126
2127 #if WITH_PROFILE_MODEL_P
2128 /* Record the fields for profiling. */
2129 if (PROFILE_MODEL_P (current_cpu))
2130 {
2131 FLD (in_sr) = f_r2;
2132 FLD (out_dr) = f_r1;
2133 }
2134 #endif
2135 #undef FLD
2136 return idesc;
2137 }
2138
2139 extract_sfmt_sat:
2140 {
2141 const IDESC *idesc = &m32rxf_insn_data[itype];
2142 CGEN_INSN_INT insn = entire_insn;
2143 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2144 UINT f_r1;
2145 UINT f_r2;
2146
2147 f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2148 f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2149
2150 /* Record the fields for the semantic handler. */
2151 FLD (f_r2) = f_r2;
2152 FLD (f_r1) = f_r1;
2153 FLD (i_sr) = & CPU (h_gr)[f_r2];
2154 FLD (i_dr) = & CPU (h_gr)[f_r1];
2155 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2156
2157 #if WITH_PROFILE_MODEL_P
2158 /* Record the fields for profiling. */
2159 if (PROFILE_MODEL_P (current_cpu))
2160 {
2161 FLD (in_sr) = f_r2;
2162 FLD (out_dr) = f_r1;
2163 }
2164 #endif
2165 #undef FLD
2166 return idesc;
2167 }
2168
2169 extract_sfmt_sadd:
2170 {
2171 const IDESC *idesc = &m32rxf_insn_data[itype];
2172 CGEN_INSN_INT insn = entire_insn;
2173 #define FLD(f) abuf->fields.fmt_empty.f
2174
2175
2176 /* Record the fields for the semantic handler. */
2177 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
2178
2179 #undef FLD
2180 return idesc;
2181 }
2182
2183 extract_sfmt_macwu1:
2184 {
2185 const IDESC *idesc = &m32rxf_insn_data[itype];
2186 CGEN_INSN_INT insn = entire_insn;
2187 #define FLD(f) abuf->fields.sfmt_st_plus.f
2188 UINT f_r1;
2189 UINT f_r2;
2190
2191 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2192 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2193
2194 /* Record the fields for the semantic handler. */
2195 FLD (f_r1) = f_r1;
2196 FLD (f_r2) = f_r2;
2197 FLD (i_src1) = & CPU (h_gr)[f_r1];
2198 FLD (i_src2) = & CPU (h_gr)[f_r2];
2199 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2200
2201 #if WITH_PROFILE_MODEL_P
2202 /* Record the fields for profiling. */
2203 if (PROFILE_MODEL_P (current_cpu))
2204 {
2205 FLD (in_src1) = f_r1;
2206 FLD (in_src2) = f_r2;
2207 }
2208 #endif
2209 #undef FLD
2210 return idesc;
2211 }
2212
2213 extract_sfmt_msblo:
2214 {
2215 const IDESC *idesc = &m32rxf_insn_data[itype];
2216 CGEN_INSN_INT insn = entire_insn;
2217 #define FLD(f) abuf->fields.sfmt_st_plus.f
2218 UINT f_r1;
2219 UINT f_r2;
2220
2221 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2222 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2223
2224 /* Record the fields for the semantic handler. */
2225 FLD (f_r1) = f_r1;
2226 FLD (f_r2) = f_r2;
2227 FLD (i_src1) = & CPU (h_gr)[f_r1];
2228 FLD (i_src2) = & CPU (h_gr)[f_r2];
2229 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2230
2231 #if WITH_PROFILE_MODEL_P
2232 /* Record the fields for profiling. */
2233 if (PROFILE_MODEL_P (current_cpu))
2234 {
2235 FLD (in_src1) = f_r1;
2236 FLD (in_src2) = f_r2;
2237 }
2238 #endif
2239 #undef FLD
2240 return idesc;
2241 }
2242
2243 extract_sfmt_mulwu1:
2244 {
2245 const IDESC *idesc = &m32rxf_insn_data[itype];
2246 CGEN_INSN_INT insn = entire_insn;
2247 #define FLD(f) abuf->fields.sfmt_st_plus.f
2248 UINT f_r1;
2249 UINT f_r2;
2250
2251 f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2252 f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2253
2254 /* Record the fields for the semantic handler. */
2255 FLD (f_r1) = f_r1;
2256 FLD (f_r2) = f_r2;
2257 FLD (i_src1) = & CPU (h_gr)[f_r1];
2258 FLD (i_src2) = & CPU (h_gr)[f_r2];
2259 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2260
2261 #if WITH_PROFILE_MODEL_P
2262 /* Record the fields for profiling. */
2263 if (PROFILE_MODEL_P (current_cpu))
2264 {
2265 FLD (in_src1) = f_r1;
2266 FLD (in_src2) = f_r2;
2267 }
2268 #endif
2269 #undef FLD
2270 return idesc;
2271 }
2272
2273 extract_sfmt_sc:
2274 {
2275 const IDESC *idesc = &m32rxf_insn_data[itype];
2276 CGEN_INSN_INT insn = entire_insn;
2277 #define FLD(f) abuf->fields.fmt_empty.f
2278
2279
2280 /* Record the fields for the semantic handler. */
2281 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
2282
2283 #undef FLD
2284 return idesc;
2285 }
2286
2287 }
GDB Binutils - Deliverables
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