sim/m32r/decodex.c

   1 /* Simulator instruction decoder for m32rxf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #define WANT_CPU m32rxf
  26 #define WANT_CPU_M32RXF
  27
  28 #include "sim-main.h"
  29 #include "sim-assert.h"
  30
  31 /* Insn can't be executed in parallel.
  32    Or is that "do NOt Pass to Air defense Radar"? :-) */
  33 #define NOPAR (-1)
  34
  35 /* The instruction descriptor array.
  36    This is computed at runtime.  Space for it is not malloc'd to save a
  37    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
  38    but won't be done until necessary (we don't currently support the runtime
  39    addition of instructions nor an SMP machine with different cpus).  */
  40 static IDESC m32rxf_insn_data[M32RXF_INSN_MAX];
  41
  42 /* Commas between elements are contained in the macros.
  43    Some of these are conditionally compiled out.  */
  44
  45 static const struct insn_sem m32rxf_insn_sem[] =
  46 {
  47   { VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
  48   { VIRTUAL_INSN_X_AFTER, M32RXF_INSN_X_AFTER, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
  49   { VIRTUAL_INSN_X_BEFORE, M32RXF_INSN_X_BEFORE, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
  50   { VIRTUAL_INSN_X_CTI_CHAIN, M32RXF_INSN_X_CTI_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
  51   { VIRTUAL_INSN_X_CHAIN, M32RXF_INSN_X_CHAIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
  52   { VIRTUAL_INSN_X_BEGIN, M32RXF_INSN_X_BEGIN, M32RXF_SFMT_EMPTY, NOPAR, NOPAR  },
  53   { M32R_INSN_ADD, M32RXF_INSN_ADD, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_ADD, M32RXF_INSN_WRITE_ADD },
  54   { M32R_INSN_ADD3, M32RXF_INSN_ADD3, M32RXF_SFMT_ADD3, NOPAR, NOPAR  },
  55   { M32R_INSN_AND, M32RXF_INSN_AND, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_AND, M32RXF_INSN_WRITE_AND },
  56   { M32R_INSN_AND3, M32RXF_INSN_AND3, M32RXF_SFMT_AND3, NOPAR, NOPAR  },
  57   { M32R_INSN_OR, M32RXF_INSN_OR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_OR, M32RXF_INSN_WRITE_OR },
  58   { M32R_INSN_OR3, M32RXF_INSN_OR3, M32RXF_SFMT_OR3, NOPAR, NOPAR  },
  59   { M32R_INSN_XOR, M32RXF_INSN_XOR, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_XOR, M32RXF_INSN_WRITE_XOR },
  60   { M32R_INSN_XOR3, M32RXF_INSN_XOR3, M32RXF_SFMT_AND3, NOPAR, NOPAR  },
  61   { M32R_INSN_ADDI, M32RXF_INSN_ADDI, M32RXF_SFMT_ADDI, M32RXF_INSN_PAR_ADDI, M32RXF_INSN_WRITE_ADDI },
  62   { M32R_INSN_ADDV, M32RXF_INSN_ADDV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_ADDV, M32RXF_INSN_WRITE_ADDV },
  63   { M32R_INSN_ADDV3, M32RXF_INSN_ADDV3, M32RXF_SFMT_ADDV3, NOPAR, NOPAR  },
  64   { M32R_INSN_ADDX, M32RXF_INSN_ADDX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_ADDX, M32RXF_INSN_WRITE_ADDX },
  65   { M32R_INSN_BC8, M32RXF_INSN_BC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BC8, M32RXF_INSN_WRITE_BC8 },
  66   { M32R_INSN_BC24, M32RXF_INSN_BC24, M32RXF_SFMT_BC24, NOPAR, NOPAR  },
  67   { M32R_INSN_BEQ, M32RXF_INSN_BEQ, M32RXF_SFMT_BEQ, NOPAR, NOPAR  },
  68   { M32R_INSN_BEQZ, M32RXF_INSN_BEQZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
  69   { M32R_INSN_BGEZ, M32RXF_INSN_BGEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
  70   { M32R_INSN_BGTZ, M32RXF_INSN_BGTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
  71   { M32R_INSN_BLEZ, M32RXF_INSN_BLEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
  72   { M32R_INSN_BLTZ, M32RXF_INSN_BLTZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
  73   { M32R_INSN_BNEZ, M32RXF_INSN_BNEZ, M32RXF_SFMT_BEQZ, NOPAR, NOPAR  },
  74   { M32R_INSN_BL8, M32RXF_INSN_BL8, M32RXF_SFMT_BL8, M32RXF_INSN_PAR_BL8, M32RXF_INSN_WRITE_BL8 },
  75   { M32R_INSN_BL24, M32RXF_INSN_BL24, M32RXF_SFMT_BL24, NOPAR, NOPAR  },
  76   { M32R_INSN_BCL8, M32RXF_INSN_BCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BCL8, M32RXF_INSN_WRITE_BCL8 },
  77   { M32R_INSN_BCL24, M32RXF_INSN_BCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR  },
  78   { M32R_INSN_BNC8, M32RXF_INSN_BNC8, M32RXF_SFMT_BC8, M32RXF_INSN_PAR_BNC8, M32RXF_INSN_WRITE_BNC8 },
  79   { M32R_INSN_BNC24, M32RXF_INSN_BNC24, M32RXF_SFMT_BC24, NOPAR, NOPAR  },
  80   { M32R_INSN_BNE, M32RXF_INSN_BNE, M32RXF_SFMT_BEQ, NOPAR, NOPAR  },
  81   { M32R_INSN_BRA8, M32RXF_INSN_BRA8, M32RXF_SFMT_BRA8, M32RXF_INSN_PAR_BRA8, M32RXF_INSN_WRITE_BRA8 },
  82   { M32R_INSN_BRA24, M32RXF_INSN_BRA24, M32RXF_SFMT_BRA24, NOPAR, NOPAR  },
  83   { M32R_INSN_BNCL8, M32RXF_INSN_BNCL8, M32RXF_SFMT_BCL8, M32RXF_INSN_PAR_BNCL8, M32RXF_INSN_WRITE_BNCL8 },
  84   { M32R_INSN_BNCL24, M32RXF_INSN_BNCL24, M32RXF_SFMT_BCL24, NOPAR, NOPAR  },
  85   { M32R_INSN_CMP, M32RXF_INSN_CMP, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMP, M32RXF_INSN_WRITE_CMP },
  86   { M32R_INSN_CMPI, M32RXF_INSN_CMPI, M32RXF_SFMT_CMPI, NOPAR, NOPAR  },
  87   { M32R_INSN_CMPU, M32RXF_INSN_CMPU, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPU, M32RXF_INSN_WRITE_CMPU },
  88   { M32R_INSN_CMPUI, M32RXF_INSN_CMPUI, M32RXF_SFMT_CMPI, NOPAR, NOPAR  },
  89   { M32R_INSN_CMPEQ, M32RXF_INSN_CMPEQ, M32RXF_SFMT_CMP, M32RXF_INSN_PAR_CMPEQ, M32RXF_INSN_WRITE_CMPEQ },
  90   { M32R_INSN_CMPZ, M32RXF_INSN_CMPZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_CMPZ, M32RXF_INSN_WRITE_CMPZ },
  91   { M32R_INSN_DIV, M32RXF_INSN_DIV, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
  92   { M32R_INSN_DIVU, M32RXF_INSN_DIVU, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
  93   { M32R_INSN_REM, M32RXF_INSN_REM, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
  94   { M32R_INSN_REMU, M32RXF_INSN_REMU, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
  95   { M32R_INSN_DIVH, M32RXF_INSN_DIVH, M32RXF_SFMT_DIV, NOPAR, NOPAR  },
  96   { M32R_INSN_JC, M32RXF_INSN_JC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JC, M32RXF_INSN_WRITE_JC },
  97   { M32R_INSN_JNC, M32RXF_INSN_JNC, M32RXF_SFMT_JC, M32RXF_INSN_PAR_JNC, M32RXF_INSN_WRITE_JNC },
  98   { M32R_INSN_JL, M32RXF_INSN_JL, M32RXF_SFMT_JL, M32RXF_INSN_PAR_JL, M32RXF_INSN_WRITE_JL },
  99   { M32R_INSN_JMP, M32RXF_INSN_JMP, M32RXF_SFMT_JMP, M32RXF_INSN_PAR_JMP, M32RXF_INSN_WRITE_JMP },
 100   { M32R_INSN_LD, M32RXF_INSN_LD, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LD, M32RXF_INSN_WRITE_LD },
 101   { M32R_INSN_LD_D, M32RXF_INSN_LD_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
 102   { M32R_INSN_LDB, M32RXF_INSN_LDB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDB, M32RXF_INSN_WRITE_LDB },
 103   { M32R_INSN_LDB_D, M32RXF_INSN_LDB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
 104   { M32R_INSN_LDH, M32RXF_INSN_LDH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDH, M32RXF_INSN_WRITE_LDH },
 105   { M32R_INSN_LDH_D, M32RXF_INSN_LDH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
 106   { M32R_INSN_LDUB, M32RXF_INSN_LDUB, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUB, M32RXF_INSN_WRITE_LDUB },
 107   { M32R_INSN_LDUB_D, M32RXF_INSN_LDUB_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
 108   { M32R_INSN_LDUH, M32RXF_INSN_LDUH, M32RXF_SFMT_LD, M32RXF_INSN_PAR_LDUH, M32RXF_INSN_WRITE_LDUH },
 109   { M32R_INSN_LDUH_D, M32RXF_INSN_LDUH_D, M32RXF_SFMT_LD_D, NOPAR, NOPAR  },
 110   { M32R_INSN_LD_PLUS, M32RXF_INSN_LD_PLUS, M32RXF_SFMT_LD_PLUS, M32RXF_INSN_PAR_LD_PLUS, M32RXF_INSN_WRITE_LD_PLUS },
 111   { M32R_INSN_LD24, M32RXF_INSN_LD24, M32RXF_SFMT_LD24, NOPAR, NOPAR  },
 112   { M32R_INSN_LDI8, M32RXF_INSN_LDI8, M32RXF_SFMT_LDI8, M32RXF_INSN_PAR_LDI8, M32RXF_INSN_WRITE_LDI8 },
 113   { M32R_INSN_LDI16, M32RXF_INSN_LDI16, M32RXF_SFMT_LDI16, NOPAR, NOPAR  },
 114   { M32R_INSN_LOCK, M32RXF_INSN_LOCK, M32RXF_SFMT_LOCK, M32RXF_INSN_PAR_LOCK, M32RXF_INSN_WRITE_LOCK },
 115   { M32R_INSN_MACHI_A, M32RXF_INSN_MACHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACHI_A, M32RXF_INSN_WRITE_MACHI_A },
 116   { M32R_INSN_MACLO_A, M32RXF_INSN_MACLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACLO_A, M32RXF_INSN_WRITE_MACLO_A },
 117   { M32R_INSN_MACWHI_A, M32RXF_INSN_MACWHI_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWHI_A, M32RXF_INSN_WRITE_MACWHI_A },
 118   { M32R_INSN_MACWLO_A, M32RXF_INSN_MACWLO_A, M32RXF_SFMT_MACHI_A, M32RXF_INSN_PAR_MACWLO_A, M32RXF_INSN_WRITE_MACWLO_A },
 119   { M32R_INSN_MUL, M32RXF_INSN_MUL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_MUL, M32RXF_INSN_WRITE_MUL },
 120   { M32R_INSN_MULHI_A, M32RXF_INSN_MULHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULHI_A, M32RXF_INSN_WRITE_MULHI_A },
 121   { M32R_INSN_MULLO_A, M32RXF_INSN_MULLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULLO_A, M32RXF_INSN_WRITE_MULLO_A },
 122   { M32R_INSN_MULWHI_A, M32RXF_INSN_MULWHI_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWHI_A, M32RXF_INSN_WRITE_MULWHI_A },
 123   { M32R_INSN_MULWLO_A, M32RXF_INSN_MULWLO_A, M32RXF_SFMT_MULHI_A, M32RXF_INSN_PAR_MULWLO_A, M32RXF_INSN_WRITE_MULWLO_A },
 124   { M32R_INSN_MV, M32RXF_INSN_MV, M32RXF_SFMT_MV, M32RXF_INSN_PAR_MV, M32RXF_INSN_WRITE_MV },
 125   { M32R_INSN_MVFACHI_A, M32RXF_INSN_MVFACHI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACHI_A, M32RXF_INSN_WRITE_MVFACHI_A },
 126   { M32R_INSN_MVFACLO_A, M32RXF_INSN_MVFACLO_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACLO_A, M32RXF_INSN_WRITE_MVFACLO_A },
 127   { M32R_INSN_MVFACMI_A, M32RXF_INSN_MVFACMI_A, M32RXF_SFMT_MVFACHI_A, M32RXF_INSN_PAR_MVFACMI_A, M32RXF_INSN_WRITE_MVFACMI_A },
 128   { M32R_INSN_MVFC, M32RXF_INSN_MVFC, M32RXF_SFMT_MVFC, M32RXF_INSN_PAR_MVFC, M32RXF_INSN_WRITE_MVFC },
 129   { M32R_INSN_MVTACHI_A, M32RXF_INSN_MVTACHI_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACHI_A, M32RXF_INSN_WRITE_MVTACHI_A },
 130   { M32R_INSN_MVTACLO_A, M32RXF_INSN_MVTACLO_A, M32RXF_SFMT_MVTACHI_A, M32RXF_INSN_PAR_MVTACLO_A, M32RXF_INSN_WRITE_MVTACLO_A },
 131   { M32R_INSN_MVTC, M32RXF_INSN_MVTC, M32RXF_SFMT_MVTC, M32RXF_INSN_PAR_MVTC, M32RXF_INSN_WRITE_MVTC },
 132   { M32R_INSN_NEG, M32RXF_INSN_NEG, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NEG, M32RXF_INSN_WRITE_NEG },
 133   { M32R_INSN_NOP, M32RXF_INSN_NOP, M32RXF_SFMT_NOP, M32RXF_INSN_PAR_NOP, M32RXF_INSN_WRITE_NOP },
 134   { M32R_INSN_NOT, M32RXF_INSN_NOT, M32RXF_SFMT_MV, M32RXF_INSN_PAR_NOT, M32RXF_INSN_WRITE_NOT },
 135   { M32R_INSN_RAC_DSI, M32RXF_INSN_RAC_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RAC_DSI, M32RXF_INSN_WRITE_RAC_DSI },
 136   { M32R_INSN_RACH_DSI, M32RXF_INSN_RACH_DSI, M32RXF_SFMT_RAC_DSI, M32RXF_INSN_PAR_RACH_DSI, M32RXF_INSN_WRITE_RACH_DSI },
 137   { M32R_INSN_RTE, M32RXF_INSN_RTE, M32RXF_SFMT_RTE, M32RXF_INSN_PAR_RTE, M32RXF_INSN_WRITE_RTE },
 138   { M32R_INSN_SETH, M32RXF_INSN_SETH, M32RXF_SFMT_SETH, NOPAR, NOPAR  },
 139   { M32R_INSN_SLL, M32RXF_INSN_SLL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SLL, M32RXF_INSN_WRITE_SLL },
 140   { M32R_INSN_SLL3, M32RXF_INSN_SLL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR  },
 141   { M32R_INSN_SLLI, M32RXF_INSN_SLLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SLLI, M32RXF_INSN_WRITE_SLLI },
 142   { M32R_INSN_SRA, M32RXF_INSN_SRA, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRA, M32RXF_INSN_WRITE_SRA },
 143   { M32R_INSN_SRA3, M32RXF_INSN_SRA3, M32RXF_SFMT_SLL3, NOPAR, NOPAR  },
 144   { M32R_INSN_SRAI, M32RXF_INSN_SRAI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRAI, M32RXF_INSN_WRITE_SRAI },
 145   { M32R_INSN_SRL, M32RXF_INSN_SRL, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SRL, M32RXF_INSN_WRITE_SRL },
 146   { M32R_INSN_SRL3, M32RXF_INSN_SRL3, M32RXF_SFMT_SLL3, NOPAR, NOPAR  },
 147   { M32R_INSN_SRLI, M32RXF_INSN_SRLI, M32RXF_SFMT_SLLI, M32RXF_INSN_PAR_SRLI, M32RXF_INSN_WRITE_SRLI },
 148   { M32R_INSN_ST, M32RXF_INSN_ST, M32RXF_SFMT_ST, M32RXF_INSN_PAR_ST, M32RXF_INSN_WRITE_ST },
 149   { M32R_INSN_ST_D, M32RXF_INSN_ST_D, M32RXF_SFMT_ST_D, NOPAR, NOPAR  },
 150   { M32R_INSN_STB, M32RXF_INSN_STB, M32RXF_SFMT_STB, M32RXF_INSN_PAR_STB, M32RXF_INSN_WRITE_STB },
 151   { M32R_INSN_STB_D, M32RXF_INSN_STB_D, M32RXF_SFMT_STB_D, NOPAR, NOPAR  },
 152   { M32R_INSN_STH, M32RXF_INSN_STH, M32RXF_SFMT_STH, M32RXF_INSN_PAR_STH, M32RXF_INSN_WRITE_STH },
 153   { M32R_INSN_STH_D, M32RXF_INSN_STH_D, M32RXF_SFMT_STH_D, NOPAR, NOPAR  },
 154   { M32R_INSN_ST_PLUS, M32RXF_INSN_ST_PLUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_PLUS, M32RXF_INSN_WRITE_ST_PLUS },
 155   { M32R_INSN_ST_MINUS, M32RXF_INSN_ST_MINUS, M32RXF_SFMT_ST_PLUS, M32RXF_INSN_PAR_ST_MINUS, M32RXF_INSN_WRITE_ST_MINUS },
 156   { M32R_INSN_SUB, M32RXF_INSN_SUB, M32RXF_SFMT_ADD, M32RXF_INSN_PAR_SUB, M32RXF_INSN_WRITE_SUB },
 157   { M32R_INSN_SUBV, M32RXF_INSN_SUBV, M32RXF_SFMT_ADDV, M32RXF_INSN_PAR_SUBV, M32RXF_INSN_WRITE_SUBV },
 158   { M32R_INSN_SUBX, M32RXF_INSN_SUBX, M32RXF_SFMT_ADDX, M32RXF_INSN_PAR_SUBX, M32RXF_INSN_WRITE_SUBX },
 159   { M32R_INSN_TRAP, M32RXF_INSN_TRAP, M32RXF_SFMT_TRAP, M32RXF_INSN_PAR_TRAP, M32RXF_INSN_WRITE_TRAP },
 160   { M32R_INSN_UNLOCK, M32RXF_INSN_UNLOCK, M32RXF_SFMT_UNLOCK, M32RXF_INSN_PAR_UNLOCK, M32RXF_INSN_WRITE_UNLOCK },
 161   { M32R_INSN_SATB, M32RXF_INSN_SATB, M32RXF_SFMT_SATB, NOPAR, NOPAR  },
 162   { M32R_INSN_SATH, M32RXF_INSN_SATH, M32RXF_SFMT_SATB, NOPAR, NOPAR  },
 163   { M32R_INSN_SAT, M32RXF_INSN_SAT, M32RXF_SFMT_SAT, NOPAR, NOPAR  },
 164   { M32R_INSN_PCMPBZ, M32RXF_INSN_PCMPBZ, M32RXF_SFMT_CMPZ, M32RXF_INSN_PAR_PCMPBZ, M32RXF_INSN_WRITE_PCMPBZ },
 165   { M32R_INSN_SADD, M32RXF_INSN_SADD, M32RXF_SFMT_SADD, M32RXF_INSN_PAR_SADD, M32RXF_INSN_WRITE_SADD },
 166   { M32R_INSN_MACWU1, M32RXF_INSN_MACWU1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACWU1, M32RXF_INSN_WRITE_MACWU1 },
 167   { M32R_INSN_MSBLO, M32RXF_INSN_MSBLO, M32RXF_SFMT_MSBLO, M32RXF_INSN_PAR_MSBLO, M32RXF_INSN_WRITE_MSBLO },
 168   { M32R_INSN_MULWU1, M32RXF_INSN_MULWU1, M32RXF_SFMT_MULWU1, M32RXF_INSN_PAR_MULWU1, M32RXF_INSN_WRITE_MULWU1 },
 169   { M32R_INSN_MACLH1, M32RXF_INSN_MACLH1, M32RXF_SFMT_MACWU1, M32RXF_INSN_PAR_MACLH1, M32RXF_INSN_WRITE_MACLH1 },
 170   { M32R_INSN_SC, M32RXF_INSN_SC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SC, M32RXF_INSN_WRITE_SC },
 171   { M32R_INSN_SNC, M32RXF_INSN_SNC, M32RXF_SFMT_SC, M32RXF_INSN_PAR_SNC, M32RXF_INSN_WRITE_SNC },
 172 };
 173
 174 static const struct insn_sem m32rxf_insn_sem_invalid = {
 175   VIRTUAL_INSN_X_INVALID, M32RXF_INSN_X_INVALID, M32RXF_SFMT_EMPTY, NOPAR, NOPAR
 176 };
 177
 178 /* Initialize an IDESC from the compile-time computable parts.  */
 179
 180 static INLINE void
 181 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
 182 {
 183   const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
 184
 185   id->num = t->index;
 186   id->sfmt = t->sfmt;
 187   if ((int) t->type <= 0)
 188     id->idata = & cgen_virtual_insn_table[- (int) t->type];
 189   else
 190     id->idata = & insn_table[t->type];
 191   id->attrs = CGEN_INSN_ATTRS (id->idata);
 192   /* Oh my god, a magic number.  */
 193   id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
 194
 195 #if WITH_PROFILE_MODEL_P
 196   id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
 197   {
 198     SIM_DESC sd = CPU_STATE (cpu);
 199     SIM_ASSERT (t->index == id->timing->num);
 200   }
 201 #endif
 202
 203   /* Semantic pointers are initialized elsewhere.  */
 204 }
 205
 206 /* Initialize the instruction descriptor table.  */
 207
 208 void
 209 m32rxf_init_idesc_table (SIM_CPU *cpu)
 210 {
 211   IDESC *id,*tabend;
 212   const struct insn_sem *t,*tend;
 213   int tabsize = M32RXF_INSN_MAX;
 214   IDESC *table = m32rxf_insn_data;
 215
 216   memset (table, 0, tabsize * sizeof (IDESC));
 217
 218   /* First set all entries to the `invalid insn'.  */
 219   t = & m32rxf_insn_sem_invalid;
 220   for (id = table, tabend = table + tabsize; id < tabend; ++id)
 221     init_idesc (cpu, id, t);
 222
 223   /* Now fill in the values for the chosen cpu.  */
 224   for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
 225        t != tend; ++t)
 226     {
 227       init_idesc (cpu, & table[t->index], t);
 228       if (t->par_index != NOPAR)
 229         {
 230           init_idesc (cpu, &table[t->par_index], t);
 231           table[t->index].par_idesc = &table[t->par_index];
 232         }
 233       if (t->par_index != NOPAR)
 234         {
 235           init_idesc (cpu, &table[t->write_index], t);
 236           table[t->par_index].par_idesc = &table[t->write_index];
 237         }
 238     }
 239
 240   /* Link the IDESC table into the cpu.  */
 241   CPU_IDESC (cpu) = table;
 242 }
 243
 244 /* Given an instruction, return a pointer to its IDESC entry.  */
 245
 246 const IDESC *
 247 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
 248               CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
 249               ARGBUF *abuf)
 250 {
 251   /* Result of decoder.  */
 252   M32RXF_INSN_TYPE itype;
 253
 254   {
 255     CGEN_INSN_INT insn = base_insn;
 256
 257     {
 258       unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
 259       switch (val)
 260       {
 261       case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv;
 262       case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx;
 263       case 2 : itype = M32RXF_INSN_SUB; goto extract_sfmt_add;
 264       case 3 : itype = M32RXF_INSN_NEG; goto extract_sfmt_mv;
 265       case 4 : itype = M32RXF_INSN_CMP; goto extract_sfmt_cmp;
 266       case 5 : itype = M32RXF_INSN_CMPU; goto extract_sfmt_cmp;
 267       case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp;
 268       case 7 :
 269         {
 270           unsigned int val = (((insn >> 8) & (15 << 0)));
 271           switch (val)
 272           {
 273           case 0 : itype = M32RXF_INSN_CMPZ; goto extract_sfmt_cmpz;
 274           case 3 : itype = M32RXF_INSN_PCMPBZ; goto extract_sfmt_cmpz;
 275           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 276           }
 277         }
 278       case 8 : itype = M32RXF_INSN_ADDV; goto extract_sfmt_addv;
 279       case 9 : itype = M32RXF_INSN_ADDX; goto extract_sfmt_addx;
 280       case 10 : itype = M32RXF_INSN_ADD; goto extract_sfmt_add;
 281       case 11 : itype = M32RXF_INSN_NOT; goto extract_sfmt_mv;
 282       case 12 : itype = M32RXF_INSN_AND; goto extract_sfmt_add;
 283       case 13 : itype = M32RXF_INSN_XOR; goto extract_sfmt_add;
 284       case 14 : itype = M32RXF_INSN_OR; goto extract_sfmt_add;
 285       case 16 : itype = M32RXF_INSN_SRL; goto extract_sfmt_add;
 286       case 18 : itype = M32RXF_INSN_SRA; goto extract_sfmt_add;
 287       case 20 : itype = M32RXF_INSN_SLL; goto extract_sfmt_add;
 288       case 22 : itype = M32RXF_INSN_MUL; goto extract_sfmt_add;
 289       case 24 : itype = M32RXF_INSN_MV; goto extract_sfmt_mv;
 290       case 25 : itype = M32RXF_INSN_MVFC; goto extract_sfmt_mvfc;
 291       case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc;
 292       case 28 :
 293         {
 294           unsigned int val = (((insn >> 8) & (15 << 0)));
 295           switch (val)
 296           {
 297           case 12 : itype = M32RXF_INSN_JC; goto extract_sfmt_jc;
 298           case 13 : itype = M32RXF_INSN_JNC; goto extract_sfmt_jc;
 299           case 14 : itype = M32RXF_INSN_JL; goto extract_sfmt_jl;
 300           case 15 : itype = M32RXF_INSN_JMP; goto extract_sfmt_jmp;
 301           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 302           }
 303         }
 304       case 29 : itype = M32RXF_INSN_RTE; goto extract_sfmt_rte;
 305       case 31 : itype = M32RXF_INSN_TRAP; goto extract_sfmt_trap;
 306       case 32 : itype = M32RXF_INSN_STB; goto extract_sfmt_stb;
 307       case 34 : itype = M32RXF_INSN_STH; goto extract_sfmt_sth;
 308       case 36 : itype = M32RXF_INSN_ST; goto extract_sfmt_st;
 309       case 37 : itype = M32RXF_INSN_UNLOCK; goto extract_sfmt_unlock;
 310       case 38 : itype = M32RXF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
 311       case 39 : itype = M32RXF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
 312       case 40 : itype = M32RXF_INSN_LDB; goto extract_sfmt_ld;
 313       case 41 : itype = M32RXF_INSN_LDUB; goto extract_sfmt_ld;
 314       case 42 : itype = M32RXF_INSN_LDH; goto extract_sfmt_ld;
 315       case 43 : itype = M32RXF_INSN_LDUH; goto extract_sfmt_ld;
 316       case 44 : itype = M32RXF_INSN_LD; goto extract_sfmt_ld;
 317       case 45 : itype = M32RXF_INSN_LOCK; goto extract_sfmt_lock;
 318       case 46 : itype = M32RXF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
 319       case 48 : /* fall through */
 320       case 56 : itype = M32RXF_INSN_MULHI_A; goto extract_sfmt_mulhi_a;
 321       case 49 : /* fall through */
 322       case 57 : itype = M32RXF_INSN_MULLO_A; goto extract_sfmt_mulhi_a;
 323       case 50 : /* fall through */
 324       case 58 : itype = M32RXF_INSN_MULWHI_A; goto extract_sfmt_mulhi_a;
 325       case 51 : /* fall through */
 326       case 59 : itype = M32RXF_INSN_MULWLO_A; goto extract_sfmt_mulhi_a;
 327       case 52 : /* fall through */
 328       case 60 : itype = M32RXF_INSN_MACHI_A; goto extract_sfmt_machi_a;
 329       case 53 : /* fall through */
 330       case 61 : itype = M32RXF_INSN_MACLO_A; goto extract_sfmt_machi_a;
 331       case 54 : /* fall through */
 332       case 62 : itype = M32RXF_INSN_MACWHI_A; goto extract_sfmt_machi_a;
 333       case 55 : /* fall through */
 334       case 63 : itype = M32RXF_INSN_MACWLO_A; goto extract_sfmt_machi_a;
 335       case 64 : /* fall through */
 336       case 65 : /* fall through */
 337       case 66 : /* fall through */
 338       case 67 : /* fall through */
 339       case 68 : /* fall through */
 340       case 69 : /* fall through */
 341       case 70 : /* fall through */
 342       case 71 : /* fall through */
 343       case 72 : /* fall through */
 344       case 73 : /* fall through */
 345       case 74 : /* fall through */
 346       case 75 : /* fall through */
 347       case 76 : /* fall through */
 348       case 77 : /* fall through */
 349       case 78 : /* fall through */
 350       case 79 : itype = M32RXF_INSN_ADDI; goto extract_sfmt_addi;
 351       case 80 : /* fall through */
 352       case 81 : itype = M32RXF_INSN_SRLI; goto extract_sfmt_slli;
 353       case 82 : /* fall through */
 354       case 83 : itype = M32RXF_INSN_SRAI; goto extract_sfmt_slli;
 355       case 84 : /* fall through */
 356       case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli;
 357       case 87 :
 358         {
 359           unsigned int val = (((insn >> 0) & (3 << 0)));
 360           switch (val)
 361           {
 362           case 0 : itype = M32RXF_INSN_MVTACHI_A; goto extract_sfmt_mvtachi_a;
 363           case 1 : itype = M32RXF_INSN_MVTACLO_A; goto extract_sfmt_mvtachi_a;
 364           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 365           }
 366         }
 367       case 88 : itype = M32RXF_INSN_RACH_DSI; goto extract_sfmt_rac_dsi;
 368       case 89 : itype = M32RXF_INSN_RAC_DSI; goto extract_sfmt_rac_dsi;
 369       case 90 : itype = M32RXF_INSN_MULWU1; goto extract_sfmt_mulwu1;
 370       case 91 : itype = M32RXF_INSN_MACWU1; goto extract_sfmt_macwu1;
 371       case 92 : itype = M32RXF_INSN_MACLH1; goto extract_sfmt_macwu1;
 372       case 93 : itype = M32RXF_INSN_MSBLO; goto extract_sfmt_msblo;
 373       case 94 : itype = M32RXF_INSN_SADD; goto extract_sfmt_sadd;
 374       case 95 :
 375         {
 376           unsigned int val = (((insn >> 0) & (3 << 0)));
 377           switch (val)
 378           {
 379           case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
 380           case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
 381           case 2 : itype = M32RXF_INSN_MVFACMI_A; goto extract_sfmt_mvfachi_a;
 382           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 383           }
 384         }
 385       case 96 : /* fall through */
 386       case 97 : /* fall through */
 387       case 98 : /* fall through */
 388       case 99 : /* fall through */
 389       case 100 : /* fall through */
 390       case 101 : /* fall through */
 391       case 102 : /* fall through */
 392       case 103 : /* fall through */
 393       case 104 : /* fall through */
 394       case 105 : /* fall through */
 395       case 106 : /* fall through */
 396       case 107 : /* fall through */
 397       case 108 : /* fall through */
 398       case 109 : /* fall through */
 399       case 110 : /* fall through */
 400       case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8;
 401       case 112 :
 402         {
 403           unsigned int val = (((insn >> 8) & (15 << 0)));
 404           switch (val)
 405           {
 406           case 0 : itype = M32RXF_INSN_NOP; goto extract_sfmt_nop;
 407           case 4 : itype = M32RXF_INSN_SC; goto extract_sfmt_sc;
 408           case 5 : itype = M32RXF_INSN_SNC; goto extract_sfmt_sc;
 409           case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
 410           case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
 411           case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
 412           case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
 413           case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
 414           case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
 415           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 416           }
 417         }
 418       case 113 : /* fall through */
 419       case 114 : /* fall through */
 420       case 115 : /* fall through */
 421       case 116 : /* fall through */
 422       case 117 : /* fall through */
 423       case 118 : /* fall through */
 424       case 119 : /* fall through */
 425       case 120 : /* fall through */
 426       case 121 : /* fall through */
 427       case 122 : /* fall through */
 428       case 123 : /* fall through */
 429       case 124 : /* fall through */
 430       case 125 : /* fall through */
 431       case 126 : /* fall through */
 432       case 127 :
 433         {
 434           unsigned int val = (((insn >> 8) & (15 << 0)));
 435           switch (val)
 436           {
 437           case 8 : itype = M32RXF_INSN_BCL8; goto extract_sfmt_bcl8;
 438           case 9 : itype = M32RXF_INSN_BNCL8; goto extract_sfmt_bcl8;
 439           case 12 : itype = M32RXF_INSN_BC8; goto extract_sfmt_bc8;
 440           case 13 : itype = M32RXF_INSN_BNC8; goto extract_sfmt_bc8;
 441           case 14 : itype = M32RXF_INSN_BL8; goto extract_sfmt_bl8;
 442           case 15 : itype = M32RXF_INSN_BRA8; goto extract_sfmt_bra8;
 443           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 444           }
 445         }
 446       case 132 : itype = M32RXF_INSN_CMPI; goto extract_sfmt_cmpi;
 447       case 133 : itype = M32RXF_INSN_CMPUI; goto extract_sfmt_cmpi;
 448       case 134 :
 449         {
 450           unsigned int val;
 451           /* Must fetch more bits.  */
 452           insn = GETIMEMUHI (current_cpu, pc + 2);
 453           val = (((insn >> 12) & (15 << 0)));
 454           switch (val)
 455           {
 456           case 0 :
 457             {
 458               unsigned int val = (((insn >> 8) & (15 << 0)));
 459               switch (val)
 460               {
 461               case 0 : itype = M32RXF_INSN_SAT; goto extract_sfmt_sat;
 462               case 2 : itype = M32RXF_INSN_SATH; goto extract_sfmt_satb;
 463               case 3 : itype = M32RXF_INSN_SATB; goto extract_sfmt_satb;
 464               default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 465               }
 466             }
 467           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 468           }
 469         }
 470       case 136 : itype = M32RXF_INSN_ADDV3; goto extract_sfmt_addv3;
 471       case 138 : itype = M32RXF_INSN_ADD3; goto extract_sfmt_add3;
 472       case 140 : itype = M32RXF_INSN_AND3; goto extract_sfmt_and3;
 473       case 141 : itype = M32RXF_INSN_XOR3; goto extract_sfmt_and3;
 474       case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
 475       case 144 :
 476         {
 477           unsigned int val;
 478           /* Must fetch more bits.  */
 479           insn = GETIMEMUHI (current_cpu, pc + 2);
 480           val = (((insn >> 12) & (15 << 0)));
 481           switch (val)
 482           {
 483           case 0 :
 484             {
 485               unsigned int val = (((insn >> 8) & (15 << 0)));
 486               switch (val)
 487               {
 488               case 0 :
 489                 {
 490                   unsigned int val = (((insn >> 4) & (15 << 0)));
 491                   switch (val)
 492                   {
 493                   case 0 : itype = M32RXF_INSN_DIV; goto extract_sfmt_div;
 494                   case 1 : itype = M32RXF_INSN_DIVH; goto extract_sfmt_div;
 495                   default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 496                   }
 497                 }
 498               default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 499               }
 500             }
 501           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 502           }
 503         }
 504       case 145 : itype = M32RXF_INSN_DIVU; goto extract_sfmt_div;
 505       case 146 : itype = M32RXF_INSN_REM; goto extract_sfmt_div;
 506       case 147 : itype = M32RXF_INSN_REMU; goto extract_sfmt_div;
 507       case 152 : itype = M32RXF_INSN_SRL3; goto extract_sfmt_sll3;
 508       case 154 : itype = M32RXF_INSN_SRA3; goto extract_sfmt_sll3;
 509       case 156 : itype = M32RXF_INSN_SLL3; goto extract_sfmt_sll3;
 510       case 159 : itype = M32RXF_INSN_LDI16; goto extract_sfmt_ldi16;
 511       case 160 : itype = M32RXF_INSN_STB_D; goto extract_sfmt_stb_d;
 512       case 162 : itype = M32RXF_INSN_STH_D; goto extract_sfmt_sth_d;
 513       case 164 : itype = M32RXF_INSN_ST_D; goto extract_sfmt_st_d;
 514       case 168 : itype = M32RXF_INSN_LDB_D; goto extract_sfmt_ld_d;
 515       case 169 : itype = M32RXF_INSN_LDUB_D; goto extract_sfmt_ld_d;
 516       case 170 : itype = M32RXF_INSN_LDH_D; goto extract_sfmt_ld_d;
 517       case 171 : itype = M32RXF_INSN_LDUH_D; goto extract_sfmt_ld_d;
 518       case 172 : itype = M32RXF_INSN_LD_D; goto extract_sfmt_ld_d;
 519       case 176 : itype = M32RXF_INSN_BEQ; goto extract_sfmt_beq;
 520       case 177 : itype = M32RXF_INSN_BNE; goto extract_sfmt_beq;
 521       case 184 : itype = M32RXF_INSN_BEQZ; goto extract_sfmt_beqz;
 522       case 185 : itype = M32RXF_INSN_BNEZ; goto extract_sfmt_beqz;
 523       case 186 : itype = M32RXF_INSN_BLTZ; goto extract_sfmt_beqz;
 524       case 187 : itype = M32RXF_INSN_BGEZ; goto extract_sfmt_beqz;
 525       case 188 : itype = M32RXF_INSN_BLEZ; goto extract_sfmt_beqz;
 526       case 189 : itype = M32RXF_INSN_BGTZ; goto extract_sfmt_beqz;
 527       case 220 : itype = M32RXF_INSN_SETH; goto extract_sfmt_seth;
 528       case 224 : /* fall through */
 529       case 225 : /* fall through */
 530       case 226 : /* fall through */
 531       case 227 : /* fall through */
 532       case 228 : /* fall through */
 533       case 229 : /* fall through */
 534       case 230 : /* fall through */
 535       case 231 : /* fall through */
 536       case 232 : /* fall through */
 537       case 233 : /* fall through */
 538       case 234 : /* fall through */
 539       case 235 : /* fall through */
 540       case 236 : /* fall through */
 541       case 237 : /* fall through */
 542       case 238 : /* fall through */
 543       case 239 : itype = M32RXF_INSN_LD24; goto extract_sfmt_ld24;
 544       case 240 : /* fall through */
 545       case 241 : /* fall through */
 546       case 242 : /* fall through */
 547       case 243 : /* fall through */
 548       case 244 : /* fall through */
 549       case 245 : /* fall through */
 550       case 246 : /* fall through */
 551       case 247 : /* fall through */
 552       case 248 : /* fall through */
 553       case 249 : /* fall through */
 554       case 250 : /* fall through */
 555       case 251 : /* fall through */
 556       case 252 : /* fall through */
 557       case 253 : /* fall through */
 558       case 254 : /* fall through */
 559       case 255 :
 560         {
 561           unsigned int val = (((insn >> 8) & (15 << 0)));
 562           switch (val)
 563           {
 564           case 8 : itype = M32RXF_INSN_BCL24; goto extract_sfmt_bcl24;
 565           case 9 : itype = M32RXF_INSN_BNCL24; goto extract_sfmt_bcl24;
 566           case 12 : itype = M32RXF_INSN_BC24; goto extract_sfmt_bc24;
 567           case 13 : itype = M32RXF_INSN_BNC24; goto extract_sfmt_bc24;
 568           case 14 : itype = M32RXF_INSN_BL24; goto extract_sfmt_bl24;
 569           case 15 : itype = M32RXF_INSN_BRA24; goto extract_sfmt_bra24;
 570           default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 571           }
 572         }
 573       default : itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
 574       }
 575     }
 576   }
 577
 578   /* The instruction has been decoded, now extract the fields.  */
 579
 580  extract_sfmt_empty:
 581   {
 582     const IDESC *idesc = &m32rxf_insn_data[itype];
 583     CGEN_INSN_INT insn = entire_insn;
 584 #define FLD(f) abuf->fields.fmt_empty.f
 585
 586
 587   /* Record the fields for the semantic handler.  */
 588   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
 589
 590 #undef FLD
 591     return idesc;
 592   }
 593
 594  extract_sfmt_add:
 595   {
 596     const IDESC *idesc = &m32rxf_insn_data[itype];
 597     CGEN_INSN_INT insn = entire_insn;
 598 #define FLD(f) abuf->fields.sfmt_add.f
 599     UINT f_r1;
 600     UINT f_r2;
 601
 602     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 603     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 604
 605   /* Record the fields for the semantic handler.  */
 606   FLD (i_dr) = & CPU (h_gr)[f_r1];
 607   FLD (i_sr) = & CPU (h_gr)[f_r2];
 608   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 609
 610 #if WITH_PROFILE_MODEL_P
 611   /* Record the fields for profiling.  */
 612   if (PROFILE_MODEL_P (current_cpu))
 613     {
 614       FLD (in_dr) = f_r1;
 615       FLD (in_sr) = f_r2;
 616       FLD (out_dr) = f_r1;
 617     }
 618 #endif
 619 #undef FLD
 620     return idesc;
 621   }
 622
 623  extract_sfmt_add3:
 624   {
 625     const IDESC *idesc = &m32rxf_insn_data[itype];
 626     CGEN_INSN_INT insn = entire_insn;
 627 #define FLD(f) abuf->fields.sfmt_add3.f
 628     UINT f_r1;
 629     UINT f_r2;
 630     INT f_simm16;
 631
 632     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 633     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 634     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 635
 636   /* Record the fields for the semantic handler.  */
 637   FLD (f_simm16) = f_simm16;
 638   FLD (i_sr) = & CPU (h_gr)[f_r2];
 639   FLD (i_dr) = & CPU (h_gr)[f_r1];
 640   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 641
 642 #if WITH_PROFILE_MODEL_P
 643   /* Record the fields for profiling.  */
 644   if (PROFILE_MODEL_P (current_cpu))
 645     {
 646       FLD (in_sr) = f_r2;
 647       FLD (out_dr) = f_r1;
 648     }
 649 #endif
 650 #undef FLD
 651     return idesc;
 652   }
 653
 654  extract_sfmt_and3:
 655   {
 656     const IDESC *idesc = &m32rxf_insn_data[itype];
 657     CGEN_INSN_INT insn = entire_insn;
 658 #define FLD(f) abuf->fields.sfmt_and3.f
 659     UINT f_r1;
 660     UINT f_r2;
 661     UINT f_uimm16;
 662
 663     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 664     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 665     f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
 666
 667   /* Record the fields for the semantic handler.  */
 668   FLD (f_uimm16) = f_uimm16;
 669   FLD (i_sr) = & CPU (h_gr)[f_r2];
 670   FLD (i_dr) = & CPU (h_gr)[f_r1];
 671   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 672
 673 #if WITH_PROFILE_MODEL_P
 674   /* Record the fields for profiling.  */
 675   if (PROFILE_MODEL_P (current_cpu))
 676     {
 677       FLD (in_sr) = f_r2;
 678       FLD (out_dr) = f_r1;
 679     }
 680 #endif
 681 #undef FLD
 682     return idesc;
 683   }
 684
 685  extract_sfmt_or3:
 686   {
 687     const IDESC *idesc = &m32rxf_insn_data[itype];
 688     CGEN_INSN_INT insn = entire_insn;
 689 #define FLD(f) abuf->fields.sfmt_and3.f
 690     UINT f_r1;
 691     UINT f_r2;
 692     UINT f_uimm16;
 693
 694     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 695     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 696     f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
 697
 698   /* Record the fields for the semantic handler.  */
 699   FLD (f_uimm16) = f_uimm16;
 700   FLD (i_sr) = & CPU (h_gr)[f_r2];
 701   FLD (i_dr) = & CPU (h_gr)[f_r1];
 702   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 703
 704 #if WITH_PROFILE_MODEL_P
 705   /* Record the fields for profiling.  */
 706   if (PROFILE_MODEL_P (current_cpu))
 707     {
 708       FLD (in_sr) = f_r2;
 709       FLD (out_dr) = f_r1;
 710     }
 711 #endif
 712 #undef FLD
 713     return idesc;
 714   }
 715
 716  extract_sfmt_addi:
 717   {
 718     const IDESC *idesc = &m32rxf_insn_data[itype];
 719     CGEN_INSN_INT insn = entire_insn;
 720 #define FLD(f) abuf->fields.sfmt_addi.f
 721     UINT f_r1;
 722     INT f_simm8;
 723
 724     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 725     f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
 726
 727   /* Record the fields for the semantic handler.  */
 728   FLD (f_simm8) = f_simm8;
 729   FLD (i_dr) = & CPU (h_gr)[f_r1];
 730   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
 731
 732 #if WITH_PROFILE_MODEL_P
 733   /* Record the fields for profiling.  */
 734   if (PROFILE_MODEL_P (current_cpu))
 735     {
 736       FLD (in_dr) = f_r1;
 737       FLD (out_dr) = f_r1;
 738     }
 739 #endif
 740 #undef FLD
 741     return idesc;
 742   }
 743
 744  extract_sfmt_addv:
 745   {
 746     const IDESC *idesc = &m32rxf_insn_data[itype];
 747     CGEN_INSN_INT insn = entire_insn;
 748 #define FLD(f) abuf->fields.sfmt_add.f
 749     UINT f_r1;
 750     UINT f_r2;
 751
 752     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 753     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 754
 755   /* Record the fields for the semantic handler.  */
 756   FLD (i_dr) = & CPU (h_gr)[f_r1];
 757   FLD (i_sr) = & CPU (h_gr)[f_r2];
 758   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 759
 760 #if WITH_PROFILE_MODEL_P
 761   /* Record the fields for profiling.  */
 762   if (PROFILE_MODEL_P (current_cpu))
 763     {
 764       FLD (in_dr) = f_r1;
 765       FLD (in_sr) = f_r2;
 766       FLD (out_dr) = f_r1;
 767     }
 768 #endif
 769 #undef FLD
 770     return idesc;
 771   }
 772
 773  extract_sfmt_addv3:
 774   {
 775     const IDESC *idesc = &m32rxf_insn_data[itype];
 776     CGEN_INSN_INT insn = entire_insn;
 777 #define FLD(f) abuf->fields.sfmt_add3.f
 778     UINT f_r1;
 779     UINT f_r2;
 780     INT f_simm16;
 781
 782     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 783     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 784     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
 785
 786   /* Record the fields for the semantic handler.  */
 787   FLD (f_simm16) = f_simm16;
 788   FLD (i_sr) = & CPU (h_gr)[f_r2];
 789   FLD (i_dr) = & CPU (h_gr)[f_r1];
 790   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 791
 792 #if WITH_PROFILE_MODEL_P
 793   /* Record the fields for profiling.  */
 794   if (PROFILE_MODEL_P (current_cpu))
 795     {
 796       FLD (in_sr) = f_r2;
 797       FLD (out_dr) = f_r1;
 798     }
 799 #endif
 800 #undef FLD
 801     return idesc;
 802   }
 803
 804  extract_sfmt_addx:
 805   {
 806     const IDESC *idesc = &m32rxf_insn_data[itype];
 807     CGEN_INSN_INT insn = entire_insn;
 808 #define FLD(f) abuf->fields.sfmt_add.f
 809     UINT f_r1;
 810     UINT f_r2;
 811
 812     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 813     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 814
 815   /* Record the fields for the semantic handler.  */
 816   FLD (i_dr) = & CPU (h_gr)[f_r1];
 817   FLD (i_sr) = & CPU (h_gr)[f_r2];
 818   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 819
 820 #if WITH_PROFILE_MODEL_P
 821   /* Record the fields for profiling.  */
 822   if (PROFILE_MODEL_P (current_cpu))
 823     {
 824       FLD (in_dr) = f_r1;
 825       FLD (in_sr) = f_r2;
 826       FLD (out_dr) = f_r1;
 827     }
 828 #endif
 829 #undef FLD
 830     return idesc;
 831   }
 832
 833  extract_sfmt_bc8:
 834   {
 835     const IDESC *idesc = &m32rxf_insn_data[itype];
 836     CGEN_INSN_INT insn = entire_insn;
 837 #define FLD(f) abuf->fields.sfmt_bl8.f
 838     SI f_disp8;
 839
 840     f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 841
 842   /* Record the fields for the semantic handler.  */
 843   FLD (i_disp8) = f_disp8;
 844   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 845
 846 #if WITH_PROFILE_MODEL_P
 847   /* Record the fields for profiling.  */
 848   if (PROFILE_MODEL_P (current_cpu))
 849     {
 850     }
 851 #endif
 852 #undef FLD
 853     return idesc;
 854   }
 855
 856  extract_sfmt_bc24:
 857   {
 858     const IDESC *idesc = &m32rxf_insn_data[itype];
 859     CGEN_INSN_INT insn = entire_insn;
 860 #define FLD(f) abuf->fields.sfmt_bl24.f
 861     SI f_disp24;
 862
 863     f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
 864
 865   /* Record the fields for the semantic handler.  */
 866   FLD (i_disp24) = f_disp24;
 867   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 868
 869 #if WITH_PROFILE_MODEL_P
 870   /* Record the fields for profiling.  */
 871   if (PROFILE_MODEL_P (current_cpu))
 872     {
 873     }
 874 #endif
 875 #undef FLD
 876     return idesc;
 877   }
 878
 879  extract_sfmt_beq:
 880   {
 881     const IDESC *idesc = &m32rxf_insn_data[itype];
 882     CGEN_INSN_INT insn = entire_insn;
 883 #define FLD(f) abuf->fields.sfmt_beq.f
 884     UINT f_r1;
 885     UINT f_r2;
 886     SI f_disp16;
 887
 888     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 889     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 890     f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
 891
 892   /* Record the fields for the semantic handler.  */
 893   FLD (i_disp16) = f_disp16;
 894   FLD (i_src1) = & CPU (h_gr)[f_r1];
 895   FLD (i_src2) = & CPU (h_gr)[f_r2];
 896   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 897
 898 #if WITH_PROFILE_MODEL_P
 899   /* Record the fields for profiling.  */
 900   if (PROFILE_MODEL_P (current_cpu))
 901     {
 902       FLD (in_src1) = f_r1;
 903       FLD (in_src2) = f_r2;
 904     }
 905 #endif
 906 #undef FLD
 907     return idesc;
 908   }
 909
 910  extract_sfmt_beqz:
 911   {
 912     const IDESC *idesc = &m32rxf_insn_data[itype];
 913     CGEN_INSN_INT insn = entire_insn;
 914 #define FLD(f) abuf->fields.sfmt_beq.f
 915     UINT f_r2;
 916     SI f_disp16;
 917
 918     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 919     f_disp16 = ((((EXTRACT_MSB0_INT (insn, 32, 16, 16)) << (2))) + (pc));
 920
 921   /* Record the fields for the semantic handler.  */
 922   FLD (i_disp16) = f_disp16;
 923   FLD (i_src2) = & CPU (h_gr)[f_r2];
 924   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
 925
 926 #if WITH_PROFILE_MODEL_P
 927   /* Record the fields for profiling.  */
 928   if (PROFILE_MODEL_P (current_cpu))
 929     {
 930       FLD (in_src2) = f_r2;
 931     }
 932 #endif
 933 #undef FLD
 934     return idesc;
 935   }
 936
 937  extract_sfmt_bl8:
 938   {
 939     const IDESC *idesc = &m32rxf_insn_data[itype];
 940     CGEN_INSN_INT insn = entire_insn;
 941 #define FLD(f) abuf->fields.sfmt_bl8.f
 942     SI f_disp8;
 943
 944     f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 945
 946   /* Record the fields for the semantic handler.  */
 947   FLD (i_disp8) = f_disp8;
 948   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 949
 950 #if WITH_PROFILE_MODEL_P
 951   /* Record the fields for profiling.  */
 952   if (PROFILE_MODEL_P (current_cpu))
 953     {
 954       FLD (out_h_gr_14) = 14;
 955     }
 956 #endif
 957 #undef FLD
 958     return idesc;
 959   }
 960
 961  extract_sfmt_bl24:
 962   {
 963     const IDESC *idesc = &m32rxf_insn_data[itype];
 964     CGEN_INSN_INT insn = entire_insn;
 965 #define FLD(f) abuf->fields.sfmt_bl24.f
 966     SI f_disp24;
 967
 968     f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
 969
 970   /* Record the fields for the semantic handler.  */
 971   FLD (i_disp24) = f_disp24;
 972   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 973
 974 #if WITH_PROFILE_MODEL_P
 975   /* Record the fields for profiling.  */
 976   if (PROFILE_MODEL_P (current_cpu))
 977     {
 978       FLD (out_h_gr_14) = 14;
 979     }
 980 #endif
 981 #undef FLD
 982     return idesc;
 983   }
 984
 985  extract_sfmt_bcl8:
 986   {
 987     const IDESC *idesc = &m32rxf_insn_data[itype];
 988     CGEN_INSN_INT insn = entire_insn;
 989 #define FLD(f) abuf->fields.sfmt_bl8.f
 990     SI f_disp8;
 991
 992     f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
 993
 994   /* Record the fields for the semantic handler.  */
 995   FLD (i_disp8) = f_disp8;
 996   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 997
 998 #if WITH_PROFILE_MODEL_P
 999   /* Record the fields for profiling.  */
1000   if (PROFILE_MODEL_P (current_cpu))
1001     {
1002       FLD (out_h_gr_14) = 14;
1003     }
1004 #endif
1005 #undef FLD
1006     return idesc;
1007   }
1008
1009  extract_sfmt_bcl24:
1010   {
1011     const IDESC *idesc = &m32rxf_insn_data[itype];
1012     CGEN_INSN_INT insn = entire_insn;
1013 #define FLD(f) abuf->fields.sfmt_bl24.f
1014     SI f_disp24;
1015
1016     f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1017
1018   /* Record the fields for the semantic handler.  */
1019   FLD (i_disp24) = f_disp24;
1020   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1021
1022 #if WITH_PROFILE_MODEL_P
1023   /* Record the fields for profiling.  */
1024   if (PROFILE_MODEL_P (current_cpu))
1025     {
1026       FLD (out_h_gr_14) = 14;
1027     }
1028 #endif
1029 #undef FLD
1030     return idesc;
1031   }
1032
1033  extract_sfmt_bra8:
1034   {
1035     const IDESC *idesc = &m32rxf_insn_data[itype];
1036     CGEN_INSN_INT insn = entire_insn;
1037 #define FLD(f) abuf->fields.sfmt_bl8.f
1038     SI f_disp8;
1039
1040     f_disp8 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4))));
1041
1042   /* Record the fields for the semantic handler.  */
1043   FLD (i_disp8) = f_disp8;
1044   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1045
1046 #if WITH_PROFILE_MODEL_P
1047   /* Record the fields for profiling.  */
1048   if (PROFILE_MODEL_P (current_cpu))
1049     {
1050     }
1051 #endif
1052 #undef FLD
1053     return idesc;
1054   }
1055
1056  extract_sfmt_bra24:
1057   {
1058     const IDESC *idesc = &m32rxf_insn_data[itype];
1059     CGEN_INSN_INT insn = entire_insn;
1060 #define FLD(f) abuf->fields.sfmt_bl24.f
1061     SI f_disp24;
1062
1063     f_disp24 = ((((EXTRACT_MSB0_INT (insn, 32, 8, 24)) << (2))) + (pc));
1064
1065   /* Record the fields for the semantic handler.  */
1066   FLD (i_disp24) = f_disp24;
1067   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1068
1069 #if WITH_PROFILE_MODEL_P
1070   /* Record the fields for profiling.  */
1071   if (PROFILE_MODEL_P (current_cpu))
1072     {
1073     }
1074 #endif
1075 #undef FLD
1076     return idesc;
1077   }
1078
1079  extract_sfmt_cmp:
1080   {
1081     const IDESC *idesc = &m32rxf_insn_data[itype];
1082     CGEN_INSN_INT insn = entire_insn;
1083 #define FLD(f) abuf->fields.sfmt_st_plus.f
1084     UINT f_r1;
1085     UINT f_r2;
1086
1087     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1088     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1089
1090   /* Record the fields for the semantic handler.  */
1091   FLD (i_src1) = & CPU (h_gr)[f_r1];
1092   FLD (i_src2) = & CPU (h_gr)[f_r2];
1093   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1094
1095 #if WITH_PROFILE_MODEL_P
1096   /* Record the fields for profiling.  */
1097   if (PROFILE_MODEL_P (current_cpu))
1098     {
1099       FLD (in_src1) = f_r1;
1100       FLD (in_src2) = f_r2;
1101     }
1102 #endif
1103 #undef FLD
1104     return idesc;
1105   }
1106
1107  extract_sfmt_cmpi:
1108   {
1109     const IDESC *idesc = &m32rxf_insn_data[itype];
1110     CGEN_INSN_INT insn = entire_insn;
1111 #define FLD(f) abuf->fields.sfmt_st_d.f
1112     UINT f_r2;
1113     INT f_simm16;
1114
1115     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1116     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1117
1118   /* Record the fields for the semantic handler.  */
1119   FLD (f_simm16) = f_simm16;
1120   FLD (i_src2) = & CPU (h_gr)[f_r2];
1121   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
1122
1123 #if WITH_PROFILE_MODEL_P
1124   /* Record the fields for profiling.  */
1125   if (PROFILE_MODEL_P (current_cpu))
1126     {
1127       FLD (in_src2) = f_r2;
1128     }
1129 #endif
1130 #undef FLD
1131     return idesc;
1132   }
1133
1134  extract_sfmt_cmpz:
1135   {
1136     const IDESC *idesc = &m32rxf_insn_data[itype];
1137     CGEN_INSN_INT insn = entire_insn;
1138 #define FLD(f) abuf->fields.sfmt_st_plus.f
1139     UINT f_r2;
1140
1141     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1142
1143   /* Record the fields for the semantic handler.  */
1144   FLD (i_src2) = & CPU (h_gr)[f_r2];
1145   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpz", "src2 0x%x", 'x', f_r2, (char *) 0));
1146
1147 #if WITH_PROFILE_MODEL_P
1148   /* Record the fields for profiling.  */
1149   if (PROFILE_MODEL_P (current_cpu))
1150     {
1151       FLD (in_src2) = f_r2;
1152     }
1153 #endif
1154 #undef FLD
1155     return idesc;
1156   }
1157
1158  extract_sfmt_div:
1159   {
1160     const IDESC *idesc = &m32rxf_insn_data[itype];
1161     CGEN_INSN_INT insn = entire_insn;
1162 #define FLD(f) abuf->fields.sfmt_add.f
1163     UINT f_r1;
1164     UINT f_r2;
1165
1166     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1167     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1168
1169   /* Record the fields for the semantic handler.  */
1170   FLD (i_dr) = & CPU (h_gr)[f_r1];
1171   FLD (i_sr) = & CPU (h_gr)[f_r2];
1172   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1173
1174 #if WITH_PROFILE_MODEL_P
1175   /* Record the fields for profiling.  */
1176   if (PROFILE_MODEL_P (current_cpu))
1177     {
1178       FLD (in_dr) = f_r1;
1179       FLD (in_sr) = f_r2;
1180       FLD (out_dr) = f_r1;
1181     }
1182 #endif
1183 #undef FLD
1184     return idesc;
1185   }
1186
1187  extract_sfmt_jc:
1188   {
1189     const IDESC *idesc = &m32rxf_insn_data[itype];
1190     CGEN_INSN_INT insn = entire_insn;
1191 #define FLD(f) abuf->fields.sfmt_mvtc.f
1192     UINT f_r2;
1193
1194     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1195
1196   /* Record the fields for the semantic handler.  */
1197   FLD (i_sr) = & CPU (h_gr)[f_r2];
1198   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jc", "sr 0x%x", 'x', f_r2, (char *) 0));
1199
1200 #if WITH_PROFILE_MODEL_P
1201   /* Record the fields for profiling.  */
1202   if (PROFILE_MODEL_P (current_cpu))
1203     {
1204       FLD (in_sr) = f_r2;
1205     }
1206 #endif
1207 #undef FLD
1208     return idesc;
1209   }
1210
1211  extract_sfmt_jl:
1212   {
1213     const IDESC *idesc = &m32rxf_insn_data[itype];
1214     CGEN_INSN_INT insn = entire_insn;
1215 #define FLD(f) abuf->fields.sfmt_jl.f
1216     UINT f_r2;
1217
1218     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1219
1220   /* Record the fields for the semantic handler.  */
1221   FLD (i_sr) = & CPU (h_gr)[f_r2];
1222   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
1223
1224 #if WITH_PROFILE_MODEL_P
1225   /* Record the fields for profiling.  */
1226   if (PROFILE_MODEL_P (current_cpu))
1227     {
1228       FLD (in_sr) = f_r2;
1229       FLD (out_h_gr_14) = 14;
1230     }
1231 #endif
1232 #undef FLD
1233     return idesc;
1234   }
1235
1236  extract_sfmt_jmp:
1237   {
1238     const IDESC *idesc = &m32rxf_insn_data[itype];
1239     CGEN_INSN_INT insn = entire_insn;
1240 #define FLD(f) abuf->fields.sfmt_mvtc.f
1241     UINT f_r2;
1242
1243     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1244
1245   /* Record the fields for the semantic handler.  */
1246   FLD (i_sr) = & CPU (h_gr)[f_r2];
1247   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
1248
1249 #if WITH_PROFILE_MODEL_P
1250   /* Record the fields for profiling.  */
1251   if (PROFILE_MODEL_P (current_cpu))
1252     {
1253       FLD (in_sr) = f_r2;
1254     }
1255 #endif
1256 #undef FLD
1257     return idesc;
1258   }
1259
1260  extract_sfmt_ld:
1261   {
1262     const IDESC *idesc = &m32rxf_insn_data[itype];
1263     CGEN_INSN_INT insn = entire_insn;
1264 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1265     UINT f_r1;
1266     UINT f_r2;
1267
1268     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1269     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1270
1271   /* Record the fields for the semantic handler.  */
1272   FLD (i_sr) = & CPU (h_gr)[f_r2];
1273   FLD (i_dr) = & CPU (h_gr)[f_r1];
1274   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1275
1276 #if WITH_PROFILE_MODEL_P
1277   /* Record the fields for profiling.  */
1278   if (PROFILE_MODEL_P (current_cpu))
1279     {
1280       FLD (in_sr) = f_r2;
1281       FLD (out_dr) = f_r1;
1282     }
1283 #endif
1284 #undef FLD
1285     return idesc;
1286   }
1287
1288  extract_sfmt_ld_d:
1289   {
1290     const IDESC *idesc = &m32rxf_insn_data[itype];
1291     CGEN_INSN_INT insn = entire_insn;
1292 #define FLD(f) abuf->fields.sfmt_add3.f
1293     UINT f_r1;
1294     UINT f_r2;
1295     INT f_simm16;
1296
1297     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1298     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1299     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1300
1301   /* Record the fields for the semantic handler.  */
1302   FLD (f_simm16) = f_simm16;
1303   FLD (i_sr) = & CPU (h_gr)[f_r2];
1304   FLD (i_dr) = & CPU (h_gr)[f_r1];
1305   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1306
1307 #if WITH_PROFILE_MODEL_P
1308   /* Record the fields for profiling.  */
1309   if (PROFILE_MODEL_P (current_cpu))
1310     {
1311       FLD (in_sr) = f_r2;
1312       FLD (out_dr) = f_r1;
1313     }
1314 #endif
1315 #undef FLD
1316     return idesc;
1317   }
1318
1319  extract_sfmt_ld_plus:
1320   {
1321     const IDESC *idesc = &m32rxf_insn_data[itype];
1322     CGEN_INSN_INT insn = entire_insn;
1323 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1324     UINT f_r1;
1325     UINT f_r2;
1326
1327     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1328     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1329
1330   /* Record the fields for the semantic handler.  */
1331   FLD (i_sr) = & CPU (h_gr)[f_r2];
1332   FLD (i_dr) = & CPU (h_gr)[f_r1];
1333   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1334
1335 #if WITH_PROFILE_MODEL_P
1336   /* Record the fields for profiling.  */
1337   if (PROFILE_MODEL_P (current_cpu))
1338     {
1339       FLD (in_sr) = f_r2;
1340       FLD (out_dr) = f_r1;
1341       FLD (out_sr) = f_r2;
1342     }
1343 #endif
1344 #undef FLD
1345     return idesc;
1346   }
1347
1348  extract_sfmt_ld24:
1349   {
1350     const IDESC *idesc = &m32rxf_insn_data[itype];
1351     CGEN_INSN_INT insn = entire_insn;
1352 #define FLD(f) abuf->fields.sfmt_ld24.f
1353     UINT f_r1;
1354     UINT f_uimm24;
1355
1356     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1357     f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
1358
1359   /* Record the fields for the semantic handler.  */
1360   FLD (i_uimm24) = f_uimm24;
1361   FLD (i_dr) = & CPU (h_gr)[f_r1];
1362   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1363
1364 #if WITH_PROFILE_MODEL_P
1365   /* Record the fields for profiling.  */
1366   if (PROFILE_MODEL_P (current_cpu))
1367     {
1368       FLD (out_dr) = f_r1;
1369     }
1370 #endif
1371 #undef FLD
1372     return idesc;
1373   }
1374
1375  extract_sfmt_ldi8:
1376   {
1377     const IDESC *idesc = &m32rxf_insn_data[itype];
1378     CGEN_INSN_INT insn = entire_insn;
1379 #define FLD(f) abuf->fields.sfmt_addi.f
1380     UINT f_r1;
1381     INT f_simm8;
1382
1383     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1384     f_simm8 = EXTRACT_MSB0_INT (insn, 16, 8, 8);
1385
1386   /* Record the fields for the semantic handler.  */
1387   FLD (f_simm8) = f_simm8;
1388   FLD (i_dr) = & CPU (h_gr)[f_r1];
1389   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
1390
1391 #if WITH_PROFILE_MODEL_P
1392   /* Record the fields for profiling.  */
1393   if (PROFILE_MODEL_P (current_cpu))
1394     {
1395       FLD (out_dr) = f_r1;
1396     }
1397 #endif
1398 #undef FLD
1399     return idesc;
1400   }
1401
1402  extract_sfmt_ldi16:
1403   {
1404     const IDESC *idesc = &m32rxf_insn_data[itype];
1405     CGEN_INSN_INT insn = entire_insn;
1406 #define FLD(f) abuf->fields.sfmt_add3.f
1407     UINT f_r1;
1408     INT f_simm16;
1409
1410     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1411     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1412
1413   /* Record the fields for the semantic handler.  */
1414   FLD (f_simm16) = f_simm16;
1415   FLD (i_dr) = & CPU (h_gr)[f_r1];
1416   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
1417
1418 #if WITH_PROFILE_MODEL_P
1419   /* Record the fields for profiling.  */
1420   if (PROFILE_MODEL_P (current_cpu))
1421     {
1422       FLD (out_dr) = f_r1;
1423     }
1424 #endif
1425 #undef FLD
1426     return idesc;
1427   }
1428
1429  extract_sfmt_lock:
1430   {
1431     const IDESC *idesc = &m32rxf_insn_data[itype];
1432     CGEN_INSN_INT insn = entire_insn;
1433 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1434     UINT f_r1;
1435     UINT f_r2;
1436
1437     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1438     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1439
1440   /* Record the fields for the semantic handler.  */
1441   FLD (i_sr) = & CPU (h_gr)[f_r2];
1442   FLD (i_dr) = & CPU (h_gr)[f_r1];
1443   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1444
1445 #if WITH_PROFILE_MODEL_P
1446   /* Record the fields for profiling.  */
1447   if (PROFILE_MODEL_P (current_cpu))
1448     {
1449       FLD (in_sr) = f_r2;
1450       FLD (out_dr) = f_r1;
1451     }
1452 #endif
1453 #undef FLD
1454     return idesc;
1455   }
1456
1457  extract_sfmt_machi_a:
1458   {
1459     const IDESC *idesc = &m32rxf_insn_data[itype];
1460     CGEN_INSN_INT insn = entire_insn;
1461 #define FLD(f) abuf->fields.sfmt_machi_a.f
1462     UINT f_r1;
1463     UINT f_acc;
1464     UINT f_r2;
1465
1466     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1467     f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1468     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1469
1470   /* Record the fields for the semantic handler.  */
1471   FLD (f_acc) = f_acc;
1472   FLD (i_src1) = & CPU (h_gr)[f_r1];
1473   FLD (i_src2) = & CPU (h_gr)[f_r2];
1474   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1475
1476 #if WITH_PROFILE_MODEL_P
1477   /* Record the fields for profiling.  */
1478   if (PROFILE_MODEL_P (current_cpu))
1479     {
1480       FLD (in_src1) = f_r1;
1481       FLD (in_src2) = f_r2;
1482     }
1483 #endif
1484 #undef FLD
1485     return idesc;
1486   }
1487
1488  extract_sfmt_mulhi_a:
1489   {
1490     const IDESC *idesc = &m32rxf_insn_data[itype];
1491     CGEN_INSN_INT insn = entire_insn;
1492 #define FLD(f) abuf->fields.sfmt_machi_a.f
1493     UINT f_r1;
1494     UINT f_acc;
1495     UINT f_r2;
1496
1497     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1498     f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1);
1499     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1500
1501   /* Record the fields for the semantic handler.  */
1502   FLD (f_acc) = f_acc;
1503   FLD (i_src1) = & CPU (h_gr)[f_r1];
1504   FLD (i_src2) = & CPU (h_gr)[f_r2];
1505   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1506
1507 #if WITH_PROFILE_MODEL_P
1508   /* Record the fields for profiling.  */
1509   if (PROFILE_MODEL_P (current_cpu))
1510     {
1511       FLD (in_src1) = f_r1;
1512       FLD (in_src2) = f_r2;
1513     }
1514 #endif
1515 #undef FLD
1516     return idesc;
1517   }
1518
1519  extract_sfmt_mv:
1520   {
1521     const IDESC *idesc = &m32rxf_insn_data[itype];
1522     CGEN_INSN_INT insn = entire_insn;
1523 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1524     UINT f_r1;
1525     UINT f_r2;
1526
1527     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1528     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1529
1530   /* Record the fields for the semantic handler.  */
1531   FLD (i_sr) = & CPU (h_gr)[f_r2];
1532   FLD (i_dr) = & CPU (h_gr)[f_r1];
1533   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1534
1535 #if WITH_PROFILE_MODEL_P
1536   /* Record the fields for profiling.  */
1537   if (PROFILE_MODEL_P (current_cpu))
1538     {
1539       FLD (in_sr) = f_r2;
1540       FLD (out_dr) = f_r1;
1541     }
1542 #endif
1543 #undef FLD
1544     return idesc;
1545   }
1546
1547  extract_sfmt_mvfachi_a:
1548   {
1549     const IDESC *idesc = &m32rxf_insn_data[itype];
1550     CGEN_INSN_INT insn = entire_insn;
1551 #define FLD(f) abuf->fields.sfmt_mvfachi_a.f
1552     UINT f_r1;
1553     UINT f_accs;
1554
1555     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1556     f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1557
1558   /* Record the fields for the semantic handler.  */
1559   FLD (f_accs) = f_accs;
1560   FLD (i_dr) = & CPU (h_gr)[f_r1];
1561   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "dr 0x%x", 'x', f_r1, (char *) 0));
1562
1563 #if WITH_PROFILE_MODEL_P
1564   /* Record the fields for profiling.  */
1565   if (PROFILE_MODEL_P (current_cpu))
1566     {
1567       FLD (out_dr) = f_r1;
1568     }
1569 #endif
1570 #undef FLD
1571     return idesc;
1572   }
1573
1574  extract_sfmt_mvfc:
1575   {
1576     const IDESC *idesc = &m32rxf_insn_data[itype];
1577     CGEN_INSN_INT insn = entire_insn;
1578 #define FLD(f) abuf->fields.sfmt_mvfc.f
1579     UINT f_r1;
1580     UINT f_r2;
1581
1582     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1583     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1584
1585   /* Record the fields for the semantic handler.  */
1586   FLD (f_r2) = f_r2;
1587   FLD (i_dr) = & CPU (h_gr)[f_r1];
1588   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1589
1590 #if WITH_PROFILE_MODEL_P
1591   /* Record the fields for profiling.  */
1592   if (PROFILE_MODEL_P (current_cpu))
1593     {
1594       FLD (out_dr) = f_r1;
1595     }
1596 #endif
1597 #undef FLD
1598     return idesc;
1599   }
1600
1601  extract_sfmt_mvtachi_a:
1602   {
1603     const IDESC *idesc = &m32rxf_insn_data[itype];
1604     CGEN_INSN_INT insn = entire_insn;
1605 #define FLD(f) abuf->fields.sfmt_mvtachi_a.f
1606     UINT f_r1;
1607     UINT f_accs;
1608
1609     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1610     f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1611
1612   /* Record the fields for the semantic handler.  */
1613   FLD (f_accs) = f_accs;
1614   FLD (i_src1) = & CPU (h_gr)[f_r1];
1615   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "src1 0x%x", 'x', f_r1, (char *) 0));
1616
1617 #if WITH_PROFILE_MODEL_P
1618   /* Record the fields for profiling.  */
1619   if (PROFILE_MODEL_P (current_cpu))
1620     {
1621       FLD (in_src1) = f_r1;
1622     }
1623 #endif
1624 #undef FLD
1625     return idesc;
1626   }
1627
1628  extract_sfmt_mvtc:
1629   {
1630     const IDESC *idesc = &m32rxf_insn_data[itype];
1631     CGEN_INSN_INT insn = entire_insn;
1632 #define FLD(f) abuf->fields.sfmt_mvtc.f
1633     UINT f_r1;
1634     UINT f_r2;
1635
1636     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1637     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1638
1639   /* Record the fields for the semantic handler.  */
1640   FLD (f_r1) = f_r1;
1641   FLD (i_sr) = & CPU (h_gr)[f_r2];
1642   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1643
1644 #if WITH_PROFILE_MODEL_P
1645   /* Record the fields for profiling.  */
1646   if (PROFILE_MODEL_P (current_cpu))
1647     {
1648       FLD (in_sr) = f_r2;
1649     }
1650 #endif
1651 #undef FLD
1652     return idesc;
1653   }
1654
1655  extract_sfmt_nop:
1656   {
1657     const IDESC *idesc = &m32rxf_insn_data[itype];
1658     CGEN_INSN_INT insn = entire_insn;
1659 #define FLD(f) abuf->fields.fmt_empty.f
1660
1661
1662   /* Record the fields for the semantic handler.  */
1663   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
1664
1665 #undef FLD
1666     return idesc;
1667   }
1668
1669  extract_sfmt_rac_dsi:
1670   {
1671     const IDESC *idesc = &m32rxf_insn_data[itype];
1672     CGEN_INSN_INT insn = entire_insn;
1673 #define FLD(f) abuf->fields.sfmt_rac_dsi.f
1674     UINT f_accd;
1675     UINT f_accs;
1676     SI f_imm1;
1677
1678     f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2);
1679     f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2);
1680     f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1));
1681
1682   /* Record the fields for the semantic handler.  */
1683   FLD (f_accs) = f_accs;
1684   FLD (f_imm1) = f_imm1;
1685   FLD (f_accd) = f_accd;
1686   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
1687
1688 #undef FLD
1689     return idesc;
1690   }
1691
1692  extract_sfmt_rte:
1693   {
1694     const IDESC *idesc = &m32rxf_insn_data[itype];
1695     CGEN_INSN_INT insn = entire_insn;
1696 #define FLD(f) abuf->fields.fmt_empty.f
1697
1698
1699   /* Record the fields for the semantic handler.  */
1700   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
1701
1702 #if WITH_PROFILE_MODEL_P
1703   /* Record the fields for profiling.  */
1704   if (PROFILE_MODEL_P (current_cpu))
1705     {
1706     }
1707 #endif
1708 #undef FLD
1709     return idesc;
1710   }
1711
1712  extract_sfmt_seth:
1713   {
1714     const IDESC *idesc = &m32rxf_insn_data[itype];
1715     CGEN_INSN_INT insn = entire_insn;
1716 #define FLD(f) abuf->fields.sfmt_seth.f
1717     UINT f_r1;
1718     UINT f_hi16;
1719
1720     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1721     f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
1722
1723   /* Record the fields for the semantic handler.  */
1724   FLD (f_hi16) = f_hi16;
1725   FLD (i_dr) = & CPU (h_gr)[f_r1];
1726   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
1727
1728 #if WITH_PROFILE_MODEL_P
1729   /* Record the fields for profiling.  */
1730   if (PROFILE_MODEL_P (current_cpu))
1731     {
1732       FLD (out_dr) = f_r1;
1733     }
1734 #endif
1735 #undef FLD
1736     return idesc;
1737   }
1738
1739  extract_sfmt_sll3:
1740   {
1741     const IDESC *idesc = &m32rxf_insn_data[itype];
1742     CGEN_INSN_INT insn = entire_insn;
1743 #define FLD(f) abuf->fields.sfmt_add3.f
1744     UINT f_r1;
1745     UINT f_r2;
1746     INT f_simm16;
1747
1748     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1749     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1750     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1751
1752   /* Record the fields for the semantic handler.  */
1753   FLD (f_simm16) = f_simm16;
1754   FLD (i_sr) = & CPU (h_gr)[f_r2];
1755   FLD (i_dr) = & CPU (h_gr)[f_r1];
1756   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1757
1758 #if WITH_PROFILE_MODEL_P
1759   /* Record the fields for profiling.  */
1760   if (PROFILE_MODEL_P (current_cpu))
1761     {
1762       FLD (in_sr) = f_r2;
1763       FLD (out_dr) = f_r1;
1764     }
1765 #endif
1766 #undef FLD
1767     return idesc;
1768   }
1769
1770  extract_sfmt_slli:
1771   {
1772     const IDESC *idesc = &m32rxf_insn_data[itype];
1773     CGEN_INSN_INT insn = entire_insn;
1774 #define FLD(f) abuf->fields.sfmt_slli.f
1775     UINT f_r1;
1776     UINT f_uimm5;
1777
1778     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1779     f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
1780
1781   /* Record the fields for the semantic handler.  */
1782   FLD (f_uimm5) = f_uimm5;
1783   FLD (i_dr) = & CPU (h_gr)[f_r1];
1784   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
1785
1786 #if WITH_PROFILE_MODEL_P
1787   /* Record the fields for profiling.  */
1788   if (PROFILE_MODEL_P (current_cpu))
1789     {
1790       FLD (in_dr) = f_r1;
1791       FLD (out_dr) = f_r1;
1792     }
1793 #endif
1794 #undef FLD
1795     return idesc;
1796   }
1797
1798  extract_sfmt_st:
1799   {
1800     const IDESC *idesc = &m32rxf_insn_data[itype];
1801     CGEN_INSN_INT insn = entire_insn;
1802 #define FLD(f) abuf->fields.sfmt_st_plus.f
1803     UINT f_r1;
1804     UINT f_r2;
1805
1806     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1807     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1808
1809   /* Record the fields for the semantic handler.  */
1810   FLD (i_src1) = & CPU (h_gr)[f_r1];
1811   FLD (i_src2) = & CPU (h_gr)[f_r2];
1812   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1813
1814 #if WITH_PROFILE_MODEL_P
1815   /* Record the fields for profiling.  */
1816   if (PROFILE_MODEL_P (current_cpu))
1817     {
1818       FLD (in_src1) = f_r1;
1819       FLD (in_src2) = f_r2;
1820     }
1821 #endif
1822 #undef FLD
1823     return idesc;
1824   }
1825
1826  extract_sfmt_st_d:
1827   {
1828     const IDESC *idesc = &m32rxf_insn_data[itype];
1829     CGEN_INSN_INT insn = entire_insn;
1830 #define FLD(f) abuf->fields.sfmt_st_d.f
1831     UINT f_r1;
1832     UINT f_r2;
1833     INT f_simm16;
1834
1835     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1836     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1837     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1838
1839   /* Record the fields for the semantic handler.  */
1840   FLD (f_simm16) = f_simm16;
1841   FLD (i_src1) = & CPU (h_gr)[f_r1];
1842   FLD (i_src2) = & CPU (h_gr)[f_r2];
1843   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1844
1845 #if WITH_PROFILE_MODEL_P
1846   /* Record the fields for profiling.  */
1847   if (PROFILE_MODEL_P (current_cpu))
1848     {
1849       FLD (in_src1) = f_r1;
1850       FLD (in_src2) = f_r2;
1851     }
1852 #endif
1853 #undef FLD
1854     return idesc;
1855   }
1856
1857  extract_sfmt_stb:
1858   {
1859     const IDESC *idesc = &m32rxf_insn_data[itype];
1860     CGEN_INSN_INT insn = entire_insn;
1861 #define FLD(f) abuf->fields.sfmt_st_plus.f
1862     UINT f_r1;
1863     UINT f_r2;
1864
1865     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1866     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1867
1868   /* Record the fields for the semantic handler.  */
1869   FLD (i_src1) = & CPU (h_gr)[f_r1];
1870   FLD (i_src2) = & CPU (h_gr)[f_r2];
1871   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1872
1873 #if WITH_PROFILE_MODEL_P
1874   /* Record the fields for profiling.  */
1875   if (PROFILE_MODEL_P (current_cpu))
1876     {
1877       FLD (in_src1) = f_r1;
1878       FLD (in_src2) = f_r2;
1879     }
1880 #endif
1881 #undef FLD
1882     return idesc;
1883   }
1884
1885  extract_sfmt_stb_d:
1886   {
1887     const IDESC *idesc = &m32rxf_insn_data[itype];
1888     CGEN_INSN_INT insn = entire_insn;
1889 #define FLD(f) abuf->fields.sfmt_st_d.f
1890     UINT f_r1;
1891     UINT f_r2;
1892     INT f_simm16;
1893
1894     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1895     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1896     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1897
1898   /* Record the fields for the semantic handler.  */
1899   FLD (f_simm16) = f_simm16;
1900   FLD (i_src1) = & CPU (h_gr)[f_r1];
1901   FLD (i_src2) = & CPU (h_gr)[f_r2];
1902   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1903
1904 #if WITH_PROFILE_MODEL_P
1905   /* Record the fields for profiling.  */
1906   if (PROFILE_MODEL_P (current_cpu))
1907     {
1908       FLD (in_src1) = f_r1;
1909       FLD (in_src2) = f_r2;
1910     }
1911 #endif
1912 #undef FLD
1913     return idesc;
1914   }
1915
1916  extract_sfmt_sth:
1917   {
1918     const IDESC *idesc = &m32rxf_insn_data[itype];
1919     CGEN_INSN_INT insn = entire_insn;
1920 #define FLD(f) abuf->fields.sfmt_st_plus.f
1921     UINT f_r1;
1922     UINT f_r2;
1923
1924     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1925     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1926
1927   /* Record the fields for the semantic handler.  */
1928   FLD (i_src1) = & CPU (h_gr)[f_r1];
1929   FLD (i_src2) = & CPU (h_gr)[f_r2];
1930   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1931
1932 #if WITH_PROFILE_MODEL_P
1933   /* Record the fields for profiling.  */
1934   if (PROFILE_MODEL_P (current_cpu))
1935     {
1936       FLD (in_src1) = f_r1;
1937       FLD (in_src2) = f_r2;
1938     }
1939 #endif
1940 #undef FLD
1941     return idesc;
1942   }
1943
1944  extract_sfmt_sth_d:
1945   {
1946     const IDESC *idesc = &m32rxf_insn_data[itype];
1947     CGEN_INSN_INT insn = entire_insn;
1948 #define FLD(f) abuf->fields.sfmt_st_d.f
1949     UINT f_r1;
1950     UINT f_r2;
1951     INT f_simm16;
1952
1953     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1954     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1955     f_simm16 = EXTRACT_MSB0_INT (insn, 32, 16, 16);
1956
1957   /* Record the fields for the semantic handler.  */
1958   FLD (f_simm16) = f_simm16;
1959   FLD (i_src1) = & CPU (h_gr)[f_r1];
1960   FLD (i_src2) = & CPU (h_gr)[f_r2];
1961   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1962
1963 #if WITH_PROFILE_MODEL_P
1964   /* Record the fields for profiling.  */
1965   if (PROFILE_MODEL_P (current_cpu))
1966     {
1967       FLD (in_src1) = f_r1;
1968       FLD (in_src2) = f_r2;
1969     }
1970 #endif
1971 #undef FLD
1972     return idesc;
1973   }
1974
1975  extract_sfmt_st_plus:
1976   {
1977     const IDESC *idesc = &m32rxf_insn_data[itype];
1978     CGEN_INSN_INT insn = entire_insn;
1979 #define FLD(f) abuf->fields.sfmt_st_plus.f
1980     UINT f_r1;
1981     UINT f_r2;
1982
1983     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1984     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1985
1986   /* Record the fields for the semantic handler.  */
1987   FLD (i_src1) = & CPU (h_gr)[f_r1];
1988   FLD (i_src2) = & CPU (h_gr)[f_r2];
1989   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1990
1991 #if WITH_PROFILE_MODEL_P
1992   /* Record the fields for profiling.  */
1993   if (PROFILE_MODEL_P (current_cpu))
1994     {
1995       FLD (in_src1) = f_r1;
1996       FLD (in_src2) = f_r2;
1997       FLD (out_src2) = f_r2;
1998     }
1999 #endif
2000 #undef FLD
2001     return idesc;
2002   }
2003
2004  extract_sfmt_trap:
2005   {
2006     const IDESC *idesc = &m32rxf_insn_data[itype];
2007     CGEN_INSN_INT insn = entire_insn;
2008 #define FLD(f) abuf->fields.sfmt_trap.f
2009     UINT f_uimm4;
2010
2011     f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2012
2013   /* Record the fields for the semantic handler.  */
2014   FLD (f_uimm4) = f_uimm4;
2015   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
2016
2017 #if WITH_PROFILE_MODEL_P
2018   /* Record the fields for profiling.  */
2019   if (PROFILE_MODEL_P (current_cpu))
2020     {
2021     }
2022 #endif
2023 #undef FLD
2024     return idesc;
2025   }
2026
2027  extract_sfmt_unlock:
2028   {
2029     const IDESC *idesc = &m32rxf_insn_data[itype];
2030     CGEN_INSN_INT insn = entire_insn;
2031 #define FLD(f) abuf->fields.sfmt_st_plus.f
2032     UINT f_r1;
2033     UINT f_r2;
2034
2035     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2036     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2037
2038   /* Record the fields for the semantic handler.  */
2039   FLD (i_src1) = & CPU (h_gr)[f_r1];
2040   FLD (i_src2) = & CPU (h_gr)[f_r2];
2041   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2042
2043 #if WITH_PROFILE_MODEL_P
2044   /* Record the fields for profiling.  */
2045   if (PROFILE_MODEL_P (current_cpu))
2046     {
2047       FLD (in_src1) = f_r1;
2048       FLD (in_src2) = f_r2;
2049     }
2050 #endif
2051 #undef FLD
2052     return idesc;
2053   }
2054
2055  extract_sfmt_satb:
2056   {
2057     const IDESC *idesc = &m32rxf_insn_data[itype];
2058     CGEN_INSN_INT insn = entire_insn;
2059 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2060     UINT f_r1;
2061     UINT f_r2;
2062
2063     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2064     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2065
2066   /* Record the fields for the semantic handler.  */
2067   FLD (i_sr) = & CPU (h_gr)[f_r2];
2068   FLD (i_dr) = & CPU (h_gr)[f_r1];
2069   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_satb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2070
2071 #if WITH_PROFILE_MODEL_P
2072   /* Record the fields for profiling.  */
2073   if (PROFILE_MODEL_P (current_cpu))
2074     {
2075       FLD (in_sr) = f_r2;
2076       FLD (out_dr) = f_r1;
2077     }
2078 #endif
2079 #undef FLD
2080     return idesc;
2081   }
2082
2083  extract_sfmt_sat:
2084   {
2085     const IDESC *idesc = &m32rxf_insn_data[itype];
2086     CGEN_INSN_INT insn = entire_insn;
2087 #define FLD(f) abuf->fields.sfmt_ld_plus.f
2088     UINT f_r1;
2089     UINT f_r2;
2090
2091     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2092     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2093
2094   /* Record the fields for the semantic handler.  */
2095   FLD (i_sr) = & CPU (h_gr)[f_r2];
2096   FLD (i_dr) = & CPU (h_gr)[f_r1];
2097   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sat", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2098
2099 #if WITH_PROFILE_MODEL_P
2100   /* Record the fields for profiling.  */
2101   if (PROFILE_MODEL_P (current_cpu))
2102     {
2103       FLD (in_sr) = f_r2;
2104       FLD (out_dr) = f_r1;
2105     }
2106 #endif
2107 #undef FLD
2108     return idesc;
2109   }
2110
2111  extract_sfmt_sadd:
2112   {
2113     const IDESC *idesc = &m32rxf_insn_data[itype];
2114     CGEN_INSN_INT insn = entire_insn;
2115 #define FLD(f) abuf->fields.fmt_empty.f
2116
2117
2118   /* Record the fields for the semantic handler.  */
2119   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sadd", (char *) 0));
2120
2121 #undef FLD
2122     return idesc;
2123   }
2124
2125  extract_sfmt_macwu1:
2126   {
2127     const IDESC *idesc = &m32rxf_insn_data[itype];
2128     CGEN_INSN_INT insn = entire_insn;
2129 #define FLD(f) abuf->fields.sfmt_st_plus.f
2130     UINT f_r1;
2131     UINT f_r2;
2132
2133     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2134     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2135
2136   /* Record the fields for the semantic handler.  */
2137   FLD (i_src1) = & CPU (h_gr)[f_r1];
2138   FLD (i_src2) = & CPU (h_gr)[f_r2];
2139   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_macwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2140
2141 #if WITH_PROFILE_MODEL_P
2142   /* Record the fields for profiling.  */
2143   if (PROFILE_MODEL_P (current_cpu))
2144     {
2145       FLD (in_src1) = f_r1;
2146       FLD (in_src2) = f_r2;
2147     }
2148 #endif
2149 #undef FLD
2150     return idesc;
2151   }
2152
2153  extract_sfmt_msblo:
2154   {
2155     const IDESC *idesc = &m32rxf_insn_data[itype];
2156     CGEN_INSN_INT insn = entire_insn;
2157 #define FLD(f) abuf->fields.sfmt_st_plus.f
2158     UINT f_r1;
2159     UINT f_r2;
2160
2161     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2162     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2163
2164   /* Record the fields for the semantic handler.  */
2165   FLD (i_src1) = & CPU (h_gr)[f_r1];
2166   FLD (i_src2) = & CPU (h_gr)[f_r2];
2167   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_msblo", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2168
2169 #if WITH_PROFILE_MODEL_P
2170   /* Record the fields for profiling.  */
2171   if (PROFILE_MODEL_P (current_cpu))
2172     {
2173       FLD (in_src1) = f_r1;
2174       FLD (in_src2) = f_r2;
2175     }
2176 #endif
2177 #undef FLD
2178     return idesc;
2179   }
2180
2181  extract_sfmt_mulwu1:
2182   {
2183     const IDESC *idesc = &m32rxf_insn_data[itype];
2184     CGEN_INSN_INT insn = entire_insn;
2185 #define FLD(f) abuf->fields.sfmt_st_plus.f
2186     UINT f_r1;
2187     UINT f_r2;
2188
2189     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2190     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2191
2192   /* Record the fields for the semantic handler.  */
2193   FLD (i_src1) = & CPU (h_gr)[f_r1];
2194   FLD (i_src2) = & CPU (h_gr)[f_r2];
2195   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2196
2197 #if WITH_PROFILE_MODEL_P
2198   /* Record the fields for profiling.  */
2199   if (PROFILE_MODEL_P (current_cpu))
2200     {
2201       FLD (in_src1) = f_r1;
2202       FLD (in_src2) = f_r2;
2203     }
2204 #endif
2205 #undef FLD
2206     return idesc;
2207   }
2208
2209  extract_sfmt_sc:
2210   {
2211     const IDESC *idesc = &m32rxf_insn_data[itype];
2212     CGEN_INSN_INT insn = entire_insn;
2213 #define FLD(f) abuf->fields.fmt_empty.f
2214
2215
2216   /* Record the fields for the semantic handler.  */
2217   TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sc", (char *) 0));
2218
2219 #undef FLD
2220     return idesc;
2221   }
2222
2223 }