1 /* m32r simulator support code
2 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #define WANT_CPU m32rbf
22 #define WANT_CPU_M32RBF
28 /* Decode gdb ctrl register number. */
31 m32r_decode_gdb_ctrl_regnum (int gdb_regnum
)
35 case PSW_REGNUM
: return H_CR_PSW
;
36 case CBR_REGNUM
: return H_CR_CBR
;
37 case SPI_REGNUM
: return H_CR_SPI
;
38 case SPU_REGNUM
: return H_CR_SPU
;
39 case BPC_REGNUM
: return H_CR_BPC
;
40 case BBPSW_REGNUM
: return H_CR_BBPSW
;
41 case BBPC_REGNUM
: return H_CR_BBPC
;
46 /* The contents of BUF are in target byte order. */
49 m32rbf_fetch_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
51 int mach
= MACH_NUM (CPU_MACH (current_cpu
));
54 SETTWI (buf
, a_m32r_h_gr_get (current_cpu
, rn
));
65 SETTWI (buf
, a_m32r_h_cr_get (current_cpu
,
66 m32r_decode_gdb_ctrl_regnum (rn
)));
69 if (mach
== MACH_M32R
)
70 SETTWI (buf
, m32rbf_h_pc_get (current_cpu
));
72 SETTWI (buf
, m32rxf_h_pc_get (current_cpu
));
75 if (mach
== MACH_M32R
)
76 SETTWI (buf
, GETLODI (m32rbf_h_accum_get (current_cpu
)));
78 SETTWI (buf
, GETLODI (m32rxf_h_accum_get (current_cpu
)));
81 if (mach
== MACH_M32R
)
82 SETTWI (buf
, GETHIDI (m32rbf_h_accum_get (current_cpu
)));
84 SETTWI (buf
, GETHIDI (m32rxf_h_accum_get (current_cpu
)));
93 /* The contents of BUF are in target byte order. */
96 m32rbf_store_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
98 int mach
= MACH_NUM (CPU_MACH (current_cpu
));
101 a_m32r_h_gr_set (current_cpu
, rn
, GETTWI (buf
));
112 a_m32r_h_cr_set (current_cpu
,
113 m32r_decode_gdb_ctrl_regnum (rn
),
117 if (mach
== MACH_M32R
)
118 m32rbf_h_pc_set (current_cpu
, GETTWI (buf
));
120 m32rxf_h_pc_set (current_cpu
, GETTWI (buf
));
125 if (mach
== MACH_M32R
)
126 val
= m32rbf_h_accum_get (current_cpu
);
128 val
= m32rxf_h_accum_get (current_cpu
);
129 SETLODI (val
, GETTWI (buf
));
130 if (mach
== MACH_M32R
)
131 m32rbf_h_accum_set (current_cpu
, val
);
133 m32rxf_h_accum_set (current_cpu
, val
);
139 if (mach
== MACH_M32R
)
140 val
= m32rbf_h_accum_get (current_cpu
);
142 val
= m32rxf_h_accum_get (current_cpu
);
143 SETHIDI (val
, GETTWI (buf
));
144 if (mach
== MACH_M32R
)
145 m32rbf_h_accum_set (current_cpu
, val
);
147 m32rxf_h_accum_set (current_cpu
, val
);
157 /* Cover fns for mach independent register accesses. */
160 a_m32r_h_gr_get (SIM_CPU
*current_cpu
, UINT regno
)
162 switch (MACH_NUM (CPU_MACH (current_cpu
)))
164 #ifdef HAVE_CPU_M32RBF
166 return m32rbf_h_gr_get (current_cpu
, regno
);
168 #ifdef HAVE_CPU_M32RXF
170 return m32rxf_h_gr_get (current_cpu
, regno
);
178 a_m32r_h_gr_set (SIM_CPU
*current_cpu
, UINT regno
, SI newval
)
180 switch (MACH_NUM (CPU_MACH (current_cpu
)))
182 #ifdef HAVE_CPU_M32RBF
184 m32rbf_h_gr_set (current_cpu
, regno
, newval
);
187 #ifdef HAVE_CPU_M32RXF
189 m32rxf_h_gr_set (current_cpu
, regno
, newval
);
198 a_m32r_h_cr_get (SIM_CPU
*current_cpu
, UINT regno
)
200 switch (MACH_NUM (CPU_MACH (current_cpu
)))
202 #ifdef HAVE_CPU_M32RBF
204 return m32rbf_h_cr_get (current_cpu
, regno
);
206 #ifdef HAVE_CPU_M32RXF
208 return m32rxf_h_cr_get (current_cpu
, regno
);
216 a_m32r_h_cr_set (SIM_CPU
*current_cpu
, UINT regno
, USI newval
)
218 switch (MACH_NUM (CPU_MACH (current_cpu
)))
220 #ifdef HAVE_CPU_M32RBF
222 m32rbf_h_cr_set (current_cpu
, regno
, newval
);
225 #ifdef HAVE_CPU_M32RXF
227 m32rxf_h_cr_set (current_cpu
, regno
, newval
);
236 m32rbf_h_cr_get_handler (SIM_CPU
*current_cpu
, UINT cr
)
240 case H_CR_PSW
: /* psw */
241 return (((CPU (h_bpsw
) & 0xc1) << 8)
242 | ((CPU (h_psw
) & 0xc0) << 0)
244 case H_CR_BBPSW
: /* backup backup psw */
245 return CPU (h_bbpsw
) & 0xc1;
246 case H_CR_CBR
: /* condition bit */
247 return GET_H_COND ();
248 case H_CR_SPI
: /* interrupt stack pointer */
250 return CPU (h_gr
[H_GR_SP
]);
252 return CPU (h_cr
[H_CR_SPI
]);
253 case H_CR_SPU
: /* user stack pointer */
255 return CPU (h_gr
[H_GR_SP
]);
257 return CPU (h_cr
[H_CR_SPU
]);
258 case H_CR_BPC
: /* backup pc */
259 return CPU (h_cr
[H_CR_BPC
]) & 0xfffffffe;
260 case H_CR_BBPC
: /* backup backup pc */
261 return CPU (h_cr
[H_CR_BBPC
]) & 0xfffffffe;
262 case 4 : /* ??? unspecified, but apparently available */
263 case 5 : /* ??? unspecified, but apparently available */
264 return CPU (h_cr
[cr
]);
271 m32rbf_h_cr_set_handler (SIM_CPU
*current_cpu
, UINT cr
, USI newval
)
275 case H_CR_PSW
: /* psw */
277 int old_sm
= (CPU (h_psw
) & 0x80) != 0;
278 int new_sm
= (newval
& 0x80) != 0;
279 CPU (h_bpsw
) = (newval
>> 8) & 0xff;
280 CPU (h_psw
) = newval
& 0xff;
281 SET_H_COND (newval
& 1);
282 /* When switching stack modes, update the registers. */
283 if (old_sm
!= new_sm
)
287 /* Switching user -> system. */
288 CPU (h_cr
[H_CR_SPU
]) = CPU (h_gr
[H_GR_SP
]);
289 CPU (h_gr
[H_GR_SP
]) = CPU (h_cr
[H_CR_SPI
]);
293 /* Switching system -> user. */
294 CPU (h_cr
[H_CR_SPI
]) = CPU (h_gr
[H_GR_SP
]);
295 CPU (h_gr
[H_GR_SP
]) = CPU (h_cr
[H_CR_SPU
]);
300 case H_CR_BBPSW
: /* backup backup psw */
301 CPU (h_bbpsw
) = newval
& 0xff;
303 case H_CR_CBR
: /* condition bit */
304 SET_H_COND (newval
& 1);
306 case H_CR_SPI
: /* interrupt stack pointer */
308 CPU (h_gr
[H_GR_SP
]) = newval
;
310 CPU (h_cr
[H_CR_SPI
]) = newval
;
312 case H_CR_SPU
: /* user stack pointer */
314 CPU (h_gr
[H_GR_SP
]) = newval
;
316 CPU (h_cr
[H_CR_SPU
]) = newval
;
318 case H_CR_BPC
: /* backup pc */
319 CPU (h_cr
[H_CR_BPC
]) = newval
;
321 case H_CR_BBPC
: /* backup backup pc */
322 CPU (h_cr
[H_CR_BBPC
]) = newval
;
324 case 4 : /* ??? unspecified, but apparently available */
325 case 5 : /* ??? unspecified, but apparently available */
326 CPU (h_cr
[cr
]) = newval
;
334 /* Cover fns to access h-psw. */
337 m32rbf_h_psw_get_handler (SIM_CPU
*current_cpu
)
339 return (CPU (h_psw
) & 0xfe) | (CPU (h_cond
) & 1);
343 m32rbf_h_psw_set_handler (SIM_CPU
*current_cpu
, UQI newval
)
345 CPU (h_psw
) = newval
;
346 CPU (h_cond
) = newval
& 1;
349 /* Cover fns to access h-accum. */
352 m32rbf_h_accum_get_handler (SIM_CPU
*current_cpu
)
354 /* Sign extend the top 8 bits. */
357 r
= ANDDI (CPU (h_accum
), MAKEDI (0xffffff, 0xffffffff));
358 r
= XORDI (r
, MAKEDI (0x800000, 0));
359 r
= SUBDI (r
, MAKEDI (0x800000, 0));
365 hi
= ((hi
& 0xffffff) ^ 0x800000) - 0x800000;
372 m32rbf_h_accum_set_handler (SIM_CPU
*current_cpu
, DI newval
)
374 CPU (h_accum
) = newval
;
377 #if WITH_PROFILE_MODEL_P
379 /* FIXME: Some of these should be inline or macros. Later. */
381 /* Initialize cycle counting for an insn.
382 FIRST_P is non-zero if this is the first insn in a set of parallel
386 m32rbf_model_insn_before (SIM_CPU
*cpu
, int first_p
)
388 M32R_MISC_PROFILE
*mp
= CPU_M32R_MISC_PROFILE (cpu
);
393 mp
->load_regs_pending
= 0;
394 mp
->biggest_cycles
= 0;
398 /* Record the cycles computed for an insn.
399 LAST_P is non-zero if this is the last insn in a set of parallel insns,
400 and we update the total cycle count.
401 CYCLES is the cycle count of the insn. */
404 m32rbf_model_insn_after (SIM_CPU
*cpu
, int last_p
, int cycles
)
406 PROFILE_DATA
*p
= CPU_PROFILE_DATA (cpu
);
407 M32R_MISC_PROFILE
*mp
= CPU_M32R_MISC_PROFILE (cpu
);
408 unsigned long total
= cycles
+ mp
->cti_stall
+ mp
->load_stall
;
412 unsigned long biggest
= total
> mp
->biggest_cycles
? total
: mp
->biggest_cycles
;
413 PROFILE_MODEL_TOTAL_CYCLES (p
) += biggest
;
414 PROFILE_MODEL_CUR_INSN_CYCLES (p
) = total
;
418 /* Here we take advantage of the fact that !last_p -> first_p. */
419 mp
->biggest_cycles
= total
;
420 PROFILE_MODEL_CUR_INSN_CYCLES (p
) = total
;
423 /* Branch and load stall counts are recorded independently of the
424 total cycle count. */
425 PROFILE_MODEL_CTI_STALL_CYCLES (p
) += mp
->cti_stall
;
426 PROFILE_MODEL_LOAD_STALL_CYCLES (p
) += mp
->load_stall
;
428 mp
->load_regs
= mp
->load_regs_pending
;
432 check_load_stall (SIM_CPU
*cpu
, int regno
)
434 UINT h_gr
= CPU_M32R_MISC_PROFILE (cpu
)->load_regs
;
437 && (h_gr
& (1 << regno
)) != 0)
439 CPU_M32R_MISC_PROFILE (cpu
)->load_stall
+= 2;
440 if (TRACE_INSN_P (cpu
))
441 cgen_trace_printf (cpu
, " ; Load stall of 2 cycles.");
446 m32rbf_model_m32r_d_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
447 int unit_num
, int referenced
,
448 INT sr
, INT sr2
, INT dr
)
450 check_load_stall (cpu
, sr
);
451 check_load_stall (cpu
, sr2
);
452 return idesc
->timing
->units
[unit_num
].done
;
456 m32rbf_model_m32r_d_u_cmp (SIM_CPU
*cpu
, const IDESC
*idesc
,
457 int unit_num
, int referenced
,
460 check_load_stall (cpu
, src1
);
461 check_load_stall (cpu
, src2
);
462 return idesc
->timing
->units
[unit_num
].done
;
466 m32rbf_model_m32r_d_u_mac (SIM_CPU
*cpu
, const IDESC
*idesc
,
467 int unit_num
, int referenced
,
470 check_load_stall (cpu
, src1
);
471 check_load_stall (cpu
, src2
);
472 return idesc
->timing
->units
[unit_num
].done
;
476 m32rbf_model_m32r_d_u_cti (SIM_CPU
*cpu
, const IDESC
*idesc
,
477 int unit_num
, int referenced
,
480 PROFILE_DATA
*profile
= CPU_PROFILE_DATA (cpu
);
481 int taken_p
= (referenced
& (1 << 1)) != 0;
483 check_load_stall (cpu
, sr
);
486 CPU_M32R_MISC_PROFILE (cpu
)->cti_stall
+= 2;
487 PROFILE_MODEL_TAKEN_COUNT (profile
) += 1;
490 PROFILE_MODEL_UNTAKEN_COUNT (profile
) += 1;
491 return idesc
->timing
->units
[unit_num
].done
;
495 m32rbf_model_m32r_d_u_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
496 int unit_num
, int referenced
,
499 CPU_M32R_MISC_PROFILE (cpu
)->load_regs_pending
|= (1 << dr
);
500 check_load_stall (cpu
, sr
);
501 return idesc
->timing
->units
[unit_num
].done
;
505 m32rbf_model_m32r_d_u_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
506 int unit_num
, int referenced
,
509 check_load_stall (cpu
, src1
);
510 check_load_stall (cpu
, src2
);
511 return idesc
->timing
->units
[unit_num
].done
;
515 m32rbf_model_test_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
516 int unit_num
, int referenced
)
518 return idesc
->timing
->units
[unit_num
].done
;
521 #endif /* WITH_PROFILE_MODEL_P */
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