1 /* m32r simulator support code
2 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 #include "libiberty.h"
28 /* FIXME: need to provide general mechanism for accessing target files
29 these. For now this is a hack to avoid getting the host version. */
30 #include "../../libgloss/m32r/sys/syscall.h"
31 #include "targ-vals.h"
33 /* The contents of BUF are in target byte order. */
36 m32r_fetch_register (sd
, rn
, buf
)
41 SIM_CPU
*current_cpu
= STATE_CPU (sd
, 0);
44 SETTWI (buf
, GET_H_GR (rn
));
46 SETTWI (buf
, GET_H_CR (rn
- 16));
49 SETTWI (buf
, GET_H_PC ());
52 SETTWI (buf
, GETLODI (GET_H_ACCUM ()));
55 SETTWI (buf
, GETHIDI (GET_H_ACCUM ()));
58 case 23: *reg
= STATE_CPU_CPU (sd
, 0)->h_cond
; break;
59 case 24: *reg
= STATE_CPU_CPU (sd
, 0)->h_sm
; break;
60 case 25: *reg
= STATE_CPU_CPU (sd
, 0)->h_bsm
; break;
61 case 26: *reg
= STATE_CPU_CPU (sd
, 0)->h_ie
; break;
62 case 27: *reg
= STATE_CPU_CPU (sd
, 0)->h_bie
; break;
63 case 28: *reg
= STATE_CPU_CPU (sd
, 0)->h_bcarry
; break; /* rename: bc */
64 case 29: memcpy (buf
, &STATE_CPU_CPU (sd
, 0)->h_bpc
, sizeof(WI
)); break; /* duplicate */
70 /* The contents of BUF are in target byte order. */
73 m32r_store_register (sd
, rn
, buf
)
78 SIM_CPU
*current_cpu
= STATE_CPU (sd
, 0);
81 SET_H_GR (rn
, GETTWI (buf
));
83 SET_H_CR (rn
- 16, GETTWI (buf
));
86 SET_H_PC (GETTWI (buf
));
89 SETLODI (CPU (h_accum
), GETTWI (buf
));
92 SETHIDI (CPU (h_accum
), GETTWI (buf
));
95 case 23: STATE_CPU_CPU (sd
, 0)->h_cond
= *reg
; break;
96 case 24: STATE_CPU_CPU (sd
, 0)->h_sm
= *reg
; break;
97 case 25: STATE_CPU_CPU (sd
, 0)->h_bsm
= *reg
; break;
98 case 26: STATE_CPU_CPU (sd
, 0)->h_ie
= *reg
; break;
99 case 27: STATE_CPU_CPU (sd
, 0)->h_bie
= *reg
; break;
100 case 28: STATE_CPU_CPU (sd
, 0)->h_bcarry
= *reg
; break; /* rename: bc */
101 case 29: memcpy (&STATE_CPU_CPU (sd
, 0)->h_bpc
, buf
, sizeof(DI
)); break; /* duplicate */
106 /* Handling the MSPR register is done by creating a device in the core
107 mapping that winds up here. */
109 device m32r_mspr_device
;
112 device_io_read_buffer (device
*me
, const void *source
, int space
,
113 address_word addr
, unsigned nr_bytes
,
114 SIM_CPU
*cpu
, sim_cia cia
)
120 device_io_write_buffer (device
*me
, const void *source
, int space
,
121 address_word addr
, unsigned nr_bytes
,
122 SIM_CPU
*cpu
, sim_cia cia
)
125 if (addr
== MSPR_ADDR
126 && (*(char *) source
& 1) != 0)
127 scache_flush (CPU_STATE (cpu
));
132 void device_error () {}
134 #if WITH_PROFILE_MODEL_P
137 m32r_model_mark_get_h_gr (SIM_CPU
*cpu
, ARGBUF
*abuf
)
139 if ((CPU_CGEN_PROFILE (cpu
)->h_gr
& abuf
->h_gr_get
) != 0)
141 PROFILE_MODEL_LOAD_STALL_COUNT (CPU_PROFILE_DATA (cpu
)) += 2;
142 if (TRACE_INSN_P (cpu
))
143 cgen_trace_printf (cpu
, " ; Load stall of 2 cycles.");
148 m32r_model_mark_set_h_gr (SIM_CPU
*cpu
, ARGBUF
*abuf
)
153 m32r_model_mark_busy_reg (SIM_CPU
*cpu
, ARGBUF
*abuf
)
155 CPU_CGEN_PROFILE (cpu
)->h_gr
= abuf
->h_gr_set
;
159 m32r_model_mark_unbusy_reg (SIM_CPU
*cpu
, ARGBUF
*abuf
)
161 CPU_CGEN_PROFILE (cpu
)->h_gr
= 0;
164 #endif /* WITH_PROFILE_MODEL_P */
167 m32r_h_cr_get (SIM_CPU
*current_cpu
, UINT cr
)
169 /* FIXME: Create enums H_CR_FOO, etc. */
173 return ((CPU (h_bsm
) << 15)
174 | (CPU (h_bie
) << 14)
175 | (CPU (h_bcond
) << 8)
178 | (CPU (h_cond
) << 0));
179 case 1 : /* condition bit */
181 case 2 : /* interrupt stack pointer */
183 return CPU (h_gr
[15]);
185 return CPU (h_cr
[2]);
186 case 3 : /* user stack pointer */
188 return CPU (h_gr
[15]);
190 return CPU (h_cr
[3]);
191 case 6 : /* backup pc */
192 /* ??? We don't really support this yet. */
193 case 4 : /* unused */
194 case 5 : /* unused */
195 return CPU (h_cr
[cr
]);
202 m32r_h_cr_set (SIM_CPU
*current_cpu
, UINT cr
, USI newval
)
204 /* FIXME: Create enums H_CR_FOO, etc. */
209 int old_sm
= CPU (h_sm
);
210 CPU (h_bsm
) = (newval
& (1 << 15)) != 0;
211 CPU (h_bie
) = (newval
& (1 << 14)) != 0;
212 CPU (h_bcond
) = (newval
& (1 << 8)) != 0;
213 CPU (h_sm
) = (newval
& (1 << 7)) != 0;
214 CPU (h_ie
) = (newval
& (1 << 6)) != 0;
215 CPU (h_cond
) = (newval
& (1 << 0)) != 0;
216 /* When switching stack modes, update the registers. */
217 if (old_sm
!= CPU (h_sm
))
221 /* Switching user -> system. */
222 CPU (h_cr
[3]) = CPU (h_gr
[15]);
223 CPU (h_gr
[15]) = CPU (h_cr
[2]);
227 /* Switching system -> user. */
228 CPU (h_cr
[2]) = CPU (h_gr
[15]);
229 CPU (h_gr
[15]) = CPU (h_cr
[3]);
234 case 1 : /* condition bit */
235 CPU (h_cond
) = (newval
& 1) != 0;
237 case 2 : /* interrupt stack pointer */
239 CPU (h_gr
[15]) = newval
;
241 CPU (h_cr
[2]) = newval
;
243 case 3 : /* user stack pointer */
245 CPU (h_gr
[15]) = newval
;
247 CPU (h_cr
[3]) = newval
;
249 case 4 : /* unused */
250 case 5 : /* unused */
251 case 6 : /* backup pc */
252 CPU (h_cr
[cr
]) = newval
;
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