sim/m32r/m32r.c

   1 /* m32r simulator support code
   2    Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #define WANT_CPU m32rbf
  22 #define WANT_CPU_M32RBF
  23
  24 #include "sim-main.h"
  25 #include "cgen-mem.h"
  26 #include "cgen-ops.h"
  27
  28 /* Decode gdb ctrl register number.  */
  29
  30 int
  31 m32r_decode_gdb_ctrl_regnum (int gdb_regnum)
  32 {
  33   switch (gdb_regnum)
  34     {
  35       case PSW_REGNUM : return H_CR_PSW;
  36       case CBR_REGNUM : return H_CR_CBR;
  37       case SPI_REGNUM : return H_CR_SPI;
  38       case SPU_REGNUM : return H_CR_SPU;
  39       case BPC_REGNUM : return H_CR_BPC;
  40       case BBPSW_REGNUM : return H_CR_BBPSW;
  41       case BBPC_REGNUM : return H_CR_BBPC;
  42       case EVB_REGNUM : return H_CR_CR5;
  43     }
  44   abort ();
  45 }
  46
  47 /* The contents of BUF are in target byte order.  */
  48
  49 int
  50 m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
  51 {
  52   int mach = MACH_NUM (CPU_MACH (current_cpu));
  53
  54   if (rn < 16)
  55     SETTWI (buf, a_m32r_h_gr_get (current_cpu, rn));
  56   else
  57     switch (rn)
  58       {
  59       case PSW_REGNUM :
  60       case CBR_REGNUM :
  61       case SPI_REGNUM :
  62       case SPU_REGNUM :
  63       case BPC_REGNUM :
  64       case BBPSW_REGNUM :
  65       case BBPC_REGNUM :
  66       case EVB_REGNUM :
  67         SETTWI (buf, a_m32r_h_cr_get (current_cpu,
  68                                       m32r_decode_gdb_ctrl_regnum (rn)));
  69         break;
  70       case PC_REGNUM :
  71         if (mach == MACH_M32R)
  72           SETTWI (buf, m32rbf_h_pc_get (current_cpu));
  73         else if (mach == MACH_M32RX)
  74           SETTWI (buf, m32rxf_h_pc_get (current_cpu));
  75         else
  76           SETTWI (buf, m32r2f_h_pc_get (current_cpu));
  77         break;
  78       case ACCL_REGNUM :
  79         if (mach == MACH_M32R)
  80           SETTWI (buf, GETLODI (m32rbf_h_accum_get (current_cpu)));
  81         else if (mach == MACH_M32RX)
  82           SETTWI (buf, GETLODI (m32rxf_h_accum_get (current_cpu)));
  83         else
  84           SETTWI (buf, GETLODI (m32r2f_h_accum_get (current_cpu)));
  85         break;
  86       case ACCH_REGNUM :
  87         if (mach == MACH_M32R)
  88           SETTWI (buf, GETHIDI (m32rbf_h_accum_get (current_cpu)));
  89         else if (mach == MACH_M32RX)
  90           SETTWI (buf, GETHIDI (m32rxf_h_accum_get (current_cpu)));
  91         else
  92           SETTWI (buf, GETHIDI (m32r2f_h_accum_get (current_cpu)));
  93         break;
  94       default :
  95         return 0;
  96       }
  97
  98   return -1; /*FIXME*/
  99 }
 100
 101 /* The contents of BUF are in target byte order.  */
 102
 103 int
 104 m32rbf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
 105 {
 106   int mach = MACH_NUM (CPU_MACH (current_cpu));
 107
 108   if (rn < 16)
 109     a_m32r_h_gr_set (current_cpu, rn, GETTWI (buf));
 110   else
 111     switch (rn)
 112       {
 113       case PSW_REGNUM :
 114       case CBR_REGNUM :
 115       case SPI_REGNUM :
 116       case SPU_REGNUM :
 117       case BPC_REGNUM :
 118       case BBPSW_REGNUM :
 119       case BBPC_REGNUM :
 120       case EVB_REGNUM :
 121         a_m32r_h_cr_set (current_cpu,
 122                          m32r_decode_gdb_ctrl_regnum (rn),
 123                          GETTWI (buf));
 124         break;
 125       case PC_REGNUM :
 126         if (mach == MACH_M32R)
 127           m32rbf_h_pc_set (current_cpu, GETTWI (buf));
 128         else if (mach == MACH_M32RX)
 129           m32rxf_h_pc_set (current_cpu, GETTWI (buf));
 130         else
 131           m32r2f_h_pc_set (current_cpu, GETTWI (buf));
 132         break;
 133       case ACCL_REGNUM :
 134         {
 135           DI val;
 136           if (mach == MACH_M32R)
 137             val = m32rbf_h_accum_get (current_cpu);
 138           else if (mach == MACH_M32RX)
 139             val = m32rxf_h_accum_get (current_cpu);
 140           else
 141             val = m32r2f_h_accum_get (current_cpu);
 142           SETLODI (val, GETTWI (buf));
 143           if (mach == MACH_M32R)
 144             m32rbf_h_accum_set (current_cpu, val);
 145           else if (mach == MACH_M32RX)
 146             m32rxf_h_accum_set (current_cpu, val);
 147           else
 148             m32r2f_h_accum_set (current_cpu, val);
 149           break;
 150         }
 151       case ACCH_REGNUM :
 152         {
 153           DI val;
 154           if (mach == MACH_M32R)
 155             val = m32rbf_h_accum_get (current_cpu);
 156           else if (mach == MACH_M32RX)
 157             val = m32rxf_h_accum_get (current_cpu);
 158           else
 159             val = m32r2f_h_accum_get (current_cpu);
 160           SETHIDI (val, GETTWI (buf));
 161           if (mach == MACH_M32R)
 162             m32rbf_h_accum_set (current_cpu, val);
 163           else if (mach == MACH_M32RX)
 164             m32rxf_h_accum_set (current_cpu, val);
 165           else
 166             m32r2f_h_accum_set (current_cpu, val);
 167           break;
 168         }
 169       default :
 170         return 0;
 171       }
 172
 173   return -1; /*FIXME*/
 174 }
 175 \f
 176 /* Cover fns for mach independent register accesses.  */
 177
 178 SI
 179 a_m32r_h_gr_get (SIM_CPU *current_cpu, UINT regno)
 180 {
 181   switch (MACH_NUM (CPU_MACH (current_cpu)))
 182     {
 183 #ifdef HAVE_CPU_M32RBF
 184     case MACH_M32R :
 185       return m32rbf_h_gr_get (current_cpu, regno);
 186 #endif
 187 #ifdef HAVE_CPU_M32RXF
 188     case MACH_M32RX :
 189       return m32rxf_h_gr_get (current_cpu, regno);
 190 #endif
 191 #ifdef HAVE_CPU_M32R2F
 192     case MACH_M32R2 :
 193       return m32r2f_h_gr_get (current_cpu, regno);
 194 #endif
 195     default :
 196       abort ();
 197     }
 198 }
 199
 200 void
 201 a_m32r_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
 202 {
 203   switch (MACH_NUM (CPU_MACH (current_cpu)))
 204     {
 205 #ifdef HAVE_CPU_M32RBF
 206     case MACH_M32R :
 207       m32rbf_h_gr_set (current_cpu, regno, newval);
 208       break;
 209 #endif
 210 #ifdef HAVE_CPU_M32RXF
 211     case MACH_M32RX :
 212       m32rxf_h_gr_set (current_cpu, regno, newval);
 213       break;
 214 #endif
 215 #ifdef HAVE_CPU_M32RXF
 216     case MACH_M32R2 :
 217       m32r2f_h_gr_set (current_cpu, regno, newval);
 218       break;
 219 #endif
 220     default :
 221       abort ();
 222     }
 223 }
 224
 225 USI
 226 a_m32r_h_cr_get (SIM_CPU *current_cpu, UINT regno)
 227 {
 228   switch (MACH_NUM (CPU_MACH (current_cpu)))
 229     {
 230 #ifdef HAVE_CPU_M32RBF
 231     case MACH_M32R :
 232       return m32rbf_h_cr_get (current_cpu, regno);
 233 #endif
 234 #ifdef HAVE_CPU_M32RXF
 235     case MACH_M32RX :
 236       return m32rxf_h_cr_get (current_cpu, regno);
 237 #endif
 238 #ifdef HAVE_CPU_M32R2F
 239     case MACH_M32R2 :
 240       return m32r2f_h_cr_get (current_cpu, regno);
 241 #endif
 242     default :
 243       abort ();
 244     }
 245 }
 246
 247 void
 248 a_m32r_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
 249 {
 250   switch (MACH_NUM (CPU_MACH (current_cpu)))
 251     {
 252 #ifdef HAVE_CPU_M32RBF
 253     case MACH_M32R :
 254       m32rbf_h_cr_set (current_cpu, regno, newval);
 255       break;
 256 #endif
 257 #ifdef HAVE_CPU_M32RXF
 258     case MACH_M32RX :
 259       m32rxf_h_cr_set (current_cpu, regno, newval);
 260       break;
 261 #endif
 262 #ifdef HAVE_CPU_M32RXF
 263     case MACH_M32R2 :
 264       m32r2f_h_cr_set (current_cpu, regno, newval);
 265       break;
 266 #endif
 267     default :
 268       abort ();
 269     }
 270 }
 271 \f
 272 USI
 273 m32rbf_h_cr_get_handler (SIM_CPU *current_cpu, UINT cr)
 274 {
 275   switch (cr)
 276     {
 277     case H_CR_PSW : /* psw */
 278       return (((CPU (h_bpsw) & 0xc1) << 8)
 279               | ((CPU (h_psw) & 0xc0) << 0)
 280               | GET_H_COND ());
 281     case H_CR_BBPSW : /* backup backup psw */
 282       return CPU (h_bbpsw) & 0xc1;
 283     case H_CR_CBR : /* condition bit */
 284       return GET_H_COND ();
 285     case H_CR_SPI : /* interrupt stack pointer */
 286       if (! GET_H_SM ())
 287         return CPU (h_gr[H_GR_SP]);
 288       else
 289         return CPU (h_cr[H_CR_SPI]);
 290     case H_CR_SPU : /* user stack pointer */
 291       if (GET_H_SM ())
 292         return CPU (h_gr[H_GR_SP]);
 293       else
 294         return CPU (h_cr[H_CR_SPU]);
 295     case H_CR_BPC : /* backup pc */
 296       return CPU (h_cr[H_CR_BPC]) & 0xfffffffe;
 297     case H_CR_BBPC : /* backup backup pc */
 298       return CPU (h_cr[H_CR_BBPC]) & 0xfffffffe;
 299     case 4 : /* ??? unspecified, but apparently available */
 300     case 5 : /* ??? unspecified, but apparently available */
 301       return CPU (h_cr[cr]);
 302     default :
 303       return 0;
 304     }
 305 }
 306
 307 void
 308 m32rbf_h_cr_set_handler (SIM_CPU *current_cpu, UINT cr, USI newval)
 309 {
 310   switch (cr)
 311     {
 312     case H_CR_PSW : /* psw */
 313       {
 314         int old_sm = (CPU (h_psw) & 0x80) != 0;
 315         int new_sm = (newval & 0x80) != 0;
 316         CPU (h_bpsw) = (newval >> 8) & 0xff;
 317         CPU (h_psw) = newval & 0xff;
 318         SET_H_COND (newval & 1);
 319         /* When switching stack modes, update the registers.  */
 320         if (old_sm != new_sm)
 321           {
 322             if (old_sm)
 323               {
 324                 /* Switching user -> system.  */
 325                 CPU (h_cr[H_CR_SPU]) = CPU (h_gr[H_GR_SP]);
 326                 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPI]);
 327               }
 328             else
 329               {
 330                 /* Switching system -> user.  */
 331                 CPU (h_cr[H_CR_SPI]) = CPU (h_gr[H_GR_SP]);
 332                 CPU (h_gr[H_GR_SP]) = CPU (h_cr[H_CR_SPU]);
 333               }
 334           }
 335         break;
 336       }
 337     case H_CR_BBPSW : /* backup backup psw */
 338       CPU (h_bbpsw) = newval & 0xff;
 339       break;
 340     case H_CR_CBR : /* condition bit */
 341       SET_H_COND (newval & 1);
 342       break;
 343     case H_CR_SPI : /* interrupt stack pointer */
 344       if (! GET_H_SM ())
 345         CPU (h_gr[H_GR_SP]) = newval;
 346       else
 347         CPU (h_cr[H_CR_SPI]) = newval;
 348       break;
 349     case H_CR_SPU : /* user stack pointer */
 350       if (GET_H_SM ())
 351         CPU (h_gr[H_GR_SP]) = newval;
 352       else
 353         CPU (h_cr[H_CR_SPU]) = newval;
 354       break;
 355     case H_CR_BPC : /* backup pc */
 356       CPU (h_cr[H_CR_BPC]) = newval;
 357       break;
 358     case H_CR_BBPC : /* backup backup pc */
 359       CPU (h_cr[H_CR_BBPC]) = newval;
 360       break;
 361     case 4 : /* ??? unspecified, but apparently available */
 362     case 5 : /* ??? unspecified, but apparently available */
 363       CPU (h_cr[cr]) = newval;
 364       break;
 365     default :
 366       /* ignore */
 367       break;
 368     }
 369 }
 370
 371 /* Cover fns to access h-psw.  */
 372
 373 UQI
 374 m32rbf_h_psw_get_handler (SIM_CPU *current_cpu)
 375 {
 376   return (CPU (h_psw) & 0xfe) | (CPU (h_cond) & 1);
 377 }
 378
 379 void
 380 m32rbf_h_psw_set_handler (SIM_CPU *current_cpu, UQI newval)
 381 {
 382   CPU (h_psw) = newval;
 383   CPU (h_cond) = newval & 1;
 384 }
 385
 386 /* Cover fns to access h-accum.  */
 387
 388 DI
 389 m32rbf_h_accum_get_handler (SIM_CPU *current_cpu)
 390 {
 391   /* Sign extend the top 8 bits.  */
 392   DI r;
 393 #if 1
 394   r = ANDDI (CPU (h_accum), MAKEDI (0xffffff, 0xffffffff));
 395   r = XORDI (r, MAKEDI (0x800000, 0));
 396   r = SUBDI (r, MAKEDI (0x800000, 0));
 397 #else
 398   SI hi,lo;
 399   r = CPU (h_accum);
 400   hi = GETHIDI (r);
 401   lo = GETLODI (r);
 402   hi = ((hi & 0xffffff) ^ 0x800000) - 0x800000;
 403   r = MAKEDI (hi, lo);
 404 #endif
 405   return r;
 406 }
 407
 408 void
 409 m32rbf_h_accum_set_handler (SIM_CPU *current_cpu, DI newval)
 410 {
 411   CPU (h_accum) = newval;
 412 }
 413 \f
 414 #if WITH_PROFILE_MODEL_P
 415
 416 /* FIXME: Some of these should be inline or macros.  Later.  */
 417
 418 /* Initialize cycle counting for an insn.
 419    FIRST_P is non-zero if this is the first insn in a set of parallel
 420    insns.  */
 421
 422 void
 423 m32rbf_model_insn_before (SIM_CPU *cpu, int first_p)
 424 {
 425   M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
 426   mp->cti_stall = 0;
 427   mp->load_stall = 0;
 428   if (first_p)
 429     {
 430       mp->load_regs_pending = 0;
 431       mp->biggest_cycles = 0;
 432     }
 433 }
 434
 435 /* Record the cycles computed for an insn.
 436    LAST_P is non-zero if this is the last insn in a set of parallel insns,
 437    and we update the total cycle count.
 438    CYCLES is the cycle count of the insn.  */
 439
 440 void
 441 m32rbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
 442 {
 443   PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
 444   M32R_MISC_PROFILE *mp = CPU_M32R_MISC_PROFILE (cpu);
 445   unsigned long total = cycles + mp->cti_stall + mp->load_stall;
 446
 447   if (last_p)
 448     {
 449       unsigned long biggest = total > mp->biggest_cycles ? total : mp->biggest_cycles;
 450       PROFILE_MODEL_TOTAL_CYCLES (p) += biggest;
 451       PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
 452     }
 453   else
 454     {
 455       /* Here we take advantage of the fact that !last_p -> first_p.  */
 456       mp->biggest_cycles = total;
 457       PROFILE_MODEL_CUR_INSN_CYCLES (p) = total;
 458     }
 459
 460   /* Branch and load stall counts are recorded independently of the
 461      total cycle count.  */
 462   PROFILE_MODEL_CTI_STALL_CYCLES (p) += mp->cti_stall;
 463   PROFILE_MODEL_LOAD_STALL_CYCLES (p) += mp->load_stall;
 464
 465   mp->load_regs = mp->load_regs_pending;
 466 }
 467
 468 static INLINE void
 469 check_load_stall (SIM_CPU *cpu, int regno)
 470 {
 471   UINT h_gr = CPU_M32R_MISC_PROFILE (cpu)->load_regs;
 472
 473   if (regno != -1
 474       && (h_gr & (1 << regno)) != 0)
 475     {
 476       CPU_M32R_MISC_PROFILE (cpu)->load_stall += 2;
 477       if (TRACE_INSN_P (cpu))
 478         cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
 479     }
 480 }
 481
 482 int
 483 m32rbf_model_m32r_d_u_exec (SIM_CPU *cpu, const IDESC *idesc,
 484                             int unit_num, int referenced,
 485                             INT sr, INT sr2, INT dr)
 486 {
 487   check_load_stall (cpu, sr);
 488   check_load_stall (cpu, sr2);
 489   return idesc->timing->units[unit_num].done;
 490 }
 491
 492 int
 493 m32rbf_model_m32r_d_u_cmp (SIM_CPU *cpu, const IDESC *idesc,
 494                            int unit_num, int referenced,
 495                            INT src1, INT src2)
 496 {
 497   check_load_stall (cpu, src1);
 498   check_load_stall (cpu, src2);
 499   return idesc->timing->units[unit_num].done;
 500 }
 501
 502 int
 503 m32rbf_model_m32r_d_u_mac (SIM_CPU *cpu, const IDESC *idesc,
 504                            int unit_num, int referenced,
 505                            INT src1, INT src2)
 506 {
 507   check_load_stall (cpu, src1);
 508   check_load_stall (cpu, src2);
 509   return idesc->timing->units[unit_num].done;
 510 }
 511
 512 int
 513 m32rbf_model_m32r_d_u_cti (SIM_CPU *cpu, const IDESC *idesc,
 514                            int unit_num, int referenced,
 515                            INT sr)
 516 {
 517   PROFILE_DATA *profile = CPU_PROFILE_DATA (cpu);
 518   int taken_p = (referenced & (1 << 1)) != 0;
 519
 520   check_load_stall (cpu, sr);
 521   if (taken_p)
 522     {
 523       CPU_M32R_MISC_PROFILE (cpu)->cti_stall += 2;
 524       PROFILE_MODEL_TAKEN_COUNT (profile) += 1;
 525     }
 526   else
 527     PROFILE_MODEL_UNTAKEN_COUNT (profile) += 1;
 528   return idesc->timing->units[unit_num].done;
 529 }
 530
 531 int
 532 m32rbf_model_m32r_d_u_load (SIM_CPU *cpu, const IDESC *idesc,
 533                             int unit_num, int referenced,
 534                             INT sr, INT dr)
 535 {
 536   CPU_M32R_MISC_PROFILE (cpu)->load_regs_pending |= (1 << dr);
 537   check_load_stall (cpu, sr);
 538   return idesc->timing->units[unit_num].done;
 539 }
 540
 541 int
 542 m32rbf_model_m32r_d_u_store (SIM_CPU *cpu, const IDESC *idesc,
 543                              int unit_num, int referenced,
 544                              INT src1, INT src2)
 545 {
 546   check_load_stall (cpu, src1);
 547   check_load_stall (cpu, src2);
 548   return idesc->timing->units[unit_num].done;
 549 }
 550
 551 int
 552 m32rbf_model_test_u_exec (SIM_CPU *cpu, const IDESC *idesc,
 553                           int unit_num, int referenced)
 554 {
 555   return idesc->timing->units[unit_num].done;
 556 }
 557
 558 #endif /* WITH_PROFILE_MODEL_P */