1 /* m32r2 simulator support code
2 Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
21 #define WANT_CPU m32r2f
22 #define WANT_CPU_M32R2F
28 /* The contents of BUF are in target byte order. */
31 m32r2f_fetch_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
33 return m32rbf_fetch_register (current_cpu
, rn
, buf
, len
);
36 /* The contents of BUF are in target byte order. */
39 m32r2f_store_register (SIM_CPU
*current_cpu
, int rn
, unsigned char *buf
, int len
)
41 return m32rbf_store_register (current_cpu
, rn
, buf
, len
);
44 /* Cover fns to get/set the control registers.
45 FIXME: Duplicated from m32r.c. The issue is structure offsets. */
48 m32r2f_h_cr_get_handler (SIM_CPU
*current_cpu
, UINT cr
)
52 case H_CR_PSW
: /* PSW. */
53 return (((CPU (h_bpsw
) & 0xc1) << 8)
54 | ((CPU (h_psw
) & 0xc0) << 0)
56 case H_CR_BBPSW
: /* Backup backup psw. */
57 return CPU (h_bbpsw
) & 0xc1;
58 case H_CR_CBR
: /* Condition bit. */
60 case H_CR_SPI
: /* Interrupt stack pointer. */
62 return CPU (h_gr
[H_GR_SP
]);
64 return CPU (h_cr
[H_CR_SPI
]);
65 case H_CR_SPU
: /* User stack pointer. */
67 return CPU (h_gr
[H_GR_SP
]);
69 return CPU (h_cr
[H_CR_SPU
]);
70 case H_CR_BPC
: /* Backup pc. */
71 return CPU (h_cr
[H_CR_BPC
]) & 0xfffffffe;
72 case H_CR_BBPC
: /* Backup backup pc. */
73 return CPU (h_cr
[H_CR_BBPC
]) & 0xfffffffe;
74 case 4 : /* ??? unspecified, but apparently available */
75 case 5 : /* ??? unspecified, but apparently available */
76 return CPU (h_cr
[cr
]);
83 m32r2f_h_cr_set_handler (SIM_CPU
*current_cpu
, UINT cr
, USI newval
)
87 case H_CR_PSW
: /* psw */
89 int old_sm
= (CPU (h_psw
) & 0x80) != 0;
90 int new_sm
= (newval
& 0x80) != 0;
91 CPU (h_bpsw
) = (newval
>> 8) & 0xff;
92 CPU (h_psw
) = newval
& 0xff;
93 SET_H_COND (newval
& 1);
94 /* When switching stack modes, update the registers. */
99 /* Switching user -> system. */
100 CPU (h_cr
[H_CR_SPU
]) = CPU (h_gr
[H_GR_SP
]);
101 CPU (h_gr
[H_GR_SP
]) = CPU (h_cr
[H_CR_SPI
]);
105 /* Switching system -> user. */
106 CPU (h_cr
[H_CR_SPI
]) = CPU (h_gr
[H_GR_SP
]);
107 CPU (h_gr
[H_GR_SP
]) = CPU (h_cr
[H_CR_SPU
]);
112 case H_CR_BBPSW
: /* backup backup psw */
113 CPU (h_bbpsw
) = newval
& 0xff;
115 case H_CR_CBR
: /* condition bit */
116 SET_H_COND (newval
& 1);
118 case H_CR_SPI
: /* interrupt stack pointer */
120 CPU (h_gr
[H_GR_SP
]) = newval
;
122 CPU (h_cr
[H_CR_SPI
]) = newval
;
124 case H_CR_SPU
: /* user stack pointer */
126 CPU (h_gr
[H_GR_SP
]) = newval
;
128 CPU (h_cr
[H_CR_SPU
]) = newval
;
130 case H_CR_BPC
: /* backup pc */
131 CPU (h_cr
[H_CR_BPC
]) = newval
;
133 case H_CR_BBPC
: /* backup backup pc */
134 CPU (h_cr
[H_CR_BBPC
]) = newval
;
136 case 4 : /* ??? unspecified, but apparently available */
137 case 5 : /* ??? unspecified, but apparently available */
138 CPU (h_cr
[cr
]) = newval
;
146 /* Cover fns to access h-psw. */
149 m32r2f_h_psw_get_handler (SIM_CPU
*current_cpu
)
151 return (CPU (h_psw
) & 0xfe) | (CPU (h_cond
) & 1);
155 m32r2f_h_psw_set_handler (SIM_CPU
*current_cpu
, UQI newval
)
157 CPU (h_psw
) = newval
;
158 CPU (h_cond
) = newval
& 1;
161 /* Cover fns to access h-accum. */
164 m32r2f_h_accum_get_handler (SIM_CPU
*current_cpu
)
166 /* Sign extend the top 8 bits. */
168 r
= ANDDI (CPU (h_accum
), MAKEDI (0xffffff, 0xffffffff));
169 r
= XORDI (r
, MAKEDI (0x800000, 0));
170 r
= SUBDI (r
, MAKEDI (0x800000, 0));
175 m32r2f_h_accum_set_handler (SIM_CPU
*current_cpu
, DI newval
)
177 CPU (h_accum
) = newval
;
180 /* Cover fns to access h-accums. */
183 m32r2f_h_accums_get_handler (SIM_CPU
*current_cpu
, UINT regno
)
185 /* FIXME: Yes, this is just a quick hack. */
190 r
= CPU (h_accums
[1]);
191 /* Sign extend the top 8 bits. */
192 r
= ANDDI (r
, MAKEDI (0xffffff, 0xffffffff));
193 r
= XORDI (r
, MAKEDI (0x800000, 0));
194 r
= SUBDI (r
, MAKEDI (0x800000, 0));
199 m32r2f_h_accums_set_handler (SIM_CPU
*current_cpu
, UINT regno
, DI newval
)
201 /* FIXME: Yes, this is just a quick hack. */
203 CPU (h_accum
) = newval
;
205 CPU (h_accums
[1]) = newval
;
208 #if WITH_PROFILE_MODEL_P
210 /* Initialize cycle counting for an insn.
211 FIRST_P is non-zero if this is the first insn in a set of parallel
215 m32r2f_model_insn_before (SIM_CPU
*cpu
, int first_p
)
217 m32rbf_model_insn_before (cpu
, first_p
);
220 /* Record the cycles computed for an insn.
221 LAST_P is non-zero if this is the last insn in a set of parallel insns,
222 and we update the total cycle count.
223 CYCLES is the cycle count of the insn. */
226 m32r2f_model_insn_after (SIM_CPU
*cpu
, int last_p
, int cycles
)
228 m32rbf_model_insn_after (cpu
, last_p
, cycles
);
232 check_load_stall (SIM_CPU
*cpu
, int regno
)
234 UINT h_gr
= CPU_M32R_MISC_PROFILE (cpu
)->load_regs
;
237 && (h_gr
& (1 << regno
)) != 0)
239 CPU_M32R_MISC_PROFILE (cpu
)->load_stall
+= 2;
240 if (TRACE_INSN_P (cpu
))
241 cgen_trace_printf (cpu
, " ; Load stall of 2 cycles.");
246 m32r2f_model_m32r2_u_exec (SIM_CPU
*cpu
, const IDESC
*idesc
,
247 int unit_num
, int referenced
,
248 INT sr
, INT sr2
, INT dr
)
250 check_load_stall (cpu
, sr
);
251 check_load_stall (cpu
, sr2
);
252 return idesc
->timing
->units
[unit_num
].done
;
256 m32r2f_model_m32r2_u_cmp (SIM_CPU
*cpu
, const IDESC
*idesc
,
257 int unit_num
, int referenced
,
260 check_load_stall (cpu
, src1
);
261 check_load_stall (cpu
, src2
);
262 return idesc
->timing
->units
[unit_num
].done
;
266 m32r2f_model_m32r2_u_mac (SIM_CPU
*cpu
, const IDESC
*idesc
,
267 int unit_num
, int referenced
,
270 check_load_stall (cpu
, src1
);
271 check_load_stall (cpu
, src2
);
272 return idesc
->timing
->units
[unit_num
].done
;
276 m32r2f_model_m32r2_u_cti (SIM_CPU
*cpu
, const IDESC
*idesc
,
277 int unit_num
, int referenced
,
280 PROFILE_DATA
*profile
= CPU_PROFILE_DATA (cpu
);
281 int taken_p
= (referenced
& (1 << 1)) != 0;
283 check_load_stall (cpu
, sr
);
286 CPU_M32R_MISC_PROFILE (cpu
)->cti_stall
+= 2;
287 PROFILE_MODEL_TAKEN_COUNT (profile
) += 1;
290 PROFILE_MODEL_UNTAKEN_COUNT (profile
) += 1;
291 return idesc
->timing
->units
[unit_num
].done
;
295 m32r2f_model_m32r2_u_load (SIM_CPU
*cpu
, const IDESC
*idesc
,
296 int unit_num
, int referenced
,
299 CPU_M32R_MISC_PROFILE (cpu
)->load_regs_pending
|= (1 << dr
);
300 return idesc
->timing
->units
[unit_num
].done
;
304 m32r2f_model_m32r2_u_store (SIM_CPU
*cpu
, const IDESC
*idesc
,
305 int unit_num
, int referenced
,
308 return idesc
->timing
->units
[unit_num
].done
;
311 #endif /* WITH_PROFILE_MODEL_P */
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