sim/m32r/mloopx.in

   1 # Simulator main loop for m32rx. -*- C -*-
   2 # Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   3 #
   4 # This file is part of the GNU Simulators.
   5 #
   6 # This program is free software; you can redistribute it and/or modify
   7 # it under the terms of the GNU General Public License as published by
   8 # the Free Software Foundation; either version 2, or (at your option)
   9 # any later version.
  10 #
  11 # This program is distributed in the hope that it will be useful,
  12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 # GNU General Public License for more details.
  15 #
  16 # You should have received a copy of the GNU General Public License along
  17 # with this program; if not, write to the Free Software Foundation, Inc.,
  18 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19
  20 # Syntax:
  21 # /bin/sh mainloop.in init|support|{full,fast}-{extract,exec}-{scache,noscache}
  22
  23 # ??? After a few more ports are done, revisit.
  24 # Will eventually need to machine generate a lot of this.
  25
  26 case "x$1" in
  27
  28 xsupport)
  29
  30 cat <<EOF
  31
  32 EOF
  33
  34 ;;
  35
  36 xinit)
  37
  38 cat <<EOF
  39   const IDESC *d1,*d2;
  40   ARGBUF abufs[MAX_PARALLEL_INSNS];
  41   PAREXEC pbufs[MAX_PARALLEL_INSNS];
  42 EOF
  43
  44 ;;
  45
  46 xfull-extract-* | xfast-extract-*)
  47
  48 cat <<EOF
  49 {
  50   PCADDR pc = CPU (h_pc);
  51
  52   /* ??? This code isn't very fast.  Let's get it working first.  */
  53
  54   if ((pc & 3) != 0)
  55     {
  56       USI insn = GETIMEMUHI (current_cpu, pc);
  57       insn &= 0x7fff;
  58       d1 = m32rx_decode (current_cpu, pc, insn);
  59       abufs[0].insn = insn;
  60       abufs[0].idesc = d1;
  61       abufs[0].addr = pc; /* FIXME: wip */
  62       icount = 1;
  63     }
  64   else
  65     {
  66       USI insn = GETIMEMUSI (current_cpu, pc);
  67       if ((SI) insn < 0)
  68         {
  69           d1 = m32rx_decode (current_cpu, pc, insn >> 16);
  70           abufs[0].insn = insn;
  71           abufs[0].idesc = d1;
  72           abufs[0].addr = pc; /* FIXME: wip */
  73           icount = 1;
  74         }
  75       else
  76         {
  77           if (insn & 0x8000)
  78             {
  79               d1 = m32rx_decode (current_cpu, pc, insn >> 16);
  80               abufs[0].insn = insn >> 16;
  81               abufs[0].idesc = d1;
  82               abufs[0].addr = pc; /* FIXME: wip */
  83               d2 = m32rx_decode (current_cpu, pc + 2, insn & 0x7fff);
  84               abufs[1].insn = insn & 0x7fff;
  85               abufs[1].idesc = d2;
  86               abufs[1].addr = pc + 2; /* FIXME: wip */
  87               icount = 2;
  88             }
  89           else
  90             {
  91               d1 = m32rx_decode (current_cpu, pc, insn >> 16);
  92               abufs[0].insn = insn >> 16;
  93               abufs[0].idesc = d1;
  94               abufs[0].addr = pc; /* FIXME: wip */
  95               icount = 1;
  96             }
  97         }
  98     }
  99
 100   {
 101     int icount2 = icount;
 102     USI insn = abufs[0].insn;
 103     const IDESC *decode = d1;
 104     /* decode, par_exec, and insn are refered to by readx.c.  */
 105     PAREXEC *par_exec = &pbufs[0];
 106     do
 107       {
 108 #define DEFINE_SWITCH
 109 #include "readx.c"
 110
 111         decode = d2;
 112         insn = abufs[1].insn;
 113         ++par_exec;
 114       }
 115     while (--icount2 != 0);
 116   }
 117 }
 118 EOF
 119
 120 ;;
 121
 122 xfull-exec-* | xfast-exec-*)
 123
 124 cat <<EOF
 125 {
 126   SEM_ARG sem_arg = &abufs[0];
 127   PAREXEC *par_exec = &pbufs[0];
 128   PCADDR new_pc;
 129
 130 #if 0 /* wip */
 131   /* If doing parallel execution, verify insns are in the right pipeline.  */
 132   if (icount == 2)
 133     {
 134       ...
 135     }
 136 #endif
 137
 138   m32r_model_init_insn_cycles (current_cpu, 1);
 139   TRACE_INSN_INIT (current_cpu, 1);
 140   TRACE_INSN (current_cpu, d1->opcode, sem_arg, CPU (h_pc));
 141   new_pc = (*d1->sem_full) (current_cpu, sem_arg, par_exec);
 142   m32r_model_update_insn_cycles (current_cpu, icount == 1);
 143   TRACE_INSN_FINI (current_cpu, icount == 1);
 144
 145   /* The result of the semantic fn is one of:
 146      - next address, branch only
 147      - NEW_PC_SKIP, sc/snc insn
 148      - NEW_PC_2, 2 byte non-branch non-sc/snc insn
 149      - NEW_PC_4, 4 byte non-branch insn
 150      */
 151
 152   /* The tests are ordered to try to favor the more frequent cases, while
 153      keeping the over all costs down.  */
 154   if (new_pc == NEW_PC_4)
 155     CPU (h_pc) += 4;
 156   else if (icount == 2)
 157     {
 158       /* Note that we only get here if doing parallel execution.  */
 159
 160       if (new_pc == NEW_PC_SKIP)
 161         {
 162           /* ??? Need generic notion of bypassing an insn for the name of
 163              this macro.  Annulled?  On the otherhand such tracing can go
 164              in the sc/snc semantic fn.  */
 165           ; /*TRACE_INSN_SKIPPED (current_cpu);*/
 166           CPU (h_pc) += 4;
 167         }
 168       else
 169         {
 170           PCADDR pc2;
 171
 172           ++sem_arg;
 173           ++par_exec;
 174           m32r_model_init_insn_cycles (current_cpu, 0);
 175           TRACE_INSN_INIT (current_cpu, 0);
 176           TRACE_INSN (current_cpu, d2->opcode, sem_arg, CPU (h_pc) + 2);
 177           /* pc2 isn't used.  It's assigned a value for debugging.  */
 178           pc2 = (*d2->sem_full) (current_cpu, sem_arg, par_exec);
 179           m32r_model_update_insn_cycles (current_cpu, 1);
 180           TRACE_INSN_FINI (current_cpu, 1);
 181
 182           if (NEW_PC_BRANCH_P (new_pc))
 183             CPU (h_pc) = new_pc;
 184           else
 185             CPU (h_pc) += 4;
 186         }
 187
 188       /* Update count of parallel insns executed.  */
 189       PROFILE_COUNT_PARINSNS (current_cpu);
 190     }
 191   else if (NEW_PC_BRANCH_P (new_pc))
 192     CPU (h_pc) = new_pc;
 193   else
 194     CPU (h_pc) += 2;
 195 }
 196 EOF
 197
 198 ;;
 199
 200 *)
 201   echo "Invalid argument to mainloop.in: $1" >&2
 202   exit 1
 203   ;;
 204
 205 esac