1 # Simulator main loop for m32rx. -*- C -*-
2 # Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
4 # This file is part of the GNU Simulators.
6 # This program is free software; you can redistribute it and/or modify
7 # it under the terms of the GNU General Public License as published by
8 # the Free Software Foundation; either version 2, or (at your option)
11 # This program is distributed in the hope that it will be useful,
12 # but WITHOUT ANY WARRANTY; without even the implied warranty of
13 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 # GNU General Public License for more details.
16 # You should have received a copy of the GNU General Public License along
17 # with this program; if not, write to the Free Software Foundation, Inc.,
18 # 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 # /bin/sh mainloop.in init|support|{full,fast}-{extract,exec}-{scache,noscache}
23 # ??? After a few more ports are done, revisit.
24 # Will eventually need to machine generate a lot of this.
40 ARGBUF abufs[MAX_PARALLEL_INSNS];
41 PAREXEC pbufs[MAX_PARALLEL_INSNS];
46 xfull-extract-* | xfast-extract-*)
50 PCADDR pc = CPU (h_pc);
52 /* ??? This code isn't very fast. Let's get it working first. */
56 USI insn = GETIMEMUHI (current_cpu, pc);
58 d1 = m32rx_decode (current_cpu, pc, insn);
65 USI insn = GETIMEMUSI (current_cpu, pc);
68 d1 = m32rx_decode (current_cpu, pc, insn >> 16);
77 d1 = m32rx_decode (current_cpu, pc, insn >> 16);
78 abufs[0].insn = insn >> 16;
80 d2 = m32rx_decode (current_cpu, pc, insn & 0x7fff);
81 abufs[1].insn = insn & 0x7fff;
87 d1 = m32rx_decode (current_cpu, pc, insn >> 16);
88 abufs[0].insn = insn >> 16;
97 USI insn = abufs[0].insn;
98 const IDESC *decode = d1;
99 /* decode, par_exec, and insn are refered to by readx.c. */
100 PAREXEC *par_exec = &pbufs[0];
103 #define DEFINE_SWITCH
107 insn = abufs[1].insn;
110 while (--icount2 != 0);
117 xfull-exec-* | xfast-exec-*)
121 SEM_ARG sem_arg = &abufs[0];
122 PAREXEC *par_exec = &pbufs[0];
126 /* If doing parallel execution, verify insns are in the right pipeline. */
133 TRACE_INSN_INIT (current_cpu, 1);
134 TRACE_INSN (current_cpu, d1->opcode, sem_arg, CPU (h_pc));
135 new_pc = (*d1->sem_full) (current_cpu, sem_arg, par_exec);
136 TRACE_INSN_FINI (current_cpu, icount == 1);
138 /* The result of the semantic fn is one of:
139 - next address, branch only
140 - NEW_PC_SKIP, sc/snc insn
141 - NEW_PC_2, 2 byte non-branch non-sc/snc insn
142 - NEW_PC_4, 4 byte non-branch insn
145 /* The tests are ordered to try to favor the more frequent cases, while
146 keeping the over all costs down. */
147 if (new_pc == NEW_PC_4)
149 else if (icount == 2)
151 /* Note that we only get here if doing parallel execution. */
153 if (new_pc == NEW_PC_SKIP)
155 /* ??? Need generic notion of bypassing an insn for the name of
156 this macro. Annulled? On the otherhand such tracing can go
157 in the sc/snc semantic fn. */
158 ; /*TRACE_INSN_SKIPPED (current_cpu);*/
167 TRACE_INSN_INIT (current_cpu, 0);
168 TRACE_INSN (current_cpu, d2->opcode, sem_arg, CPU (h_pc) + 2);
169 /* pc2 isn't used. It's assigned a value for debugging. */
170 pc2 = (*d2->sem_full) (current_cpu, sem_arg, par_exec);
171 TRACE_INSN_FINI (current_cpu, 1);
173 if (NEW_PC_BRANCH_P (new_pc))
179 else if (NEW_PC_BRANCH_P (new_pc))
189 echo "Invalid argument to mainloop.in: $1" >&2