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* Makefile.in (MAIN_INCLUDE_DEPS): Delete.
[deliverable/binutils-gdb.git] / sim / m32r / modelx.c
1 /* Simulator model support for m32rxf.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
6
7 This file is part of the GNU Simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23 */
24
25 #define WANT_CPU m32rxf
26 #define WANT_CPU_M32RXF
27
28 #include "sim-main.h"
29
30 /* The profiling data is recorded here, but is accessed via the profiling
31 mechanism. After all, this is information for profiling. */
32
33 #if WITH_PROFILE_MODEL_P
34
35 /* Model handlers for each insn. */
36
37 static int
38 model_m32rx_x_invalid (SIM_CPU *current_cpu, void *sem_arg)
39 {
40 #define FLD(f) abuf->fields.fmt_empty.f
41 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
42 int cycles = 0;
43 {
44 int referenced = 0;
45 int UNUSED insn_referenced = abuf->written;
46 INT sr = -1;
47 INT sr2 = -1;
48 INT dr = -1;
49 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
50 }
51 return cycles;
52 #undef FLD
53 }
54
55 static int
56 model_m32rx_x_after (SIM_CPU *current_cpu, void *sem_arg)
57 {
58 #define FLD(f) abuf->fields.fmt_empty.f
59 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
60 int cycles = 0;
61 {
62 int referenced = 0;
63 int UNUSED insn_referenced = abuf->written;
64 INT sr = -1;
65 INT sr2 = -1;
66 INT dr = -1;
67 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
68 }
69 return cycles;
70 #undef FLD
71 }
72
73 static int
74 model_m32rx_x_before (SIM_CPU *current_cpu, void *sem_arg)
75 {
76 #define FLD(f) abuf->fields.fmt_empty.f
77 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
78 int cycles = 0;
79 {
80 int referenced = 0;
81 int UNUSED insn_referenced = abuf->written;
82 INT sr = -1;
83 INT sr2 = -1;
84 INT dr = -1;
85 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
86 }
87 return cycles;
88 #undef FLD
89 }
90
91 static int
92 model_m32rx_x_cti_chain (SIM_CPU *current_cpu, void *sem_arg)
93 {
94 #define FLD(f) abuf->fields.fmt_empty.f
95 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
96 int cycles = 0;
97 {
98 int referenced = 0;
99 int UNUSED insn_referenced = abuf->written;
100 INT sr = -1;
101 INT sr2 = -1;
102 INT dr = -1;
103 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
104 }
105 return cycles;
106 #undef FLD
107 }
108
109 static int
110 model_m32rx_x_chain (SIM_CPU *current_cpu, void *sem_arg)
111 {
112 #define FLD(f) abuf->fields.fmt_empty.f
113 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
114 int cycles = 0;
115 {
116 int referenced = 0;
117 int UNUSED insn_referenced = abuf->written;
118 INT sr = -1;
119 INT sr2 = -1;
120 INT dr = -1;
121 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
122 }
123 return cycles;
124 #undef FLD
125 }
126
127 static int
128 model_m32rx_x_begin (SIM_CPU *current_cpu, void *sem_arg)
129 {
130 #define FLD(f) abuf->fields.fmt_empty.f
131 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
132 int cycles = 0;
133 {
134 int referenced = 0;
135 int UNUSED insn_referenced = abuf->written;
136 INT sr = -1;
137 INT sr2 = -1;
138 INT dr = -1;
139 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
140 }
141 return cycles;
142 #undef FLD
143 }
144
145 static int
146 model_m32rx_add (SIM_CPU *current_cpu, void *sem_arg)
147 {
148 #define FLD(f) abuf->fields.fmt_add.f
149 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
150 int cycles = 0;
151 {
152 int referenced = 0;
153 int UNUSED insn_referenced = abuf->written;
154 INT sr = -1;
155 INT sr2 = -1;
156 INT dr = -1;
157 sr = FLD (in_sr);
158 dr = FLD (out_dr);
159 referenced |= 1 << 0;
160 referenced |= 1 << 2;
161 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
162 }
163 return cycles;
164 #undef FLD
165 }
166
167 static int
168 model_m32rx_add3 (SIM_CPU *current_cpu, void *sem_arg)
169 {
170 #define FLD(f) abuf->fields.fmt_add3.f
171 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
172 int cycles = 0;
173 {
174 int referenced = 0;
175 int UNUSED insn_referenced = abuf->written;
176 INT sr = -1;
177 INT sr2 = -1;
178 INT dr = -1;
179 sr = FLD (in_sr);
180 dr = FLD (out_dr);
181 referenced |= 1 << 0;
182 referenced |= 1 << 2;
183 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
184 }
185 return cycles;
186 #undef FLD
187 }
188
189 static int
190 model_m32rx_and (SIM_CPU *current_cpu, void *sem_arg)
191 {
192 #define FLD(f) abuf->fields.fmt_add.f
193 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
194 int cycles = 0;
195 {
196 int referenced = 0;
197 int UNUSED insn_referenced = abuf->written;
198 INT sr = -1;
199 INT sr2 = -1;
200 INT dr = -1;
201 sr = FLD (in_sr);
202 dr = FLD (out_dr);
203 referenced |= 1 << 0;
204 referenced |= 1 << 2;
205 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
206 }
207 return cycles;
208 #undef FLD
209 }
210
211 static int
212 model_m32rx_and3 (SIM_CPU *current_cpu, void *sem_arg)
213 {
214 #define FLD(f) abuf->fields.fmt_and3.f
215 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
216 int cycles = 0;
217 {
218 int referenced = 0;
219 int UNUSED insn_referenced = abuf->written;
220 INT sr = -1;
221 INT sr2 = -1;
222 INT dr = -1;
223 sr = FLD (in_sr);
224 dr = FLD (out_dr);
225 referenced |= 1 << 0;
226 referenced |= 1 << 2;
227 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
228 }
229 return cycles;
230 #undef FLD
231 }
232
233 static int
234 model_m32rx_or (SIM_CPU *current_cpu, void *sem_arg)
235 {
236 #define FLD(f) abuf->fields.fmt_add.f
237 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
238 int cycles = 0;
239 {
240 int referenced = 0;
241 int UNUSED insn_referenced = abuf->written;
242 INT sr = -1;
243 INT sr2 = -1;
244 INT dr = -1;
245 sr = FLD (in_sr);
246 dr = FLD (out_dr);
247 referenced |= 1 << 0;
248 referenced |= 1 << 2;
249 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
250 }
251 return cycles;
252 #undef FLD
253 }
254
255 static int
256 model_m32rx_or3 (SIM_CPU *current_cpu, void *sem_arg)
257 {
258 #define FLD(f) abuf->fields.fmt_or3.f
259 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
260 int cycles = 0;
261 {
262 int referenced = 0;
263 int UNUSED insn_referenced = abuf->written;
264 INT sr = -1;
265 INT sr2 = -1;
266 INT dr = -1;
267 sr = FLD (in_sr);
268 dr = FLD (out_dr);
269 referenced |= 1 << 0;
270 referenced |= 1 << 2;
271 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
272 }
273 return cycles;
274 #undef FLD
275 }
276
277 static int
278 model_m32rx_xor (SIM_CPU *current_cpu, void *sem_arg)
279 {
280 #define FLD(f) abuf->fields.fmt_add.f
281 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
282 int cycles = 0;
283 {
284 int referenced = 0;
285 int UNUSED insn_referenced = abuf->written;
286 INT sr = -1;
287 INT sr2 = -1;
288 INT dr = -1;
289 sr = FLD (in_sr);
290 dr = FLD (out_dr);
291 referenced |= 1 << 0;
292 referenced |= 1 << 2;
293 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
294 }
295 return cycles;
296 #undef FLD
297 }
298
299 static int
300 model_m32rx_xor3 (SIM_CPU *current_cpu, void *sem_arg)
301 {
302 #define FLD(f) abuf->fields.fmt_and3.f
303 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
304 int cycles = 0;
305 {
306 int referenced = 0;
307 int UNUSED insn_referenced = abuf->written;
308 INT sr = -1;
309 INT sr2 = -1;
310 INT dr = -1;
311 sr = FLD (in_sr);
312 dr = FLD (out_dr);
313 referenced |= 1 << 0;
314 referenced |= 1 << 2;
315 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
316 }
317 return cycles;
318 #undef FLD
319 }
320
321 static int
322 model_m32rx_addi (SIM_CPU *current_cpu, void *sem_arg)
323 {
324 #define FLD(f) abuf->fields.fmt_addi.f
325 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
326 int cycles = 0;
327 {
328 int referenced = 0;
329 int UNUSED insn_referenced = abuf->written;
330 INT sr = -1;
331 INT sr2 = -1;
332 INT dr = -1;
333 dr = FLD (out_dr);
334 sr = FLD (in_dr);
335 referenced |= 1 << 0;
336 referenced |= 1 << 2;
337 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
338 }
339 return cycles;
340 #undef FLD
341 }
342
343 static int
344 model_m32rx_addv (SIM_CPU *current_cpu, void *sem_arg)
345 {
346 #define FLD(f) abuf->fields.fmt_addv.f
347 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
348 int cycles = 0;
349 {
350 int referenced = 0;
351 int UNUSED insn_referenced = abuf->written;
352 INT sr = -1;
353 INT sr2 = -1;
354 INT dr = -1;
355 sr = FLD (in_sr);
356 dr = FLD (out_dr);
357 referenced |= 1 << 0;
358 referenced |= 1 << 2;
359 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
360 }
361 return cycles;
362 #undef FLD
363 }
364
365 static int
366 model_m32rx_addv3 (SIM_CPU *current_cpu, void *sem_arg)
367 {
368 #define FLD(f) abuf->fields.fmt_addv3.f
369 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
370 int cycles = 0;
371 {
372 int referenced = 0;
373 int UNUSED insn_referenced = abuf->written;
374 INT sr = -1;
375 INT sr2 = -1;
376 INT dr = -1;
377 sr = FLD (in_sr);
378 dr = FLD (out_dr);
379 referenced |= 1 << 0;
380 referenced |= 1 << 2;
381 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
382 }
383 return cycles;
384 #undef FLD
385 }
386
387 static int
388 model_m32rx_addx (SIM_CPU *current_cpu, void *sem_arg)
389 {
390 #define FLD(f) abuf->fields.fmt_addx.f
391 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
392 int cycles = 0;
393 {
394 int referenced = 0;
395 int UNUSED insn_referenced = abuf->written;
396 INT sr = -1;
397 INT sr2 = -1;
398 INT dr = -1;
399 sr = FLD (in_sr);
400 dr = FLD (out_dr);
401 referenced |= 1 << 0;
402 referenced |= 1 << 2;
403 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
404 }
405 return cycles;
406 #undef FLD
407 }
408
409 static int
410 model_m32rx_bc8 (SIM_CPU *current_cpu, void *sem_arg)
411 {
412 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
413 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
414 int cycles = 0;
415 {
416 int referenced = 0;
417 int UNUSED insn_referenced = abuf->written;
418 INT sr = -1;
419 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
420 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
421 }
422 return cycles;
423 #undef FLD
424 }
425
426 static int
427 model_m32rx_bc24 (SIM_CPU *current_cpu, void *sem_arg)
428 {
429 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
430 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
431 int cycles = 0;
432 {
433 int referenced = 0;
434 int UNUSED insn_referenced = abuf->written;
435 INT sr = -1;
436 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
437 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
438 }
439 return cycles;
440 #undef FLD
441 }
442
443 static int
444 model_m32rx_beq (SIM_CPU *current_cpu, void *sem_arg)
445 {
446 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
447 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
448 int cycles = 0;
449 {
450 int referenced = 0;
451 int UNUSED insn_referenced = abuf->written;
452 INT sr = -1;
453 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
454 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
455 }
456 {
457 int referenced = 0;
458 int UNUSED insn_referenced = abuf->written;
459 INT src1 = -1;
460 INT src2 = -1;
461 src1 = FLD (in_src1);
462 src2 = FLD (in_src2);
463 referenced |= 1 << 0;
464 referenced |= 1 << 1;
465 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 1, referenced, src1, src2);
466 }
467 return cycles;
468 #undef FLD
469 }
470
471 static int
472 model_m32rx_beqz (SIM_CPU *current_cpu, void *sem_arg)
473 {
474 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
475 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
476 int cycles = 0;
477 {
478 int referenced = 0;
479 int UNUSED insn_referenced = abuf->written;
480 INT sr = -1;
481 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
482 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
483 }
484 {
485 int referenced = 0;
486 int UNUSED insn_referenced = abuf->written;
487 INT src1 = -1;
488 INT src2 = -1;
489 src2 = FLD (in_src2);
490 referenced |= 1 << 1;
491 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 1, referenced, src1, src2);
492 }
493 return cycles;
494 #undef FLD
495 }
496
497 static int
498 model_m32rx_bgez (SIM_CPU *current_cpu, void *sem_arg)
499 {
500 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
501 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
502 int cycles = 0;
503 {
504 int referenced = 0;
505 int UNUSED insn_referenced = abuf->written;
506 INT sr = -1;
507 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
508 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
509 }
510 {
511 int referenced = 0;
512 int UNUSED insn_referenced = abuf->written;
513 INT src1 = -1;
514 INT src2 = -1;
515 src2 = FLD (in_src2);
516 referenced |= 1 << 1;
517 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 1, referenced, src1, src2);
518 }
519 return cycles;
520 #undef FLD
521 }
522
523 static int
524 model_m32rx_bgtz (SIM_CPU *current_cpu, void *sem_arg)
525 {
526 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
527 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
528 int cycles = 0;
529 {
530 int referenced = 0;
531 int UNUSED insn_referenced = abuf->written;
532 INT sr = -1;
533 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
534 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
535 }
536 {
537 int referenced = 0;
538 int UNUSED insn_referenced = abuf->written;
539 INT src1 = -1;
540 INT src2 = -1;
541 src2 = FLD (in_src2);
542 referenced |= 1 << 1;
543 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 1, referenced, src1, src2);
544 }
545 return cycles;
546 #undef FLD
547 }
548
549 static int
550 model_m32rx_blez (SIM_CPU *current_cpu, void *sem_arg)
551 {
552 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
553 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
554 int cycles = 0;
555 {
556 int referenced = 0;
557 int UNUSED insn_referenced = abuf->written;
558 INT sr = -1;
559 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
560 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
561 }
562 {
563 int referenced = 0;
564 int UNUSED insn_referenced = abuf->written;
565 INT src1 = -1;
566 INT src2 = -1;
567 src2 = FLD (in_src2);
568 referenced |= 1 << 1;
569 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 1, referenced, src1, src2);
570 }
571 return cycles;
572 #undef FLD
573 }
574
575 static int
576 model_m32rx_bltz (SIM_CPU *current_cpu, void *sem_arg)
577 {
578 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
579 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
580 int cycles = 0;
581 {
582 int referenced = 0;
583 int UNUSED insn_referenced = abuf->written;
584 INT sr = -1;
585 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
586 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
587 }
588 {
589 int referenced = 0;
590 int UNUSED insn_referenced = abuf->written;
591 INT src1 = -1;
592 INT src2 = -1;
593 src2 = FLD (in_src2);
594 referenced |= 1 << 1;
595 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 1, referenced, src1, src2);
596 }
597 return cycles;
598 #undef FLD
599 }
600
601 static int
602 model_m32rx_bnez (SIM_CPU *current_cpu, void *sem_arg)
603 {
604 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
605 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
606 int cycles = 0;
607 {
608 int referenced = 0;
609 int UNUSED insn_referenced = abuf->written;
610 INT sr = -1;
611 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
612 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
613 }
614 {
615 int referenced = 0;
616 int UNUSED insn_referenced = abuf->written;
617 INT src1 = -1;
618 INT src2 = -1;
619 src2 = FLD (in_src2);
620 referenced |= 1 << 1;
621 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 1, referenced, src1, src2);
622 }
623 return cycles;
624 #undef FLD
625 }
626
627 static int
628 model_m32rx_bl8 (SIM_CPU *current_cpu, void *sem_arg)
629 {
630 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
631 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
632 int cycles = 0;
633 {
634 int referenced = 0;
635 int UNUSED insn_referenced = abuf->written;
636 INT sr = -1;
637 referenced |= 1 << 1;
638 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
639 }
640 return cycles;
641 #undef FLD
642 }
643
644 static int
645 model_m32rx_bl24 (SIM_CPU *current_cpu, void *sem_arg)
646 {
647 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
648 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
649 int cycles = 0;
650 {
651 int referenced = 0;
652 int UNUSED insn_referenced = abuf->written;
653 INT sr = -1;
654 referenced |= 1 << 1;
655 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
656 }
657 return cycles;
658 #undef FLD
659 }
660
661 static int
662 model_m32rx_bcl8 (SIM_CPU *current_cpu, void *sem_arg)
663 {
664 #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
665 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
666 int cycles = 0;
667 {
668 int referenced = 0;
669 int UNUSED insn_referenced = abuf->written;
670 INT sr = -1;
671 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
672 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
673 }
674 return cycles;
675 #undef FLD
676 }
677
678 static int
679 model_m32rx_bcl24 (SIM_CPU *current_cpu, void *sem_arg)
680 {
681 #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
682 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
683 int cycles = 0;
684 {
685 int referenced = 0;
686 int UNUSED insn_referenced = abuf->written;
687 INT sr = -1;
688 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
689 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
690 }
691 return cycles;
692 #undef FLD
693 }
694
695 static int
696 model_m32rx_bnc8 (SIM_CPU *current_cpu, void *sem_arg)
697 {
698 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
699 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
700 int cycles = 0;
701 {
702 int referenced = 0;
703 int UNUSED insn_referenced = abuf->written;
704 INT sr = -1;
705 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
706 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
707 }
708 return cycles;
709 #undef FLD
710 }
711
712 static int
713 model_m32rx_bnc24 (SIM_CPU *current_cpu, void *sem_arg)
714 {
715 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
716 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
717 int cycles = 0;
718 {
719 int referenced = 0;
720 int UNUSED insn_referenced = abuf->written;
721 INT sr = -1;
722 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
723 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
724 }
725 return cycles;
726 #undef FLD
727 }
728
729 static int
730 model_m32rx_bne (SIM_CPU *current_cpu, void *sem_arg)
731 {
732 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
733 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
734 int cycles = 0;
735 {
736 int referenced = 0;
737 int UNUSED insn_referenced = abuf->written;
738 INT sr = -1;
739 if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
740 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
741 }
742 {
743 int referenced = 0;
744 int UNUSED insn_referenced = abuf->written;
745 INT src1 = -1;
746 INT src2 = -1;
747 src1 = FLD (in_src1);
748 src2 = FLD (in_src2);
749 referenced |= 1 << 0;
750 referenced |= 1 << 1;
751 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 1, referenced, src1, src2);
752 }
753 return cycles;
754 #undef FLD
755 }
756
757 static int
758 model_m32rx_bra8 (SIM_CPU *current_cpu, void *sem_arg)
759 {
760 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
761 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
762 int cycles = 0;
763 {
764 int referenced = 0;
765 int UNUSED insn_referenced = abuf->written;
766 INT sr = -1;
767 referenced |= 1 << 1;
768 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
769 }
770 return cycles;
771 #undef FLD
772 }
773
774 static int
775 model_m32rx_bra24 (SIM_CPU *current_cpu, void *sem_arg)
776 {
777 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
778 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
779 int cycles = 0;
780 {
781 int referenced = 0;
782 int UNUSED insn_referenced = abuf->written;
783 INT sr = -1;
784 referenced |= 1 << 1;
785 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
786 }
787 return cycles;
788 #undef FLD
789 }
790
791 static int
792 model_m32rx_bncl8 (SIM_CPU *current_cpu, void *sem_arg)
793 {
794 #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
795 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
796 int cycles = 0;
797 {
798 int referenced = 0;
799 int UNUSED insn_referenced = abuf->written;
800 INT sr = -1;
801 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
802 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
803 }
804 return cycles;
805 #undef FLD
806 }
807
808 static int
809 model_m32rx_bncl24 (SIM_CPU *current_cpu, void *sem_arg)
810 {
811 #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
812 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
813 int cycles = 0;
814 {
815 int referenced = 0;
816 int UNUSED insn_referenced = abuf->written;
817 INT sr = -1;
818 if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
819 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
820 }
821 return cycles;
822 #undef FLD
823 }
824
825 static int
826 model_m32rx_cmp (SIM_CPU *current_cpu, void *sem_arg)
827 {
828 #define FLD(f) abuf->fields.fmt_cmp.f
829 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
830 int cycles = 0;
831 {
832 int referenced = 0;
833 int UNUSED insn_referenced = abuf->written;
834 INT src1 = -1;
835 INT src2 = -1;
836 src1 = FLD (in_src1);
837 src2 = FLD (in_src2);
838 referenced |= 1 << 0;
839 referenced |= 1 << 1;
840 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 0, referenced, src1, src2);
841 }
842 return cycles;
843 #undef FLD
844 }
845
846 static int
847 model_m32rx_cmpi (SIM_CPU *current_cpu, void *sem_arg)
848 {
849 #define FLD(f) abuf->fields.fmt_cmpi.f
850 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
851 int cycles = 0;
852 {
853 int referenced = 0;
854 int UNUSED insn_referenced = abuf->written;
855 INT src1 = -1;
856 INT src2 = -1;
857 src2 = FLD (in_src2);
858 referenced |= 1 << 1;
859 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 0, referenced, src1, src2);
860 }
861 return cycles;
862 #undef FLD
863 }
864
865 static int
866 model_m32rx_cmpu (SIM_CPU *current_cpu, void *sem_arg)
867 {
868 #define FLD(f) abuf->fields.fmt_cmp.f
869 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
870 int cycles = 0;
871 {
872 int referenced = 0;
873 int UNUSED insn_referenced = abuf->written;
874 INT src1 = -1;
875 INT src2 = -1;
876 src1 = FLD (in_src1);
877 src2 = FLD (in_src2);
878 referenced |= 1 << 0;
879 referenced |= 1 << 1;
880 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 0, referenced, src1, src2);
881 }
882 return cycles;
883 #undef FLD
884 }
885
886 static int
887 model_m32rx_cmpui (SIM_CPU *current_cpu, void *sem_arg)
888 {
889 #define FLD(f) abuf->fields.fmt_cmpi.f
890 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
891 int cycles = 0;
892 {
893 int referenced = 0;
894 int UNUSED insn_referenced = abuf->written;
895 INT src1 = -1;
896 INT src2 = -1;
897 src2 = FLD (in_src2);
898 referenced |= 1 << 1;
899 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 0, referenced, src1, src2);
900 }
901 return cycles;
902 #undef FLD
903 }
904
905 static int
906 model_m32rx_cmpeq (SIM_CPU *current_cpu, void *sem_arg)
907 {
908 #define FLD(f) abuf->fields.fmt_cmp.f
909 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
910 int cycles = 0;
911 {
912 int referenced = 0;
913 int UNUSED insn_referenced = abuf->written;
914 INT src1 = -1;
915 INT src2 = -1;
916 src1 = FLD (in_src1);
917 src2 = FLD (in_src2);
918 referenced |= 1 << 0;
919 referenced |= 1 << 1;
920 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 0, referenced, src1, src2);
921 }
922 return cycles;
923 #undef FLD
924 }
925
926 static int
927 model_m32rx_cmpz (SIM_CPU *current_cpu, void *sem_arg)
928 {
929 #define FLD(f) abuf->fields.fmt_cmpz.f
930 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
931 int cycles = 0;
932 {
933 int referenced = 0;
934 int UNUSED insn_referenced = abuf->written;
935 INT src1 = -1;
936 INT src2 = -1;
937 src2 = FLD (in_src2);
938 referenced |= 1 << 1;
939 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 0, referenced, src1, src2);
940 }
941 return cycles;
942 #undef FLD
943 }
944
945 static int
946 model_m32rx_div (SIM_CPU *current_cpu, void *sem_arg)
947 {
948 #define FLD(f) abuf->fields.fmt_div.f
949 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
950 int cycles = 0;
951 {
952 int referenced = 0;
953 int UNUSED insn_referenced = abuf->written;
954 INT sr = -1;
955 INT sr2 = -1;
956 INT dr = -1;
957 sr = FLD (in_sr);
958 dr = FLD (out_dr);
959 referenced |= 1 << 0;
960 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
961 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
962 }
963 return cycles;
964 #undef FLD
965 }
966
967 static int
968 model_m32rx_divu (SIM_CPU *current_cpu, void *sem_arg)
969 {
970 #define FLD(f) abuf->fields.fmt_div.f
971 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
972 int cycles = 0;
973 {
974 int referenced = 0;
975 int UNUSED insn_referenced = abuf->written;
976 INT sr = -1;
977 INT sr2 = -1;
978 INT dr = -1;
979 sr = FLD (in_sr);
980 dr = FLD (out_dr);
981 referenced |= 1 << 0;
982 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
983 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
984 }
985 return cycles;
986 #undef FLD
987 }
988
989 static int
990 model_m32rx_rem (SIM_CPU *current_cpu, void *sem_arg)
991 {
992 #define FLD(f) abuf->fields.fmt_div.f
993 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
994 int cycles = 0;
995 {
996 int referenced = 0;
997 int UNUSED insn_referenced = abuf->written;
998 INT sr = -1;
999 INT sr2 = -1;
1000 INT dr = -1;
1001 sr = FLD (in_sr);
1002 dr = FLD (out_dr);
1003 referenced |= 1 << 0;
1004 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1005 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1006 }
1007 return cycles;
1008 #undef FLD
1009 }
1010
1011 static int
1012 model_m32rx_remu (SIM_CPU *current_cpu, void *sem_arg)
1013 {
1014 #define FLD(f) abuf->fields.fmt_div.f
1015 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1016 int cycles = 0;
1017 {
1018 int referenced = 0;
1019 int UNUSED insn_referenced = abuf->written;
1020 INT sr = -1;
1021 INT sr2 = -1;
1022 INT dr = -1;
1023 sr = FLD (in_sr);
1024 dr = FLD (out_dr);
1025 referenced |= 1 << 0;
1026 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1027 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1028 }
1029 return cycles;
1030 #undef FLD
1031 }
1032
1033 static int
1034 model_m32rx_divh (SIM_CPU *current_cpu, void *sem_arg)
1035 {
1036 #define FLD(f) abuf->fields.fmt_div.f
1037 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1038 int cycles = 0;
1039 {
1040 int referenced = 0;
1041 int UNUSED insn_referenced = abuf->written;
1042 INT sr = -1;
1043 INT sr2 = -1;
1044 INT dr = -1;
1045 sr = FLD (in_sr);
1046 dr = FLD (out_dr);
1047 referenced |= 1 << 0;
1048 if (insn_referenced & (1 << 2)) referenced |= 1 << 2;
1049 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1050 }
1051 return cycles;
1052 #undef FLD
1053 }
1054
1055 static int
1056 model_m32rx_jc (SIM_CPU *current_cpu, void *sem_arg)
1057 {
1058 #define FLD(f) abuf->fields.cti.fields.fmt_jc.f
1059 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1060 int cycles = 0;
1061 {
1062 int referenced = 0;
1063 int UNUSED insn_referenced = abuf->written;
1064 INT sr = -1;
1065 sr = FLD (in_sr);
1066 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1067 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
1068 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
1069 }
1070 return cycles;
1071 #undef FLD
1072 }
1073
1074 static int
1075 model_m32rx_jnc (SIM_CPU *current_cpu, void *sem_arg)
1076 {
1077 #define FLD(f) abuf->fields.cti.fields.fmt_jc.f
1078 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1079 int cycles = 0;
1080 {
1081 int referenced = 0;
1082 int UNUSED insn_referenced = abuf->written;
1083 INT sr = -1;
1084 sr = FLD (in_sr);
1085 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
1086 if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
1087 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
1088 }
1089 return cycles;
1090 #undef FLD
1091 }
1092
1093 static int
1094 model_m32rx_jl (SIM_CPU *current_cpu, void *sem_arg)
1095 {
1096 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
1097 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1098 int cycles = 0;
1099 {
1100 int referenced = 0;
1101 int UNUSED insn_referenced = abuf->written;
1102 INT sr = -1;
1103 sr = FLD (in_sr);
1104 referenced |= 1 << 0;
1105 referenced |= 1 << 1;
1106 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
1107 }
1108 return cycles;
1109 #undef FLD
1110 }
1111
1112 static int
1113 model_m32rx_jmp (SIM_CPU *current_cpu, void *sem_arg)
1114 {
1115 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
1116 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1117 int cycles = 0;
1118 {
1119 int referenced = 0;
1120 int UNUSED insn_referenced = abuf->written;
1121 INT sr = -1;
1122 sr = FLD (in_sr);
1123 referenced |= 1 << 0;
1124 referenced |= 1 << 1;
1125 cycles += m32rxf_model_m32rx_u_cti (current_cpu, abuf->idesc, 0, referenced, sr);
1126 }
1127 return cycles;
1128 #undef FLD
1129 }
1130
1131 static int
1132 model_m32rx_ld (SIM_CPU *current_cpu, void *sem_arg)
1133 {
1134 #define FLD(f) abuf->fields.fmt_ld.f
1135 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1136 int cycles = 0;
1137 {
1138 int referenced = 0;
1139 int UNUSED insn_referenced = abuf->written;
1140 INT sr = 0;
1141 INT dr = 0;
1142 sr = FLD (in_sr);
1143 dr = FLD (out_dr);
1144 referenced |= 1 << 0;
1145 referenced |= 1 << 1;
1146 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1147 }
1148 return cycles;
1149 #undef FLD
1150 }
1151
1152 static int
1153 model_m32rx_ld_d (SIM_CPU *current_cpu, void *sem_arg)
1154 {
1155 #define FLD(f) abuf->fields.fmt_ld_d.f
1156 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1157 int cycles = 0;
1158 {
1159 int referenced = 0;
1160 int UNUSED insn_referenced = abuf->written;
1161 INT sr = 0;
1162 INT dr = 0;
1163 sr = FLD (in_sr);
1164 dr = FLD (out_dr);
1165 referenced |= 1 << 0;
1166 referenced |= 1 << 1;
1167 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1168 }
1169 return cycles;
1170 #undef FLD
1171 }
1172
1173 static int
1174 model_m32rx_ldb (SIM_CPU *current_cpu, void *sem_arg)
1175 {
1176 #define FLD(f) abuf->fields.fmt_ldb.f
1177 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1178 int cycles = 0;
1179 {
1180 int referenced = 0;
1181 int UNUSED insn_referenced = abuf->written;
1182 INT sr = 0;
1183 INT dr = 0;
1184 sr = FLD (in_sr);
1185 dr = FLD (out_dr);
1186 referenced |= 1 << 0;
1187 referenced |= 1 << 1;
1188 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1189 }
1190 return cycles;
1191 #undef FLD
1192 }
1193
1194 static int
1195 model_m32rx_ldb_d (SIM_CPU *current_cpu, void *sem_arg)
1196 {
1197 #define FLD(f) abuf->fields.fmt_ldb_d.f
1198 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1199 int cycles = 0;
1200 {
1201 int referenced = 0;
1202 int UNUSED insn_referenced = abuf->written;
1203 INT sr = 0;
1204 INT dr = 0;
1205 sr = FLD (in_sr);
1206 dr = FLD (out_dr);
1207 referenced |= 1 << 0;
1208 referenced |= 1 << 1;
1209 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1210 }
1211 return cycles;
1212 #undef FLD
1213 }
1214
1215 static int
1216 model_m32rx_ldh (SIM_CPU *current_cpu, void *sem_arg)
1217 {
1218 #define FLD(f) abuf->fields.fmt_ldh.f
1219 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1220 int cycles = 0;
1221 {
1222 int referenced = 0;
1223 int UNUSED insn_referenced = abuf->written;
1224 INT sr = 0;
1225 INT dr = 0;
1226 sr = FLD (in_sr);
1227 dr = FLD (out_dr);
1228 referenced |= 1 << 0;
1229 referenced |= 1 << 1;
1230 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1231 }
1232 return cycles;
1233 #undef FLD
1234 }
1235
1236 static int
1237 model_m32rx_ldh_d (SIM_CPU *current_cpu, void *sem_arg)
1238 {
1239 #define FLD(f) abuf->fields.fmt_ldh_d.f
1240 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1241 int cycles = 0;
1242 {
1243 int referenced = 0;
1244 int UNUSED insn_referenced = abuf->written;
1245 INT sr = 0;
1246 INT dr = 0;
1247 sr = FLD (in_sr);
1248 dr = FLD (out_dr);
1249 referenced |= 1 << 0;
1250 referenced |= 1 << 1;
1251 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1252 }
1253 return cycles;
1254 #undef FLD
1255 }
1256
1257 static int
1258 model_m32rx_ldub (SIM_CPU *current_cpu, void *sem_arg)
1259 {
1260 #define FLD(f) abuf->fields.fmt_ldb.f
1261 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1262 int cycles = 0;
1263 {
1264 int referenced = 0;
1265 int UNUSED insn_referenced = abuf->written;
1266 INT sr = 0;
1267 INT dr = 0;
1268 sr = FLD (in_sr);
1269 dr = FLD (out_dr);
1270 referenced |= 1 << 0;
1271 referenced |= 1 << 1;
1272 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1273 }
1274 return cycles;
1275 #undef FLD
1276 }
1277
1278 static int
1279 model_m32rx_ldub_d (SIM_CPU *current_cpu, void *sem_arg)
1280 {
1281 #define FLD(f) abuf->fields.fmt_ldb_d.f
1282 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1283 int cycles = 0;
1284 {
1285 int referenced = 0;
1286 int UNUSED insn_referenced = abuf->written;
1287 INT sr = 0;
1288 INT dr = 0;
1289 sr = FLD (in_sr);
1290 dr = FLD (out_dr);
1291 referenced |= 1 << 0;
1292 referenced |= 1 << 1;
1293 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1294 }
1295 return cycles;
1296 #undef FLD
1297 }
1298
1299 static int
1300 model_m32rx_lduh (SIM_CPU *current_cpu, void *sem_arg)
1301 {
1302 #define FLD(f) abuf->fields.fmt_ldh.f
1303 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1304 int cycles = 0;
1305 {
1306 int referenced = 0;
1307 int UNUSED insn_referenced = abuf->written;
1308 INT sr = 0;
1309 INT dr = 0;
1310 sr = FLD (in_sr);
1311 dr = FLD (out_dr);
1312 referenced |= 1 << 0;
1313 referenced |= 1 << 1;
1314 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1315 }
1316 return cycles;
1317 #undef FLD
1318 }
1319
1320 static int
1321 model_m32rx_lduh_d (SIM_CPU *current_cpu, void *sem_arg)
1322 {
1323 #define FLD(f) abuf->fields.fmt_ldh_d.f
1324 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1325 int cycles = 0;
1326 {
1327 int referenced = 0;
1328 int UNUSED insn_referenced = abuf->written;
1329 INT sr = 0;
1330 INT dr = 0;
1331 sr = FLD (in_sr);
1332 dr = FLD (out_dr);
1333 referenced |= 1 << 0;
1334 referenced |= 1 << 1;
1335 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1336 }
1337 return cycles;
1338 #undef FLD
1339 }
1340
1341 static int
1342 model_m32rx_ld_plus (SIM_CPU *current_cpu, void *sem_arg)
1343 {
1344 #define FLD(f) abuf->fields.fmt_ld_plus.f
1345 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1346 int cycles = 0;
1347 {
1348 int referenced = 0;
1349 int UNUSED insn_referenced = abuf->written;
1350 INT sr = 0;
1351 INT dr = 0;
1352 sr = FLD (in_sr);
1353 dr = FLD (out_dr);
1354 referenced |= 1 << 0;
1355 referenced |= 1 << 1;
1356 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1357 }
1358 {
1359 int referenced = 0;
1360 int UNUSED insn_referenced = abuf->written;
1361 INT sr = -1;
1362 INT sr2 = -1;
1363 INT dr = -1;
1364 sr = FLD (in_sr);
1365 dr = FLD (out_sr);
1366 referenced |= 1 << 0;
1367 referenced |= 1 << 2;
1368 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 1, referenced, sr, sr2, dr);
1369 }
1370 return cycles;
1371 #undef FLD
1372 }
1373
1374 static int
1375 model_m32rx_ld24 (SIM_CPU *current_cpu, void *sem_arg)
1376 {
1377 #define FLD(f) abuf->fields.fmt_ld24.f
1378 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1379 int cycles = 0;
1380 {
1381 int referenced = 0;
1382 int UNUSED insn_referenced = abuf->written;
1383 INT sr = -1;
1384 INT sr2 = -1;
1385 INT dr = -1;
1386 dr = FLD (out_dr);
1387 referenced |= 1 << 2;
1388 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1389 }
1390 return cycles;
1391 #undef FLD
1392 }
1393
1394 static int
1395 model_m32rx_ldi8 (SIM_CPU *current_cpu, void *sem_arg)
1396 {
1397 #define FLD(f) abuf->fields.fmt_ldi8.f
1398 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1399 int cycles = 0;
1400 {
1401 int referenced = 0;
1402 int UNUSED insn_referenced = abuf->written;
1403 INT sr = -1;
1404 INT sr2 = -1;
1405 INT dr = -1;
1406 dr = FLD (out_dr);
1407 referenced |= 1 << 2;
1408 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1409 }
1410 return cycles;
1411 #undef FLD
1412 }
1413
1414 static int
1415 model_m32rx_ldi16 (SIM_CPU *current_cpu, void *sem_arg)
1416 {
1417 #define FLD(f) abuf->fields.fmt_ldi16.f
1418 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1419 int cycles = 0;
1420 {
1421 int referenced = 0;
1422 int UNUSED insn_referenced = abuf->written;
1423 INT sr = -1;
1424 INT sr2 = -1;
1425 INT dr = -1;
1426 dr = FLD (out_dr);
1427 referenced |= 1 << 2;
1428 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1429 }
1430 return cycles;
1431 #undef FLD
1432 }
1433
1434 static int
1435 model_m32rx_lock (SIM_CPU *current_cpu, void *sem_arg)
1436 {
1437 #define FLD(f) abuf->fields.fmt_lock.f
1438 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1439 int cycles = 0;
1440 {
1441 int referenced = 0;
1442 int UNUSED insn_referenced = abuf->written;
1443 INT sr = 0;
1444 INT dr = 0;
1445 sr = FLD (in_sr);
1446 dr = FLD (out_dr);
1447 referenced |= 1 << 0;
1448 referenced |= 1 << 1;
1449 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
1450 }
1451 return cycles;
1452 #undef FLD
1453 }
1454
1455 static int
1456 model_m32rx_machi_a (SIM_CPU *current_cpu, void *sem_arg)
1457 {
1458 #define FLD(f) abuf->fields.fmt_machi_a.f
1459 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1460 int cycles = 0;
1461 {
1462 int referenced = 0;
1463 int UNUSED insn_referenced = abuf->written;
1464 INT src1 = -1;
1465 INT src2 = -1;
1466 src1 = FLD (in_src1);
1467 src2 = FLD (in_src2);
1468 referenced |= 1 << 0;
1469 referenced |= 1 << 1;
1470 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1471 }
1472 return cycles;
1473 #undef FLD
1474 }
1475
1476 static int
1477 model_m32rx_maclo_a (SIM_CPU *current_cpu, void *sem_arg)
1478 {
1479 #define FLD(f) abuf->fields.fmt_machi_a.f
1480 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1481 int cycles = 0;
1482 {
1483 int referenced = 0;
1484 int UNUSED insn_referenced = abuf->written;
1485 INT src1 = -1;
1486 INT src2 = -1;
1487 src1 = FLD (in_src1);
1488 src2 = FLD (in_src2);
1489 referenced |= 1 << 0;
1490 referenced |= 1 << 1;
1491 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1492 }
1493 return cycles;
1494 #undef FLD
1495 }
1496
1497 static int
1498 model_m32rx_macwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1499 {
1500 #define FLD(f) abuf->fields.fmt_machi_a.f
1501 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1502 int cycles = 0;
1503 {
1504 int referenced = 0;
1505 int UNUSED insn_referenced = abuf->written;
1506 INT src1 = -1;
1507 INT src2 = -1;
1508 src1 = FLD (in_src1);
1509 src2 = FLD (in_src2);
1510 referenced |= 1 << 0;
1511 referenced |= 1 << 1;
1512 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1513 }
1514 return cycles;
1515 #undef FLD
1516 }
1517
1518 static int
1519 model_m32rx_macwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1520 {
1521 #define FLD(f) abuf->fields.fmt_machi_a.f
1522 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1523 int cycles = 0;
1524 {
1525 int referenced = 0;
1526 int UNUSED insn_referenced = abuf->written;
1527 INT src1 = -1;
1528 INT src2 = -1;
1529 src1 = FLD (in_src1);
1530 src2 = FLD (in_src2);
1531 referenced |= 1 << 0;
1532 referenced |= 1 << 1;
1533 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1534 }
1535 return cycles;
1536 #undef FLD
1537 }
1538
1539 static int
1540 model_m32rx_mul (SIM_CPU *current_cpu, void *sem_arg)
1541 {
1542 #define FLD(f) abuf->fields.fmt_add.f
1543 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1544 int cycles = 0;
1545 {
1546 int referenced = 0;
1547 int UNUSED insn_referenced = abuf->written;
1548 INT sr = -1;
1549 INT sr2 = -1;
1550 INT dr = -1;
1551 sr = FLD (in_sr);
1552 dr = FLD (out_dr);
1553 referenced |= 1 << 0;
1554 referenced |= 1 << 2;
1555 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1556 }
1557 return cycles;
1558 #undef FLD
1559 }
1560
1561 static int
1562 model_m32rx_mulhi_a (SIM_CPU *current_cpu, void *sem_arg)
1563 {
1564 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1565 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1566 int cycles = 0;
1567 {
1568 int referenced = 0;
1569 int UNUSED insn_referenced = abuf->written;
1570 INT src1 = -1;
1571 INT src2 = -1;
1572 src1 = FLD (in_src1);
1573 src2 = FLD (in_src2);
1574 referenced |= 1 << 0;
1575 referenced |= 1 << 1;
1576 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1577 }
1578 return cycles;
1579 #undef FLD
1580 }
1581
1582 static int
1583 model_m32rx_mullo_a (SIM_CPU *current_cpu, void *sem_arg)
1584 {
1585 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1586 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1587 int cycles = 0;
1588 {
1589 int referenced = 0;
1590 int UNUSED insn_referenced = abuf->written;
1591 INT src1 = -1;
1592 INT src2 = -1;
1593 src1 = FLD (in_src1);
1594 src2 = FLD (in_src2);
1595 referenced |= 1 << 0;
1596 referenced |= 1 << 1;
1597 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1598 }
1599 return cycles;
1600 #undef FLD
1601 }
1602
1603 static int
1604 model_m32rx_mulwhi_a (SIM_CPU *current_cpu, void *sem_arg)
1605 {
1606 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1607 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1608 int cycles = 0;
1609 {
1610 int referenced = 0;
1611 int UNUSED insn_referenced = abuf->written;
1612 INT src1 = -1;
1613 INT src2 = -1;
1614 src1 = FLD (in_src1);
1615 src2 = FLD (in_src2);
1616 referenced |= 1 << 0;
1617 referenced |= 1 << 1;
1618 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1619 }
1620 return cycles;
1621 #undef FLD
1622 }
1623
1624 static int
1625 model_m32rx_mulwlo_a (SIM_CPU *current_cpu, void *sem_arg)
1626 {
1627 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1628 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1629 int cycles = 0;
1630 {
1631 int referenced = 0;
1632 int UNUSED insn_referenced = abuf->written;
1633 INT src1 = -1;
1634 INT src2 = -1;
1635 src1 = FLD (in_src1);
1636 src2 = FLD (in_src2);
1637 referenced |= 1 << 0;
1638 referenced |= 1 << 1;
1639 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1640 }
1641 return cycles;
1642 #undef FLD
1643 }
1644
1645 static int
1646 model_m32rx_mv (SIM_CPU *current_cpu, void *sem_arg)
1647 {
1648 #define FLD(f) abuf->fields.fmt_mv.f
1649 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1650 int cycles = 0;
1651 {
1652 int referenced = 0;
1653 int UNUSED insn_referenced = abuf->written;
1654 INT sr = -1;
1655 INT sr2 = -1;
1656 INT dr = -1;
1657 sr = FLD (in_sr);
1658 dr = FLD (out_dr);
1659 referenced |= 1 << 0;
1660 referenced |= 1 << 2;
1661 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1662 }
1663 return cycles;
1664 #undef FLD
1665 }
1666
1667 static int
1668 model_m32rx_mvfachi_a (SIM_CPU *current_cpu, void *sem_arg)
1669 {
1670 #define FLD(f) abuf->fields.fmt_mvfachi_a.f
1671 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1672 int cycles = 0;
1673 {
1674 int referenced = 0;
1675 int UNUSED insn_referenced = abuf->written;
1676 INT sr = -1;
1677 INT sr2 = -1;
1678 INT dr = -1;
1679 dr = FLD (out_dr);
1680 referenced |= 1 << 2;
1681 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1682 }
1683 return cycles;
1684 #undef FLD
1685 }
1686
1687 static int
1688 model_m32rx_mvfaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1689 {
1690 #define FLD(f) abuf->fields.fmt_mvfachi_a.f
1691 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1692 int cycles = 0;
1693 {
1694 int referenced = 0;
1695 int UNUSED insn_referenced = abuf->written;
1696 INT sr = -1;
1697 INT sr2 = -1;
1698 INT dr = -1;
1699 dr = FLD (out_dr);
1700 referenced |= 1 << 2;
1701 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1702 }
1703 return cycles;
1704 #undef FLD
1705 }
1706
1707 static int
1708 model_m32rx_mvfacmi_a (SIM_CPU *current_cpu, void *sem_arg)
1709 {
1710 #define FLD(f) abuf->fields.fmt_mvfachi_a.f
1711 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1712 int cycles = 0;
1713 {
1714 int referenced = 0;
1715 int UNUSED insn_referenced = abuf->written;
1716 INT sr = -1;
1717 INT sr2 = -1;
1718 INT dr = -1;
1719 dr = FLD (out_dr);
1720 referenced |= 1 << 2;
1721 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1722 }
1723 return cycles;
1724 #undef FLD
1725 }
1726
1727 static int
1728 model_m32rx_mvfc (SIM_CPU *current_cpu, void *sem_arg)
1729 {
1730 #define FLD(f) abuf->fields.fmt_mvfc.f
1731 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1732 int cycles = 0;
1733 {
1734 int referenced = 0;
1735 int UNUSED insn_referenced = abuf->written;
1736 INT sr = -1;
1737 INT sr2 = -1;
1738 INT dr = -1;
1739 dr = FLD (out_dr);
1740 referenced |= 1 << 2;
1741 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1742 }
1743 return cycles;
1744 #undef FLD
1745 }
1746
1747 static int
1748 model_m32rx_mvtachi_a (SIM_CPU *current_cpu, void *sem_arg)
1749 {
1750 #define FLD(f) abuf->fields.fmt_mvtachi_a.f
1751 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1752 int cycles = 0;
1753 {
1754 int referenced = 0;
1755 int UNUSED insn_referenced = abuf->written;
1756 INT sr = -1;
1757 INT sr2 = -1;
1758 INT dr = -1;
1759 sr = FLD (in_src1);
1760 referenced |= 1 << 0;
1761 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1762 }
1763 return cycles;
1764 #undef FLD
1765 }
1766
1767 static int
1768 model_m32rx_mvtaclo_a (SIM_CPU *current_cpu, void *sem_arg)
1769 {
1770 #define FLD(f) abuf->fields.fmt_mvtachi_a.f
1771 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1772 int cycles = 0;
1773 {
1774 int referenced = 0;
1775 int UNUSED insn_referenced = abuf->written;
1776 INT sr = -1;
1777 INT sr2 = -1;
1778 INT dr = -1;
1779 sr = FLD (in_src1);
1780 referenced |= 1 << 0;
1781 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1782 }
1783 return cycles;
1784 #undef FLD
1785 }
1786
1787 static int
1788 model_m32rx_mvtc (SIM_CPU *current_cpu, void *sem_arg)
1789 {
1790 #define FLD(f) abuf->fields.fmt_mvtc.f
1791 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1792 int cycles = 0;
1793 {
1794 int referenced = 0;
1795 int UNUSED insn_referenced = abuf->written;
1796 INT sr = -1;
1797 INT sr2 = -1;
1798 INT dr = -1;
1799 sr = FLD (in_sr);
1800 referenced |= 1 << 0;
1801 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1802 }
1803 return cycles;
1804 #undef FLD
1805 }
1806
1807 static int
1808 model_m32rx_neg (SIM_CPU *current_cpu, void *sem_arg)
1809 {
1810 #define FLD(f) abuf->fields.fmt_mv.f
1811 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1812 int cycles = 0;
1813 {
1814 int referenced = 0;
1815 int UNUSED insn_referenced = abuf->written;
1816 INT sr = -1;
1817 INT sr2 = -1;
1818 INT dr = -1;
1819 sr = FLD (in_sr);
1820 dr = FLD (out_dr);
1821 referenced |= 1 << 0;
1822 referenced |= 1 << 2;
1823 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1824 }
1825 return cycles;
1826 #undef FLD
1827 }
1828
1829 static int
1830 model_m32rx_nop (SIM_CPU *current_cpu, void *sem_arg)
1831 {
1832 #define FLD(f) abuf->fields.fmt_nop.f
1833 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1834 int cycles = 0;
1835 {
1836 int referenced = 0;
1837 int UNUSED insn_referenced = abuf->written;
1838 INT sr = -1;
1839 INT sr2 = -1;
1840 INT dr = -1;
1841 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1842 }
1843 return cycles;
1844 #undef FLD
1845 }
1846
1847 static int
1848 model_m32rx_not (SIM_CPU *current_cpu, void *sem_arg)
1849 {
1850 #define FLD(f) abuf->fields.fmt_mv.f
1851 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1852 int cycles = 0;
1853 {
1854 int referenced = 0;
1855 int UNUSED insn_referenced = abuf->written;
1856 INT sr = -1;
1857 INT sr2 = -1;
1858 INT dr = -1;
1859 sr = FLD (in_sr);
1860 dr = FLD (out_dr);
1861 referenced |= 1 << 0;
1862 referenced |= 1 << 2;
1863 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1864 }
1865 return cycles;
1866 #undef FLD
1867 }
1868
1869 static int
1870 model_m32rx_rac_dsi (SIM_CPU *current_cpu, void *sem_arg)
1871 {
1872 #define FLD(f) abuf->fields.fmt_rac_dsi.f
1873 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1874 int cycles = 0;
1875 {
1876 int referenced = 0;
1877 int UNUSED insn_referenced = abuf->written;
1878 INT src1 = -1;
1879 INT src2 = -1;
1880 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1881 }
1882 return cycles;
1883 #undef FLD
1884 }
1885
1886 static int
1887 model_m32rx_rach_dsi (SIM_CPU *current_cpu, void *sem_arg)
1888 {
1889 #define FLD(f) abuf->fields.fmt_rac_dsi.f
1890 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1891 int cycles = 0;
1892 {
1893 int referenced = 0;
1894 int UNUSED insn_referenced = abuf->written;
1895 INT src1 = -1;
1896 INT src2 = -1;
1897 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
1898 }
1899 return cycles;
1900 #undef FLD
1901 }
1902
1903 static int
1904 model_m32rx_rte (SIM_CPU *current_cpu, void *sem_arg)
1905 {
1906 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1907 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1908 int cycles = 0;
1909 {
1910 int referenced = 0;
1911 int UNUSED insn_referenced = abuf->written;
1912 INT sr = -1;
1913 INT sr2 = -1;
1914 INT dr = -1;
1915 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1916 }
1917 return cycles;
1918 #undef FLD
1919 }
1920
1921 static int
1922 model_m32rx_seth (SIM_CPU *current_cpu, void *sem_arg)
1923 {
1924 #define FLD(f) abuf->fields.fmt_seth.f
1925 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1926 int cycles = 0;
1927 {
1928 int referenced = 0;
1929 int UNUSED insn_referenced = abuf->written;
1930 INT sr = -1;
1931 INT sr2 = -1;
1932 INT dr = -1;
1933 dr = FLD (out_dr);
1934 referenced |= 1 << 2;
1935 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1936 }
1937 return cycles;
1938 #undef FLD
1939 }
1940
1941 static int
1942 model_m32rx_sll (SIM_CPU *current_cpu, void *sem_arg)
1943 {
1944 #define FLD(f) abuf->fields.fmt_add.f
1945 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1946 int cycles = 0;
1947 {
1948 int referenced = 0;
1949 int UNUSED insn_referenced = abuf->written;
1950 INT sr = -1;
1951 INT sr2 = -1;
1952 INT dr = -1;
1953 sr = FLD (in_sr);
1954 dr = FLD (out_dr);
1955 referenced |= 1 << 0;
1956 referenced |= 1 << 2;
1957 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1958 }
1959 return cycles;
1960 #undef FLD
1961 }
1962
1963 static int
1964 model_m32rx_sll3 (SIM_CPU *current_cpu, void *sem_arg)
1965 {
1966 #define FLD(f) abuf->fields.fmt_sll3.f
1967 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1968 int cycles = 0;
1969 {
1970 int referenced = 0;
1971 int UNUSED insn_referenced = abuf->written;
1972 INT sr = -1;
1973 INT sr2 = -1;
1974 INT dr = -1;
1975 sr = FLD (in_sr);
1976 dr = FLD (out_dr);
1977 referenced |= 1 << 0;
1978 referenced |= 1 << 2;
1979 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
1980 }
1981 return cycles;
1982 #undef FLD
1983 }
1984
1985 static int
1986 model_m32rx_slli (SIM_CPU *current_cpu, void *sem_arg)
1987 {
1988 #define FLD(f) abuf->fields.fmt_slli.f
1989 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
1990 int cycles = 0;
1991 {
1992 int referenced = 0;
1993 int UNUSED insn_referenced = abuf->written;
1994 INT sr = -1;
1995 INT sr2 = -1;
1996 INT dr = -1;
1997 dr = FLD (out_dr);
1998 referenced |= 1 << 2;
1999 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2000 }
2001 return cycles;
2002 #undef FLD
2003 }
2004
2005 static int
2006 model_m32rx_sra (SIM_CPU *current_cpu, void *sem_arg)
2007 {
2008 #define FLD(f) abuf->fields.fmt_add.f
2009 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2010 int cycles = 0;
2011 {
2012 int referenced = 0;
2013 int UNUSED insn_referenced = abuf->written;
2014 INT sr = -1;
2015 INT sr2 = -1;
2016 INT dr = -1;
2017 sr = FLD (in_sr);
2018 dr = FLD (out_dr);
2019 referenced |= 1 << 0;
2020 referenced |= 1 << 2;
2021 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2022 }
2023 return cycles;
2024 #undef FLD
2025 }
2026
2027 static int
2028 model_m32rx_sra3 (SIM_CPU *current_cpu, void *sem_arg)
2029 {
2030 #define FLD(f) abuf->fields.fmt_sll3.f
2031 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2032 int cycles = 0;
2033 {
2034 int referenced = 0;
2035 int UNUSED insn_referenced = abuf->written;
2036 INT sr = -1;
2037 INT sr2 = -1;
2038 INT dr = -1;
2039 sr = FLD (in_sr);
2040 dr = FLD (out_dr);
2041 referenced |= 1 << 0;
2042 referenced |= 1 << 2;
2043 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2044 }
2045 return cycles;
2046 #undef FLD
2047 }
2048
2049 static int
2050 model_m32rx_srai (SIM_CPU *current_cpu, void *sem_arg)
2051 {
2052 #define FLD(f) abuf->fields.fmt_slli.f
2053 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2054 int cycles = 0;
2055 {
2056 int referenced = 0;
2057 int UNUSED insn_referenced = abuf->written;
2058 INT sr = -1;
2059 INT sr2 = -1;
2060 INT dr = -1;
2061 dr = FLD (out_dr);
2062 referenced |= 1 << 2;
2063 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2064 }
2065 return cycles;
2066 #undef FLD
2067 }
2068
2069 static int
2070 model_m32rx_srl (SIM_CPU *current_cpu, void *sem_arg)
2071 {
2072 #define FLD(f) abuf->fields.fmt_add.f
2073 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2074 int cycles = 0;
2075 {
2076 int referenced = 0;
2077 int UNUSED insn_referenced = abuf->written;
2078 INT sr = -1;
2079 INT sr2 = -1;
2080 INT dr = -1;
2081 sr = FLD (in_sr);
2082 dr = FLD (out_dr);
2083 referenced |= 1 << 0;
2084 referenced |= 1 << 2;
2085 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2086 }
2087 return cycles;
2088 #undef FLD
2089 }
2090
2091 static int
2092 model_m32rx_srl3 (SIM_CPU *current_cpu, void *sem_arg)
2093 {
2094 #define FLD(f) abuf->fields.fmt_sll3.f
2095 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2096 int cycles = 0;
2097 {
2098 int referenced = 0;
2099 int UNUSED insn_referenced = abuf->written;
2100 INT sr = -1;
2101 INT sr2 = -1;
2102 INT dr = -1;
2103 sr = FLD (in_sr);
2104 dr = FLD (out_dr);
2105 referenced |= 1 << 0;
2106 referenced |= 1 << 2;
2107 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2108 }
2109 return cycles;
2110 #undef FLD
2111 }
2112
2113 static int
2114 model_m32rx_srli (SIM_CPU *current_cpu, void *sem_arg)
2115 {
2116 #define FLD(f) abuf->fields.fmt_slli.f
2117 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2118 int cycles = 0;
2119 {
2120 int referenced = 0;
2121 int UNUSED insn_referenced = abuf->written;
2122 INT sr = -1;
2123 INT sr2 = -1;
2124 INT dr = -1;
2125 dr = FLD (out_dr);
2126 referenced |= 1 << 2;
2127 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2128 }
2129 return cycles;
2130 #undef FLD
2131 }
2132
2133 static int
2134 model_m32rx_st (SIM_CPU *current_cpu, void *sem_arg)
2135 {
2136 #define FLD(f) abuf->fields.fmt_st.f
2137 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2138 int cycles = 0;
2139 {
2140 int referenced = 0;
2141 int UNUSED insn_referenced = abuf->written;
2142 INT src1 = 0;
2143 INT src2 = 0;
2144 src1 = FLD (in_src1);
2145 src2 = FLD (in_src2);
2146 referenced |= 1 << 0;
2147 referenced |= 1 << 1;
2148 cycles += m32rxf_model_m32rx_u_store (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2149 }
2150 return cycles;
2151 #undef FLD
2152 }
2153
2154 static int
2155 model_m32rx_st_d (SIM_CPU *current_cpu, void *sem_arg)
2156 {
2157 #define FLD(f) abuf->fields.fmt_st_d.f
2158 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2159 int cycles = 0;
2160 {
2161 int referenced = 0;
2162 int UNUSED insn_referenced = abuf->written;
2163 INT src1 = 0;
2164 INT src2 = 0;
2165 src1 = FLD (in_src1);
2166 src2 = FLD (in_src2);
2167 referenced |= 1 << 0;
2168 referenced |= 1 << 1;
2169 cycles += m32rxf_model_m32rx_u_store (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2170 }
2171 return cycles;
2172 #undef FLD
2173 }
2174
2175 static int
2176 model_m32rx_stb (SIM_CPU *current_cpu, void *sem_arg)
2177 {
2178 #define FLD(f) abuf->fields.fmt_stb.f
2179 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2180 int cycles = 0;
2181 {
2182 int referenced = 0;
2183 int UNUSED insn_referenced = abuf->written;
2184 INT src1 = 0;
2185 INT src2 = 0;
2186 src1 = FLD (in_src1);
2187 src2 = FLD (in_src2);
2188 referenced |= 1 << 0;
2189 referenced |= 1 << 1;
2190 cycles += m32rxf_model_m32rx_u_store (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2191 }
2192 return cycles;
2193 #undef FLD
2194 }
2195
2196 static int
2197 model_m32rx_stb_d (SIM_CPU *current_cpu, void *sem_arg)
2198 {
2199 #define FLD(f) abuf->fields.fmt_stb_d.f
2200 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2201 int cycles = 0;
2202 {
2203 int referenced = 0;
2204 int UNUSED insn_referenced = abuf->written;
2205 INT src1 = 0;
2206 INT src2 = 0;
2207 src1 = FLD (in_src1);
2208 src2 = FLD (in_src2);
2209 referenced |= 1 << 0;
2210 referenced |= 1 << 1;
2211 cycles += m32rxf_model_m32rx_u_store (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2212 }
2213 return cycles;
2214 #undef FLD
2215 }
2216
2217 static int
2218 model_m32rx_sth (SIM_CPU *current_cpu, void *sem_arg)
2219 {
2220 #define FLD(f) abuf->fields.fmt_sth.f
2221 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2222 int cycles = 0;
2223 {
2224 int referenced = 0;
2225 int UNUSED insn_referenced = abuf->written;
2226 INT src1 = 0;
2227 INT src2 = 0;
2228 src1 = FLD (in_src1);
2229 src2 = FLD (in_src2);
2230 referenced |= 1 << 0;
2231 referenced |= 1 << 1;
2232 cycles += m32rxf_model_m32rx_u_store (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2233 }
2234 return cycles;
2235 #undef FLD
2236 }
2237
2238 static int
2239 model_m32rx_sth_d (SIM_CPU *current_cpu, void *sem_arg)
2240 {
2241 #define FLD(f) abuf->fields.fmt_sth_d.f
2242 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2243 int cycles = 0;
2244 {
2245 int referenced = 0;
2246 int UNUSED insn_referenced = abuf->written;
2247 INT src1 = 0;
2248 INT src2 = 0;
2249 src1 = FLD (in_src1);
2250 src2 = FLD (in_src2);
2251 referenced |= 1 << 0;
2252 referenced |= 1 << 1;
2253 cycles += m32rxf_model_m32rx_u_store (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2254 }
2255 return cycles;
2256 #undef FLD
2257 }
2258
2259 static int
2260 model_m32rx_st_plus (SIM_CPU *current_cpu, void *sem_arg)
2261 {
2262 #define FLD(f) abuf->fields.fmt_st_plus.f
2263 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2264 int cycles = 0;
2265 {
2266 int referenced = 0;
2267 int UNUSED insn_referenced = abuf->written;
2268 INT src1 = 0;
2269 INT src2 = 0;
2270 src1 = FLD (in_src1);
2271 src2 = FLD (in_src2);
2272 referenced |= 1 << 0;
2273 referenced |= 1 << 1;
2274 cycles += m32rxf_model_m32rx_u_store (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2275 }
2276 {
2277 int referenced = 0;
2278 int UNUSED insn_referenced = abuf->written;
2279 INT sr = -1;
2280 INT sr2 = -1;
2281 INT dr = -1;
2282 dr = FLD (out_src2);
2283 sr = FLD (in_src2);
2284 referenced |= 1 << 0;
2285 referenced |= 1 << 2;
2286 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 1, referenced, sr, sr2, dr);
2287 }
2288 return cycles;
2289 #undef FLD
2290 }
2291
2292 static int
2293 model_m32rx_st_minus (SIM_CPU *current_cpu, void *sem_arg)
2294 {
2295 #define FLD(f) abuf->fields.fmt_st_plus.f
2296 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2297 int cycles = 0;
2298 {
2299 int referenced = 0;
2300 int UNUSED insn_referenced = abuf->written;
2301 INT src1 = 0;
2302 INT src2 = 0;
2303 src1 = FLD (in_src1);
2304 src2 = FLD (in_src2);
2305 referenced |= 1 << 0;
2306 referenced |= 1 << 1;
2307 cycles += m32rxf_model_m32rx_u_store (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2308 }
2309 {
2310 int referenced = 0;
2311 int UNUSED insn_referenced = abuf->written;
2312 INT sr = -1;
2313 INT sr2 = -1;
2314 INT dr = -1;
2315 dr = FLD (out_src2);
2316 sr = FLD (in_src2);
2317 referenced |= 1 << 0;
2318 referenced |= 1 << 2;
2319 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 1, referenced, sr, sr2, dr);
2320 }
2321 return cycles;
2322 #undef FLD
2323 }
2324
2325 static int
2326 model_m32rx_sub (SIM_CPU *current_cpu, void *sem_arg)
2327 {
2328 #define FLD(f) abuf->fields.fmt_add.f
2329 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2330 int cycles = 0;
2331 {
2332 int referenced = 0;
2333 int UNUSED insn_referenced = abuf->written;
2334 INT sr = -1;
2335 INT sr2 = -1;
2336 INT dr = -1;
2337 sr = FLD (in_sr);
2338 dr = FLD (out_dr);
2339 referenced |= 1 << 0;
2340 referenced |= 1 << 2;
2341 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2342 }
2343 return cycles;
2344 #undef FLD
2345 }
2346
2347 static int
2348 model_m32rx_subv (SIM_CPU *current_cpu, void *sem_arg)
2349 {
2350 #define FLD(f) abuf->fields.fmt_addv.f
2351 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2352 int cycles = 0;
2353 {
2354 int referenced = 0;
2355 int UNUSED insn_referenced = abuf->written;
2356 INT sr = -1;
2357 INT sr2 = -1;
2358 INT dr = -1;
2359 sr = FLD (in_sr);
2360 dr = FLD (out_dr);
2361 referenced |= 1 << 0;
2362 referenced |= 1 << 2;
2363 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2364 }
2365 return cycles;
2366 #undef FLD
2367 }
2368
2369 static int
2370 model_m32rx_subx (SIM_CPU *current_cpu, void *sem_arg)
2371 {
2372 #define FLD(f) abuf->fields.fmt_addx.f
2373 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2374 int cycles = 0;
2375 {
2376 int referenced = 0;
2377 int UNUSED insn_referenced = abuf->written;
2378 INT sr = -1;
2379 INT sr2 = -1;
2380 INT dr = -1;
2381 sr = FLD (in_sr);
2382 dr = FLD (out_dr);
2383 referenced |= 1 << 0;
2384 referenced |= 1 << 2;
2385 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2386 }
2387 return cycles;
2388 #undef FLD
2389 }
2390
2391 static int
2392 model_m32rx_trap (SIM_CPU *current_cpu, void *sem_arg)
2393 {
2394 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
2395 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2396 int cycles = 0;
2397 {
2398 int referenced = 0;
2399 int UNUSED insn_referenced = abuf->written;
2400 INT sr = -1;
2401 INT sr2 = -1;
2402 INT dr = -1;
2403 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2404 }
2405 return cycles;
2406 #undef FLD
2407 }
2408
2409 static int
2410 model_m32rx_unlock (SIM_CPU *current_cpu, void *sem_arg)
2411 {
2412 #define FLD(f) abuf->fields.fmt_unlock.f
2413 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2414 int cycles = 0;
2415 {
2416 int referenced = 0;
2417 int UNUSED insn_referenced = abuf->written;
2418 INT sr = 0;
2419 INT dr = 0;
2420 cycles += m32rxf_model_m32rx_u_load (current_cpu, abuf->idesc, 0, referenced, sr, dr);
2421 }
2422 return cycles;
2423 #undef FLD
2424 }
2425
2426 static int
2427 model_m32rx_satb (SIM_CPU *current_cpu, void *sem_arg)
2428 {
2429 #define FLD(f) abuf->fields.fmt_satb.f
2430 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2431 int cycles = 0;
2432 {
2433 int referenced = 0;
2434 int UNUSED insn_referenced = abuf->written;
2435 INT sr = -1;
2436 INT sr2 = -1;
2437 INT dr = -1;
2438 sr = FLD (in_sr);
2439 dr = FLD (out_dr);
2440 referenced |= 1 << 0;
2441 referenced |= 1 << 2;
2442 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2443 }
2444 return cycles;
2445 #undef FLD
2446 }
2447
2448 static int
2449 model_m32rx_sath (SIM_CPU *current_cpu, void *sem_arg)
2450 {
2451 #define FLD(f) abuf->fields.fmt_satb.f
2452 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2453 int cycles = 0;
2454 {
2455 int referenced = 0;
2456 int UNUSED insn_referenced = abuf->written;
2457 INT sr = -1;
2458 INT sr2 = -1;
2459 INT dr = -1;
2460 sr = FLD (in_sr);
2461 dr = FLD (out_dr);
2462 referenced |= 1 << 0;
2463 referenced |= 1 << 2;
2464 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2465 }
2466 return cycles;
2467 #undef FLD
2468 }
2469
2470 static int
2471 model_m32rx_sat (SIM_CPU *current_cpu, void *sem_arg)
2472 {
2473 #define FLD(f) abuf->fields.fmt_sat.f
2474 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2475 int cycles = 0;
2476 {
2477 int referenced = 0;
2478 int UNUSED insn_referenced = abuf->written;
2479 INT sr = -1;
2480 INT sr2 = -1;
2481 INT dr = -1;
2482 sr = FLD (in_sr);
2483 dr = FLD (out_dr);
2484 if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
2485 referenced |= 1 << 2;
2486 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2487 }
2488 return cycles;
2489 #undef FLD
2490 }
2491
2492 static int
2493 model_m32rx_pcmpbz (SIM_CPU *current_cpu, void *sem_arg)
2494 {
2495 #define FLD(f) abuf->fields.fmt_cmpz.f
2496 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2497 int cycles = 0;
2498 {
2499 int referenced = 0;
2500 int UNUSED insn_referenced = abuf->written;
2501 INT src1 = -1;
2502 INT src2 = -1;
2503 src2 = FLD (in_src2);
2504 referenced |= 1 << 1;
2505 cycles += m32rxf_model_m32rx_u_cmp (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2506 }
2507 return cycles;
2508 #undef FLD
2509 }
2510
2511 static int
2512 model_m32rx_sadd (SIM_CPU *current_cpu, void *sem_arg)
2513 {
2514 #define FLD(f) abuf->fields.fmt_sadd.f
2515 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2516 int cycles = 0;
2517 {
2518 int referenced = 0;
2519 int UNUSED insn_referenced = abuf->written;
2520 INT src1 = -1;
2521 INT src2 = -1;
2522 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2523 }
2524 return cycles;
2525 #undef FLD
2526 }
2527
2528 static int
2529 model_m32rx_macwu1 (SIM_CPU *current_cpu, void *sem_arg)
2530 {
2531 #define FLD(f) abuf->fields.fmt_macwu1.f
2532 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2533 int cycles = 0;
2534 {
2535 int referenced = 0;
2536 int UNUSED insn_referenced = abuf->written;
2537 INT src1 = -1;
2538 INT src2 = -1;
2539 src1 = FLD (in_src1);
2540 src2 = FLD (in_src2);
2541 referenced |= 1 << 0;
2542 referenced |= 1 << 1;
2543 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2544 }
2545 return cycles;
2546 #undef FLD
2547 }
2548
2549 static int
2550 model_m32rx_msblo (SIM_CPU *current_cpu, void *sem_arg)
2551 {
2552 #define FLD(f) abuf->fields.fmt_msblo.f
2553 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2554 int cycles = 0;
2555 {
2556 int referenced = 0;
2557 int UNUSED insn_referenced = abuf->written;
2558 INT src1 = -1;
2559 INT src2 = -1;
2560 src1 = FLD (in_src1);
2561 src2 = FLD (in_src2);
2562 referenced |= 1 << 0;
2563 referenced |= 1 << 1;
2564 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2565 }
2566 return cycles;
2567 #undef FLD
2568 }
2569
2570 static int
2571 model_m32rx_mulwu1 (SIM_CPU *current_cpu, void *sem_arg)
2572 {
2573 #define FLD(f) abuf->fields.fmt_mulwu1.f
2574 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2575 int cycles = 0;
2576 {
2577 int referenced = 0;
2578 int UNUSED insn_referenced = abuf->written;
2579 INT src1 = -1;
2580 INT src2 = -1;
2581 src1 = FLD (in_src1);
2582 src2 = FLD (in_src2);
2583 referenced |= 1 << 0;
2584 referenced |= 1 << 1;
2585 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2586 }
2587 return cycles;
2588 #undef FLD
2589 }
2590
2591 static int
2592 model_m32rx_maclh1 (SIM_CPU *current_cpu, void *sem_arg)
2593 {
2594 #define FLD(f) abuf->fields.fmt_macwu1.f
2595 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2596 int cycles = 0;
2597 {
2598 int referenced = 0;
2599 int UNUSED insn_referenced = abuf->written;
2600 INT src1 = -1;
2601 INT src2 = -1;
2602 src1 = FLD (in_src1);
2603 src2 = FLD (in_src2);
2604 referenced |= 1 << 0;
2605 referenced |= 1 << 1;
2606 cycles += m32rxf_model_m32rx_u_mac (current_cpu, abuf->idesc, 0, referenced, src1, src2);
2607 }
2608 return cycles;
2609 #undef FLD
2610 }
2611
2612 static int
2613 model_m32rx_sc (SIM_CPU *current_cpu, void *sem_arg)
2614 {
2615 #define FLD(f) abuf->fields.cti.fields.fmt_sc.f
2616 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2617 int cycles = 0;
2618 {
2619 int referenced = 0;
2620 int UNUSED insn_referenced = abuf->written;
2621 INT sr = -1;
2622 INT sr2 = -1;
2623 INT dr = -1;
2624 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2625 }
2626 return cycles;
2627 #undef FLD
2628 }
2629
2630 static int
2631 model_m32rx_snc (SIM_CPU *current_cpu, void *sem_arg)
2632 {
2633 #define FLD(f) abuf->fields.cti.fields.fmt_sc.f
2634 ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
2635 int cycles = 0;
2636 {
2637 int referenced = 0;
2638 int UNUSED insn_referenced = abuf->written;
2639 INT sr = -1;
2640 INT sr2 = -1;
2641 INT dr = -1;
2642 cycles += m32rxf_model_m32rx_u_exec (current_cpu, abuf->idesc, 0, referenced, sr, sr2, dr);
2643 }
2644 return cycles;
2645 #undef FLD
2646 }
2647
2648 /* We assume UNIT_NONE == 0 because the tables don't always terminate
2649 entries with it. */
2650
2651 /* Model timing data for `m32rx'. */
2652
2653 static const INSN_TIMING m32rx_timing[] = {
2654 { M32RXF_INSN_X_INVALID, model_m32rx_x_invalid, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2655 { M32RXF_INSN_X_AFTER, model_m32rx_x_after, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2656 { M32RXF_INSN_X_BEFORE, model_m32rx_x_before, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2657 { M32RXF_INSN_X_CTI_CHAIN, model_m32rx_x_cti_chain, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2658 { M32RXF_INSN_X_CHAIN, model_m32rx_x_chain, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2659 { M32RXF_INSN_X_BEGIN, model_m32rx_x_begin, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2660 { M32RXF_INSN_ADD, model_m32rx_add, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2661 { M32RXF_INSN_ADD3, model_m32rx_add3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2662 { M32RXF_INSN_AND, model_m32rx_and, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2663 { M32RXF_INSN_AND3, model_m32rx_and3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2664 { M32RXF_INSN_OR, model_m32rx_or, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2665 { M32RXF_INSN_OR3, model_m32rx_or3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2666 { M32RXF_INSN_XOR, model_m32rx_xor, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2667 { M32RXF_INSN_XOR3, model_m32rx_xor3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2668 { M32RXF_INSN_ADDI, model_m32rx_addi, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2669 { M32RXF_INSN_ADDV, model_m32rx_addv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2670 { M32RXF_INSN_ADDV3, model_m32rx_addv3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2671 { M32RXF_INSN_ADDX, model_m32rx_addx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2672 { M32RXF_INSN_BC8, model_m32rx_bc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2673 { M32RXF_INSN_BC24, model_m32rx_bc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2674 { M32RXF_INSN_BEQ, model_m32rx_beq, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2675 { M32RXF_INSN_BEQZ, model_m32rx_beqz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2676 { M32RXF_INSN_BGEZ, model_m32rx_bgez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2677 { M32RXF_INSN_BGTZ, model_m32rx_bgtz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2678 { M32RXF_INSN_BLEZ, model_m32rx_blez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2679 { M32RXF_INSN_BLTZ, model_m32rx_bltz, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2680 { M32RXF_INSN_BNEZ, model_m32rx_bnez, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2681 { M32RXF_INSN_BL8, model_m32rx_bl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2682 { M32RXF_INSN_BL24, model_m32rx_bl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2683 { M32RXF_INSN_BCL8, model_m32rx_bcl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2684 { M32RXF_INSN_BCL24, model_m32rx_bcl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2685 { M32RXF_INSN_BNC8, model_m32rx_bnc8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2686 { M32RXF_INSN_BNC24, model_m32rx_bnc24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2687 { M32RXF_INSN_BNE, model_m32rx_bne, { { (int) UNIT_M32RX_U_CTI, 1, 1 }, { (int) UNIT_M32RX_U_CMP, 1, 0 } } },
2688 { M32RXF_INSN_BRA8, model_m32rx_bra8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2689 { M32RXF_INSN_BRA24, model_m32rx_bra24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2690 { M32RXF_INSN_BNCL8, model_m32rx_bncl8, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2691 { M32RXF_INSN_BNCL24, model_m32rx_bncl24, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2692 { M32RXF_INSN_CMP, model_m32rx_cmp, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2693 { M32RXF_INSN_CMPI, model_m32rx_cmpi, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2694 { M32RXF_INSN_CMPU, model_m32rx_cmpu, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2695 { M32RXF_INSN_CMPUI, model_m32rx_cmpui, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2696 { M32RXF_INSN_CMPEQ, model_m32rx_cmpeq, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2697 { M32RXF_INSN_CMPZ, model_m32rx_cmpz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2698 { M32RXF_INSN_DIV, model_m32rx_div, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2699 { M32RXF_INSN_DIVU, model_m32rx_divu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2700 { M32RXF_INSN_REM, model_m32rx_rem, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2701 { M32RXF_INSN_REMU, model_m32rx_remu, { { (int) UNIT_M32RX_U_EXEC, 1, 37 } } },
2702 { M32RXF_INSN_DIVH, model_m32rx_divh, { { (int) UNIT_M32RX_U_EXEC, 1, 21 } } },
2703 { M32RXF_INSN_JC, model_m32rx_jc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2704 { M32RXF_INSN_JNC, model_m32rx_jnc, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2705 { M32RXF_INSN_JL, model_m32rx_jl, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2706 { M32RXF_INSN_JMP, model_m32rx_jmp, { { (int) UNIT_M32RX_U_CTI, 1, 1 } } },
2707 { M32RXF_INSN_LD, model_m32rx_ld, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2708 { M32RXF_INSN_LD_D, model_m32rx_ld_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2709 { M32RXF_INSN_LDB, model_m32rx_ldb, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2710 { M32RXF_INSN_LDB_D, model_m32rx_ldb_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2711 { M32RXF_INSN_LDH, model_m32rx_ldh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2712 { M32RXF_INSN_LDH_D, model_m32rx_ldh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2713 { M32RXF_INSN_LDUB, model_m32rx_ldub, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2714 { M32RXF_INSN_LDUB_D, model_m32rx_ldub_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2715 { M32RXF_INSN_LDUH, model_m32rx_lduh, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2716 { M32RXF_INSN_LDUH_D, model_m32rx_lduh_d, { { (int) UNIT_M32RX_U_LOAD, 1, 2 } } },
2717 { M32RXF_INSN_LD_PLUS, model_m32rx_ld_plus, { { (int) UNIT_M32RX_U_LOAD, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2718 { M32RXF_INSN_LD24, model_m32rx_ld24, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2719 { M32RXF_INSN_LDI8, model_m32rx_ldi8, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2720 { M32RXF_INSN_LDI16, model_m32rx_ldi16, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2721 { M32RXF_INSN_LOCK, model_m32rx_lock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2722 { M32RXF_INSN_MACHI_A, model_m32rx_machi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2723 { M32RXF_INSN_MACLO_A, model_m32rx_maclo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2724 { M32RXF_INSN_MACWHI_A, model_m32rx_macwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2725 { M32RXF_INSN_MACWLO_A, model_m32rx_macwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2726 { M32RXF_INSN_MUL, model_m32rx_mul, { { (int) UNIT_M32RX_U_EXEC, 1, 4 } } },
2727 { M32RXF_INSN_MULHI_A, model_m32rx_mulhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2728 { M32RXF_INSN_MULLO_A, model_m32rx_mullo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2729 { M32RXF_INSN_MULWHI_A, model_m32rx_mulwhi_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2730 { M32RXF_INSN_MULWLO_A, model_m32rx_mulwlo_a, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2731 { M32RXF_INSN_MV, model_m32rx_mv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2732 { M32RXF_INSN_MVFACHI_A, model_m32rx_mvfachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2733 { M32RXF_INSN_MVFACLO_A, model_m32rx_mvfaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2734 { M32RXF_INSN_MVFACMI_A, model_m32rx_mvfacmi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 2 } } },
2735 { M32RXF_INSN_MVFC, model_m32rx_mvfc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2736 { M32RXF_INSN_MVTACHI_A, model_m32rx_mvtachi_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2737 { M32RXF_INSN_MVTACLO_A, model_m32rx_mvtaclo_a, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2738 { M32RXF_INSN_MVTC, model_m32rx_mvtc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2739 { M32RXF_INSN_NEG, model_m32rx_neg, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2740 { M32RXF_INSN_NOP, model_m32rx_nop, { { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2741 { M32RXF_INSN_NOT, model_m32rx_not, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2742 { M32RXF_INSN_RAC_DSI, model_m32rx_rac_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2743 { M32RXF_INSN_RACH_DSI, model_m32rx_rach_dsi, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2744 { M32RXF_INSN_RTE, model_m32rx_rte, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2745 { M32RXF_INSN_SETH, model_m32rx_seth, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2746 { M32RXF_INSN_SLL, model_m32rx_sll, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2747 { M32RXF_INSN_SLL3, model_m32rx_sll3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2748 { M32RXF_INSN_SLLI, model_m32rx_slli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2749 { M32RXF_INSN_SRA, model_m32rx_sra, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2750 { M32RXF_INSN_SRA3, model_m32rx_sra3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2751 { M32RXF_INSN_SRAI, model_m32rx_srai, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2752 { M32RXF_INSN_SRL, model_m32rx_srl, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2753 { M32RXF_INSN_SRL3, model_m32rx_srl3, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2754 { M32RXF_INSN_SRLI, model_m32rx_srli, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2755 { M32RXF_INSN_ST, model_m32rx_st, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2756 { M32RXF_INSN_ST_D, model_m32rx_st_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2757 { M32RXF_INSN_STB, model_m32rx_stb, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2758 { M32RXF_INSN_STB_D, model_m32rx_stb_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2759 { M32RXF_INSN_STH, model_m32rx_sth, { { (int) UNIT_M32RX_U_STORE, 1, 1 } } },
2760 { M32RXF_INSN_STH_D, model_m32rx_sth_d, { { (int) UNIT_M32RX_U_STORE, 1, 2 } } },
2761 { M32RXF_INSN_ST_PLUS, model_m32rx_st_plus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2762 { M32RXF_INSN_ST_MINUS, model_m32rx_st_minus, { { (int) UNIT_M32RX_U_STORE, 1, 1 }, { (int) UNIT_M32RX_U_EXEC, 1, 0 } } },
2763 { M32RXF_INSN_SUB, model_m32rx_sub, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2764 { M32RXF_INSN_SUBV, model_m32rx_subv, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2765 { M32RXF_INSN_SUBX, model_m32rx_subx, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2766 { M32RXF_INSN_TRAP, model_m32rx_trap, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2767 { M32RXF_INSN_UNLOCK, model_m32rx_unlock, { { (int) UNIT_M32RX_U_LOAD, 1, 1 } } },
2768 { M32RXF_INSN_SATB, model_m32rx_satb, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2769 { M32RXF_INSN_SATH, model_m32rx_sath, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2770 { M32RXF_INSN_SAT, model_m32rx_sat, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2771 { M32RXF_INSN_PCMPBZ, model_m32rx_pcmpbz, { { (int) UNIT_M32RX_U_CMP, 1, 1 } } },
2772 { M32RXF_INSN_SADD, model_m32rx_sadd, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2773 { M32RXF_INSN_MACWU1, model_m32rx_macwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2774 { M32RXF_INSN_MSBLO, model_m32rx_msblo, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2775 { M32RXF_INSN_MULWU1, model_m32rx_mulwu1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2776 { M32RXF_INSN_MACLH1, model_m32rx_maclh1, { { (int) UNIT_M32RX_U_MAC, 1, 1 } } },
2777 { M32RXF_INSN_SC, model_m32rx_sc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2778 { M32RXF_INSN_SNC, model_m32rx_snc, { { (int) UNIT_M32RX_U_EXEC, 1, 1 } } },
2779 };
2780
2781 #endif /* WITH_PROFILE_MODEL_P */
2782
2783 static void
2784 m32rx_model_init (SIM_CPU *cpu)
2785 {
2786 CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_M32RX_DATA));
2787 }
2788
2789 #if WITH_PROFILE_MODEL_P
2790 #define TIMING_DATA(td) td
2791 #else
2792 #define TIMING_DATA(td) 0
2793 #endif
2794
2795 static const MODEL m32rx_models[] =
2796 {
2797 { "m32rx", & m32rx_mach, MODEL_M32RX, TIMING_DATA (& m32rx_timing[0]), m32rx_model_init },
2798 { 0 }
2799 };
2800
2801 /* The properties of this cpu's implementation. */
2802
2803 static const MACH_IMP_PROPERTIES m32rxf_imp_properties =
2804 {
2805 sizeof (SIM_CPU),
2806 #if WITH_SCACHE
2807 sizeof (SCACHE)
2808 #else
2809 0
2810 #endif
2811 };
2812
2813 static const CGEN_INSN *
2814 m32rxf_opcode (SIM_CPU *cpu, int inum)
2815 {
2816 return CPU_IDESC (cpu) [inum].opcode;
2817 }
2818
2819 /* start-sanitize-m32rx */
2820 static void
2821 m32rx_init_cpu (SIM_CPU *cpu)
2822 {
2823 CPU_REG_FETCH (cpu) = m32rxf_fetch_register;
2824 CPU_REG_STORE (cpu) = m32rxf_store_register;
2825 CPU_PC_FETCH (cpu) = m32rxf_h_pc_get;
2826 CPU_PC_STORE (cpu) = m32rxf_h_pc_set;
2827 CPU_OPCODE (cpu) = m32rxf_opcode;
2828 CPU_MAX_INSNS (cpu) = M32RXF_INSN_MAX;
2829 CPU_INSN_NAME (cpu) = cgen_insn_name;
2830 CPU_FULL_ENGINE_FN (cpu) = m32rxf_engine_run_full;
2831 #if WITH_FAST
2832 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_fast;
2833 #else
2834 CPU_FAST_ENGINE_FN (cpu) = m32rxf_engine_run_full;
2835 #endif
2836 m32rxf_init_idesc_table (cpu);
2837 }
2838
2839 const MACH m32rx_mach =
2840 {
2841 "m32rx", "m32rx",
2842 32, 32, & m32rx_models[0], & m32rxf_imp_properties,
2843 m32rx_init_cpu
2844 };
2845
2846 /* end-sanitize-m32rx */
GDB Binutils - Deliverables
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