sim/m32r/semx.c

   1 /* Simulator instruction semantics for m32rx.
   2
   3 This file is machine generated with CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #define WANT_CPU
  26 #define WANT_CPU_M32RX
  27
  28 #include "sim-main.h"
  29 #include "cgen-mem.h"
  30 #include "cgen-ops.h"
  31 #include "cpu-sim.h"
  32
  33 #if ! defined (SCACHE_P) || (defined (SCACHE_P) && WITH_SCACHE)
  34
  35 #undef GET_ATTR
  36 #define GET_ATTR(cpu, num, attr) CGEN_INSN_ATTR (abuf->opcode, CGEN_INSN_##attr)
  37
  38 /* Perform add: add $dr,$sr.  */
  39 CIA
  40 SEM_FN_NAME (m32rx,add) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
  41 {
  42   insn_t insn = SEM_INSN (sem_arg);
  43 #define OPRND(f) par_exec->operands.fmt_0_add.f
  44   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
  45   CIA new_pc = CPU (h_pc) + 2;
  46   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
  47   EXTRACT_FMT_0_ADD_CODE
  48
  49   CPU (h_gr[f_r1]) = ADDSI (OPRND (dr), OPRND (sr));
  50   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
  51
  52 #if WITH_PROFILE_MODEL_P
  53   if (PROFILE_MODEL_P (current_cpu))
  54     {
  55       m32rx_model_mark_get_h_gr (current_cpu, abuf);
  56       m32rx_model_mark_set_h_gr (current_cpu, abuf);
  57       m32rx_model_profile_insn (current_cpu, abuf);
  58     }
  59 #endif
  60
  61   return new_pc;
  62 #undef OPRND
  63 }
  64
  65 /* Perform add3: add3 $dr,$sr,#$slo16.  */
  66 CIA
  67 SEM_FN_NAME (m32rx,add3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
  68 {
  69   insn_t insn = SEM_INSN (sem_arg);
  70 #define OPRND(f) par_exec->operands.fmt_1_add3.f
  71   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
  72   CIA new_pc = CPU (h_pc) + 4;
  73   EXTRACT_FMT_1_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
  74   EXTRACT_FMT_1_ADD3_CODE
  75
  76   CPU (h_gr[f_r1]) = ADDSI (OPRND (sr), OPRND (slo16));
  77   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
  78
  79 #if WITH_PROFILE_MODEL_P
  80   if (PROFILE_MODEL_P (current_cpu))
  81     {
  82       m32rx_model_mark_get_h_gr (current_cpu, abuf);
  83       m32rx_model_mark_set_h_gr (current_cpu, abuf);
  84       m32rx_model_profile_insn (current_cpu, abuf);
  85     }
  86 #endif
  87
  88   return new_pc;
  89 #undef OPRND
  90 }
  91
  92 /* Perform and: and $dr,$sr.  */
  93 CIA
  94 SEM_FN_NAME (m32rx,and) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
  95 {
  96   insn_t insn = SEM_INSN (sem_arg);
  97 #define OPRND(f) par_exec->operands.fmt_0_add.f
  98   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
  99   CIA new_pc = CPU (h_pc) + 2;
 100   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 101   EXTRACT_FMT_0_ADD_CODE
 102
 103   CPU (h_gr[f_r1]) = ANDSI (OPRND (dr), OPRND (sr));
 104   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 105
 106 #if WITH_PROFILE_MODEL_P
 107   if (PROFILE_MODEL_P (current_cpu))
 108     {
 109       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 110       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 111       m32rx_model_profile_insn (current_cpu, abuf);
 112     }
 113 #endif
 114
 115   return new_pc;
 116 #undef OPRND
 117 }
 118
 119 /* Perform and3: and3 $dr,$sr,#$uimm16.  */
 120 CIA
 121 SEM_FN_NAME (m32rx,and3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 122 {
 123   insn_t insn = SEM_INSN (sem_arg);
 124 #define OPRND(f) par_exec->operands.fmt_2_and3.f
 125   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 126   CIA new_pc = CPU (h_pc) + 4;
 127   EXTRACT_FMT_2_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 128   EXTRACT_FMT_2_AND3_CODE
 129
 130   CPU (h_gr[f_r1]) = ANDSI (OPRND (sr), OPRND (uimm16));
 131   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 132
 133 #if WITH_PROFILE_MODEL_P
 134   if (PROFILE_MODEL_P (current_cpu))
 135     {
 136       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 137       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 138       m32rx_model_profile_insn (current_cpu, abuf);
 139     }
 140 #endif
 141
 142   return new_pc;
 143 #undef OPRND
 144 }
 145
 146 /* Perform or: or $dr,$sr.  */
 147 CIA
 148 SEM_FN_NAME (m32rx,or) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 149 {
 150   insn_t insn = SEM_INSN (sem_arg);
 151 #define OPRND(f) par_exec->operands.fmt_0_add.f
 152   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 153   CIA new_pc = CPU (h_pc) + 2;
 154   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 155   EXTRACT_FMT_0_ADD_CODE
 156
 157   CPU (h_gr[f_r1]) = ORSI (OPRND (dr), OPRND (sr));
 158   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 159
 160 #if WITH_PROFILE_MODEL_P
 161   if (PROFILE_MODEL_P (current_cpu))
 162     {
 163       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 164       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 165       m32rx_model_profile_insn (current_cpu, abuf);
 166     }
 167 #endif
 168
 169   return new_pc;
 170 #undef OPRND
 171 }
 172
 173 /* Perform or3: or3 $dr,$sr,#$ulo16.  */
 174 CIA
 175 SEM_FN_NAME (m32rx,or3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 176 {
 177   insn_t insn = SEM_INSN (sem_arg);
 178 #define OPRND(f) par_exec->operands.fmt_3_or3.f
 179   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 180   CIA new_pc = CPU (h_pc) + 4;
 181   EXTRACT_FMT_3_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 182   EXTRACT_FMT_3_OR3_CODE
 183
 184   CPU (h_gr[f_r1]) = ORSI (OPRND (sr), OPRND (ulo16));
 185   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 186
 187 #if WITH_PROFILE_MODEL_P
 188   if (PROFILE_MODEL_P (current_cpu))
 189     {
 190       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 191       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 192       m32rx_model_profile_insn (current_cpu, abuf);
 193     }
 194 #endif
 195
 196   return new_pc;
 197 #undef OPRND
 198 }
 199
 200 /* Perform xor: xor $dr,$sr.  */
 201 CIA
 202 SEM_FN_NAME (m32rx,xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 203 {
 204   insn_t insn = SEM_INSN (sem_arg);
 205 #define OPRND(f) par_exec->operands.fmt_0_add.f
 206   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 207   CIA new_pc = CPU (h_pc) + 2;
 208   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
 209   EXTRACT_FMT_0_ADD_CODE
 210
 211   CPU (h_gr[f_r1]) = XORSI (OPRND (dr), OPRND (sr));
 212   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 213
 214 #if WITH_PROFILE_MODEL_P
 215   if (PROFILE_MODEL_P (current_cpu))
 216     {
 217       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 218       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 219       m32rx_model_profile_insn (current_cpu, abuf);
 220     }
 221 #endif
 222
 223   return new_pc;
 224 #undef OPRND
 225 }
 226
 227 /* Perform xor3: xor3 $dr,$sr,#$uimm16.  */
 228 CIA
 229 SEM_FN_NAME (m32rx,xor3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 230 {
 231   insn_t insn = SEM_INSN (sem_arg);
 232 #define OPRND(f) par_exec->operands.fmt_2_and3.f
 233   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 234   CIA new_pc = CPU (h_pc) + 4;
 235   EXTRACT_FMT_2_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
 236   EXTRACT_FMT_2_AND3_CODE
 237
 238   CPU (h_gr[f_r1]) = XORSI (OPRND (sr), OPRND (uimm16));
 239   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 240
 241 #if WITH_PROFILE_MODEL_P
 242   if (PROFILE_MODEL_P (current_cpu))
 243     {
 244       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 245       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 246       m32rx_model_profile_insn (current_cpu, abuf);
 247     }
 248 #endif
 249
 250   return new_pc;
 251 #undef OPRND
 252 }
 253
 254 /* Perform addi: addi $dr,#$simm8.  */
 255 CIA
 256 SEM_FN_NAME (m32rx,addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 257 {
 258   insn_t insn = SEM_INSN (sem_arg);
 259 #define OPRND(f) par_exec->operands.fmt_4_addi.f
 260   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 261   CIA new_pc = CPU (h_pc) + 2;
 262   EXTRACT_FMT_4_ADDI_VARS /* f-op1 f-r1 f-simm8 */
 263   EXTRACT_FMT_4_ADDI_CODE
 264
 265   CPU (h_gr[f_r1]) = ADDSI (OPRND (dr), OPRND (simm8));
 266   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 267
 268 #if WITH_PROFILE_MODEL_P
 269   if (PROFILE_MODEL_P (current_cpu))
 270     {
 271       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 272       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 273       m32rx_model_profile_insn (current_cpu, abuf);
 274     }
 275 #endif
 276
 277   return new_pc;
 278 #undef OPRND
 279 }
 280
 281 /* Perform addv: addv $dr,$sr.  */
 282 CIA
 283 SEM_FN_NAME (m32rx,addv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 284 {
 285   insn_t insn = SEM_INSN (sem_arg);
 286 #define OPRND(f) par_exec->operands.fmt_5_addv.f
 287   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 288   CIA new_pc = CPU (h_pc) + 2;
 289   EXTRACT_FMT_5_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
 290   EXTRACT_FMT_5_ADDV_CODE
 291
 292 do {
 293   BI temp1;SI temp0;
 294   temp0 = ADDSI (OPRND (dr), OPRND (sr));
 295   temp1 = ADDOFSI (OPRND (dr), OPRND (sr), 0);
 296   CPU (h_gr[f_r1]) = temp0;
 297   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 298   CPU (h_cond) = temp1;
 299   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 300 } while (0);
 301
 302 #if WITH_PROFILE_MODEL_P
 303   if (PROFILE_MODEL_P (current_cpu))
 304     {
 305       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 306       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 307       m32rx_model_profile_insn (current_cpu, abuf);
 308     }
 309 #endif
 310
 311   return new_pc;
 312 #undef OPRND
 313 }
 314
 315 /* Perform addv3: addv3 $dr,$sr,#$simm16.  */
 316 CIA
 317 SEM_FN_NAME (m32rx,addv3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 318 {
 319   insn_t insn = SEM_INSN (sem_arg);
 320 #define OPRND(f) par_exec->operands.fmt_6_addv3.f
 321   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 322   CIA new_pc = CPU (h_pc) + 4;
 323   EXTRACT_FMT_6_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
 324   EXTRACT_FMT_6_ADDV3_CODE
 325
 326 do {
 327   BI temp1;SI temp0;
 328   temp0 = ADDSI (OPRND (sr), OPRND (simm16));
 329   temp1 = ADDOFSI (OPRND (sr), OPRND (simm16), 0);
 330   CPU (h_gr[f_r1]) = temp0;
 331   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 332   CPU (h_cond) = temp1;
 333   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 334 } while (0);
 335
 336 #if WITH_PROFILE_MODEL_P
 337   if (PROFILE_MODEL_P (current_cpu))
 338     {
 339       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 340       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 341       m32rx_model_profile_insn (current_cpu, abuf);
 342     }
 343 #endif
 344
 345   return new_pc;
 346 #undef OPRND
 347 }
 348
 349 /* Perform addx: addx $dr,$sr.  */
 350 CIA
 351 SEM_FN_NAME (m32rx,addx) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 352 {
 353   insn_t insn = SEM_INSN (sem_arg);
 354 #define OPRND(f) par_exec->operands.fmt_7_addx.f
 355   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 356   CIA new_pc = CPU (h_pc) + 2;
 357   EXTRACT_FMT_7_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
 358   EXTRACT_FMT_7_ADDX_CODE
 359
 360 do {
 361   BI temp1;SI temp0;
 362   temp0 = ADDCSI (OPRND (dr), OPRND (sr), OPRND (condbit));
 363   temp1 = ADDCFSI (OPRND (dr), OPRND (sr), OPRND (condbit));
 364   CPU (h_gr[f_r1]) = temp0;
 365   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
 366   CPU (h_cond) = temp1;
 367   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 368 } while (0);
 369
 370 #if WITH_PROFILE_MODEL_P
 371   if (PROFILE_MODEL_P (current_cpu))
 372     {
 373       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 374       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 375       m32rx_model_profile_insn (current_cpu, abuf);
 376     }
 377 #endif
 378
 379   return new_pc;
 380 #undef OPRND
 381 }
 382
 383 /* Perform bc8: bc $disp8.  */
 384 CIA
 385 SEM_FN_NAME (m32rx,bc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 386 {
 387   insn_t insn = SEM_INSN (sem_arg);
 388 #define OPRND(f) par_exec->operands.fmt_8_bc8.f
 389   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 390   CIA new_pc = CPU (h_pc) + 2;
 391   int taken_p = 0;
 392   EXTRACT_FMT_8_BC8_VARS /* f-op1 f-r1 f-disp8 */
 393   EXTRACT_FMT_8_BC8_CODE
 394
 395 if (OPRND (condbit)) {
 396   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 397   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 398 }
 399
 400 #if WITH_PROFILE_MODEL_P
 401   if (PROFILE_MODEL_P (current_cpu))
 402     {
 403       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 404     }
 405 #endif
 406
 407   return new_pc;
 408 #undef OPRND
 409 }
 410
 411 /* Perform bc24: bc $disp24.  */
 412 CIA
 413 SEM_FN_NAME (m32rx,bc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 414 {
 415   insn_t insn = SEM_INSN (sem_arg);
 416 #define OPRND(f) par_exec->operands.fmt_9_bc24.f
 417   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 418   CIA new_pc = CPU (h_pc) + 4;
 419   int taken_p = 0;
 420   EXTRACT_FMT_9_BC24_VARS /* f-op1 f-r1 f-disp24 */
 421   EXTRACT_FMT_9_BC24_CODE
 422
 423 if (OPRND (condbit)) {
 424   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 425   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 426 }
 427
 428 #if WITH_PROFILE_MODEL_P
 429   if (PROFILE_MODEL_P (current_cpu))
 430     {
 431       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 432     }
 433 #endif
 434
 435   return new_pc;
 436 #undef OPRND
 437 }
 438
 439 /* Perform beq: beq $src1,$src2,$disp16.  */
 440 CIA
 441 SEM_FN_NAME (m32rx,beq) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 442 {
 443   insn_t insn = SEM_INSN (sem_arg);
 444 #define OPRND(f) par_exec->operands.fmt_10_beq.f
 445   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 446   CIA new_pc = CPU (h_pc) + 4;
 447   int taken_p = 0;
 448   EXTRACT_FMT_10_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 449   EXTRACT_FMT_10_BEQ_CODE
 450
 451 if (EQSI (OPRND (src1), OPRND (src2))) {
 452   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 453   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 454 }
 455
 456 #if WITH_PROFILE_MODEL_P
 457   if (PROFILE_MODEL_P (current_cpu))
 458     {
 459       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 460       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 461     }
 462 #endif
 463
 464   return new_pc;
 465 #undef OPRND
 466 }
 467
 468 /* Perform beqz: beqz $src2,$disp16.  */
 469 CIA
 470 SEM_FN_NAME (m32rx,beqz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 471 {
 472   insn_t insn = SEM_INSN (sem_arg);
 473 #define OPRND(f) par_exec->operands.fmt_11_beqz.f
 474   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 475   CIA new_pc = CPU (h_pc) + 4;
 476   int taken_p = 0;
 477   EXTRACT_FMT_11_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 478   EXTRACT_FMT_11_BEQZ_CODE
 479
 480 if (EQSI (OPRND (src2), 0)) {
 481   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 482   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 483 }
 484
 485 #if WITH_PROFILE_MODEL_P
 486   if (PROFILE_MODEL_P (current_cpu))
 487     {
 488       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 489       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 490     }
 491 #endif
 492
 493   return new_pc;
 494 #undef OPRND
 495 }
 496
 497 /* Perform bgez: bgez $src2,$disp16.  */
 498 CIA
 499 SEM_FN_NAME (m32rx,bgez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 500 {
 501   insn_t insn = SEM_INSN (sem_arg);
 502 #define OPRND(f) par_exec->operands.fmt_11_beqz.f
 503   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 504   CIA new_pc = CPU (h_pc) + 4;
 505   int taken_p = 0;
 506   EXTRACT_FMT_11_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 507   EXTRACT_FMT_11_BEQZ_CODE
 508
 509 if (GESI (OPRND (src2), 0)) {
 510   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 511   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 512 }
 513
 514 #if WITH_PROFILE_MODEL_P
 515   if (PROFILE_MODEL_P (current_cpu))
 516     {
 517       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 518       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 519     }
 520 #endif
 521
 522   return new_pc;
 523 #undef OPRND
 524 }
 525
 526 /* Perform bgtz: bgtz $src2,$disp16.  */
 527 CIA
 528 SEM_FN_NAME (m32rx,bgtz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 529 {
 530   insn_t insn = SEM_INSN (sem_arg);
 531 #define OPRND(f) par_exec->operands.fmt_11_beqz.f
 532   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 533   CIA new_pc = CPU (h_pc) + 4;
 534   int taken_p = 0;
 535   EXTRACT_FMT_11_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 536   EXTRACT_FMT_11_BEQZ_CODE
 537
 538 if (GTSI (OPRND (src2), 0)) {
 539   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 540   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 541 }
 542
 543 #if WITH_PROFILE_MODEL_P
 544   if (PROFILE_MODEL_P (current_cpu))
 545     {
 546       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 547       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 548     }
 549 #endif
 550
 551   return new_pc;
 552 #undef OPRND
 553 }
 554
 555 /* Perform blez: blez $src2,$disp16.  */
 556 CIA
 557 SEM_FN_NAME (m32rx,blez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 558 {
 559   insn_t insn = SEM_INSN (sem_arg);
 560 #define OPRND(f) par_exec->operands.fmt_11_beqz.f
 561   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 562   CIA new_pc = CPU (h_pc) + 4;
 563   int taken_p = 0;
 564   EXTRACT_FMT_11_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 565   EXTRACT_FMT_11_BEQZ_CODE
 566
 567 if (LESI (OPRND (src2), 0)) {
 568   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 569   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 570 }
 571
 572 #if WITH_PROFILE_MODEL_P
 573   if (PROFILE_MODEL_P (current_cpu))
 574     {
 575       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 576       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 577     }
 578 #endif
 579
 580   return new_pc;
 581 #undef OPRND
 582 }
 583
 584 /* Perform bltz: bltz $src2,$disp16.  */
 585 CIA
 586 SEM_FN_NAME (m32rx,bltz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 587 {
 588   insn_t insn = SEM_INSN (sem_arg);
 589 #define OPRND(f) par_exec->operands.fmt_11_beqz.f
 590   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 591   CIA new_pc = CPU (h_pc) + 4;
 592   int taken_p = 0;
 593   EXTRACT_FMT_11_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 594   EXTRACT_FMT_11_BEQZ_CODE
 595
 596 if (LTSI (OPRND (src2), 0)) {
 597   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 598   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 599 }
 600
 601 #if WITH_PROFILE_MODEL_P
 602   if (PROFILE_MODEL_P (current_cpu))
 603     {
 604       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 605       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 606     }
 607 #endif
 608
 609   return new_pc;
 610 #undef OPRND
 611 }
 612
 613 /* Perform bnez: bnez $src2,$disp16.  */
 614 CIA
 615 SEM_FN_NAME (m32rx,bnez) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 616 {
 617   insn_t insn = SEM_INSN (sem_arg);
 618 #define OPRND(f) par_exec->operands.fmt_11_beqz.f
 619   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 620   CIA new_pc = CPU (h_pc) + 4;
 621   int taken_p = 0;
 622   EXTRACT_FMT_11_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 623   EXTRACT_FMT_11_BEQZ_CODE
 624
 625 if (NESI (OPRND (src2), 0)) {
 626   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 627   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 628 }
 629
 630 #if WITH_PROFILE_MODEL_P
 631   if (PROFILE_MODEL_P (current_cpu))
 632     {
 633       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 634       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 635     }
 636 #endif
 637
 638   return new_pc;
 639 #undef OPRND
 640 }
 641
 642 /* Perform bl8: bl $disp8.  */
 643 CIA
 644 SEM_FN_NAME (m32rx,bl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 645 {
 646   insn_t insn = SEM_INSN (sem_arg);
 647 #define OPRND(f) par_exec->operands.fmt_12_bl8.f
 648   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 649   CIA new_pc = CPU (h_pc) + 2;
 650   int taken_p = 0;
 651   EXTRACT_FMT_12_BL8_VARS /* f-op1 f-r1 f-disp8 */
 652   EXTRACT_FMT_12_BL8_CODE
 653
 654 do {
 655   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
 656   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
 657   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 658   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 659 } while (0);
 660
 661 #if WITH_PROFILE_MODEL_P
 662   if (PROFILE_MODEL_P (current_cpu))
 663     {
 664       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 665       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 666     }
 667 #endif
 668
 669   return new_pc;
 670 #undef OPRND
 671 }
 672
 673 /* Perform bl24: bl $disp24.  */
 674 CIA
 675 SEM_FN_NAME (m32rx,bl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 676 {
 677   insn_t insn = SEM_INSN (sem_arg);
 678 #define OPRND(f) par_exec->operands.fmt_13_bl24.f
 679   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 680   CIA new_pc = CPU (h_pc) + 4;
 681   int taken_p = 0;
 682   EXTRACT_FMT_13_BL24_VARS /* f-op1 f-r1 f-disp24 */
 683   EXTRACT_FMT_13_BL24_CODE
 684
 685 do {
 686   CPU (h_gr[14]) = ADDSI (OPRND (pc), 4);
 687   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
 688   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 689   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 690 } while (0);
 691
 692 #if WITH_PROFILE_MODEL_P
 693   if (PROFILE_MODEL_P (current_cpu))
 694     {
 695       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 696       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 697     }
 698 #endif
 699
 700   return new_pc;
 701 #undef OPRND
 702 }
 703
 704 /* Perform bcl8: bcl $disp8.  */
 705 CIA
 706 SEM_FN_NAME (m32rx,bcl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 707 {
 708   insn_t insn = SEM_INSN (sem_arg);
 709 #define OPRND(f) par_exec->operands.fmt_14_bcl8.f
 710   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 711   CIA new_pc = CPU (h_pc) + 2;
 712   int taken_p = 0;
 713   EXTRACT_FMT_14_BCL8_VARS /* f-op1 f-r1 f-disp8 */
 714   EXTRACT_FMT_14_BCL8_CODE
 715
 716 if (OPRND (condbit)) {
 717 do {
 718   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
 719   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
 720   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 721   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 722 } while (0);
 723 }
 724
 725 #if WITH_PROFILE_MODEL_P
 726   if (PROFILE_MODEL_P (current_cpu))
 727     {
 728       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 729       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 730     }
 731 #endif
 732
 733   return new_pc;
 734 #undef OPRND
 735 }
 736
 737 /* Perform bcl24: bcl $disp24.  */
 738 CIA
 739 SEM_FN_NAME (m32rx,bcl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 740 {
 741   insn_t insn = SEM_INSN (sem_arg);
 742 #define OPRND(f) par_exec->operands.fmt_15_bcl24.f
 743   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 744   CIA new_pc = CPU (h_pc) + 4;
 745   int taken_p = 0;
 746   EXTRACT_FMT_15_BCL24_VARS /* f-op1 f-r1 f-disp24 */
 747   EXTRACT_FMT_15_BCL24_CODE
 748
 749 if (OPRND (condbit)) {
 750 do {
 751   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
 752   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
 753   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 754   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 755 } while (0);
 756 }
 757
 758 #if WITH_PROFILE_MODEL_P
 759   if (PROFILE_MODEL_P (current_cpu))
 760     {
 761       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 762       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 763     }
 764 #endif
 765
 766   return new_pc;
 767 #undef OPRND
 768 }
 769
 770 /* Perform bnc8: bnc $disp8.  */
 771 CIA
 772 SEM_FN_NAME (m32rx,bnc8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 773 {
 774   insn_t insn = SEM_INSN (sem_arg);
 775 #define OPRND(f) par_exec->operands.fmt_8_bc8.f
 776   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 777   CIA new_pc = CPU (h_pc) + 2;
 778   int taken_p = 0;
 779   EXTRACT_FMT_8_BC8_VARS /* f-op1 f-r1 f-disp8 */
 780   EXTRACT_FMT_8_BC8_CODE
 781
 782 if (NOTBI (OPRND (condbit))) {
 783   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 784   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 785 }
 786
 787 #if WITH_PROFILE_MODEL_P
 788   if (PROFILE_MODEL_P (current_cpu))
 789     {
 790       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 791     }
 792 #endif
 793
 794   return new_pc;
 795 #undef OPRND
 796 }
 797
 798 /* Perform bnc24: bnc $disp24.  */
 799 CIA
 800 SEM_FN_NAME (m32rx,bnc24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 801 {
 802   insn_t insn = SEM_INSN (sem_arg);
 803 #define OPRND(f) par_exec->operands.fmt_9_bc24.f
 804   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 805   CIA new_pc = CPU (h_pc) + 4;
 806   int taken_p = 0;
 807   EXTRACT_FMT_9_BC24_VARS /* f-op1 f-r1 f-disp24 */
 808   EXTRACT_FMT_9_BC24_CODE
 809
 810 if (NOTBI (OPRND (condbit))) {
 811   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 812   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 813 }
 814
 815 #if WITH_PROFILE_MODEL_P
 816   if (PROFILE_MODEL_P (current_cpu))
 817     {
 818       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 819     }
 820 #endif
 821
 822   return new_pc;
 823 #undef OPRND
 824 }
 825
 826 /* Perform bne: bne $src1,$src2,$disp16.  */
 827 CIA
 828 SEM_FN_NAME (m32rx,bne) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 829 {
 830   insn_t insn = SEM_INSN (sem_arg);
 831 #define OPRND(f) par_exec->operands.fmt_10_beq.f
 832   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 833   CIA new_pc = CPU (h_pc) + 4;
 834   int taken_p = 0;
 835   EXTRACT_FMT_10_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
 836   EXTRACT_FMT_10_BEQ_CODE
 837
 838 if (NESI (OPRND (src1), OPRND (src2))) {
 839   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp16)));
 840   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 841 }
 842
 843 #if WITH_PROFILE_MODEL_P
 844   if (PROFILE_MODEL_P (current_cpu))
 845     {
 846       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 847       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 848     }
 849 #endif
 850
 851   return new_pc;
 852 #undef OPRND
 853 }
 854
 855 /* Perform bra8: bra $disp8.  */
 856 CIA
 857 SEM_FN_NAME (m32rx,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 858 {
 859   insn_t insn = SEM_INSN (sem_arg);
 860 #define OPRND(f) par_exec->operands.fmt_16_bra8.f
 861   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 862   CIA new_pc = CPU (h_pc) + 2;
 863   int taken_p = 0;
 864   EXTRACT_FMT_16_BRA8_VARS /* f-op1 f-r1 f-disp8 */
 865   EXTRACT_FMT_16_BRA8_CODE
 866
 867   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 868   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 869
 870 #if WITH_PROFILE_MODEL_P
 871   if (PROFILE_MODEL_P (current_cpu))
 872     {
 873       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 874     }
 875 #endif
 876
 877   return new_pc;
 878 #undef OPRND
 879 }
 880
 881 /* Perform bra24: bra $disp24.  */
 882 CIA
 883 SEM_FN_NAME (m32rx,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 884 {
 885   insn_t insn = SEM_INSN (sem_arg);
 886 #define OPRND(f) par_exec->operands.fmt_17_bra24.f
 887   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 888   CIA new_pc = CPU (h_pc) + 4;
 889   int taken_p = 0;
 890   EXTRACT_FMT_17_BRA24_VARS /* f-op1 f-r1 f-disp24 */
 891   EXTRACT_FMT_17_BRA24_CODE
 892
 893   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 894   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 895
 896 #if WITH_PROFILE_MODEL_P
 897   if (PROFILE_MODEL_P (current_cpu))
 898     {
 899       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 900     }
 901 #endif
 902
 903   return new_pc;
 904 #undef OPRND
 905 }
 906
 907 /* Perform bncl8: bncl $disp8.  */
 908 CIA
 909 SEM_FN_NAME (m32rx,bncl8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 910 {
 911   insn_t insn = SEM_INSN (sem_arg);
 912 #define OPRND(f) par_exec->operands.fmt_14_bcl8.f
 913   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 914   CIA new_pc = CPU (h_pc) + 2;
 915   int taken_p = 0;
 916   EXTRACT_FMT_14_BCL8_VARS /* f-op1 f-r1 f-disp8 */
 917   EXTRACT_FMT_14_BCL8_CODE
 918
 919 if (NOTBI (OPRND (condbit))) {
 920 do {
 921   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
 922   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
 923   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp8)));
 924   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 925 } while (0);
 926 }
 927
 928 #if WITH_PROFILE_MODEL_P
 929   if (PROFILE_MODEL_P (current_cpu))
 930     {
 931       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 932       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 933     }
 934 #endif
 935
 936   return new_pc;
 937 #undef OPRND
 938 }
 939
 940 /* Perform bncl24: bncl $disp24.  */
 941 CIA
 942 SEM_FN_NAME (m32rx,bncl24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 943 {
 944   insn_t insn = SEM_INSN (sem_arg);
 945 #define OPRND(f) par_exec->operands.fmt_15_bcl24.f
 946   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 947   CIA new_pc = CPU (h_pc) + 4;
 948   int taken_p = 0;
 949   EXTRACT_FMT_15_BCL24_VARS /* f-op1 f-r1 f-disp24 */
 950   EXTRACT_FMT_15_BCL24_CODE
 951
 952 if (NOTBI (OPRND (condbit))) {
 953 do {
 954   CPU (h_gr[14]) = ADDSI (ANDSI (OPRND (pc), -4), 4);
 955   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
 956   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_CACHE (sem_arg, OPRND (disp24)));
 957   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
 958 } while (0);
 959 }
 960
 961 #if WITH_PROFILE_MODEL_P
 962   if (PROFILE_MODEL_P (current_cpu))
 963     {
 964       m32rx_model_mark_set_h_gr (current_cpu, abuf);
 965       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
 966     }
 967 #endif
 968
 969   return new_pc;
 970 #undef OPRND
 971 }
 972
 973 /* Perform cmp: cmp $src1,$src2.  */
 974 CIA
 975 SEM_FN_NAME (m32rx,cmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
 976 {
 977   insn_t insn = SEM_INSN (sem_arg);
 978 #define OPRND(f) par_exec->operands.fmt_18_cmp.f
 979   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
 980   CIA new_pc = CPU (h_pc) + 2;
 981   EXTRACT_FMT_18_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
 982   EXTRACT_FMT_18_CMP_CODE
 983
 984   CPU (h_cond) = LTSI (OPRND (src1), OPRND (src2));
 985   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
 986
 987 #if WITH_PROFILE_MODEL_P
 988   if (PROFILE_MODEL_P (current_cpu))
 989     {
 990       m32rx_model_mark_get_h_gr (current_cpu, abuf);
 991       m32rx_model_profile_insn (current_cpu, abuf);
 992     }
 993 #endif
 994
 995   return new_pc;
 996 #undef OPRND
 997 }
 998
 999 /* Perform cmpi: cmpi $src2,#$simm16.  */
1000 CIA
1001 SEM_FN_NAME (m32rx,cmpi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1002 {
1003   insn_t insn = SEM_INSN (sem_arg);
1004 #define OPRND(f) par_exec->operands.fmt_19_cmpi.f
1005   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1006   CIA new_pc = CPU (h_pc) + 4;
1007   EXTRACT_FMT_19_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1008   EXTRACT_FMT_19_CMPI_CODE
1009
1010   CPU (h_cond) = LTSI (OPRND (src2), OPRND (simm16));
1011   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1012
1013 #if WITH_PROFILE_MODEL_P
1014   if (PROFILE_MODEL_P (current_cpu))
1015     {
1016       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1017       m32rx_model_profile_insn (current_cpu, abuf);
1018     }
1019 #endif
1020
1021   return new_pc;
1022 #undef OPRND
1023 }
1024
1025 /* Perform cmpu: cmpu $src1,$src2.  */
1026 CIA
1027 SEM_FN_NAME (m32rx,cmpu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1028 {
1029   insn_t insn = SEM_INSN (sem_arg);
1030 #define OPRND(f) par_exec->operands.fmt_18_cmp.f
1031   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1032   CIA new_pc = CPU (h_pc) + 2;
1033   EXTRACT_FMT_18_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1034   EXTRACT_FMT_18_CMP_CODE
1035
1036   CPU (h_cond) = LTUSI (OPRND (src1), OPRND (src2));
1037   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1038
1039 #if WITH_PROFILE_MODEL_P
1040   if (PROFILE_MODEL_P (current_cpu))
1041     {
1042       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1043       m32rx_model_profile_insn (current_cpu, abuf);
1044     }
1045 #endif
1046
1047   return new_pc;
1048 #undef OPRND
1049 }
1050
1051 /* Perform cmpui: cmpui $src2,#$uimm16.  */
1052 CIA
1053 SEM_FN_NAME (m32rx,cmpui) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1054 {
1055   insn_t insn = SEM_INSN (sem_arg);
1056 #define OPRND(f) par_exec->operands.fmt_20_cmpui.f
1057   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1058   CIA new_pc = CPU (h_pc) + 4;
1059   EXTRACT_FMT_20_CMPUI_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
1060   EXTRACT_FMT_20_CMPUI_CODE
1061
1062   CPU (h_cond) = LTUSI (OPRND (src2), OPRND (uimm16));
1063   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1064
1065 #if WITH_PROFILE_MODEL_P
1066   if (PROFILE_MODEL_P (current_cpu))
1067     {
1068       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1069       m32rx_model_profile_insn (current_cpu, abuf);
1070     }
1071 #endif
1072
1073   return new_pc;
1074 #undef OPRND
1075 }
1076
1077 /* Perform cmpeq: cmpeq $src1,$src2.  */
1078 CIA
1079 SEM_FN_NAME (m32rx,cmpeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1080 {
1081   insn_t insn = SEM_INSN (sem_arg);
1082 #define OPRND(f) par_exec->operands.fmt_18_cmp.f
1083   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1084   CIA new_pc = CPU (h_pc) + 2;
1085   EXTRACT_FMT_18_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1086   EXTRACT_FMT_18_CMP_CODE
1087
1088   CPU (h_cond) = EQSI (OPRND (src1), OPRND (src2));
1089   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1090
1091 #if WITH_PROFILE_MODEL_P
1092   if (PROFILE_MODEL_P (current_cpu))
1093     {
1094       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1095       m32rx_model_profile_insn (current_cpu, abuf);
1096     }
1097 #endif
1098
1099   return new_pc;
1100 #undef OPRND
1101 }
1102
1103 /* Perform cmpz: cmpz $src2.  */
1104 CIA
1105 SEM_FN_NAME (m32rx,cmpz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1106 {
1107   insn_t insn = SEM_INSN (sem_arg);
1108 #define OPRND(f) par_exec->operands.fmt_21_cmpz.f
1109   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1110   CIA new_pc = CPU (h_pc) + 2;
1111   EXTRACT_FMT_21_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
1112   EXTRACT_FMT_21_CMPZ_CODE
1113
1114   CPU (h_cond) = EQSI (OPRND (src2), 0);
1115   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
1116
1117 #if WITH_PROFILE_MODEL_P
1118   if (PROFILE_MODEL_P (current_cpu))
1119     {
1120       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1121       m32rx_model_profile_insn (current_cpu, abuf);
1122     }
1123 #endif
1124
1125   return new_pc;
1126 #undef OPRND
1127 }
1128
1129 /* Perform div: div $dr,$sr.  */
1130 CIA
1131 SEM_FN_NAME (m32rx,div) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1132 {
1133   insn_t insn = SEM_INSN (sem_arg);
1134 #define OPRND(f) par_exec->operands.fmt_22_div.f
1135   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1136   CIA new_pc = CPU (h_pc) + 4;
1137   EXTRACT_FMT_22_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1138   EXTRACT_FMT_22_DIV_CODE
1139
1140 if (NESI (OPRND (sr), 0)) {
1141   CPU (h_gr[f_r1]) = DIVSI (OPRND (dr), OPRND (sr));
1142   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1143 }
1144
1145 #if WITH_PROFILE_MODEL_P
1146   if (PROFILE_MODEL_P (current_cpu))
1147     {
1148       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1149       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1150       m32rx_model_profile_insn (current_cpu, abuf);
1151     }
1152 #endif
1153
1154   return new_pc;
1155 #undef OPRND
1156 }
1157
1158 /* Perform divu: divu $dr,$sr.  */
1159 CIA
1160 SEM_FN_NAME (m32rx,divu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1161 {
1162   insn_t insn = SEM_INSN (sem_arg);
1163 #define OPRND(f) par_exec->operands.fmt_22_div.f
1164   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1165   CIA new_pc = CPU (h_pc) + 4;
1166   EXTRACT_FMT_22_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1167   EXTRACT_FMT_22_DIV_CODE
1168
1169 if (NESI (OPRND (sr), 0)) {
1170   CPU (h_gr[f_r1]) = UDIVSI (OPRND (dr), OPRND (sr));
1171   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1172 }
1173
1174 #if WITH_PROFILE_MODEL_P
1175   if (PROFILE_MODEL_P (current_cpu))
1176     {
1177       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1178       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1179       m32rx_model_profile_insn (current_cpu, abuf);
1180     }
1181 #endif
1182
1183   return new_pc;
1184 #undef OPRND
1185 }
1186
1187 /* Perform rem: rem $dr,$sr.  */
1188 CIA
1189 SEM_FN_NAME (m32rx,rem) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1190 {
1191   insn_t insn = SEM_INSN (sem_arg);
1192 #define OPRND(f) par_exec->operands.fmt_22_div.f
1193   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1194   CIA new_pc = CPU (h_pc) + 4;
1195   EXTRACT_FMT_22_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1196   EXTRACT_FMT_22_DIV_CODE
1197
1198 if (NESI (OPRND (sr), 0)) {
1199   CPU (h_gr[f_r1]) = MODSI (OPRND (dr), OPRND (sr));
1200   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1201 }
1202
1203 #if WITH_PROFILE_MODEL_P
1204   if (PROFILE_MODEL_P (current_cpu))
1205     {
1206       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1207       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1208       m32rx_model_profile_insn (current_cpu, abuf);
1209     }
1210 #endif
1211
1212   return new_pc;
1213 #undef OPRND
1214 }
1215
1216 /* Perform remu: remu $dr,$sr.  */
1217 CIA
1218 SEM_FN_NAME (m32rx,remu) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1219 {
1220   insn_t insn = SEM_INSN (sem_arg);
1221 #define OPRND(f) par_exec->operands.fmt_22_div.f
1222   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1223   CIA new_pc = CPU (h_pc) + 4;
1224   EXTRACT_FMT_22_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1225   EXTRACT_FMT_22_DIV_CODE
1226
1227 if (NESI (OPRND (sr), 0)) {
1228   CPU (h_gr[f_r1]) = UMODSI (OPRND (dr), OPRND (sr));
1229   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1230 }
1231
1232 #if WITH_PROFILE_MODEL_P
1233   if (PROFILE_MODEL_P (current_cpu))
1234     {
1235       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1236       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1237       m32rx_model_profile_insn (current_cpu, abuf);
1238     }
1239 #endif
1240
1241   return new_pc;
1242 #undef OPRND
1243 }
1244
1245 /* Perform divh: divh $dr,$sr.  */
1246 CIA
1247 SEM_FN_NAME (m32rx,divh) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1248 {
1249   insn_t insn = SEM_INSN (sem_arg);
1250 #define OPRND(f) par_exec->operands.fmt_22_div.f
1251   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1252   CIA new_pc = CPU (h_pc) + 4;
1253   EXTRACT_FMT_22_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1254   EXTRACT_FMT_22_DIV_CODE
1255
1256 if (NESI (OPRND (sr), 0)) {
1257   CPU (h_gr[f_r1]) = DIVSI (EXTHISI (TRUNCSIHI (OPRND (dr))), OPRND (sr));
1258   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1259 }
1260
1261 #if WITH_PROFILE_MODEL_P
1262   if (PROFILE_MODEL_P (current_cpu))
1263     {
1264       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1265       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1266       m32rx_model_profile_insn (current_cpu, abuf);
1267     }
1268 #endif
1269
1270   return new_pc;
1271 #undef OPRND
1272 }
1273
1274 /* Perform jc: jc $sr.  */
1275 CIA
1276 SEM_FN_NAME (m32rx,jc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1277 {
1278   insn_t insn = SEM_INSN (sem_arg);
1279 #define OPRND(f) par_exec->operands.fmt_23_jc.f
1280   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1281   CIA new_pc = CPU (h_pc) + 2;
1282   int taken_p = 0;
1283   EXTRACT_FMT_23_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1284   EXTRACT_FMT_23_JC_CODE
1285
1286 if (OPRND (condbit)) {
1287   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4)));
1288   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
1289 }
1290
1291 #if WITH_PROFILE_MODEL_P
1292   if (PROFILE_MODEL_P (current_cpu))
1293     {
1294       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1295       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
1296     }
1297 #endif
1298
1299   return new_pc;
1300 #undef OPRND
1301 }
1302
1303 /* Perform jnc: jnc $sr.  */
1304 CIA
1305 SEM_FN_NAME (m32rx,jnc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1306 {
1307   insn_t insn = SEM_INSN (sem_arg);
1308 #define OPRND(f) par_exec->operands.fmt_23_jc.f
1309   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1310   CIA new_pc = CPU (h_pc) + 2;
1311   int taken_p = 0;
1312   EXTRACT_FMT_23_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1313   EXTRACT_FMT_23_JC_CODE
1314
1315 if (NOTBI (OPRND (condbit))) {
1316   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, ANDSI (OPRND (sr), -4)));
1317   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
1318 }
1319
1320 #if WITH_PROFILE_MODEL_P
1321   if (PROFILE_MODEL_P (current_cpu))
1322     {
1323       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1324       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
1325     }
1326 #endif
1327
1328   return new_pc;
1329 #undef OPRND
1330 }
1331
1332 /* Perform jl: jl $sr.  */
1333 CIA
1334 SEM_FN_NAME (m32rx,jl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1335 {
1336   insn_t insn = SEM_INSN (sem_arg);
1337 #define OPRND(f) par_exec->operands.fmt_24_jl.f
1338   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1339   CIA new_pc = CPU (h_pc) + 2;
1340   int taken_p = 0;
1341   EXTRACT_FMT_24_JL_VARS /* f-op1 f-r1 f-op2 f-r2 */
1342   EXTRACT_FMT_24_JL_CODE
1343
1344 do {
1345   SI temp1;SI temp0;
1346   temp0 = ADDSI (ANDSI (OPRND (pc), -4), 4);
1347   temp1 = OPRND (sr);
1348   CPU (h_gr[14]) = temp0;
1349   TRACE_RESULT (current_cpu, "h-gr-14", 'x', CPU (h_gr[14]));
1350   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, temp1));
1351   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
1352 } while (0);
1353
1354 #if WITH_PROFILE_MODEL_P
1355   if (PROFILE_MODEL_P (current_cpu))
1356     {
1357       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1358       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1359       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
1360     }
1361 #endif
1362
1363   return new_pc;
1364 #undef OPRND
1365 }
1366
1367 /* Perform jmp: jmp $sr.  */
1368 CIA
1369 SEM_FN_NAME (m32rx,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1370 {
1371   insn_t insn = SEM_INSN (sem_arg);
1372 #define OPRND(f) par_exec->operands.fmt_25_jmp.f
1373   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1374   CIA new_pc = CPU (h_pc) + 2;
1375   int taken_p = 0;
1376   EXTRACT_FMT_25_JMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1377   EXTRACT_FMT_25_JMP_CODE
1378
1379   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (sr)));
1380   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
1381
1382 #if WITH_PROFILE_MODEL_P
1383   if (PROFILE_MODEL_P (current_cpu))
1384     {
1385       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1386       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
1387     }
1388 #endif
1389
1390   return new_pc;
1391 #undef OPRND
1392 }
1393
1394 /* Perform ld: ld $dr,@$sr.  */
1395 CIA
1396 SEM_FN_NAME (m32rx,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1397 {
1398   insn_t insn = SEM_INSN (sem_arg);
1399 #define OPRND(f) par_exec->operands.fmt_26_ld.f
1400   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1401   CIA new_pc = CPU (h_pc) + 2;
1402   EXTRACT_FMT_26_LD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1403   EXTRACT_FMT_26_LD_CODE
1404
1405   CPU (h_gr[f_r1]) = OPRND (h_memory_sr);
1406   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1407
1408 #if WITH_PROFILE_MODEL_P
1409   if (PROFILE_MODEL_P (current_cpu))
1410     {
1411       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1412       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1413       m32rx_model_profile_insn (current_cpu, abuf);
1414     }
1415 #endif
1416
1417   return new_pc;
1418 #undef OPRND
1419 }
1420
1421 /* Perform ld-d: ld $dr,@($slo16,$sr).  */
1422 CIA
1423 SEM_FN_NAME (m32rx,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1424 {
1425   insn_t insn = SEM_INSN (sem_arg);
1426 #define OPRND(f) par_exec->operands.fmt_27_ld_d.f
1427   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1428   CIA new_pc = CPU (h_pc) + 4;
1429   EXTRACT_FMT_27_LD_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1430   EXTRACT_FMT_27_LD_D_CODE
1431
1432   CPU (h_gr[f_r1]) = OPRND (h_memory_add_WI_sr_slo16);
1433   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1434
1435 #if WITH_PROFILE_MODEL_P
1436   if (PROFILE_MODEL_P (current_cpu))
1437     {
1438       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1439       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1440       m32rx_model_profile_insn (current_cpu, abuf);
1441     }
1442 #endif
1443
1444   return new_pc;
1445 #undef OPRND
1446 }
1447
1448 /* Perform ldb: ldb $dr,@$sr.  */
1449 CIA
1450 SEM_FN_NAME (m32rx,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1451 {
1452   insn_t insn = SEM_INSN (sem_arg);
1453 #define OPRND(f) par_exec->operands.fmt_28_ldb.f
1454   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1455   CIA new_pc = CPU (h_pc) + 2;
1456   EXTRACT_FMT_28_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
1457   EXTRACT_FMT_28_LDB_CODE
1458
1459   CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory_sr));
1460   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1461
1462 #if WITH_PROFILE_MODEL_P
1463   if (PROFILE_MODEL_P (current_cpu))
1464     {
1465       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1466       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1467       m32rx_model_profile_insn (current_cpu, abuf);
1468     }
1469 #endif
1470
1471   return new_pc;
1472 #undef OPRND
1473 }
1474
1475 /* Perform ldb-d: ldb $dr,@($slo16,$sr).  */
1476 CIA
1477 SEM_FN_NAME (m32rx,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1478 {
1479   insn_t insn = SEM_INSN (sem_arg);
1480 #define OPRND(f) par_exec->operands.fmt_29_ldb_d.f
1481   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1482   CIA new_pc = CPU (h_pc) + 4;
1483   EXTRACT_FMT_29_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1484   EXTRACT_FMT_29_LDB_D_CODE
1485
1486   CPU (h_gr[f_r1]) = EXTQISI (OPRND (h_memory_add_WI_sr_slo16));
1487   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1488
1489 #if WITH_PROFILE_MODEL_P
1490   if (PROFILE_MODEL_P (current_cpu))
1491     {
1492       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1493       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1494       m32rx_model_profile_insn (current_cpu, abuf);
1495     }
1496 #endif
1497
1498   return new_pc;
1499 #undef OPRND
1500 }
1501
1502 /* Perform ldh: ldh $dr,@$sr.  */
1503 CIA
1504 SEM_FN_NAME (m32rx,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1505 {
1506   insn_t insn = SEM_INSN (sem_arg);
1507 #define OPRND(f) par_exec->operands.fmt_30_ldh.f
1508   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1509   CIA new_pc = CPU (h_pc) + 2;
1510   EXTRACT_FMT_30_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
1511   EXTRACT_FMT_30_LDH_CODE
1512
1513   CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory_sr));
1514   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1515
1516 #if WITH_PROFILE_MODEL_P
1517   if (PROFILE_MODEL_P (current_cpu))
1518     {
1519       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1520       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1521       m32rx_model_profile_insn (current_cpu, abuf);
1522     }
1523 #endif
1524
1525   return new_pc;
1526 #undef OPRND
1527 }
1528
1529 /* Perform ldh-d: ldh $dr,@($slo16,$sr).  */
1530 CIA
1531 SEM_FN_NAME (m32rx,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1532 {
1533   insn_t insn = SEM_INSN (sem_arg);
1534 #define OPRND(f) par_exec->operands.fmt_31_ldh_d.f
1535   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1536   CIA new_pc = CPU (h_pc) + 4;
1537   EXTRACT_FMT_31_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1538   EXTRACT_FMT_31_LDH_D_CODE
1539
1540   CPU (h_gr[f_r1]) = EXTHISI (OPRND (h_memory_add_WI_sr_slo16));
1541   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1542
1543 #if WITH_PROFILE_MODEL_P
1544   if (PROFILE_MODEL_P (current_cpu))
1545     {
1546       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1547       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1548       m32rx_model_profile_insn (current_cpu, abuf);
1549     }
1550 #endif
1551
1552   return new_pc;
1553 #undef OPRND
1554 }
1555
1556 /* Perform ldub: ldub $dr,@$sr.  */
1557 CIA
1558 SEM_FN_NAME (m32rx,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1559 {
1560   insn_t insn = SEM_INSN (sem_arg);
1561 #define OPRND(f) par_exec->operands.fmt_28_ldb.f
1562   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1563   CIA new_pc = CPU (h_pc) + 2;
1564   EXTRACT_FMT_28_LDB_VARS /* f-op1 f-r1 f-op2 f-r2 */
1565   EXTRACT_FMT_28_LDB_CODE
1566
1567   CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory_sr));
1568   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1569
1570 #if WITH_PROFILE_MODEL_P
1571   if (PROFILE_MODEL_P (current_cpu))
1572     {
1573       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1574       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1575       m32rx_model_profile_insn (current_cpu, abuf);
1576     }
1577 #endif
1578
1579   return new_pc;
1580 #undef OPRND
1581 }
1582
1583 /* Perform ldub-d: ldub $dr,@($slo16,$sr).  */
1584 CIA
1585 SEM_FN_NAME (m32rx,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1586 {
1587   insn_t insn = SEM_INSN (sem_arg);
1588 #define OPRND(f) par_exec->operands.fmt_29_ldb_d.f
1589   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1590   CIA new_pc = CPU (h_pc) + 4;
1591   EXTRACT_FMT_29_LDB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1592   EXTRACT_FMT_29_LDB_D_CODE
1593
1594   CPU (h_gr[f_r1]) = ZEXTQISI (OPRND (h_memory_add_WI_sr_slo16));
1595   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1596
1597 #if WITH_PROFILE_MODEL_P
1598   if (PROFILE_MODEL_P (current_cpu))
1599     {
1600       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1601       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1602       m32rx_model_profile_insn (current_cpu, abuf);
1603     }
1604 #endif
1605
1606   return new_pc;
1607 #undef OPRND
1608 }
1609
1610 /* Perform lduh: lduh $dr,@$sr.  */
1611 CIA
1612 SEM_FN_NAME (m32rx,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1613 {
1614   insn_t insn = SEM_INSN (sem_arg);
1615 #define OPRND(f) par_exec->operands.fmt_30_ldh.f
1616   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1617   CIA new_pc = CPU (h_pc) + 2;
1618   EXTRACT_FMT_30_LDH_VARS /* f-op1 f-r1 f-op2 f-r2 */
1619   EXTRACT_FMT_30_LDH_CODE
1620
1621   CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory_sr));
1622   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1623
1624 #if WITH_PROFILE_MODEL_P
1625   if (PROFILE_MODEL_P (current_cpu))
1626     {
1627       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1628       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1629       m32rx_model_profile_insn (current_cpu, abuf);
1630     }
1631 #endif
1632
1633   return new_pc;
1634 #undef OPRND
1635 }
1636
1637 /* Perform lduh-d: lduh $dr,@($slo16,$sr).  */
1638 CIA
1639 SEM_FN_NAME (m32rx,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1640 {
1641   insn_t insn = SEM_INSN (sem_arg);
1642 #define OPRND(f) par_exec->operands.fmt_31_ldh_d.f
1643   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1644   CIA new_pc = CPU (h_pc) + 4;
1645   EXTRACT_FMT_31_LDH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1646   EXTRACT_FMT_31_LDH_D_CODE
1647
1648   CPU (h_gr[f_r1]) = ZEXTHISI (OPRND (h_memory_add_WI_sr_slo16));
1649   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1650
1651 #if WITH_PROFILE_MODEL_P
1652   if (PROFILE_MODEL_P (current_cpu))
1653     {
1654       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1655       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1656       m32rx_model_profile_insn (current_cpu, abuf);
1657     }
1658 #endif
1659
1660   return new_pc;
1661 #undef OPRND
1662 }
1663
1664 /* Perform ld-plus: ld $dr,@$sr+.  */
1665 CIA
1666 SEM_FN_NAME (m32rx,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1667 {
1668   insn_t insn = SEM_INSN (sem_arg);
1669 #define OPRND(f) par_exec->operands.fmt_32_ld_plus.f
1670   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1671   CIA new_pc = CPU (h_pc) + 2;
1672   EXTRACT_FMT_32_LD_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
1673   EXTRACT_FMT_32_LD_PLUS_CODE
1674
1675 do {
1676   SI temp1;SI temp0;
1677   temp0 = OPRND (h_memory_sr);
1678   temp1 = ADDSI (OPRND (sr), 4);
1679   CPU (h_gr[f_r1]) = temp0;
1680   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1681   CPU (h_gr[f_r2]) = temp1;
1682   TRACE_RESULT (current_cpu, "sr", 'x', CPU (h_gr[f_r2]));
1683 } while (0);
1684
1685 #if WITH_PROFILE_MODEL_P
1686   if (PROFILE_MODEL_P (current_cpu))
1687     {
1688       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1689       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1690       m32rx_model_profile_insn (current_cpu, abuf);
1691     }
1692 #endif
1693
1694   return new_pc;
1695 #undef OPRND
1696 }
1697
1698 /* Perform ld24: ld24 $dr,#$uimm24.  */
1699 CIA
1700 SEM_FN_NAME (m32rx,ld24) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1701 {
1702   insn_t insn = SEM_INSN (sem_arg);
1703 #define OPRND(f) par_exec->operands.fmt_33_ld24.f
1704   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1705   CIA new_pc = CPU (h_pc) + 4;
1706   EXTRACT_FMT_33_LD24_VARS /* f-op1 f-r1 f-uimm24 */
1707   EXTRACT_FMT_33_LD24_CODE
1708
1709   CPU (h_gr[f_r1]) = OPRND (uimm24);
1710   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1711
1712 #if WITH_PROFILE_MODEL_P
1713   if (PROFILE_MODEL_P (current_cpu))
1714     {
1715       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1716       m32rx_model_profile_insn (current_cpu, abuf);
1717     }
1718 #endif
1719
1720   return new_pc;
1721 #undef OPRND
1722 }
1723
1724 /* Perform ldi8: ldi $dr,#$simm8.  */
1725 CIA
1726 SEM_FN_NAME (m32rx,ldi8) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1727 {
1728   insn_t insn = SEM_INSN (sem_arg);
1729 #define OPRND(f) par_exec->operands.fmt_34_ldi8.f
1730   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1731   CIA new_pc = CPU (h_pc) + 2;
1732   EXTRACT_FMT_34_LDI8_VARS /* f-op1 f-r1 f-simm8 */
1733   EXTRACT_FMT_34_LDI8_CODE
1734
1735   CPU (h_gr[f_r1]) = OPRND (simm8);
1736   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1737
1738 #if WITH_PROFILE_MODEL_P
1739   if (PROFILE_MODEL_P (current_cpu))
1740     {
1741       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1742       m32rx_model_profile_insn (current_cpu, abuf);
1743     }
1744 #endif
1745
1746   return new_pc;
1747 #undef OPRND
1748 }
1749
1750 /* Perform ldi16: ldi $dr,$slo16.  */
1751 CIA
1752 SEM_FN_NAME (m32rx,ldi16) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1753 {
1754   insn_t insn = SEM_INSN (sem_arg);
1755 #define OPRND(f) par_exec->operands.fmt_35_ldi16.f
1756   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1757   CIA new_pc = CPU (h_pc) + 4;
1758   EXTRACT_FMT_35_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1759   EXTRACT_FMT_35_LDI16_CODE
1760
1761   CPU (h_gr[f_r1]) = OPRND (slo16);
1762   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1763
1764 #if WITH_PROFILE_MODEL_P
1765   if (PROFILE_MODEL_P (current_cpu))
1766     {
1767       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1768       m32rx_model_profile_insn (current_cpu, abuf);
1769     }
1770 #endif
1771
1772   return new_pc;
1773 #undef OPRND
1774 }
1775
1776 /* Perform lock: lock $dr,@$sr.  */
1777 CIA
1778 SEM_FN_NAME (m32rx,lock) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1779 {
1780   insn_t insn = SEM_INSN (sem_arg);
1781 #define OPRND(f) par_exec->operands.fmt_36_lock.f
1782   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1783   CIA new_pc = CPU (h_pc) + 2;
1784   EXTRACT_FMT_36_LOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
1785   EXTRACT_FMT_36_LOCK_CODE
1786
1787 do {
1788   CPU (h_lock) = 1;
1789   TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock));
1790   CPU (h_gr[f_r1]) = OPRND (h_memory_sr);
1791   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1792 } while (0);
1793
1794 #if WITH_PROFILE_MODEL_P
1795   if (PROFILE_MODEL_P (current_cpu))
1796     {
1797       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1798       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1799       m32rx_model_profile_insn (current_cpu, abuf);
1800     }
1801 #endif
1802
1803   return new_pc;
1804 #undef OPRND
1805 }
1806
1807 /* Perform machi-a: machi $src1,$src2,$acc.  */
1808 CIA
1809 SEM_FN_NAME (m32rx,machi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1810 {
1811   insn_t insn = SEM_INSN (sem_arg);
1812 #define OPRND(f) par_exec->operands.fmt_37_machi_a.f
1813   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1814   CIA new_pc = CPU (h_pc) + 2;
1815   EXTRACT_FMT_37_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
1816   EXTRACT_FMT_37_MACHI_A_CODE
1817
1818 m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16))))), 8), 8));
1819   TRACE_RESULT (current_cpu, "acc", 'D', m32rx_h_accums_get (current_cpu, f_acc));
1820
1821 #if WITH_PROFILE_MODEL_P
1822   if (PROFILE_MODEL_P (current_cpu))
1823     {
1824       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1825       m32rx_model_profile_insn (current_cpu, abuf);
1826     }
1827 #endif
1828
1829   return new_pc;
1830 #undef OPRND
1831 }
1832
1833 /* Perform maclo-a: maclo $src1,$src2,$acc.  */
1834 CIA
1835 SEM_FN_NAME (m32rx,maclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1836 {
1837   insn_t insn = SEM_INSN (sem_arg);
1838 #define OPRND(f) par_exec->operands.fmt_37_machi_a.f
1839   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1840   CIA new_pc = CPU (h_pc) + 2;
1841   EXTRACT_FMT_37_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
1842   EXTRACT_FMT_37_MACHI_A_CODE
1843
1844 m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (ADDDI (OPRND (acc), MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2))))), 8), 8));
1845   TRACE_RESULT (current_cpu, "acc", 'D', m32rx_h_accums_get (current_cpu, f_acc));
1846
1847 #if WITH_PROFILE_MODEL_P
1848   if (PROFILE_MODEL_P (current_cpu))
1849     {
1850       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1851       m32rx_model_profile_insn (current_cpu, abuf);
1852     }
1853 #endif
1854
1855   return new_pc;
1856 #undef OPRND
1857 }
1858
1859 /* Perform mul: mul $dr,$sr.  */
1860 CIA
1861 SEM_FN_NAME (m32rx,mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1862 {
1863   insn_t insn = SEM_INSN (sem_arg);
1864 #define OPRND(f) par_exec->operands.fmt_0_add.f
1865   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1866   CIA new_pc = CPU (h_pc) + 2;
1867   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1868   EXTRACT_FMT_0_ADD_CODE
1869
1870   CPU (h_gr[f_r1]) = MULSI (OPRND (dr), OPRND (sr));
1871   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1872
1873 #if WITH_PROFILE_MODEL_P
1874   if (PROFILE_MODEL_P (current_cpu))
1875     {
1876       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1877       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1878       m32rx_model_profile_insn (current_cpu, abuf);
1879     }
1880 #endif
1881
1882   return new_pc;
1883 #undef OPRND
1884 }
1885
1886 /* Perform mulhi-a: mulhi $src1,$src2,$acc.  */
1887 CIA
1888 SEM_FN_NAME (m32rx,mulhi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1889 {
1890   insn_t insn = SEM_INSN (sem_arg);
1891 #define OPRND(f) par_exec->operands.fmt_38_mulhi_a.f
1892   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1893   CIA new_pc = CPU (h_pc) + 2;
1894   EXTRACT_FMT_38_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
1895   EXTRACT_FMT_38_MULHI_A_CODE
1896
1897 m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (ANDSI (OPRND (src1), 0xffff0000)), EXTHIDI (TRUNCSIHI (SRASI (OPRND (src2), 16)))), 16), 16));
1898   TRACE_RESULT (current_cpu, "acc", 'D', m32rx_h_accums_get (current_cpu, f_acc));
1899
1900 #if WITH_PROFILE_MODEL_P
1901   if (PROFILE_MODEL_P (current_cpu))
1902     {
1903       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1904       m32rx_model_profile_insn (current_cpu, abuf);
1905     }
1906 #endif
1907
1908   return new_pc;
1909 #undef OPRND
1910 }
1911
1912 /* Perform mullo-a: mullo $src1,$src2,$acc.  */
1913 CIA
1914 SEM_FN_NAME (m32rx,mullo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1915 {
1916   insn_t insn = SEM_INSN (sem_arg);
1917 #define OPRND(f) par_exec->operands.fmt_38_mulhi_a.f
1918   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1919   CIA new_pc = CPU (h_pc) + 2;
1920   EXTRACT_FMT_38_MULHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
1921   EXTRACT_FMT_38_MULHI_A_CODE
1922
1923 m32rx_h_accums_set (current_cpu, f_acc, SRADI (SLLDI (MULDI (EXTSIDI (SLLSI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 16), 16));
1924   TRACE_RESULT (current_cpu, "acc", 'D', m32rx_h_accums_get (current_cpu, f_acc));
1925
1926 #if WITH_PROFILE_MODEL_P
1927   if (PROFILE_MODEL_P (current_cpu))
1928     {
1929       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1930       m32rx_model_profile_insn (current_cpu, abuf);
1931     }
1932 #endif
1933
1934   return new_pc;
1935 #undef OPRND
1936 }
1937
1938 /* Perform mv: mv $dr,$sr.  */
1939 CIA
1940 SEM_FN_NAME (m32rx,mv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1941 {
1942   insn_t insn = SEM_INSN (sem_arg);
1943 #define OPRND(f) par_exec->operands.fmt_39_mv.f
1944   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1945   CIA new_pc = CPU (h_pc) + 2;
1946   EXTRACT_FMT_39_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
1947   EXTRACT_FMT_39_MV_CODE
1948
1949   CPU (h_gr[f_r1]) = OPRND (sr);
1950   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1951
1952 #if WITH_PROFILE_MODEL_P
1953   if (PROFILE_MODEL_P (current_cpu))
1954     {
1955       m32rx_model_mark_get_h_gr (current_cpu, abuf);
1956       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1957       m32rx_model_profile_insn (current_cpu, abuf);
1958     }
1959 #endif
1960
1961   return new_pc;
1962 #undef OPRND
1963 }
1964
1965 /* Perform mvfachi-a: mvfachi $dr,$accs.  */
1966 CIA
1967 SEM_FN_NAME (m32rx,mvfachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1968 {
1969   insn_t insn = SEM_INSN (sem_arg);
1970 #define OPRND(f) par_exec->operands.fmt_40_mvfachi_a.f
1971   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1972   CIA new_pc = CPU (h_pc) + 2;
1973   EXTRACT_FMT_40_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
1974   EXTRACT_FMT_40_MVFACHI_A_CODE
1975
1976   CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 32));
1977   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
1978
1979 #if WITH_PROFILE_MODEL_P
1980   if (PROFILE_MODEL_P (current_cpu))
1981     {
1982       m32rx_model_mark_set_h_gr (current_cpu, abuf);
1983       m32rx_model_profile_insn (current_cpu, abuf);
1984     }
1985 #endif
1986
1987   return new_pc;
1988 #undef OPRND
1989 }
1990
1991 /* Perform mvfaclo-a: mvfaclo $dr,$accs.  */
1992 CIA
1993 SEM_FN_NAME (m32rx,mvfaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
1994 {
1995   insn_t insn = SEM_INSN (sem_arg);
1996 #define OPRND(f) par_exec->operands.fmt_40_mvfachi_a.f
1997   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
1998   CIA new_pc = CPU (h_pc) + 2;
1999   EXTRACT_FMT_40_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
2000   EXTRACT_FMT_40_MVFACHI_A_CODE
2001
2002   CPU (h_gr[f_r1]) = TRUNCDISI (OPRND (accs));
2003   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2004
2005 #if WITH_PROFILE_MODEL_P
2006   if (PROFILE_MODEL_P (current_cpu))
2007     {
2008       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2009       m32rx_model_profile_insn (current_cpu, abuf);
2010     }
2011 #endif
2012
2013   return new_pc;
2014 #undef OPRND
2015 }
2016
2017 /* Perform mvfacmi-a: mvfacmi $dr,$accs.  */
2018 CIA
2019 SEM_FN_NAME (m32rx,mvfacmi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2020 {
2021   insn_t insn = SEM_INSN (sem_arg);
2022 #define OPRND(f) par_exec->operands.fmt_40_mvfachi_a.f
2023   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2024   CIA new_pc = CPU (h_pc) + 2;
2025   EXTRACT_FMT_40_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
2026   EXTRACT_FMT_40_MVFACHI_A_CODE
2027
2028   CPU (h_gr[f_r1]) = TRUNCDISI (SRADI (OPRND (accs), 16));
2029   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2030
2031 #if WITH_PROFILE_MODEL_P
2032   if (PROFILE_MODEL_P (current_cpu))
2033     {
2034       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2035       m32rx_model_profile_insn (current_cpu, abuf);
2036     }
2037 #endif
2038
2039   return new_pc;
2040 #undef OPRND
2041 }
2042
2043 /* Perform mvfc: mvfc $dr,$scr.  */
2044 CIA
2045 SEM_FN_NAME (m32rx,mvfc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2046 {
2047   insn_t insn = SEM_INSN (sem_arg);
2048 #define OPRND(f) par_exec->operands.fmt_41_mvfc.f
2049   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2050   CIA new_pc = CPU (h_pc) + 2;
2051   EXTRACT_FMT_41_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
2052   EXTRACT_FMT_41_MVFC_CODE
2053
2054   CPU (h_gr[f_r1]) = OPRND (scr);
2055   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2056
2057 #if WITH_PROFILE_MODEL_P
2058   if (PROFILE_MODEL_P (current_cpu))
2059     {
2060       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2061       m32rx_model_profile_insn (current_cpu, abuf);
2062     }
2063 #endif
2064
2065   return new_pc;
2066 #undef OPRND
2067 }
2068
2069 /* Perform mvtachi-a: mvtachi $src1,$accs.  */
2070 CIA
2071 SEM_FN_NAME (m32rx,mvtachi_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2072 {
2073   insn_t insn = SEM_INSN (sem_arg);
2074 #define OPRND(f) par_exec->operands.fmt_42_mvtachi_a.f
2075   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2076   CIA new_pc = CPU (h_pc) + 2;
2077   EXTRACT_FMT_42_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
2078   EXTRACT_FMT_42_MVTACHI_A_CODE
2079
2080 m32rx_h_accums_set (current_cpu, f_accs, ORDI (ANDDI (OPRND (accs), MAKEDI (0, 0xffffffff)), SLLDI (EXTSIDI (OPRND (src1)), 32)));
2081   TRACE_RESULT (current_cpu, "accs", 'D', m32rx_h_accums_get (current_cpu, f_accs));
2082
2083 #if WITH_PROFILE_MODEL_P
2084   if (PROFILE_MODEL_P (current_cpu))
2085     {
2086       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2087       m32rx_model_profile_insn (current_cpu, abuf);
2088     }
2089 #endif
2090
2091   return new_pc;
2092 #undef OPRND
2093 }
2094
2095 /* Perform mvtaclo-a: mvtaclo $src1,$accs.  */
2096 CIA
2097 SEM_FN_NAME (m32rx,mvtaclo_a) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2098 {
2099   insn_t insn = SEM_INSN (sem_arg);
2100 #define OPRND(f) par_exec->operands.fmt_42_mvtachi_a.f
2101   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2102   CIA new_pc = CPU (h_pc) + 2;
2103   EXTRACT_FMT_42_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
2104   EXTRACT_FMT_42_MVTACHI_A_CODE
2105
2106 m32rx_h_accums_set (current_cpu, f_accs, ORDI (ANDDI (OPRND (accs), MAKEDI (0xffffffff, 0)), ZEXTSIDI (OPRND (src1))));
2107   TRACE_RESULT (current_cpu, "accs", 'D', m32rx_h_accums_get (current_cpu, f_accs));
2108
2109 #if WITH_PROFILE_MODEL_P
2110   if (PROFILE_MODEL_P (current_cpu))
2111     {
2112       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2113       m32rx_model_profile_insn (current_cpu, abuf);
2114     }
2115 #endif
2116
2117   return new_pc;
2118 #undef OPRND
2119 }
2120
2121 /* Perform mvtc: mvtc $sr,$dcr.  */
2122 CIA
2123 SEM_FN_NAME (m32rx,mvtc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2124 {
2125   insn_t insn = SEM_INSN (sem_arg);
2126 #define OPRND(f) par_exec->operands.fmt_43_mvtc.f
2127   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2128   CIA new_pc = CPU (h_pc) + 2;
2129   EXTRACT_FMT_43_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
2130   EXTRACT_FMT_43_MVTC_CODE
2131
2132 m32rx_h_cr_set (current_cpu, f_r1, OPRND (sr));
2133   TRACE_RESULT (current_cpu, "dcr", 'x', m32rx_h_cr_get (current_cpu, f_r1));
2134
2135 #if WITH_PROFILE_MODEL_P
2136   if (PROFILE_MODEL_P (current_cpu))
2137     {
2138       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2139       m32rx_model_profile_insn (current_cpu, abuf);
2140     }
2141 #endif
2142
2143   return new_pc;
2144 #undef OPRND
2145 }
2146
2147 /* Perform neg: neg $dr,$sr.  */
2148 CIA
2149 SEM_FN_NAME (m32rx,neg) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2150 {
2151   insn_t insn = SEM_INSN (sem_arg);
2152 #define OPRND(f) par_exec->operands.fmt_39_mv.f
2153   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2154   CIA new_pc = CPU (h_pc) + 2;
2155   EXTRACT_FMT_39_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
2156   EXTRACT_FMT_39_MV_CODE
2157
2158   CPU (h_gr[f_r1]) = NEGSI (OPRND (sr));
2159   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2160
2161 #if WITH_PROFILE_MODEL_P
2162   if (PROFILE_MODEL_P (current_cpu))
2163     {
2164       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2165       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2166       m32rx_model_profile_insn (current_cpu, abuf);
2167     }
2168 #endif
2169
2170   return new_pc;
2171 #undef OPRND
2172 }
2173
2174 /* Perform nop: nop.  */
2175 CIA
2176 SEM_FN_NAME (m32rx,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2177 {
2178   insn_t insn = SEM_INSN (sem_arg);
2179 #define OPRND(f) par_exec->operands.fmt_44_nop.f
2180   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2181   CIA new_pc = CPU (h_pc) + 2;
2182   EXTRACT_FMT_44_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2183   EXTRACT_FMT_44_NOP_CODE
2184
2185 PROFILE_COUNT_FILLNOPS (current_cpu, abuf->addr);
2186
2187 #if WITH_PROFILE_MODEL_P
2188   if (PROFILE_MODEL_P (current_cpu))
2189     {
2190       m32rx_model_profile_insn (current_cpu, abuf);
2191     }
2192 #endif
2193
2194   return new_pc;
2195 #undef OPRND
2196 }
2197
2198 /* Perform not: not $dr,$sr.  */
2199 CIA
2200 SEM_FN_NAME (m32rx,not) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2201 {
2202   insn_t insn = SEM_INSN (sem_arg);
2203 #define OPRND(f) par_exec->operands.fmt_39_mv.f
2204   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2205   CIA new_pc = CPU (h_pc) + 2;
2206   EXTRACT_FMT_39_MV_VARS /* f-op1 f-r1 f-op2 f-r2 */
2207   EXTRACT_FMT_39_MV_CODE
2208
2209   CPU (h_gr[f_r1]) = INVSI (OPRND (sr));
2210   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2211
2212 #if WITH_PROFILE_MODEL_P
2213   if (PROFILE_MODEL_P (current_cpu))
2214     {
2215       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2216       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2217       m32rx_model_profile_insn (current_cpu, abuf);
2218     }
2219 #endif
2220
2221   return new_pc;
2222 #undef OPRND
2223 }
2224
2225 /* Perform rac-dsi: rac $accd,$accs,#$imm1.  */
2226 CIA
2227 SEM_FN_NAME (m32rx,rac_dsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2228 {
2229   insn_t insn = SEM_INSN (sem_arg);
2230 #define OPRND(f) par_exec->operands.fmt_45_rac_dsi.f
2231   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2232   CIA new_pc = CPU (h_pc) + 2;
2233   EXTRACT_FMT_45_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
2234   EXTRACT_FMT_45_RAC_DSI_CODE
2235
2236 do {
2237   DI tmp_tmp1;
2238   tmp_tmp1 = SLLDI (OPRND (accs), OPRND (imm1));
2239   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 32768));
2240 m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0xffff0000))) ? (MAKEDI (32767, 0xffff0000)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0xffff0000))));
2241   TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd));
2242 } while (0);
2243
2244 #if WITH_PROFILE_MODEL_P
2245   if (PROFILE_MODEL_P (current_cpu))
2246     {
2247       m32rx_model_profile_insn (current_cpu, abuf);
2248     }
2249 #endif
2250
2251   return new_pc;
2252 #undef OPRND
2253 }
2254
2255 /* Perform rach-dsi: rach $accd,$accs,#$imm1.  */
2256 CIA
2257 SEM_FN_NAME (m32rx,rach_dsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2258 {
2259   insn_t insn = SEM_INSN (sem_arg);
2260 #define OPRND(f) par_exec->operands.fmt_45_rac_dsi.f
2261   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2262   CIA new_pc = CPU (h_pc) + 2;
2263   EXTRACT_FMT_45_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
2264   EXTRACT_FMT_45_RAC_DSI_CODE
2265
2266 do {
2267   DI tmp_tmp1;
2268   tmp_tmp1 = SLLDI (OPRND (accs), OPRND (imm1));
2269   tmp_tmp1 = ADDDI (tmp_tmp1, MAKEDI (0, 0x80000000));
2270 m32rx_h_accums_set (current_cpu, f_accd, (GTDI (tmp_tmp1, MAKEDI (32767, 0))) ? (MAKEDI (32767, 0)) : (LTDI (tmp_tmp1, MAKEDI (0xffff8000, 0))) ? (MAKEDI (0xffff8000, 0)) : (ANDDI (tmp_tmp1, MAKEDI (0xffffffff, 0))));
2271   TRACE_RESULT (current_cpu, "accd", 'D', m32rx_h_accums_get (current_cpu, f_accd));
2272 } while (0);
2273
2274 #if WITH_PROFILE_MODEL_P
2275   if (PROFILE_MODEL_P (current_cpu))
2276     {
2277       m32rx_model_profile_insn (current_cpu, abuf);
2278     }
2279 #endif
2280
2281   return new_pc;
2282 #undef OPRND
2283 }
2284
2285 /* Perform rte: rte.  */
2286 CIA
2287 SEM_FN_NAME (m32rx,rte) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2288 {
2289   insn_t insn = SEM_INSN (sem_arg);
2290 #define OPRND(f) par_exec->operands.fmt_46_rte.f
2291   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2292   CIA new_pc = CPU (h_pc) + 2;
2293   int taken_p = 0;
2294   EXTRACT_FMT_46_RTE_VARS /* f-op1 f-r1 f-op2 f-r2 */
2295   EXTRACT_FMT_46_RTE_CODE
2296
2297 do {
2298   CPU (h_sm) = OPRND (h_bsm_0);
2299   TRACE_RESULT (current_cpu, "h-sm-0", 'x', CPU (h_sm));
2300   CPU (h_ie) = OPRND (h_bie_0);
2301   TRACE_RESULT (current_cpu, "h-ie-0", 'x', CPU (h_ie));
2302   CPU (h_cond) = OPRND (h_bcond_0);
2303   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
2304   BRANCH_NEW_PC (current_cpu, new_pc, SEM_BRANCH_VIA_ADDR (sem_arg, OPRND (h_bpc_0)));
2305   TRACE_RESULT (current_cpu, "pc", 'x', CPU (h_pc));
2306 } while (0);
2307
2308 #if WITH_PROFILE_MODEL_P
2309   if (PROFILE_MODEL_P (current_cpu))
2310     {
2311       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
2312     }
2313 #endif
2314
2315   return new_pc;
2316 #undef OPRND
2317 }
2318
2319 /* Perform seth: seth $dr,#$hi16.  */
2320 CIA
2321 SEM_FN_NAME (m32rx,seth) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2322 {
2323   insn_t insn = SEM_INSN (sem_arg);
2324 #define OPRND(f) par_exec->operands.fmt_47_seth.f
2325   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2326   CIA new_pc = CPU (h_pc) + 4;
2327   EXTRACT_FMT_47_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
2328   EXTRACT_FMT_47_SETH_CODE
2329
2330   CPU (h_gr[f_r1]) = SLLSI (OPRND (hi16), 16);
2331   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2332
2333 #if WITH_PROFILE_MODEL_P
2334   if (PROFILE_MODEL_P (current_cpu))
2335     {
2336       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2337       m32rx_model_profile_insn (current_cpu, abuf);
2338     }
2339 #endif
2340
2341   return new_pc;
2342 #undef OPRND
2343 }
2344
2345 /* Perform sll: sll $dr,$sr.  */
2346 CIA
2347 SEM_FN_NAME (m32rx,sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2348 {
2349   insn_t insn = SEM_INSN (sem_arg);
2350 #define OPRND(f) par_exec->operands.fmt_0_add.f
2351   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2352   CIA new_pc = CPU (h_pc) + 2;
2353   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
2354   EXTRACT_FMT_0_ADD_CODE
2355
2356   CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), ANDSI (OPRND (sr), 31));
2357   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2358
2359 #if WITH_PROFILE_MODEL_P
2360   if (PROFILE_MODEL_P (current_cpu))
2361     {
2362       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2363       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2364       m32rx_model_profile_insn (current_cpu, abuf);
2365     }
2366 #endif
2367
2368   return new_pc;
2369 #undef OPRND
2370 }
2371
2372 /* Perform sll3: sll3 $dr,$sr,#$simm16.  */
2373 CIA
2374 SEM_FN_NAME (m32rx,sll3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2375 {
2376   insn_t insn = SEM_INSN (sem_arg);
2377 #define OPRND(f) par_exec->operands.fmt_48_sll3.f
2378   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2379   CIA new_pc = CPU (h_pc) + 4;
2380   EXTRACT_FMT_48_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2381   EXTRACT_FMT_48_SLL3_CODE
2382
2383   CPU (h_gr[f_r1]) = SLLSI (OPRND (sr), ANDSI (OPRND (simm16), 31));
2384   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2385
2386 #if WITH_PROFILE_MODEL_P
2387   if (PROFILE_MODEL_P (current_cpu))
2388     {
2389       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2390       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2391       m32rx_model_profile_insn (current_cpu, abuf);
2392     }
2393 #endif
2394
2395   return new_pc;
2396 #undef OPRND
2397 }
2398
2399 /* Perform slli: slli $dr,#$uimm5.  */
2400 CIA
2401 SEM_FN_NAME (m32rx,slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2402 {
2403   insn_t insn = SEM_INSN (sem_arg);
2404 #define OPRND(f) par_exec->operands.fmt_49_slli.f
2405   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2406   CIA new_pc = CPU (h_pc) + 2;
2407   EXTRACT_FMT_49_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
2408   EXTRACT_FMT_49_SLLI_CODE
2409
2410   CPU (h_gr[f_r1]) = SLLSI (OPRND (dr), OPRND (uimm5));
2411   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2412
2413 #if WITH_PROFILE_MODEL_P
2414   if (PROFILE_MODEL_P (current_cpu))
2415     {
2416       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2417       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2418       m32rx_model_profile_insn (current_cpu, abuf);
2419     }
2420 #endif
2421
2422   return new_pc;
2423 #undef OPRND
2424 }
2425
2426 /* Perform sra: sra $dr,$sr.  */
2427 CIA
2428 SEM_FN_NAME (m32rx,sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2429 {
2430   insn_t insn = SEM_INSN (sem_arg);
2431 #define OPRND(f) par_exec->operands.fmt_0_add.f
2432   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2433   CIA new_pc = CPU (h_pc) + 2;
2434   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
2435   EXTRACT_FMT_0_ADD_CODE
2436
2437   CPU (h_gr[f_r1]) = SRASI (OPRND (dr), ANDSI (OPRND (sr), 31));
2438   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2439
2440 #if WITH_PROFILE_MODEL_P
2441   if (PROFILE_MODEL_P (current_cpu))
2442     {
2443       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2444       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2445       m32rx_model_profile_insn (current_cpu, abuf);
2446     }
2447 #endif
2448
2449   return new_pc;
2450 #undef OPRND
2451 }
2452
2453 /* Perform sra3: sra3 $dr,$sr,#$simm16.  */
2454 CIA
2455 SEM_FN_NAME (m32rx,sra3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2456 {
2457   insn_t insn = SEM_INSN (sem_arg);
2458 #define OPRND(f) par_exec->operands.fmt_48_sll3.f
2459   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2460   CIA new_pc = CPU (h_pc) + 4;
2461   EXTRACT_FMT_48_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2462   EXTRACT_FMT_48_SLL3_CODE
2463
2464   CPU (h_gr[f_r1]) = SRASI (OPRND (sr), ANDSI (OPRND (simm16), 31));
2465   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2466
2467 #if WITH_PROFILE_MODEL_P
2468   if (PROFILE_MODEL_P (current_cpu))
2469     {
2470       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2471       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2472       m32rx_model_profile_insn (current_cpu, abuf);
2473     }
2474 #endif
2475
2476   return new_pc;
2477 #undef OPRND
2478 }
2479
2480 /* Perform srai: srai $dr,#$uimm5.  */
2481 CIA
2482 SEM_FN_NAME (m32rx,srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2483 {
2484   insn_t insn = SEM_INSN (sem_arg);
2485 #define OPRND(f) par_exec->operands.fmt_49_slli.f
2486   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2487   CIA new_pc = CPU (h_pc) + 2;
2488   EXTRACT_FMT_49_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
2489   EXTRACT_FMT_49_SLLI_CODE
2490
2491   CPU (h_gr[f_r1]) = SRASI (OPRND (dr), OPRND (uimm5));
2492   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2493
2494 #if WITH_PROFILE_MODEL_P
2495   if (PROFILE_MODEL_P (current_cpu))
2496     {
2497       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2498       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2499       m32rx_model_profile_insn (current_cpu, abuf);
2500     }
2501 #endif
2502
2503   return new_pc;
2504 #undef OPRND
2505 }
2506
2507 /* Perform srl: srl $dr,$sr.  */
2508 CIA
2509 SEM_FN_NAME (m32rx,srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2510 {
2511   insn_t insn = SEM_INSN (sem_arg);
2512 #define OPRND(f) par_exec->operands.fmt_0_add.f
2513   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2514   CIA new_pc = CPU (h_pc) + 2;
2515   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
2516   EXTRACT_FMT_0_ADD_CODE
2517
2518   CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), ANDSI (OPRND (sr), 31));
2519   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2520
2521 #if WITH_PROFILE_MODEL_P
2522   if (PROFILE_MODEL_P (current_cpu))
2523     {
2524       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2525       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2526       m32rx_model_profile_insn (current_cpu, abuf);
2527     }
2528 #endif
2529
2530   return new_pc;
2531 #undef OPRND
2532 }
2533
2534 /* Perform srl3: srl3 $dr,$sr,#$simm16.  */
2535 CIA
2536 SEM_FN_NAME (m32rx,srl3) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2537 {
2538   insn_t insn = SEM_INSN (sem_arg);
2539 #define OPRND(f) par_exec->operands.fmt_48_sll3.f
2540   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2541   CIA new_pc = CPU (h_pc) + 4;
2542   EXTRACT_FMT_48_SLL3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2543   EXTRACT_FMT_48_SLL3_CODE
2544
2545   CPU (h_gr[f_r1]) = SRLSI (OPRND (sr), ANDSI (OPRND (simm16), 31));
2546   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2547
2548 #if WITH_PROFILE_MODEL_P
2549   if (PROFILE_MODEL_P (current_cpu))
2550     {
2551       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2552       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2553       m32rx_model_profile_insn (current_cpu, abuf);
2554     }
2555 #endif
2556
2557   return new_pc;
2558 #undef OPRND
2559 }
2560
2561 /* Perform srli: srli $dr,#$uimm5.  */
2562 CIA
2563 SEM_FN_NAME (m32rx,srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2564 {
2565   insn_t insn = SEM_INSN (sem_arg);
2566 #define OPRND(f) par_exec->operands.fmt_49_slli.f
2567   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2568   CIA new_pc = CPU (h_pc) + 2;
2569   EXTRACT_FMT_49_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
2570   EXTRACT_FMT_49_SLLI_CODE
2571
2572   CPU (h_gr[f_r1]) = SRLSI (OPRND (dr), OPRND (uimm5));
2573   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2574
2575 #if WITH_PROFILE_MODEL_P
2576   if (PROFILE_MODEL_P (current_cpu))
2577     {
2578       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2579       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2580       m32rx_model_profile_insn (current_cpu, abuf);
2581     }
2582 #endif
2583
2584   return new_pc;
2585 #undef OPRND
2586 }
2587
2588 /* Perform st: st $src1,@$src2.  */
2589 CIA
2590 SEM_FN_NAME (m32rx,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2591 {
2592   insn_t insn = SEM_INSN (sem_arg);
2593 #define OPRND(f) par_exec->operands.fmt_50_st.f
2594   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2595   CIA new_pc = CPU (h_pc) + 2;
2596   EXTRACT_FMT_50_ST_VARS /* f-op1 f-r1 f-op2 f-r2 */
2597   EXTRACT_FMT_50_ST_CODE
2598
2599 SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
2600   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, OPRND (src2)));
2601
2602 #if WITH_PROFILE_MODEL_P
2603   if (PROFILE_MODEL_P (current_cpu))
2604     {
2605       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2606       m32rx_model_profile_insn (current_cpu, abuf);
2607     }
2608 #endif
2609
2610   return new_pc;
2611 #undef OPRND
2612 }
2613
2614 /* Perform st-d: st $src1,@($slo16,$src2).  */
2615 CIA
2616 SEM_FN_NAME (m32rx,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2617 {
2618   insn_t insn = SEM_INSN (sem_arg);
2619 #define OPRND(f) par_exec->operands.fmt_51_st_d.f
2620   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2621   CIA new_pc = CPU (h_pc) + 4;
2622   EXTRACT_FMT_51_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2623   EXTRACT_FMT_51_ST_D_CODE
2624
2625 SETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
2626   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMSI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));
2627
2628 #if WITH_PROFILE_MODEL_P
2629   if (PROFILE_MODEL_P (current_cpu))
2630     {
2631       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2632       m32rx_model_profile_insn (current_cpu, abuf);
2633     }
2634 #endif
2635
2636   return new_pc;
2637 #undef OPRND
2638 }
2639
2640 /* Perform stb: stb $src1,@$src2.  */
2641 CIA
2642 SEM_FN_NAME (m32rx,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2643 {
2644   insn_t insn = SEM_INSN (sem_arg);
2645 #define OPRND(f) par_exec->operands.fmt_52_stb.f
2646   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2647   CIA new_pc = CPU (h_pc) + 2;
2648   EXTRACT_FMT_52_STB_VARS /* f-op1 f-r1 f-op2 f-r2 */
2649   EXTRACT_FMT_52_STB_CODE
2650
2651 SETMEMQI (current_cpu, OPRND (src2), OPRND (src1));
2652   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMQI (current_cpu, OPRND (src2)));
2653
2654 #if WITH_PROFILE_MODEL_P
2655   if (PROFILE_MODEL_P (current_cpu))
2656     {
2657       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2658       m32rx_model_profile_insn (current_cpu, abuf);
2659     }
2660 #endif
2661
2662   return new_pc;
2663 #undef OPRND
2664 }
2665
2666 /* Perform stb-d: stb $src1,@($slo16,$src2).  */
2667 CIA
2668 SEM_FN_NAME (m32rx,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2669 {
2670   insn_t insn = SEM_INSN (sem_arg);
2671 #define OPRND(f) par_exec->operands.fmt_53_stb_d.f
2672   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2673   CIA new_pc = CPU (h_pc) + 4;
2674   EXTRACT_FMT_53_STB_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2675   EXTRACT_FMT_53_STB_D_CODE
2676
2677 SETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
2678   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMQI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));
2679
2680 #if WITH_PROFILE_MODEL_P
2681   if (PROFILE_MODEL_P (current_cpu))
2682     {
2683       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2684       m32rx_model_profile_insn (current_cpu, abuf);
2685     }
2686 #endif
2687
2688   return new_pc;
2689 #undef OPRND
2690 }
2691
2692 /* Perform sth: sth $src1,@$src2.  */
2693 CIA
2694 SEM_FN_NAME (m32rx,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2695 {
2696   insn_t insn = SEM_INSN (sem_arg);
2697 #define OPRND(f) par_exec->operands.fmt_54_sth.f
2698   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2699   CIA new_pc = CPU (h_pc) + 2;
2700   EXTRACT_FMT_54_STH_VARS /* f-op1 f-r1 f-op2 f-r2 */
2701   EXTRACT_FMT_54_STH_CODE
2702
2703 SETMEMHI (current_cpu, OPRND (src2), OPRND (src1));
2704   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMHI (current_cpu, OPRND (src2)));
2705
2706 #if WITH_PROFILE_MODEL_P
2707   if (PROFILE_MODEL_P (current_cpu))
2708     {
2709       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2710       m32rx_model_profile_insn (current_cpu, abuf);
2711     }
2712 #endif
2713
2714   return new_pc;
2715 #undef OPRND
2716 }
2717
2718 /* Perform sth-d: sth $src1,@($slo16,$src2).  */
2719 CIA
2720 SEM_FN_NAME (m32rx,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2721 {
2722   insn_t insn = SEM_INSN (sem_arg);
2723 #define OPRND(f) par_exec->operands.fmt_55_sth_d.f
2724   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2725   CIA new_pc = CPU (h_pc) + 4;
2726   EXTRACT_FMT_55_STH_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2727   EXTRACT_FMT_55_STH_D_CODE
2728
2729 SETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16)), OPRND (src1));
2730   TRACE_RESULT (current_cpu, "h-memory-add-WI-src2-slo16", 'x', GETMEMHI (current_cpu, ADDSI (OPRND (src2), OPRND (slo16))));
2731
2732 #if WITH_PROFILE_MODEL_P
2733   if (PROFILE_MODEL_P (current_cpu))
2734     {
2735       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2736       m32rx_model_profile_insn (current_cpu, abuf);
2737     }
2738 #endif
2739
2740   return new_pc;
2741 #undef OPRND
2742 }
2743
2744 /* Perform st-plus: st $src1,@+$src2.  */
2745 CIA
2746 SEM_FN_NAME (m32rx,st_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2747 {
2748   insn_t insn = SEM_INSN (sem_arg);
2749 #define OPRND(f) par_exec->operands.fmt_56_st_plus.f
2750   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2751   CIA new_pc = CPU (h_pc) + 2;
2752   EXTRACT_FMT_56_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
2753   EXTRACT_FMT_56_ST_PLUS_CODE
2754
2755 do {
2756   CPU (h_gr[f_r2]) = ADDSI (OPRND (src2), 4);
2757   TRACE_RESULT (current_cpu, "src2", 'x', CPU (h_gr[f_r2]));
2758 SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
2759   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, OPRND (src2)));
2760 } while (0);
2761
2762 #if WITH_PROFILE_MODEL_P
2763   if (PROFILE_MODEL_P (current_cpu))
2764     {
2765       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2766       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2767       m32rx_model_profile_insn (current_cpu, abuf);
2768     }
2769 #endif
2770
2771   return new_pc;
2772 #undef OPRND
2773 }
2774
2775 /* Perform st-minus: st $src1,@-$src2.  */
2776 CIA
2777 SEM_FN_NAME (m32rx,st_minus) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2778 {
2779   insn_t insn = SEM_INSN (sem_arg);
2780 #define OPRND(f) par_exec->operands.fmt_56_st_plus.f
2781   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2782   CIA new_pc = CPU (h_pc) + 2;
2783   EXTRACT_FMT_56_ST_PLUS_VARS /* f-op1 f-r1 f-op2 f-r2 */
2784   EXTRACT_FMT_56_ST_PLUS_CODE
2785
2786 do {
2787   CPU (h_gr[f_r2]) = SUBSI (OPRND (src2), 4);
2788   TRACE_RESULT (current_cpu, "src2", 'x', CPU (h_gr[f_r2]));
2789 SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
2790   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, OPRND (src2)));
2791 } while (0);
2792
2793 #if WITH_PROFILE_MODEL_P
2794   if (PROFILE_MODEL_P (current_cpu))
2795     {
2796       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2797       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2798       m32rx_model_profile_insn (current_cpu, abuf);
2799     }
2800 #endif
2801
2802   return new_pc;
2803 #undef OPRND
2804 }
2805
2806 /* Perform sub: sub $dr,$sr.  */
2807 CIA
2808 SEM_FN_NAME (m32rx,sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2809 {
2810   insn_t insn = SEM_INSN (sem_arg);
2811 #define OPRND(f) par_exec->operands.fmt_0_add.f
2812   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2813   CIA new_pc = CPU (h_pc) + 2;
2814   EXTRACT_FMT_0_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
2815   EXTRACT_FMT_0_ADD_CODE
2816
2817   CPU (h_gr[f_r1]) = SUBSI (OPRND (dr), OPRND (sr));
2818   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2819
2820 #if WITH_PROFILE_MODEL_P
2821   if (PROFILE_MODEL_P (current_cpu))
2822     {
2823       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2824       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2825       m32rx_model_profile_insn (current_cpu, abuf);
2826     }
2827 #endif
2828
2829   return new_pc;
2830 #undef OPRND
2831 }
2832
2833 /* Perform subv: subv $dr,$sr.  */
2834 CIA
2835 SEM_FN_NAME (m32rx,subv) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2836 {
2837   insn_t insn = SEM_INSN (sem_arg);
2838 #define OPRND(f) par_exec->operands.fmt_5_addv.f
2839   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2840   CIA new_pc = CPU (h_pc) + 2;
2841   EXTRACT_FMT_5_ADDV_VARS /* f-op1 f-r1 f-op2 f-r2 */
2842   EXTRACT_FMT_5_ADDV_CODE
2843
2844 do {
2845   BI temp1;SI temp0;
2846   temp0 = SUBSI (OPRND (dr), OPRND (sr));
2847   temp1 = SUBOFSI (OPRND (dr), OPRND (sr), 0);
2848   CPU (h_gr[f_r1]) = temp0;
2849   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2850   CPU (h_cond) = temp1;
2851   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
2852 } while (0);
2853
2854 #if WITH_PROFILE_MODEL_P
2855   if (PROFILE_MODEL_P (current_cpu))
2856     {
2857       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2858       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2859       m32rx_model_profile_insn (current_cpu, abuf);
2860     }
2861 #endif
2862
2863   return new_pc;
2864 #undef OPRND
2865 }
2866
2867 /* Perform subx: subx $dr,$sr.  */
2868 CIA
2869 SEM_FN_NAME (m32rx,subx) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2870 {
2871   insn_t insn = SEM_INSN (sem_arg);
2872 #define OPRND(f) par_exec->operands.fmt_7_addx.f
2873   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2874   CIA new_pc = CPU (h_pc) + 2;
2875   EXTRACT_FMT_7_ADDX_VARS /* f-op1 f-r1 f-op2 f-r2 */
2876   EXTRACT_FMT_7_ADDX_CODE
2877
2878 do {
2879   BI temp1;SI temp0;
2880   temp0 = SUBCSI (OPRND (dr), OPRND (sr), OPRND (condbit));
2881   temp1 = SUBCFSI (OPRND (dr), OPRND (sr), OPRND (condbit));
2882   CPU (h_gr[f_r1]) = temp0;
2883   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2884   CPU (h_cond) = temp1;
2885   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
2886 } while (0);
2887
2888 #if WITH_PROFILE_MODEL_P
2889   if (PROFILE_MODEL_P (current_cpu))
2890     {
2891       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2892       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2893       m32rx_model_profile_insn (current_cpu, abuf);
2894     }
2895 #endif
2896
2897   return new_pc;
2898 #undef OPRND
2899 }
2900
2901 /* Perform trap: trap #$uimm4.  */
2902 CIA
2903 SEM_FN_NAME (m32rx,trap) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2904 {
2905   insn_t insn = SEM_INSN (sem_arg);
2906 #define OPRND(f) par_exec->operands.fmt_57_trap.f
2907   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2908   CIA new_pc = CPU (h_pc) + 2;
2909   int taken_p = 0;
2910   EXTRACT_FMT_57_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
2911   EXTRACT_FMT_57_TRAP_CODE
2912
2913 do {
2914 m32rx_h_cr_set (current_cpu, 6, ADDSI (OPRND (pc), 4));
2915   TRACE_RESULT (current_cpu, "h-cr-6", 'x', m32rx_h_cr_get (current_cpu, 6));
2916 m32rx_h_cr_set (current_cpu, 0, ANDSI (SRLSI (OPRND (h_cr_0), 8), 33488896));
2917   TRACE_RESULT (current_cpu, "h-cr-0", 'x', m32rx_h_cr_get (current_cpu, 0));
2918 do_trap (current_cpu, OPRND (uimm4));
2919 ; /*clobber*/
2920 } while (0);
2921
2922 #if WITH_PROFILE_MODEL_P
2923   if (PROFILE_MODEL_P (current_cpu))
2924     {
2925       m32rx_model_profile_cti_insn (current_cpu, abuf, taken_p);
2926     }
2927 #endif
2928
2929   return new_pc;
2930 #undef OPRND
2931 }
2932
2933 /* Perform unlock: unlock $src1,@$src2.  */
2934 CIA
2935 SEM_FN_NAME (m32rx,unlock) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2936 {
2937   insn_t insn = SEM_INSN (sem_arg);
2938 #define OPRND(f) par_exec->operands.fmt_58_unlock.f
2939   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2940   CIA new_pc = CPU (h_pc) + 2;
2941   EXTRACT_FMT_58_UNLOCK_VARS /* f-op1 f-r1 f-op2 f-r2 */
2942   EXTRACT_FMT_58_UNLOCK_CODE
2943
2944 do {
2945 if (OPRND (h_lock_0)) {
2946 SETMEMSI (current_cpu, OPRND (src2), OPRND (src1));
2947   TRACE_RESULT (current_cpu, "h-memory-src2", 'x', GETMEMSI (current_cpu, OPRND (src2)));
2948 }
2949   CPU (h_lock) = 0;
2950   TRACE_RESULT (current_cpu, "h-lock-0", 'x', CPU (h_lock));
2951 } while (0);
2952
2953 #if WITH_PROFILE_MODEL_P
2954   if (PROFILE_MODEL_P (current_cpu))
2955     {
2956       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2957       m32rx_model_profile_insn (current_cpu, abuf);
2958     }
2959 #endif
2960
2961   return new_pc;
2962 #undef OPRND
2963 }
2964
2965 /* Perform satb: satb $dr,$sr.  */
2966 CIA
2967 SEM_FN_NAME (m32rx,satb) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2968 {
2969   insn_t insn = SEM_INSN (sem_arg);
2970 #define OPRND(f) par_exec->operands.fmt_59_satb.f
2971   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2972   CIA new_pc = CPU (h_pc) + 4;
2973   EXTRACT_FMT_59_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
2974   EXTRACT_FMT_59_SATB_CODE
2975
2976   CPU (h_gr[f_r1]) = (GESI (OPRND (sr), 127)) ? (127) : (LESI (OPRND (sr), -128)) ? (-128) : (OPRND (sr));
2977   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
2978
2979 #if WITH_PROFILE_MODEL_P
2980   if (PROFILE_MODEL_P (current_cpu))
2981     {
2982       m32rx_model_mark_get_h_gr (current_cpu, abuf);
2983       m32rx_model_mark_set_h_gr (current_cpu, abuf);
2984       m32rx_model_profile_insn (current_cpu, abuf);
2985     }
2986 #endif
2987
2988   return new_pc;
2989 #undef OPRND
2990 }
2991
2992 /* Perform sath: sath $dr,$sr.  */
2993 CIA
2994 SEM_FN_NAME (m32rx,sath) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
2995 {
2996   insn_t insn = SEM_INSN (sem_arg);
2997 #define OPRND(f) par_exec->operands.fmt_59_satb.f
2998   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
2999   CIA new_pc = CPU (h_pc) + 4;
3000   EXTRACT_FMT_59_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
3001   EXTRACT_FMT_59_SATB_CODE
3002
3003   CPU (h_gr[f_r1]) = (GESI (OPRND (sr), 32767)) ? (32767) : (LESI (OPRND (sr), -32768)) ? (-32768) : (OPRND (sr));
3004   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
3005
3006 #if WITH_PROFILE_MODEL_P
3007   if (PROFILE_MODEL_P (current_cpu))
3008     {
3009       m32rx_model_mark_get_h_gr (current_cpu, abuf);
3010       m32rx_model_mark_set_h_gr (current_cpu, abuf);
3011       m32rx_model_profile_insn (current_cpu, abuf);
3012     }
3013 #endif
3014
3015   return new_pc;
3016 #undef OPRND
3017 }
3018
3019 /* Perform sat: sat $dr,$sr.  */
3020 CIA
3021 SEM_FN_NAME (m32rx,sat) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3022 {
3023   insn_t insn = SEM_INSN (sem_arg);
3024 #define OPRND(f) par_exec->operands.fmt_60_sat.f
3025   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3026   CIA new_pc = CPU (h_pc) + 4;
3027   EXTRACT_FMT_60_SAT_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
3028   EXTRACT_FMT_60_SAT_CODE
3029
3030   CPU (h_gr[f_r1]) = (OPRND (condbit)) ? ((LTSI (OPRND (sr), 0)) ? (2147483647) : (0x80000000)) : (OPRND (sr));
3031   TRACE_RESULT (current_cpu, "dr", 'x', CPU (h_gr[f_r1]));
3032
3033 #if WITH_PROFILE_MODEL_P
3034   if (PROFILE_MODEL_P (current_cpu))
3035     {
3036       m32rx_model_mark_get_h_gr (current_cpu, abuf);
3037       m32rx_model_mark_set_h_gr (current_cpu, abuf);
3038       m32rx_model_profile_insn (current_cpu, abuf);
3039     }
3040 #endif
3041
3042   return new_pc;
3043 #undef OPRND
3044 }
3045
3046 /* Perform pcmpbz: pcmpbz $src2.  */
3047 CIA
3048 SEM_FN_NAME (m32rx,pcmpbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3049 {
3050   insn_t insn = SEM_INSN (sem_arg);
3051 #define OPRND(f) par_exec->operands.fmt_21_cmpz.f
3052   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3053   CIA new_pc = CPU (h_pc) + 2;
3054   EXTRACT_FMT_21_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
3055   EXTRACT_FMT_21_CMPZ_CODE
3056
3057   CPU (h_cond) = (EQSI (ANDSI (OPRND (src2), 255), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 65280), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 16711680), 0)) ? (1) : (EQSI (ANDSI (OPRND (src2), 0xff000000), 0)) ? (1) : (0);
3058   TRACE_RESULT (current_cpu, "condbit", 'x', CPU (h_cond));
3059
3060 #if WITH_PROFILE_MODEL_P
3061   if (PROFILE_MODEL_P (current_cpu))
3062     {
3063       m32rx_model_mark_get_h_gr (current_cpu, abuf);
3064       m32rx_model_profile_insn (current_cpu, abuf);
3065     }
3066 #endif
3067
3068   return new_pc;
3069 #undef OPRND
3070 }
3071
3072 /* Perform sadd: sadd.  */
3073 CIA
3074 SEM_FN_NAME (m32rx,sadd) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3075 {
3076   insn_t insn = SEM_INSN (sem_arg);
3077 #define OPRND(f) par_exec->operands.fmt_61_sadd.f
3078   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3079   CIA new_pc = CPU (h_pc) + 2;
3080   EXTRACT_FMT_61_SADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
3081   EXTRACT_FMT_61_SADD_CODE
3082
3083 m32rx_h_accums_set (current_cpu, 0, ADDDI (SRADI (OPRND (h_accums_1), 16), OPRND (h_accums_0)));
3084   TRACE_RESULT (current_cpu, "h-accums-0", 'D', m32rx_h_accums_get (current_cpu, 0));
3085
3086 #if WITH_PROFILE_MODEL_P
3087   if (PROFILE_MODEL_P (current_cpu))
3088     {
3089       m32rx_model_profile_insn (current_cpu, abuf);
3090     }
3091 #endif
3092
3093   return new_pc;
3094 #undef OPRND
3095 }
3096
3097 /* Perform macwu1: macwu1 $src1,$src2.  */
3098 CIA
3099 SEM_FN_NAME (m32rx,macwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3100 {
3101   insn_t insn = SEM_INSN (sem_arg);
3102 #define OPRND(f) par_exec->operands.fmt_62_macwu1.f
3103   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3104   CIA new_pc = CPU (h_pc) + 2;
3105   EXTRACT_FMT_62_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
3106   EXTRACT_FMT_62_MACWU1_CODE
3107
3108 m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535)))), 8), 8));
3109   TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));
3110
3111 #if WITH_PROFILE_MODEL_P
3112   if (PROFILE_MODEL_P (current_cpu))
3113     {
3114       m32rx_model_mark_get_h_gr (current_cpu, abuf);
3115       m32rx_model_profile_insn (current_cpu, abuf);
3116     }
3117 #endif
3118
3119   return new_pc;
3120 #undef OPRND
3121 }
3122
3123 /* Perform msblo: msblo $src1,$src2.  */
3124 CIA
3125 SEM_FN_NAME (m32rx,msblo) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3126 {
3127   insn_t insn = SEM_INSN (sem_arg);
3128 #define OPRND(f) par_exec->operands.fmt_63_msblo.f
3129   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3130   CIA new_pc = CPU (h_pc) + 2;
3131   EXTRACT_FMT_63_MSBLO_VARS /* f-op1 f-r1 f-op2 f-r2 */
3132   EXTRACT_FMT_63_MSBLO_CODE
3133
3134   CPU (h_accum) = SRADI (SLLDI (SUBDI (OPRND (accum), SRADI (SLLDI (MULDI (EXTHIDI (TRUNCSIHI (OPRND (src1))), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8);
3135   TRACE_RESULT (current_cpu, "accum", 'D', CPU (h_accum));
3136
3137 #if WITH_PROFILE_MODEL_P
3138   if (PROFILE_MODEL_P (current_cpu))
3139     {
3140       m32rx_model_mark_get_h_gr (current_cpu, abuf);
3141       m32rx_model_profile_insn (current_cpu, abuf);
3142     }
3143 #endif
3144
3145   return new_pc;
3146 #undef OPRND
3147 }
3148
3149 /* Perform mulwu1: mulwu1 $src1,$src2.  */
3150 CIA
3151 SEM_FN_NAME (m32rx,mulwu1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3152 {
3153   insn_t insn = SEM_INSN (sem_arg);
3154 #define OPRND(f) par_exec->operands.fmt_64_mulwu1.f
3155   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3156   CIA new_pc = CPU (h_pc) + 2;
3157   EXTRACT_FMT_64_MULWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
3158   EXTRACT_FMT_64_MULWU1_CODE
3159
3160 m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (MULDI (EXTSIDI (OPRND (src1)), EXTSIDI (ANDSI (OPRND (src2), 65535))), 16), 16));
3161   TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));
3162
3163 #if WITH_PROFILE_MODEL_P
3164   if (PROFILE_MODEL_P (current_cpu))
3165     {
3166       m32rx_model_mark_get_h_gr (current_cpu, abuf);
3167       m32rx_model_profile_insn (current_cpu, abuf);
3168     }
3169 #endif
3170
3171   return new_pc;
3172 #undef OPRND
3173 }
3174
3175 /* Perform maclh1: maclh1 $src1,$src2.  */
3176 CIA
3177 SEM_FN_NAME (m32rx,maclh1) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3178 {
3179   insn_t insn = SEM_INSN (sem_arg);
3180 #define OPRND(f) par_exec->operands.fmt_62_macwu1.f
3181   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3182   CIA new_pc = CPU (h_pc) + 2;
3183   EXTRACT_FMT_62_MACWU1_VARS /* f-op1 f-r1 f-op2 f-r2 */
3184   EXTRACT_FMT_62_MACWU1_CODE
3185
3186 m32rx_h_accums_set (current_cpu, 1, SRADI (SLLDI (ADDDI (OPRND (h_accums_1), SRADI (SLLDI (MULDI (EXTSIDI (SRASI (OPRND (src1), 16)), EXTHIDI (TRUNCSIHI (OPRND (src2)))), 32), 16)), 8), 8));
3187   TRACE_RESULT (current_cpu, "h-accums-1", 'D', m32rx_h_accums_get (current_cpu, 1));
3188
3189 #if WITH_PROFILE_MODEL_P
3190   if (PROFILE_MODEL_P (current_cpu))
3191     {
3192       m32rx_model_mark_get_h_gr (current_cpu, abuf);
3193       m32rx_model_profile_insn (current_cpu, abuf);
3194     }
3195 #endif
3196
3197   return new_pc;
3198 #undef OPRND
3199 }
3200
3201 /* Perform sc: sc.  */
3202 CIA
3203 SEM_FN_NAME (m32rx,sc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3204 {
3205   insn_t insn = SEM_INSN (sem_arg);
3206 #define OPRND(f) par_exec->operands.fmt_65_sc.f
3207   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3208   CIA new_pc = CPU (h_pc) + 2;
3209   EXTRACT_FMT_65_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
3210   EXTRACT_FMT_65_SC_CODE
3211
3212 if (OPRND (condbit)) {
3213   CPU (h_abort) = 1;
3214   TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', CPU (h_abort));
3215 }
3216
3217 #if WITH_PROFILE_MODEL_P
3218   if (PROFILE_MODEL_P (current_cpu))
3219     {
3220       m32rx_model_profile_insn (current_cpu, abuf);
3221     }
3222 #endif
3223
3224   return new_pc;
3225 #undef OPRND
3226 }
3227
3228 /* Perform snc: snc.  */
3229 CIA
3230 SEM_FN_NAME (m32rx,snc) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3231 {
3232   insn_t insn = SEM_INSN (sem_arg);
3233 #define OPRND(f) par_exec->operands.fmt_65_sc.f
3234   ARGBUF *abuf = SEM_ARGBUF (sem_arg);
3235   CIA new_pc = CPU (h_pc) + 2;
3236   EXTRACT_FMT_65_SC_VARS /* f-op1 f-r1 f-op2 f-r2 */
3237   EXTRACT_FMT_65_SC_CODE
3238
3239 if (NOTBI (OPRND (condbit))) {
3240   CPU (h_abort) = 1;
3241   TRACE_RESULT (current_cpu, "abort-parallel-execution", 'x', CPU (h_abort));
3242 }
3243
3244 #if WITH_PROFILE_MODEL_P
3245   if (PROFILE_MODEL_P (current_cpu))
3246     {
3247       m32rx_model_profile_insn (current_cpu, abuf);
3248     }
3249 #endif
3250
3251   return new_pc;
3252 #undef OPRND
3253 }
3254
3255 CIA
3256 SEM_FN_NAME (m32rx,illegal) (SIM_CPU *current_cpu, SEM_ARG sem_arg, PAREXEC *par_exec)
3257 {
3258   sim_engine_illegal_insn (current_cpu, NULL_CIA /*FIXME*/);
3259   return 0;
3260 }
3261
3262 #endif /* ! defined (SCACHE_P) || (defined (SCACHE_P) && WITH_SCACHE) */