sim/m32r/sim-if.c

   1 /* Main simulator entry points for the M32R.
   2    Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This program is free software; you can redistribute it and/or modify
   6 it under the terms of the GNU General Public License as published by
   7 the Free Software Foundation; either version 2, or (at your option)
   8 any later version.
   9
  10 This program is distributed in the hope that it will be useful,
  11 but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 GNU General Public License for more details.
  14
  15 You should have received a copy of the GNU General Public License along
  16 with this program; if not, write to the Free Software Foundation, Inc.,
  17 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  18
  19 #include "sim-main.h"
  20 #include <signal.h>
  21 #ifdef HAVE_STDLIB_H
  22 #include <stdlib.h>
  23 #endif
  24 #include "libiberty.h"
  25 #include "bfd.h"
  26 #include "sim-core.h"
  27
  28 static SIM_RC alloc_cpu (SIM_DESC, struct _bfd *, char **);
  29 static void free_state (SIM_DESC);
  30
  31 /* Records simulator descriptor so utilities like m32r_dump_regs can be
  32    called from gdb.  */
  33 SIM_DESC current_state;
  34 \f
  35 /* Scan the args and bfd to see what kind of cpus are in use and allocate
  36    space for them.  */
  37
  38 static SIM_RC
  39 alloc_cpu (SIM_DESC sd, struct _bfd *abfd, char **argv)
  40 {
  41   /* Compute the size of the SIM_CPU struct.
  42      For now its the max of all the possible sizes.  */
  43   int size = 0;
  44   const MACH *mach;
  45
  46   for (mach = &machs[0]; MACH_NAME (mach) != NULL; ++mach)
  47     {
  48       int mach_size = IMP_PROPS_SIM_CPU_SIZE (MACH_IMP_PROPS (mach));
  49       size = mach_size > size ? mach_size : size;
  50     }
  51   if (size == 0)
  52     abort ();
  53
  54   /* `sizeof (SIM_CPU)' is the size of the generic part, and `size' is the
  55      size of the cpu-specific part.  */
  56   STATE_CPU (sd, 0) = zalloc (sizeof (SIM_CPU) + size);
  57
  58   return SIM_RC_OK;
  59 }
  60
  61 /* Cover function of sim_state_free to free the cpu buffers as well.  */
  62
  63 static void
  64 free_state (SIM_DESC sd)
  65 {
  66   if (STATE_CPU (sd, 0))
  67     zfree (STATE_CPU (sd, 0));
  68   sim_state_free (sd);
  69 }
  70
  71 /* Create an instance of the simulator.  */
  72
  73 SIM_DESC
  74 sim_open (kind, callback, abfd, argv)
  75      SIM_OPEN_KIND kind;
  76      host_callback *callback;
  77      struct _bfd *abfd;
  78      char **argv;
  79 {
  80   SIM_DESC sd = sim_state_alloc (kind, callback);
  81
  82   /* The cpu data is kept in a separately allocated chunk of memory.  */
  83   if (alloc_cpu (sd, abfd, argv) != SIM_RC_OK)
  84     {
  85       free_state (sd);
  86       return 0;
  87     }
  88
  89   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
  90     {
  91       free_state (sd);
  92       return 0;
  93     }
  94
  95 #if 0 /* FIXME: 'twould be nice if we could do this */
  96   /* These options override any module options.
  97      Obviously ambiguity should be avoided, however the caller may wish to
  98      augment the meaning of an option.  */
  99   if (extra_options != NULL)
 100     sim_add_option_table (sd, extra_options);
 101 #endif
 102
 103   /* Allocate core managed memory */
 104   sim_do_commandf (sd, "memory region 0,0x%lx", M32R_DEFAULT_MEM_SIZE);
 105
 106   /* Allocate a handler for the MSPR register.  */
 107   sim_core_attach (sd, NULL,
 108                    0 /*level*/,
 109                    access_write,
 110                    0 /*space ???*/,
 111                    MSPR_ADDR, 1 /*nr_bytes*/, 0 /*modulo*/,
 112                    &m32r_mspr_device,
 113                    NULL /*buffer*/);
 114
 115   /* getopt will print the error message so we just have to exit if this fails.
 116      FIXME: Hmmm...  in the case of gdb we need getopt to call
 117      print_filtered.  */
 118   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 119     {
 120       sim_module_uninstall (sd);
 121       free_state (sd);
 122       return 0;
 123     }
 124
 125   /* check for/establish the a reference program image */
 126   if (sim_analyze_program (sd,
 127                            (STATE_PROG_ARGV (sd) != NULL
 128                             ? *STATE_PROG_ARGV (sd)
 129                             : NULL),
 130                            abfd) != SIM_RC_OK)
 131     {
 132       sim_module_uninstall (sd);
 133       free_state (sd);
 134       return 0;
 135     }
 136
 137   /* Establish any remaining configuration options.  */
 138   if (sim_config (sd) != SIM_RC_OK)
 139     {
 140       sim_module_uninstall (sd);
 141       free_state (sd);
 142       return 0;
 143     }
 144
 145   if (sim_post_argv_init (sd) != SIM_RC_OK)
 146     {
 147       sim_module_uninstall (sd);
 148       free_state (sd);
 149       return 0;
 150     }
 151
 152   /* Initialize various cgen things not done by common framework.  */
 153   cgen_init (sd);
 154
 155   {
 156     int i;
 157
 158     /* Only needed for profiling, but the structure member is small.  */
 159     for (i = 0; i < MAX_NR_PROCESSORS; ++i)
 160       memset (& CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i)), 0,
 161               sizeof (CPU_M32R_MISC_PROFILE (STATE_CPU (sd, i))));
 162   }
 163
 164   /* Store in a global so things like sparc32_dump_regs can be invoked
 165      from the gdb command line.  */
 166   current_state = sd;
 167
 168   return sd;
 169 }
 170
 171 void
 172 sim_close (sd, quitting)
 173      SIM_DESC sd;
 174      int quitting;
 175 {
 176   sim_module_uninstall (sd);
 177 }
 178 \f
 179 SIM_RC
 180 sim_create_inferior (sd, abfd, argv, envp)
 181      SIM_DESC sd;
 182      struct _bfd *abfd;
 183      char **argv;
 184      char **envp;
 185 {
 186   SIM_CPU *current_cpu = STATE_CPU (sd, 0);
 187   SIM_ADDR addr;
 188   SI taddr;
 189
 190   if (abfd != NULL)
 191     addr = bfd_get_start_address (abfd);
 192   else
 193     addr = 0;
 194   taddr = endian_h2t_4 (addr);
 195   sim_store_register (sd, PC_REGNUM, (unsigned char *) &taddr, 4);
 196
 197 #if 0
 198   STATE_ARGV (sd) = sim_copy_argv (argv);
 199   STATE_ENVP (sd) = sim_copy_argv (envp);
 200 #endif
 201
 202   return SIM_RC_OK;
 203 }
 204
 205 int
 206 sim_stop (SIM_DESC sd)
 207 {
 208   switch (STATE_ARCHITECTURE (sd)->mach)
 209     {
 210     case bfd_mach_m32r :
 211       return m32r_engine_stop (sd);
 212 /* start-sanitize-m32rx */
 213 #ifdef HAVE_CPU_M32RX
 214     case bfd_mach_m32rx :
 215       return m32rx_engine_stop (sd);
 216 #endif
 217 /* end-sanitize-m32rx */
 218     default :
 219       abort ();
 220     }
 221 }
 222
 223 void
 224 sim_resume (sd, step, siggnal)
 225      SIM_DESC sd;
 226      int step, siggnal;
 227 {
 228   switch (STATE_ARCHITECTURE (sd)->mach)
 229     {
 230     case bfd_mach_m32r :
 231       m32r_engine_run (sd, step, siggnal);
 232       break;
 233 /* start-sanitize-m32rx */
 234 #ifdef HAVE_CPU_M32RX
 235     case bfd_mach_m32rx :
 236       m32rx_engine_run (sd, step, siggnal);
 237       break;
 238 #endif
 239 /* end-sanitize-m32rx */
 240     default :
 241       abort ();
 242     }
 243 }
 244
 245 /* PROFILE_CPU_CALLBACK */
 246
 247 static void
 248 print_m32r_misc_cpu (SIM_CPU *cpu, int verbose)
 249 {
 250   SIM_DESC sd = CPU_STATE (cpu);
 251   char buf[20];
 252
 253   if (CPU_PROFILE_FLAGS (cpu) [PROFILE_INSN_IDX])
 254     {
 255       sim_io_printf (sd, "Miscellaneous Statistics\n\n");
 256       sim_io_printf (sd, "  %-*s %s\n\n",
 257                      PROFILE_LABEL_WIDTH, "Fill nops:",
 258                      sim_add_commas (buf, sizeof (buf),
 259                                      CPU_M32R_MISC_PROFILE (cpu).fillnop_count));
 260     }
 261 }
 262
 263 void
 264 sim_info (sd, verbose)
 265      SIM_DESC sd;
 266      int verbose;
 267 {
 268   profile_print (sd, STATE_VERBOSE_P (sd), NULL, print_m32r_misc_cpu);
 269 }
 270
 271 /* The contents of BUF are in target byte order.  */
 272
 273 int
 274 sim_fetch_register (sd, rn, buf, length)
 275      SIM_DESC sd;
 276      int rn;
 277      unsigned char *buf;
 278      int length;
 279 {
 280   switch (STATE_ARCHITECTURE (sd)->mach)
 281     {
 282     case bfd_mach_m32r :
 283       m32r_fetch_register (sd, rn, buf);
 284       break;
 285 /* start-sanitize-m32rx */
 286 #ifdef HAVE_CPU_M32RX
 287     case bfd_mach_m32rx :
 288       m32rx_fetch_register (sd, rn, buf);
 289       break;
 290 #endif
 291 /* end-sanitize-m32rx */
 292     default :
 293       abort ();
 294     }
 295   return -1;
 296 }
 297
 298 /* The contents of BUF are in target byte order.  */
 299
 300 int
 301 sim_store_register (sd, rn, buf, length)
 302      SIM_DESC sd;
 303      int rn;
 304      unsigned char *buf;
 305      int length;
 306 {
 307   switch (STATE_ARCHITECTURE (sd)->mach)
 308     {
 309     case bfd_mach_m32r :
 310       m32r_store_register (sd, rn, buf);
 311       break;
 312 /* start-sanitize-m32rx */
 313 #ifdef HAVE_CPU_M32RX
 314     case bfd_mach_m32rx :
 315       m32rx_store_register (sd, rn, buf);
 316       break;
 317 #endif
 318 /* end-sanitize-m32rx */
 319     default :
 320       abort ();
 321     }
 322   return -1;
 323 }
 324
 325 void
 326 sim_do_command (sd, cmd)
 327      SIM_DESC sd;
 328      char *cmd;
 329 {
 330   if (sim_args_command (sd, cmd) != SIM_RC_OK)
 331     sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
 332 }
 333 \f
 334 /* The semantic code invokes this for illegal (unrecognized) instructions.  */
 335
 336 void
 337 sim_engine_illegal_insn (current_cpu, pc)
 338      SIM_CPU *current_cpu;
 339      PCADDR pc;
 340 {
 341   sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, pc,
 342                    sim_stopped, SIM_SIGILL);
 343 }