1 /* m32r exception, interrupt, and trap (EIT) support
2 Copyright (C) 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22 #include "targ-vals.h"
24 /* The semantic code invokes this for invalid (unrecognized) instructions.
25 CIA is the address with the invalid insn.
26 VPC is the virtual pc of the following insn. */
29 sim_engine_invalid_insn (SIM_CPU
*current_cpu
, IADDR cia
, SEM_PC vpc
)
31 SIM_DESC sd
= CPU_STATE (current_cpu
);
34 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
36 h_bsm_set (current_cpu
, h_sm_get (current_cpu
));
37 h_bie_set (current_cpu
, h_ie_get (current_cpu
));
38 h_bcond_set (current_cpu
, h_cond_get (current_cpu
));
40 h_ie_set (current_cpu
, 0);
41 h_cond_set (current_cpu
, 0);
43 h_bpc_set (current_cpu
, cia
);
45 sim_engine_restart (CPU_STATE (current_cpu
), current_cpu
, NULL
,
50 sim_engine_halt (sd
, current_cpu
, NULL
, cia
, sim_stopped
, SIM_SIGILL
);
54 /* Process an address exception. */
57 m32r_core_signal (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
,
58 unsigned int map
, int nr_bytes
, address_word addr
,
59 transfer_type transfer
, sim_core_signals sig
)
61 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
63 a_m32r_h_cr_set (current_cpu
, H_CR_BBPC
,
64 a_m32r_h_cr_get (current_cpu
, H_CR_BPC
));
65 if (MACH_NUM (CPU_MACH (current_cpu
)) == MACH_M32R
)
67 m32rbf_h_bpsw_set (current_cpu
, m32rbf_h_psw_get (current_cpu
));
69 m32rbf_h_psw_set (current_cpu
, m32rbf_h_psw_get (current_cpu
) & 0x80);
73 m32rxf_h_bpsw_set (current_cpu
, m32rxf_h_psw_get (current_cpu
));
75 m32rxf_h_psw_set (current_cpu
, m32rxf_h_psw_get (current_cpu
) & 0x80);
77 a_m32r_h_cr_set (current_cpu
, H_CR_BPC
, cia
);
79 sim_engine_restart (CPU_STATE (current_cpu
), current_cpu
, NULL
,
83 sim_core_signal (sd
, current_cpu
, cia
, map
, nr_bytes
, addr
,
87 /* Read/write functions for system call interface. */
90 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
91 unsigned long taddr
, char *buf
, int bytes
)
93 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
94 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
96 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
100 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
101 unsigned long taddr
, const char *buf
, int bytes
)
103 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
104 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
106 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
110 The result is the pc address to continue at.
111 Preprocessing like saving the various registers has already been done. */
114 m32r_trap (SIM_CPU
*current_cpu
, PCADDR pc
, int num
)
116 SIM_DESC sd
= CPU_STATE (current_cpu
);
117 host_callback
*cb
= STATE_CALLBACK (sd
);
119 #ifdef SIM_HAVE_BREAKPOINTS
120 /* Check for breakpoints "owned" by the simulator first, regardless
122 if (num
== TRAP_BREAKPOINT
)
124 /* First try sim-break.c. If it's a breakpoint the simulator "owns"
125 it doesn't return. Otherwise it returns and let's us try. */
126 sim_handle_breakpoint (sd
, current_cpu
, pc
);
131 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
133 /* The new pc is the trap vector entry.
134 We assume there's a branch there to some handler. */
135 USI new_pc
= EIT_TRAP_BASE_ADDR
+ num
* 4;
145 CB_SYSCALL_INIT (&s
);
146 s
.func
= a_m32r_h_gr_get (current_cpu
, 0);
147 s
.arg1
= a_m32r_h_gr_get (current_cpu
, 1);
148 s
.arg2
= a_m32r_h_gr_get (current_cpu
, 2);
149 s
.arg3
= a_m32r_h_gr_get (current_cpu
, 3);
151 if (s
.func
== TARGET_SYS_exit
)
153 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
157 s
.p2
= (PTR
) current_cpu
;
158 s
.read_mem
= syscall_read_mem
;
159 s
.write_mem
= syscall_write_mem
;
161 a_m32r_h_gr_set (current_cpu
, 2, s
.errcode
);
162 a_m32r_h_gr_set (current_cpu
, 0, s
.result
);
163 a_m32r_h_gr_set (current_cpu
, 1, s
.result2
);
167 case TRAP_BREAKPOINT
:
168 sim_engine_halt (sd
, current_cpu
, NULL
, pc
,
169 sim_stopped
, SIM_SIGTRAP
);
174 USI new_pc
= EIT_TRAP_BASE_ADDR
+ num
* 4;
179 /* Fake an "rte" insn. */
180 /* FIXME: Should duplicate all of rte processing. */
181 return (pc
& -4) + 4;
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