1 /* m32r exception, interrupt, and trap (EIT) support
2 Copyright (C) 1998, 2003, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
4 Contributed by Cygnus Solutions.
6 This file is part of GDB, the GNU debugger.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "targ-vals.h"
24 #define TRAP_FLUSH_CACHE 12
25 /* The semantic code invokes this for invalid (unrecognized) instructions. */
28 sim_engine_invalid_insn (SIM_CPU
*current_cpu
, IADDR cia
, SEM_PC pc
)
30 SIM_DESC sd
= CPU_STATE (current_cpu
);
33 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
35 h_bsm_set (current_cpu
, h_sm_get (current_cpu
));
36 h_bie_set (current_cpu
, h_ie_get (current_cpu
));
37 h_bcond_set (current_cpu
, h_cond_get (current_cpu
));
39 h_ie_set (current_cpu
, 0);
40 h_cond_set (current_cpu
, 0);
42 h_bpc_set (current_cpu
, cia
);
44 sim_engine_restart (CPU_STATE (current_cpu
), current_cpu
, NULL
,
49 sim_engine_halt (sd
, current_cpu
, NULL
, cia
, sim_stopped
, SIM_SIGILL
);
54 /* Process an address exception. */
57 m32r_core_signal (SIM_DESC sd
, SIM_CPU
*current_cpu
, sim_cia cia
,
58 unsigned int map
, int nr_bytes
, address_word addr
,
59 transfer_type transfer
, sim_core_signals sig
)
61 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
63 m32rbf_h_cr_set (current_cpu
, H_CR_BBPC
,
64 m32rbf_h_cr_get (current_cpu
, H_CR_BPC
));
65 switch (MACH_NUM (CPU_MACH (current_cpu
)))
68 m32rbf_h_bpsw_set (current_cpu
, m32rbf_h_psw_get (current_cpu
));
70 m32rbf_h_psw_set (current_cpu
, m32rbf_h_psw_get (current_cpu
) & 0x80);
73 m32rxf_h_bpsw_set (current_cpu
, m32rxf_h_psw_get (current_cpu
));
75 m32rxf_h_psw_set (current_cpu
, m32rxf_h_psw_get (current_cpu
) & 0x80);
78 m32r2f_h_bpsw_set (current_cpu
, m32r2f_h_psw_get (current_cpu
));
80 m32r2f_h_psw_set (current_cpu
, m32r2f_h_psw_get (current_cpu
) & 0x80);
86 m32rbf_h_cr_set (current_cpu
, H_CR_BPC
, cia
);
88 sim_engine_restart (CPU_STATE (current_cpu
), current_cpu
, NULL
,
92 sim_core_signal (sd
, current_cpu
, cia
, map
, nr_bytes
, addr
,
96 /* Read/write functions for system call interface. */
99 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
100 unsigned long taddr
, char *buf
, int bytes
)
102 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
103 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
105 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
109 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
110 unsigned long taddr
, const char *buf
, int bytes
)
112 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
113 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
115 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
119 The result is the pc address to continue at.
120 Preprocessing like saving the various registers has already been done. */
123 m32r_trap (SIM_CPU
*current_cpu
, PCADDR pc
, int num
)
125 SIM_DESC sd
= CPU_STATE (current_cpu
);
126 host_callback
*cb
= STATE_CALLBACK (sd
);
128 #ifdef SIM_HAVE_BREAKPOINTS
129 /* Check for breakpoints "owned" by the simulator first, regardless
131 if (num
== TRAP_BREAKPOINT
)
133 /* First try sim-break.c. If it's a breakpoint the simulator "owns"
134 it doesn't return. Otherwise it returns and let's us try. */
135 sim_handle_breakpoint (sd
, current_cpu
, pc
);
140 if (STATE_ENVIRONMENT (sd
) == OPERATING_ENVIRONMENT
)
142 /* The new pc is the trap vector entry.
143 We assume there's a branch there to some handler.
144 Use cr5 as EVB (EIT Vector Base) register. */
145 /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
146 USI new_pc
= m32rbf_h_cr_get (current_cpu
, 5) + 0x40 + num
* 4;
156 CB_SYSCALL_INIT (&s
);
157 s
.func
= m32rbf_h_gr_get (current_cpu
, 0);
158 s
.arg1
= m32rbf_h_gr_get (current_cpu
, 1);
159 s
.arg2
= m32rbf_h_gr_get (current_cpu
, 2);
160 s
.arg3
= m32rbf_h_gr_get (current_cpu
, 3);
162 if (s
.func
== TARGET_SYS_exit
)
164 sim_engine_halt (sd
, current_cpu
, NULL
, pc
, sim_exited
, s
.arg1
);
168 s
.p2
= (PTR
) current_cpu
;
169 s
.read_mem
= syscall_read_mem
;
170 s
.write_mem
= syscall_write_mem
;
172 m32rbf_h_gr_set (current_cpu
, 2, s
.errcode
);
173 m32rbf_h_gr_set (current_cpu
, 0, s
.result
);
174 m32rbf_h_gr_set (current_cpu
, 1, s
.result2
);
178 case TRAP_BREAKPOINT
:
179 sim_engine_halt (sd
, current_cpu
, NULL
, pc
,
180 sim_stopped
, SIM_SIGTRAP
);
183 case TRAP_FLUSH_CACHE
:
189 /* USI new_pc = EIT_TRAP_BASE_ADDR + num * 4; */
190 /* Use cr5 as EVB (EIT Vector Base) register. */
191 USI new_pc
= m32rbf_h_cr_get (current_cpu
, 5) + 0x40 + num
* 4;
196 /* Fake an "rte" insn. */
197 /* FIXME: Should duplicate all of rte processing. */
198 return (pc
& -4) + 4;
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