1 /* dv-m68hc11sio.c -- Simulation of the 68HC11 serial device.
2 Copyright (C) 1999, 2000 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
4 (From a driver model Contributed by Cygnus Solutions.)
6 This file is part of the program GDB, the GNU debugger.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 #include "dv-sockser.h"
28 #include "sim-assert.h"
33 m68hc11sio - m68hc11 serial I/O
38 Implements the m68hc11 serial I/O controller described in the m68hc11
39 user guide. The serial I/O controller is directly connected to the CPU
40 interrupt. The simulator implements:
49 Use dv-sockser TCP-port backend or stdio for backend. Default: stdio.
56 Reset port. This port is only used to simulate a reset of the serial
57 I/O controller. It should be connected to the RESET output of the cpu.
71 static const struct hw_port_descriptor m68hc11sio_ports
[] =
73 { "reset", RESET_PORT
, 0, input_port
, },
78 /* Serial Controller information. */
81 enum {sio_tcp
, sio_stdio
} backend
; /* backend */
83 /* Number of cpu cycles to send a bit on the wire. */
84 unsigned long baud_cycle
;
86 /* Length in bits of characters sent, this includes the
87 start/stop and parity bits. Together with baud_cycle, this
88 is used to find the number of cpu cycles to send/receive a data. */
89 unsigned int data_length
;
91 /* Information about next character to be transmited. */
92 unsigned char tx_has_char
;
93 unsigned char tx_char
;
95 unsigned char rx_char
;
96 unsigned char rx_clear_scsr
;
98 /* Periodic I/O polling. */
99 struct hw_event
* tx_poll_event
;
100 struct hw_event
* rx_poll_event
;
105 /* Finish off the partially created hw device. Attach our local
106 callbacks. Wire up our port names etc. */
108 static hw_io_read_buffer_method m68hc11sio_io_read_buffer
;
109 static hw_io_write_buffer_method m68hc11sio_io_write_buffer
;
110 static hw_port_event_method m68hc11sio_port_event
;
111 static hw_ioctl_method m68hc11sio_ioctl
;
113 #define M6811_SCI_FIRST_REG (M6811_BAUD)
114 #define M6811_SCI_LAST_REG (M6811_SCDR)
118 attach_m68hc11sio_regs (struct hw
*me
,
119 struct m68hc11sio
*controller
)
121 hw_attach_address (hw_parent (me
), M6811_IO_LEVEL
, io_map
,
123 M6811_SCI_LAST_REG
- M6811_SCI_FIRST_REG
+ 1,
126 if (hw_find_property(me
, "backend") != NULL
)
128 const char *value
= hw_find_string_property(me
, "backend");
129 if(! strcmp(value
, "tcp"))
130 controller
->backend
= sio_tcp
;
131 else if(! strcmp(value
, "stdio"))
132 controller
->backend
= sio_stdio
;
134 hw_abort (me
, "illegal value for backend parameter `%s':"
135 "use tcp or stdio", value
);
141 m68hc11sio_finish (struct hw
*me
)
143 struct m68hc11sio
*controller
;
145 controller
= HW_ZALLOC (me
, struct m68hc11sio
);
146 set_hw_data (me
, controller
);
147 set_hw_io_read_buffer (me
, m68hc11sio_io_read_buffer
);
148 set_hw_io_write_buffer (me
, m68hc11sio_io_write_buffer
);
149 set_hw_ports (me
, m68hc11sio_ports
);
150 set_hw_port_event (me
, m68hc11sio_port_event
);
152 set_hw_ioctl (me
, m68hc11sio_ioctl
);
154 me
->to_ioctl
= m68hc11sio_ioctl
;
157 /* Preset defaults. */
158 controller
->backend
= sio_stdio
;
160 /* Attach ourself to our parent bus. */
161 attach_m68hc11sio_regs (me
, controller
);
163 /* Initialize to reset state. */
164 controller
->tx_poll_event
= NULL
;
165 controller
->rx_poll_event
= NULL
;
166 controller
->tx_char
= 0;
167 controller
->tx_has_char
= 0;
168 controller
->rx_clear_scsr
= 0;
169 controller
->rx_char
= 0;
174 /* An event arrives on an interrupt port. */
177 m68hc11sio_port_event (struct hw
*me
,
184 struct m68hc11sio
*controller
;
188 controller
= hw_data (me
);
190 cpu
= STATE_CPU (sd
, 0);
195 HW_TRACE ((me
, "SCI reset"));
197 /* Reset the state of SCI registers. */
199 m68hc11sio_io_write_buffer (me
, &val
, io_map
,
200 (unsigned_word
) M6811_BAUD
, 1);
201 m68hc11sio_io_write_buffer (me
, &val
, io_map
,
202 (unsigned_word
) M6811_SCCR1
, 1);
203 m68hc11sio_io_write_buffer (me
, &val
, io_map
,
204 (unsigned_word
) M6811_SCCR2
, 1);
206 cpu
->ios
[M6811_SCSR
] = M6811_TC
| M6811_TDRE
;
207 controller
->rx_char
= 0;
208 controller
->tx_char
= 0;
209 controller
->tx_has_char
= 0;
210 controller
->rx_clear_scsr
= 0;
211 if (controller
->rx_poll_event
)
213 hw_event_queue_deschedule (me
, controller
->rx_poll_event
);
214 controller
->rx_poll_event
= 0;
216 if (controller
->tx_poll_event
)
218 hw_event_queue_deschedule (me
, controller
->tx_poll_event
);
219 controller
->tx_poll_event
= 0;
222 /* In bootstrap mode, initialize the SCI to 1200 bauds to
223 simulate some initial setup by the internal rom. */
224 if (((cpu
->ios
[M6811_HPRIO
]) & (M6811_SMOD
| M6811_MDA
)) == M6811_SMOD
)
226 unsigned char val
= 0x33;
228 m68hc11sio_io_write_buffer (me
, &val
, io_map
,
229 (unsigned_word
) M6811_BAUD
, 1);
231 m68hc11sio_io_write_buffer (me
, &val
, io_map
,
232 (unsigned_word
) M6811_SCCR2
, 1);
238 hw_abort (me
, "Event on unknown port %d", my_port
);
245 m68hc11sio_rx_poll (struct hw
*me
, void *data
)
248 struct m68hc11sio
*controller
;
252 int check_interrupt
= 0;
254 controller
= hw_data (me
);
256 cpu
= STATE_CPU (sd
, 0);
257 switch (controller
->backend
)
260 cnt
= dv_sockser_read (sd
);
269 cnt
= sim_io_poll_read (sd
, 0 /* stdin */, &cc
, 1);
279 /* Raise the overrun flag if the previous character was not read. */
280 if (cpu
->ios
[M6811_SCSR
] & M6811_RDRF
)
281 cpu
->ios
[M6811_SCSR
] |= M6811_OR
;
283 cpu
->ios
[M6811_SCSR
] |= M6811_RDRF
;
284 controller
->rx_char
= cc
;
285 controller
->rx_clear_scsr
= 0;
290 /* handle idle line detect here. */
294 if (controller
->rx_poll_event
)
296 hw_event_queue_deschedule (me
, controller
->rx_poll_event
);
297 controller
->rx_poll_event
= 0;
300 if (cpu
->ios
[M6811_SCCR2
] & M6811_RE
)
302 unsigned long clock_cycle
;
304 /* Compute CPU clock cycles to wait for the next character. */
305 clock_cycle
= controller
->data_length
* controller
->baud_cycle
;
307 controller
->rx_poll_event
= hw_event_queue_schedule (me
, clock_cycle
,
313 interrupts_update_pending (&cpu
->cpu_interrupts
);
318 m68hc11sio_tx_poll (struct hw
*me
, void *data
)
321 struct m68hc11sio
*controller
;
323 int check_interrupt
= 0;
325 controller
= hw_data (me
);
327 cpu
= STATE_CPU (sd
, 0);
329 cpu
->ios
[M6811_SCSR
] |= M6811_TDRE
;
330 cpu
->ios
[M6811_SCSR
] |= M6811_TC
;
332 /* Transmitter is enabled and we have something to sent. */
333 if ((cpu
->ios
[M6811_SCCR2
] & M6811_TE
) && controller
->tx_has_char
)
335 cpu
->ios
[M6811_SCSR
] &= ~M6811_TDRE
;
336 cpu
->ios
[M6811_SCSR
] &= ~M6811_TC
;
337 controller
->tx_has_char
= 0;
339 switch (controller
->backend
)
342 dv_sockser_write (sd
, controller
->tx_char
);
346 sim_io_write_stdout (sd
, &controller
->tx_char
, 1);
347 sim_io_flush_stdout (sd
);
355 if (controller
->tx_poll_event
)
357 hw_event_queue_deschedule (me
, controller
->tx_poll_event
);
358 controller
->tx_poll_event
= 0;
361 if ((cpu
->ios
[M6811_SCCR2
] & M6811_TE
)
362 && ((cpu
->ios
[M6811_SCSR
] & M6811_TC
) == 0))
364 unsigned long clock_cycle
;
366 /* Compute CPU clock cycles to wait for the next character. */
367 clock_cycle
= controller
->data_length
* controller
->baud_cycle
;
369 controller
->tx_poll_event
= hw_event_queue_schedule (me
, clock_cycle
,
375 interrupts_update_pending (&cpu
->cpu_interrupts
);
378 /* Descriptions of the SIO I/O ports. These descriptions are only used to
379 give information of the SIO device under GDB. */
380 io_reg_desc sccr2_desc
[] = {
381 { M6811_TIE
, "TIE ", "Transmit Interrupt Enable" },
382 { M6811_TCIE
, "TCIE ", "Transmit Complete Interrupt Enable" },
383 { M6811_RIE
, "RIE ", "Receive Interrupt Enable" },
384 { M6811_ILIE
, "ILIE ", "Idle Line Interrupt Enable" },
385 { M6811_TE
, "TE ", "Transmit Enable" },
386 { M6811_RE
, "RE ", "Receive Enable" },
387 { M6811_RWU
, "RWU ", "Receiver Wake Up" },
388 { M6811_SBK
, "SBRK ", "Send Break" },
392 io_reg_desc sccr1_desc
[] = {
393 { M6811_R8
, "R8 ", "Receive Data bit 8" },
394 { M6811_T8
, "T8 ", "Transmit Data bit 8" },
395 { M6811_M
, "M ", "SCI Character length (0=8-bits, 1=9-bits)" },
396 { M6811_WAKE
, "WAKE ", "Wake up method select (0=idle, 1=addr mark" },
400 io_reg_desc scsr_desc
[] = {
401 { M6811_TDRE
, "TDRE ", "Transmit Data Register Empty" },
402 { M6811_TC
, "TC ", "Transmit Complete" },
403 { M6811_RDRF
, "RDRF ", "Receive Data Register Full" },
404 { M6811_IDLE
, "IDLE ", "Idle Line Detect" },
405 { M6811_OR
, "OR ", "Overrun Error" },
406 { M6811_NF
, "NF ", "Noise Flag" },
407 { M6811_FE
, "FE ", "Framing Error" },
411 io_reg_desc baud_desc
[] = {
412 { M6811_TCLR
, "TCLR ", "Clear baud rate (test mode)" },
413 { M6811_SCP1
, "SCP1 ", "SCI baud rate prescaler select (SCP1)" },
414 { M6811_SCP0
, "SCP0 ", "SCI baud rate prescaler select (SCP0)" },
415 { M6811_RCKB
, "RCKB ", "Baur Rate Clock Check (test mode)" },
416 { M6811_SCR2
, "SCR2 ", "SCI Baud rate select (SCR2)" },
417 { M6811_SCR1
, "SCR1 ", "SCI Baud rate select (SCR1)" },
418 { M6811_SCR0
, "SCR0 ", "SCI Baud rate select (SCR0)" },
423 m68hc11sio_info (struct hw
*me
)
428 struct m68hc11sio
*controller
;
433 cpu
= STATE_CPU (sd
, 0);
434 controller
= hw_data (me
);
436 sim_io_printf (sd
, "M68HC11 SIO:\n");
438 base
= cpu_get_io_base (cpu
);
440 val
= cpu
->ios
[M6811_BAUD
];
441 print_io_byte (sd
, "BAUD ", baud_desc
, val
, base
+ M6811_BAUD
);
442 sim_io_printf (sd
, " (%ld baud)\n",
443 (cpu
->cpu_frequency
/ 4) / controller
->baud_cycle
);
445 val
= cpu
->ios
[M6811_SCCR1
];
446 print_io_byte (sd
, "SCCR1", sccr1_desc
, val
, base
+ M6811_SCCR1
);
447 sim_io_printf (sd
, " (%d bits) (%dN1)\n",
448 controller
->data_length
, controller
->data_length
- 2);
450 val
= cpu
->ios
[M6811_SCCR2
];
451 print_io_byte (sd
, "SCCR2", sccr2_desc
, val
, base
+ M6811_SCCR2
);
452 sim_io_printf (sd
, "\n");
454 val
= cpu
->ios
[M6811_SCSR
];
455 print_io_byte (sd
, "SCSR ", scsr_desc
, val
, base
+ M6811_SCSR
);
456 sim_io_printf (sd
, "\n");
458 clock_cycle
= controller
->data_length
* controller
->baud_cycle
;
460 if (controller
->tx_poll_event
)
465 t
= hw_event_remain_time (me
, controller
->tx_poll_event
);
466 n
= (clock_cycle
- t
) / controller
->baud_cycle
;
467 n
= controller
->data_length
- n
;
468 sim_io_printf (sd
, " Transmit finished in %ld cycles (%d bit%s)\n",
469 (long) t
, n
, (n
> 1 ? "s" : ""));
471 if (controller
->rx_poll_event
)
475 t
= hw_event_remain_time (me
, controller
->rx_poll_event
);
476 sim_io_printf (sd
, " Receive finished in %ld cycles\n",
483 m68hc11sio_ioctl (struct hw
*me
,
484 hw_ioctl_request request
,
487 m68hc11sio_info (me
);
491 /* generic read/write */
494 m68hc11sio_io_read_buffer (struct hw
*me
,
501 struct m68hc11sio
*controller
;
505 HW_TRACE ((me
, "read 0x%08lx %d", (long) base
, (int) nr_bytes
));
508 cpu
= STATE_CPU (sd
, 0);
509 controller
= hw_data (me
);
514 controller
->rx_clear_scsr
= cpu
->ios
[M6811_SCSR
]
515 & (M6811_RDRF
| M6811_IDLE
| M6811_OR
| M6811_NF
| M6811_FE
);
520 val
= cpu
->ios
[base
];
524 if (controller
->rx_clear_scsr
)
526 cpu
->ios
[M6811_SCSR
] &= ~controller
->rx_clear_scsr
;
528 val
= controller
->rx_char
;
534 *((unsigned8
*) dest
) = val
;
539 m68hc11sio_io_write_buffer (struct hw
*me
,
546 struct m68hc11sio
*controller
;
550 HW_TRACE ((me
, "write 0x%08lx %d", (long) base
, (int) nr_bytes
));
553 cpu
= STATE_CPU (sd
, 0);
554 controller
= hw_data (me
);
556 val
= *((const unsigned8
*) source
);
564 cpu
->ios
[M6811_BAUD
] = val
;
565 switch (val
& (M6811_SCP1
|M6811_SCP0
))
567 case M6811_BAUD_DIV_1
:
571 case M6811_BAUD_DIV_3
:
575 case M6811_BAUD_DIV_4
:
580 case M6811_BAUD_DIV_13
:
584 val
&= (M6811_SCR2
|M6811_SCR1
|M6811_SCR0
);
585 divisor
*= (1 << val
);
587 baud
= (cpu
->cpu_frequency
/ 4) / divisor
;
589 HW_TRACE ((me
, "divide rate %ld, baud rate %ld",
592 controller
->baud_cycle
= divisor
;
599 controller
->data_length
= 11;
601 controller
->data_length
= 10;
603 cpu
->ios
[M6811_SCCR1
] = val
;
608 if ((val
& M6811_RE
) == 0)
610 val
&= ~(M6811_RDRF
|M6811_IDLE
|M6811_OR
|M6811_NF
|M6811_NF
);
611 val
|= (cpu
->ios
[M6811_SCCR2
]
612 & (M6811_RDRF
|M6811_IDLE
|M6811_OR
|M6811_NF
|M6811_NF
));
613 cpu
->ios
[M6811_SCCR2
] = val
;
617 /* Activate reception. */
618 if (controller
->rx_poll_event
== 0)
622 /* Compute CPU clock cycles to wait for the next character. */
623 clock_cycle
= controller
->data_length
* controller
->baud_cycle
;
625 controller
->rx_poll_event
= hw_event_queue_schedule (me
, clock_cycle
,
629 cpu
->ios
[M6811_SCCR2
] = val
;
630 interrupts_update_pending (&cpu
->cpu_interrupts
);
638 if (!(cpu
->ios
[M6811_SCSR
] & M6811_TDRE
))
643 controller
->tx_char
= val
;
644 controller
->tx_has_char
= 1;
645 if ((cpu
->ios
[M6811_SCCR2
] & M6811_TE
)
646 && controller
->tx_poll_event
== 0)
648 m68hc11sio_tx_poll (me
, NULL
);
659 const struct hw_descriptor dv_m68hc11sio_descriptor
[] = {
660 { "m68hc11sio", m68hc11sio_finish
, },