1 /* sim-main.h -- Simulator for Motorola 68HC11 & 68HC12
2 Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc.
3 Written by Stephane Carrez (stcarrez@worldnet.fr)
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License along
18 with this program; if not, write to the Free Software Foundation, Inc.,
19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
24 #define WITH_MODULO_MEMORY 1
25 #define WITH_WATCHPOINTS 1
26 #define SIM_HANDLES_LMA 1
28 #include "sim-basics.h"
30 typedef address_word sim_cia
;
32 #include "sim-signal.h"
37 #include "opcode/m68hc11.h"
40 #include "remote-sim.h"
41 #include "opcode/m68hc11.h"
42 #include "sim-types.h"
44 typedef unsigned8 uint8
;
45 typedef unsigned16 uint16
;
46 typedef signed16 int16
;
47 typedef unsigned32 uint32
;
48 typedef signed32 int32
;
49 typedef unsigned64 uint64
;
50 typedef signed64 int64
;
54 #include "interrupts.h"
57 /* Specifies the level of mapping for the IO, EEprom, nvram and external
58 RAM. IO registers are mapped over everything and the external RAM
59 is last (ie, it can be hidden by everything above it in the list). */
60 enum m68hc11_map_level
84 typedef struct m6811_regs
{
94 /* Description of 68HC11 IO registers. Such description is only provided
95 for the info command to display the current setting of IO registers
100 const char *short_name
;
101 const char *long_name
;
103 typedef struct io_reg_desc io_reg_desc
;
105 extern void print_io_reg_desc (SIM_DESC sd
, io_reg_desc
*desc
, int val
,
107 extern void print_io_byte (SIM_DESC sd
, const char *name
,
108 io_reg_desc
*desc
, uint8 val
, uint16 addr
);
111 /* List of special 68HC11&68HC12 instructions that are not handled by the
112 'gencode.c' generator. These complex instructions are implemented
116 /* 68HC11 instructions. */
126 /* 68HC12 instructions. */
147 #define M6811_MAX_PORTS (0x03f+1)
148 #define M6812_MAX_PORTS (0x3ff+1)
149 #define MAX_PORTS (M6812_MAX_PORTS)
151 /* Tentative to keep track of the stack frame.
152 The frame is updated each time a call or a return are made.
153 We also have to take into account changes of stack pointer
154 (either thread switch or longjmp). */
157 struct cpu_frame
*up
;
163 /* Represents a list of frames (or a thread). */
164 struct cpu_frame_list
166 struct cpu_frame_list
*next
;
167 struct cpu_frame_list
*prev
;
168 struct cpu_frame
*frame
;
173 typedef void (* cpu_interp
) (struct _sim_cpu
*);
177 struct m6811_regs cpu_regs
;
179 /* CPU interrupts. */
180 struct interrupts cpu_interrupts
;
182 struct cpu_frame_list
*cpu_frames
;
183 struct cpu_frame_list
*cpu_current_frame
;
184 int cpu_need_update_frame
;
186 /* Pointer to the interpretor routine. */
187 cpu_interp cpu_interpretor
;
189 /* Pointer to the architecture currently configured in the simulator. */
190 const struct bfd_arch_info
*cpu_configured_arch
;
192 /* CPU absolute cycle time. The cycle time is updated after
193 each instruction, by the number of cycles taken by the instruction.
194 It is cleared only when reset occurs. */
195 signed64 cpu_absolute_cycle
;
197 /* Number of cycles to increment after the current instruction.
198 This is also the number of ticks for the generic event scheduler. */
199 uint8 cpu_current_cycle
;
200 int cpu_emul_syscall
;
201 int cpu_is_initialized
;
203 int cpu_check_memory
;
204 int cpu_stop_on_interrupt
;
206 /* When this is set, start execution of program at address specified
207 in the ELF header. This is used for testing some programs that do not
208 have an interrupt table linked with them. Programs created during the
209 GCC validation are like this. A normal 68HC11 does not behave like
210 this (unless there is some OS or downloadable feature). */
211 int cpu_use_elf_start
;
213 /* The starting address specified in ELF header. */
218 /* CPU frequency. This is the quartz frequency. It is divided by 4 to
219 get the cycle time. This is used for the timer rate and for the baud
221 unsigned long cpu_frequency
;
223 /* The mode in which the CPU is configured (MODA and MODB pins). */
224 unsigned int cpu_mode
;
226 /* The cpu being configured. */
227 enum cpu_type cpu_type
;
229 /* Initial value of the CONFIG register. */
231 uint8 cpu_use_local_config
;
233 uint8 ios
[MAX_PORTS
];
235 /* ... base type ... */
239 /* Returns the cpu absolute cycle time (A virtual counter incremented
240 at each 68HC11 E clock). */
241 #define cpu_current_cycle(PROC) ((PROC)->cpu_absolute_cycle)
242 #define cpu_add_cycles(PROC,T) ((PROC)->cpu_current_cycle += (signed64) (T))
243 #define cpu_is_running(PROC) ((PROC)->cpu_running)
245 /* Get the IO/RAM base addresses depending on the M6811_INIT register. */
246 #define cpu_get_io_base(PROC) \
247 (((uint16)(((PROC)->ios[M6811_INIT]) & 0x0F))<<12)
248 #define cpu_get_reg_base(PROC) \
249 (((uint16)(((PROC)->ios[M6811_INIT]) & 0xF0))<<8)
251 /* Returns the different CPU registers. */
252 #define cpu_get_ccr(PROC) ((PROC)->cpu_regs.ccr)
253 #define cpu_get_pc(PROC) ((PROC)->cpu_regs.pc)
254 #define cpu_get_d(PROC) ((PROC)->cpu_regs.d)
255 #define cpu_get_x(PROC) ((PROC)->cpu_regs.ix)
256 #define cpu_get_y(PROC) ((PROC)->cpu_regs.iy)
257 #define cpu_get_sp(PROC) ((PROC)->cpu_regs.sp)
258 #define cpu_get_a(PROC) ((PROC->cpu_regs.d >> 8) & 0x0FF)
259 #define cpu_get_b(PROC) ((PROC->cpu_regs.d) & 0x0FF)
261 /* 68HC12 specific and Motorola internal registers. */
262 #define cpu_get_tmp3(PROC) (0)
263 #define cpu_get_tmp2(PROC) (0)
265 #define cpu_set_d(PROC,VAL) (((PROC)->cpu_regs.d) = (VAL))
266 #define cpu_set_x(PROC,VAL) (((PROC)->cpu_regs.ix) = (VAL))
267 #define cpu_set_y(PROC,VAL) (((PROC)->cpu_regs.iy) = (VAL))
269 /* 68HC12 specific and Motorola internal registers. */
270 #define cpu_set_tmp3(PROC,VAL) (0)
271 #define cpu_set_tmp2(PROC,VAL) (0)
274 /* This is a function in m68hc11_sim.c to keep track of the frame. */
275 #define cpu_set_sp(PROC,VAL) (((PROC)->cpu_regs.sp) = (VAL))
278 #define cpu_set_pc(PROC,VAL) (((PROC)->cpu_regs.pc) = (VAL))
280 #define cpu_set_a(PROC,VAL) \
281 cpu_set_d(PROC,((VAL) << 8) | cpu_get_b(PROC))
282 #define cpu_set_b(PROC,VAL) \
283 cpu_set_d(PROC,((cpu_get_a(PROC)) << 8)|(VAL & 0x0FF))
285 #define cpu_set_ccr(PROC,VAL) ((PROC)->cpu_regs.ccr = (VAL))
286 #define cpu_get_ccr_H(PROC) ((cpu_get_ccr(PROC) & M6811_H_BIT) ? 1: 0)
287 #define cpu_get_ccr_X(PROC) ((cpu_get_ccr(PROC) & M6811_X_BIT) ? 1: 0)
288 #define cpu_get_ccr_S(PROC) ((cpu_get_ccr(PROC) & M6811_S_BIT) ? 1: 0)
289 #define cpu_get_ccr_N(PROC) ((cpu_get_ccr(PROC) & M6811_N_BIT) ? 1: 0)
290 #define cpu_get_ccr_V(PROC) ((cpu_get_ccr(PROC) & M6811_V_BIT) ? 1: 0)
291 #define cpu_get_ccr_C(PROC) ((cpu_get_ccr(PROC) & M6811_C_BIT) ? 1: 0)
292 #define cpu_get_ccr_Z(PROC) ((cpu_get_ccr(PROC) & M6811_Z_BIT) ? 1: 0)
293 #define cpu_get_ccr_I(PROC) ((cpu_get_ccr(PROC) & M6811_I_BIT) ? 1: 0)
295 #define cpu_set_ccr_flag(S,B,V) \
296 cpu_set_ccr(S,(cpu_get_ccr(S) & ~(B)) | ((V) ? B : 0))
298 #define cpu_set_ccr_H(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_H_BIT, VAL)
299 #define cpu_set_ccr_X(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_X_BIT, VAL)
300 #define cpu_set_ccr_S(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_S_BIT, VAL)
301 #define cpu_set_ccr_N(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_N_BIT, VAL)
302 #define cpu_set_ccr_V(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_V_BIT, VAL)
303 #define cpu_set_ccr_C(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_C_BIT, VAL)
304 #define cpu_set_ccr_Z(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_Z_BIT, VAL)
305 #define cpu_set_ccr_I(PROC,VAL) cpu_set_ccr_flag(PROC, M6811_I_BIT, VAL)
308 #define inline static __inline__
310 extern void cpu_memory_exception (struct _sim_cpu
*proc
,
313 const char *message
);
316 memory_read8 (sim_cpu
*cpu
, uint16 addr
)
320 if (sim_core_read_buffer (CPU_STATE (cpu
), cpu
, 0, &val
, addr
, 1) != 1)
322 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
329 memory_write8 (sim_cpu
*cpu
, uint16 addr
, uint8 val
)
331 if (sim_core_write_buffer (CPU_STATE (cpu
), cpu
, 0, &val
, addr
, 1) != 1)
333 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
339 memory_read16 (sim_cpu
*cpu
, uint16 addr
)
343 if (sim_core_read_buffer (CPU_STATE (cpu
), cpu
, 0, b
, addr
, 2) != 2)
345 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
348 return (((uint16
) (b
[0])) << 8) | ((uint16
) b
[1]);
352 memory_write16 (sim_cpu
*cpu
, uint16 addr
, uint16 val
)
358 if (sim_core_write_buffer (CPU_STATE (cpu
), cpu
, 0, b
, addr
, 2) != 2)
360 cpu_memory_exception (cpu
, SIM_SIGSEGV
, addr
,
365 cpu_ccr_update_tst8 (sim_cpu
*proc
, uint8 val
);
368 cpu_ccr_update_tst16 (sim_cpu
*proc
, uint16 val
)
370 cpu_set_ccr_V (proc
, 0);
371 cpu_set_ccr_N (proc
, val
& 0x8000 ? 1 : 0);
372 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
376 cpu_ccr_update_shift8 (sim_cpu
*proc
, uint8 val
)
378 cpu_set_ccr_N (proc
, val
& 0x80 ? 1 : 0);
379 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
380 cpu_set_ccr_V (proc
, cpu_get_ccr_N (proc
) ^ cpu_get_ccr_C (proc
));
384 cpu_ccr_update_shift16 (sim_cpu
*proc
, uint16 val
)
386 cpu_set_ccr_N (proc
, val
& 0x8000 ? 1 : 0);
387 cpu_set_ccr_Z (proc
, val
== 0 ? 1 : 0);
388 cpu_set_ccr_V (proc
, cpu_get_ccr_N (proc
) ^ cpu_get_ccr_C (proc
));
392 cpu_ccr_update_add8 (sim_cpu
*proc
, uint8 r
, uint8 a
, uint8 b
)
394 cpu_set_ccr_C (proc
, ((a
& b
) | (b
& ~r
) | (a
& ~r
)) & 0x80 ? 1 : 0);
395 cpu_set_ccr_V (proc
, ((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x80 ? 1 : 0);
396 cpu_set_ccr_Z (proc
, r
== 0);
397 cpu_set_ccr_N (proc
, r
& 0x80 ? 1 : 0);
402 cpu_ccr_update_sub8 (sim_cpu
*proc
, uint8 r
, uint8 a
, uint8 b
)
404 cpu_set_ccr_C (proc
, ((~a
& b
) | (b
& r
) | (~a
& r
)) & 0x80 ? 1 : 0);
405 cpu_set_ccr_V (proc
, ((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x80 ? 1 : 0);
406 cpu_set_ccr_Z (proc
, r
== 0);
407 cpu_set_ccr_N (proc
, r
& 0x80 ? 1 : 0);
411 cpu_ccr_update_add16 (sim_cpu
*proc
, uint16 r
, uint16 a
, uint16 b
)
413 cpu_set_ccr_C (proc
, ((a
& b
) | (b
& ~r
) | (a
& ~r
)) & 0x8000 ? 1 : 0);
414 cpu_set_ccr_V (proc
, ((a
& b
& ~r
) | (~a
& ~b
& r
)) & 0x8000 ? 1 : 0);
415 cpu_set_ccr_Z (proc
, r
== 0);
416 cpu_set_ccr_N (proc
, r
& 0x8000 ? 1 : 0);
420 cpu_ccr_update_sub16 (sim_cpu
*proc
, uint16 r
, uint16 a
, uint16 b
)
422 cpu_set_ccr_C (proc
, ((~a
& b
) | (b
& r
) | (~a
& r
)) & 0x8000 ? 1 : 0);
423 cpu_set_ccr_V (proc
, ((a
& ~b
& ~r
) | (~a
& b
& r
)) & 0x8000 ? 1 : 0);
424 cpu_set_ccr_Z (proc
, r
== 0);
425 cpu_set_ccr_N (proc
, r
& 0x8000 ? 1 : 0);
428 /* Push and pop instructions for 68HC11 (next-available stack mode). */
430 cpu_m68hc11_push_uint8 (sim_cpu
*proc
, uint8 val
)
432 uint16 addr
= proc
->cpu_regs
.sp
;
434 memory_write8 (proc
, addr
, val
);
435 proc
->cpu_regs
.sp
= addr
- 1;
436 proc
->cpu_need_update_frame
|= CPU_PUSH
;
440 cpu_m68hc11_push_uint16 (sim_cpu
*proc
, uint16 val
)
442 uint16 addr
= proc
->cpu_regs
.sp
- 1;
444 memory_write16 (proc
, addr
, val
);
445 proc
->cpu_regs
.sp
= addr
- 1;
446 proc
->cpu_need_update_frame
|= CPU_PUSH
;
450 cpu_m68hc11_pop_uint8 (sim_cpu
*proc
)
452 uint16 addr
= proc
->cpu_regs
.sp
;
455 val
= memory_read8 (proc
, addr
+ 1);
456 proc
->cpu_regs
.sp
= addr
+ 1;
457 proc
->cpu_need_update_frame
|= CPU_POP
;
462 cpu_m68hc11_pop_uint16 (sim_cpu
*proc
)
464 uint16 addr
= proc
->cpu_regs
.sp
;
467 val
= memory_read16 (proc
, addr
+ 1);
468 proc
->cpu_regs
.sp
= addr
+ 2;
469 proc
->cpu_need_update_frame
|= CPU_POP
;
473 /* Push and pop instructions for 68HC12 (last-used stack mode). */
475 cpu_m68hc12_push_uint8 (sim_cpu
*proc
, uint8 val
)
477 uint16 addr
= proc
->cpu_regs
.sp
;
480 memory_write8 (proc
, addr
, val
);
481 proc
->cpu_regs
.sp
= addr
;
482 proc
->cpu_need_update_frame
|= CPU_PUSH
;
486 cpu_m68hc12_push_uint16 (sim_cpu
*proc
, uint16 val
)
488 uint16 addr
= proc
->cpu_regs
.sp
;
491 memory_write16 (proc
, addr
, val
);
492 proc
->cpu_regs
.sp
= addr
;
493 proc
->cpu_need_update_frame
|= CPU_PUSH
;
497 cpu_m68hc12_pop_uint8 (sim_cpu
*proc
)
499 uint16 addr
= proc
->cpu_regs
.sp
;
502 val
= memory_read8 (proc
, addr
);
503 proc
->cpu_regs
.sp
= addr
+ 1;
504 proc
->cpu_need_update_frame
|= CPU_POP
;
509 cpu_m68hc12_pop_uint16 (sim_cpu
*proc
)
511 uint16 addr
= proc
->cpu_regs
.sp
;
514 val
= memory_read16 (proc
, addr
);
515 proc
->cpu_regs
.sp
= addr
+ 2;
516 proc
->cpu_need_update_frame
|= CPU_POP
;
520 /* Fetch a 8/16 bit value and update the PC. */
522 cpu_fetch8 (sim_cpu
*proc
)
524 uint16 addr
= proc
->cpu_regs
.pc
;
527 val
= memory_read8 (proc
, addr
);
528 proc
->cpu_regs
.pc
= addr
+ 1;
533 cpu_fetch16 (sim_cpu
*proc
)
535 uint16 addr
= proc
->cpu_regs
.pc
;
538 val
= memory_read16 (proc
, addr
);
539 proc
->cpu_regs
.pc
= addr
+ 2;
543 extern void cpu_call (sim_cpu
* proc
, uint16 addr
);
544 extern void cpu_exg (sim_cpu
* proc
, uint8 code
);
545 extern void cpu_dbcc (sim_cpu
* proc
);
546 extern void cpu_special (sim_cpu
*proc
, enum M6811_Special special
);
547 extern void cpu_move8 (sim_cpu
*proc
, uint8 op
);
548 extern void cpu_move16 (sim_cpu
*proc
, uint8 op
);
550 extern uint16
cpu_fetch_relbranch (sim_cpu
*proc
);
551 extern uint16
cpu_fetch_relbranch16 (sim_cpu
*proc
);
552 extern void cpu_push_all (sim_cpu
*proc
);
553 extern void cpu_single_step (sim_cpu
*proc
);
555 extern void cpu_info (SIM_DESC sd
, sim_cpu
*proc
);
557 extern int cpu_initialize (SIM_DESC sd
, sim_cpu
*cpu
);
559 extern void cpu_print_frame (SIM_DESC sd
, sim_cpu
*cpu
);
560 extern void cpu_set_sp (sim_cpu
*cpu
, uint16 val
);
561 extern uint16
cpu_frame_reg (sim_cpu
*cpu
, uint16 rn
);
562 extern int cpu_reset (sim_cpu
*cpu
);
563 extern int cpu_restart (sim_cpu
*cpu
);
564 extern void sim_memory_error (sim_cpu
*cpu
, SIM_SIGNAL excep
,
565 uint16 addr
, const char *message
, ...);
566 extern void emul_os (int op
, sim_cpu
*cpu
);
567 extern void cpu_interp_m6811 (sim_cpu
*cpu
);
568 extern void cpu_interp_m6812 (sim_cpu
*cpu
);
570 /* The current state of the processor; registers, memory, etc. */
572 #define CIA_GET(CPU) (cpu_get_pc (CPU))
573 #define CIA_SET(CPU,VAL) (cpu_set_pc ((CPU), (VAL)))
576 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
578 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
582 sim_cpu cpu
[MAX_NR_PROCESSORS
];
587 extern void sim_set_profile (int n
);
588 extern void sim_set_profile_size (int n
);
589 extern void sim_board_reset (SIM_DESC sd
);
591 extern const char *cycle_to_string (sim_cpu
*cpu
, signed64 t
);