1 /* Simulator for Motorola's MCore processor
2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include <sys/times.h>
25 #include <sys/param.h>
28 #include "gdb/callback.h"
29 #include "libiberty.h"
30 #include "gdb/remote-sim.h"
34 #include "sim-syscall.h"
35 #include "sim-options.h"
37 #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
41 mcore_extract_unsigned_integer (unsigned char *addr
, int len
)
45 unsigned char * startaddr
= (unsigned char *)addr
;
46 unsigned char * endaddr
= startaddr
+ len
;
48 if (len
> (int) sizeof (unsigned long))
49 printf ("That operation is not available on integers of more than %zu bytes.",
50 sizeof (unsigned long));
52 /* Start at the most significant end of the integer, and work towards
53 the least significant. */
56 if (! target_big_endian
)
58 for (p
= endaddr
; p
> startaddr
;)
59 retval
= (retval
<< 8) | * -- p
;
63 for (p
= startaddr
; p
< endaddr
;)
64 retval
= (retval
<< 8) | * p
++;
71 mcore_store_unsigned_integer (unsigned char *addr
, int len
, unsigned long val
)
74 unsigned char * startaddr
= (unsigned char *)addr
;
75 unsigned char * endaddr
= startaddr
+ len
;
77 if (! target_big_endian
)
79 for (p
= startaddr
; p
< endaddr
;)
87 for (p
= endaddr
; p
> startaddr
;)
96 This state is maintained in host byte order. The
97 fetch/store register functions must translate between host
98 byte order and the target processor byte order.
99 Keeping this data in target byte order simplifies the register
100 read/write functions. Keeping this data in native order improves
101 the performance of the simulator. Simulation speed is deemed more
103 /* TODO: Should be moved to sim-main.h:sim_cpu. */
105 /* The ordering of the mcore_regset structure is matched in the
106 gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
109 word gregs
[16]; /* primary registers */
110 word alt_gregs
[16]; /* alt register file */
111 word cregs
[32]; /* control registers */
122 struct mcore_regset asregs
;
123 word asints
[1]; /* but accessed larger... */
126 #define LAST_VALID_CREG 32 /* only 0..12 implemented */
127 #define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
129 static int memcycles
= 1;
131 #define gr asregs.active_gregs
132 #define cr asregs.cregs
133 #define sr asregs.cregs[0]
134 #define vbr asregs.cregs[1]
135 #define esr asregs.cregs[2]
136 #define fsr asregs.cregs[3]
137 #define epc asregs.cregs[4]
138 #define fpc asregs.cregs[5]
139 #define ss0 asregs.cregs[6]
140 #define ss1 asregs.cregs[7]
141 #define ss2 asregs.cregs[8]
142 #define ss3 asregs.cregs[9]
143 #define ss4 asregs.cregs[10]
144 #define gcr asregs.cregs[11]
145 #define gsr asregs.cregs[12]
147 /* maniuplate the carry bit */
148 #define C_ON() (cpu.sr & 1)
149 #define C_VALUE() (cpu.sr & 1)
150 #define C_OFF() ((cpu.sr & 1) == 0)
151 #define SET_C() {cpu.sr |= 1;}
152 #define CLR_C() {cpu.sr &= 0xfffffffe;}
153 #define NEW_C(v) {CLR_C(); cpu.sr |= ((v) & 1);}
155 #define SR_AF() ((cpu.sr >> 1) & 1)
157 #define TRAPCODE 1 /* r1 holds which function we want */
158 #define PARM1 2 /* first parameter */
162 #define RET1 2 /* register for return values. */
164 /* Default to a 8 Mbyte (== 2^23) memory space. */
165 #define DEFAULT_MEMORY_SIZE 0x800000
168 set_initial_gprs (SIM_CPU
*scpu
)
173 /* Set up machine just out of reset. */
174 CPU_PC_SET (scpu
, 0);
177 /* Clean out the GPRs and alternate GPRs. */
178 for (i
= 0; i
< 16; i
++)
180 cpu
.asregs
.gregs
[i
] = 0;
181 cpu
.asregs
.alt_gregs
[i
] = 0;
184 /* Make our register set point to the right place. */
186 cpu
.asregs
.active_gregs
= &cpu
.asregs
.alt_gregs
[0];
188 cpu
.asregs
.active_gregs
= &cpu
.asregs
.gregs
[0];
190 /* ABI specifies initial values for these registers. */
191 cpu
.gr
[0] = DEFAULT_MEMORY_SIZE
- 4;
193 /* dac fix, the stack address must be 8-byte aligned! */
194 cpu
.gr
[0] = cpu
.gr
[0] - cpu
.gr
[0] % 8;
198 cpu
.gr
[PARM4
] = cpu
.gr
[0];
201 /* Simulate a monitor trap. */
204 handle_trap1 (SIM_DESC sd
)
206 /* XXX: We don't pass back the actual errno value. */
207 cpu
.gr
[RET1
] = sim_syscall (STATE_CPU (sd
, 0), cpu
.gr
[TRAPCODE
],
208 cpu
.gr
[PARM1
], cpu
.gr
[PARM2
], cpu
.gr
[PARM3
],
213 process_stub (SIM_DESC sd
, int what
)
215 /* These values should match those in libgloss/mcore/syscalls.s. */
222 case 10: /* _unlink */
223 case 19: /* _lseek */
224 case 43: /* _times */
225 cpu
.gr
[TRAPCODE
] = what
;
230 if (STATE_VERBOSE_P (sd
))
231 fprintf (stderr
, "Unhandled stub opcode: %d\n", what
);
237 util (SIM_DESC sd
, unsigned what
)
242 cpu
.asregs
.exception
= SIGQUIT
;
246 if (STATE_VERBOSE_P (sd
))
247 fprintf (stderr
, "WARNING: printf unimplemented\n");
251 if (STATE_VERBOSE_P (sd
))
252 fprintf (stderr
, "WARNING: scanf unimplemented\n");
256 cpu
.gr
[RET1
] = cpu
.asregs
.insts
;
260 process_stub (sd
, cpu
.gr
[1]);
264 if (STATE_VERBOSE_P (sd
))
265 fprintf (stderr
, "Unhandled util code: %x\n", what
);
270 /* For figuring out whether we carried; addc/subc use this. */
272 iu_carry (unsigned long a
, unsigned long b
, int cin
)
276 x
= (a
& 0xffff) + (b
& 0xffff) + cin
;
277 x
= (x
>> 16) + (a
>> 16) + (b
>> 16);
283 /* TODO: Convert to common watchpoints. */
284 #undef WATCHFUNCTIONS
285 #ifdef WATCHFUNCTIONS
302 #define RD (inst & 0xF)
303 #define RS ((inst >> 4) & 0xF)
304 #define RX ((inst >> 8) & 0xF)
305 #define IMM5 ((inst >> 4) & 0x1F)
306 #define IMM4 ((inst) & 0xF)
308 #define rbat(X) sim_core_read_1 (scpu, 0, read_map, X)
309 #define rhat(X) sim_core_read_2 (scpu, 0, read_map, X)
310 #define rlat(X) sim_core_read_4 (scpu, 0, read_map, X)
311 #define wbat(X, D) sim_core_write_1 (scpu, 0, write_map, X, D)
312 #define what(X, D) sim_core_write_2 (scpu, 0, write_map, X, D)
313 #define wlat(X, D) sim_core_write_4 (scpu, 0, write_map, X, D)
315 static int tracing
= 0;
318 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
320 SIM_CPU
*scpu
= STATE_CPU (sd
, 0);
330 #ifdef WATCHFUNCTIONS
334 cpu
.asregs
.exception
= step
? SIGTRAP
: 0;
335 pc
= CPU_PC_GET (scpu
);
337 /* Fetch the initial instructions that we'll decode. */
338 ibuf
= rlat (pc
& 0xFFFFFFFC);
345 /* make our register set point to the right place */
347 cpu
.asregs
.active_gregs
= & cpu
.asregs
.alt_gregs
[0];
349 cpu
.asregs
.active_gregs
= & cpu
.asregs
.gregs
[0];
351 #ifdef WATCHFUNCTIONS
352 /* make a hash to speed exec loop, hope it's nonzero */
355 for (w
= 1; w
<= ENDWL
; w
++)
356 WLhash
= WLhash
& WL
[w
];
367 if (! target_big_endian
)
370 inst
= ibuf
& 0xFFFF;
375 if (! target_big_endian
)
376 inst
= ibuf
& 0xFFFF;
381 #ifdef WATCHFUNCTIONS
382 /* now scan list of watch addresses, if match, count it and
383 note return address and count cycles until pc=return address */
385 if ((WLincyc
== 1) && (pc
== WLendpc
))
387 cycs
= (cpu
.asregs
.cycles
+ (insts
+ bonus_cycles
+
388 (memops
* memcycles
)) - WLbcyc
);
390 if (WLcnts
[WLW
] == 1)
397 if (cycs
> WLmax
[WLW
])
402 if (cycs
< WLmin
[WLW
])
412 /* Optimize with a hash to speed loop. */
415 if ((WLhash
== 0) || ((WLhash
& pc
) != 0))
417 for (w
=1; w
<= ENDWL
; w
++)
422 WLbcyc
= cpu
.asregs
.cycles
+ insts
423 + bonus_cycles
+ (memops
* memcycles
);
424 WLendpc
= cpu
.gr
[15];
435 fprintf (stderr
, "%.4lx: inst = %.4x ", pc
, inst
);
450 cpu
.asregs
.exception
= SIGTRAP
;
463 cpu
.asregs
.active_gregs
= & cpu
.asregs
.alt_gregs
[0];
465 cpu
.asregs
.active_gregs
= & cpu
.asregs
.gregs
[0];
474 cpu
.asregs
.active_gregs
= &cpu
.asregs
.alt_gregs
[0];
476 cpu
.asregs
.active_gregs
= &cpu
.asregs
.gregs
[0];
480 if (STATE_VERBOSE_P (sd
))
481 fprintf (stderr
, "WARNING: stop unimplemented\n");
485 if (STATE_VERBOSE_P (sd
))
486 fprintf (stderr
, "WARNING: wait unimplemented\n");
490 if (STATE_VERBOSE_P (sd
))
491 fprintf (stderr
, "WARNING: doze unimplemented\n");
495 cpu
.asregs
.exception
= SIGILL
; /* illegal */
498 case 0x8: /* trap 0 */
499 case 0xA: /* trap 2 */
500 case 0xB: /* trap 3 */
501 cpu
.asregs
.exception
= SIGTRAP
;
504 case 0xC: /* trap 4 */
505 case 0xD: /* trap 5 */
506 case 0xE: /* trap 6 */
507 cpu
.asregs
.exception
= SIGILL
; /* illegal */
510 case 0xF: /* trap 7 */
511 cpu
.asregs
.exception
= SIGTRAP
; /* integer div-by-0 */
514 case 0x9: /* trap 1 */
521 cpu
.asregs
.exception
= SIGILL
; /* illegal */
525 cpu
.gr
[RD
] = C_VALUE();
528 cpu
.gr
[RD
] = C_OFF();
532 word addr
= cpu
.gr
[RD
];
533 int regno
= 4; /* always r4-r7 */
539 cpu
.gr
[regno
] = rlat(addr
);
543 while ((regno
&0x3) != 0);
548 word addr
= cpu
.gr
[RD
];
549 int regno
= 4; /* always r4-r7 */
555 wlat(addr
, cpu
.gr
[regno
]);
559 while ((regno
& 0x3) != 0);
564 word addr
= cpu
.gr
[0];
567 /* bonus cycle is really only needed if
568 the next insn shifts the last reg loaded.
575 cpu
.gr
[regno
] = rlat(addr
);
583 word addr
= cpu
.gr
[0];
586 /* this should be removed! */
587 /* bonus_cycles ++; */
589 memops
+= 16 - regno
;
592 wlat(addr
, cpu
.gr
[regno
]);
600 cpu
.gr
[RD
] -= C_VALUE();
603 cpu
.gr
[RD
] -= C_OFF();
606 cpu
.gr
[RD
] += C_VALUE();
609 cpu
.gr
[RD
] += C_OFF();
613 if (tracing
&& RD
== 15)
614 fprintf (stderr
, "Func return, r2 = %lxx, r3 = %lx\n",
615 cpu
.gr
[2], cpu
.gr
[3]);
629 for (i
= 0; !(tmp
& 0x80000000) && i
< 32; i
++)
638 tmp
= ((tmp
& 0xaaaaaaaa) >> 1) | ((tmp
& 0x55555555) << 1);
639 tmp
= ((tmp
& 0xcccccccc) >> 2) | ((tmp
& 0x33333333) << 2);
640 tmp
= ((tmp
& 0xf0f0f0f0) >> 4) | ((tmp
& 0x0f0f0f0f) << 4);
641 tmp
= ((tmp
& 0xff00ff00) >> 8) | ((tmp
& 0x00ff00ff) << 8);
642 cpu
.gr
[RD
] = ((tmp
& 0xffff0000) >> 16) | ((tmp
& 0x0000ffff) << 16);
650 case 0x0: /* xtrb3 */
651 cpu
.gr
[1] = (cpu
.gr
[RD
]) & 0xFF;
652 NEW_C (cpu
.gr
[RD
] != 0);
654 case 0x1: /* xtrb2 */
655 cpu
.gr
[1] = (cpu
.gr
[RD
]>>8) & 0xFF;
656 NEW_C (cpu
.gr
[RD
] != 0);
658 case 0x2: /* xtrb1 */
659 cpu
.gr
[1] = (cpu
.gr
[RD
]>>16) & 0xFF;
660 NEW_C (cpu
.gr
[RD
] != 0);
662 case 0x3: /* xtrb0 */
663 cpu
.gr
[1] = (cpu
.gr
[RD
]>>24) & 0xFF;
664 NEW_C (cpu
.gr
[RD
] != 0);
666 case 0x4: /* zextb */
667 cpu
.gr
[RD
] &= 0x000000FF;
669 case 0x5: /* sextb */
678 case 0x6: /* zexth */
679 cpu
.gr
[RD
] &= 0x0000FFFF;
681 case 0x7: /* sexth */
690 case 0x8: /* declt */
692 NEW_C ((long)cpu
.gr
[RD
] < 0);
694 case 0x9: /* tstnbz */
696 word tmp
= cpu
.gr
[RD
];
697 NEW_C ((tmp
& 0xFF000000) != 0 &&
698 (tmp
& 0x00FF0000) != 0 && (tmp
& 0x0000FF00) != 0 &&
699 (tmp
& 0x000000FF) != 0);
702 case 0xA: /* decgt */
704 NEW_C ((long)cpu
.gr
[RD
] > 0);
706 case 0xB: /* decne */
708 NEW_C ((long)cpu
.gr
[RD
] != 0);
719 if (cpu
.gr
[RD
] & 0x80000000)
720 cpu
.gr
[RD
] = ~cpu
.gr
[RD
] + 1;
723 cpu
.gr
[RD
] = ~cpu
.gr
[RD
];
727 case 0x02: /* movt */
729 cpu
.gr
[RD
] = cpu
.gr
[RS
];
731 case 0x03: /* mult */
732 /* consume 2 bits per cycle from rs, until rs is 0 */
734 unsigned int t
= cpu
.gr
[RS
];
736 for (ticks
= 0; t
!= 0 ; t
>>= 2)
738 bonus_cycles
+= ticks
;
740 bonus_cycles
+= 2; /* min. is 3, so add 2, plus ticks above */
742 fprintf (stderr
, " mult %lx by %lx to give %lx",
743 cpu
.gr
[RD
], cpu
.gr
[RS
], cpu
.gr
[RD
] * cpu
.gr
[RS
]);
744 cpu
.gr
[RD
] = cpu
.gr
[RD
] * cpu
.gr
[RS
];
746 case 0x04: /* loopt */
749 pc
+= (IMM4
<< 1) - 32;
753 --cpu
.gr
[RS
]; /* not RD! */
754 NEW_C (((long)cpu
.gr
[RS
]) > 0);
756 case 0x05: /* subu */
757 cpu
.gr
[RD
] -= cpu
.gr
[RS
];
759 case 0x06: /* addc */
761 unsigned long tmp
, a
, b
;
764 cpu
.gr
[RD
] = a
+ b
+ C_VALUE ();
765 tmp
= iu_carry (a
, b
, C_VALUE ());
769 case 0x07: /* subc */
771 unsigned long tmp
, a
, b
;
774 cpu
.gr
[RD
] = a
- b
+ C_VALUE () - 1;
775 tmp
= iu_carry (a
,~b
, C_VALUE ());
779 case 0x08: /* illegal */
780 case 0x09: /* illegal*/
781 cpu
.asregs
.exception
= SIGILL
;
783 case 0x0A: /* movf */
785 cpu
.gr
[RD
] = cpu
.gr
[RS
];
789 unsigned long dst
, src
;
792 /* We must not rely solely upon the native shift operations, since they
793 may not match the M*Core's behaviour on boundary conditions. */
794 dst
= src
> 31 ? 0 : dst
>> src
;
798 case 0x0C: /* cmphs */
799 NEW_C ((unsigned long )cpu
.gr
[RD
] >=
800 (unsigned long)cpu
.gr
[RS
]);
802 case 0x0D: /* cmplt */
803 NEW_C ((long)cpu
.gr
[RD
] < (long)cpu
.gr
[RS
]);
806 NEW_C ((cpu
.gr
[RD
] & cpu
.gr
[RS
]) != 0);
808 case 0x0F: /* cmpne */
809 NEW_C (cpu
.gr
[RD
] != cpu
.gr
[RS
]);
811 case 0x10: case 0x11: /* mfcr */
815 if (r
<= LAST_VALID_CREG
)
816 cpu
.gr
[RD
] = cpu
.cr
[r
];
818 cpu
.asregs
.exception
= SIGILL
;
823 cpu
.gr
[RD
] = cpu
.gr
[RS
];
825 fprintf (stderr
, "MOV %lx into reg %d", cpu
.gr
[RD
], RD
);
828 case 0x13: /* bgenr */
829 if (cpu
.gr
[RS
] & 0x20)
832 cpu
.gr
[RD
] = 1 << (cpu
.gr
[RS
] & 0x1F);
835 case 0x14: /* rsub */
836 cpu
.gr
[RD
] = cpu
.gr
[RS
] - cpu
.gr
[RD
];
840 cpu
.gr
[RD
] += cpu
.gr
[RS
]<<2;
844 cpu
.gr
[RD
] &= cpu
.gr
[RS
];
848 cpu
.gr
[RD
] ^= cpu
.gr
[RS
];
851 case 0x18: case 0x19: /* mtcr */
855 if (r
<= LAST_VALID_CREG
)
856 cpu
.cr
[r
] = cpu
.gr
[RD
];
858 cpu
.asregs
.exception
= SIGILL
;
860 /* we might have changed register sets... */
862 cpu
.asregs
.active_gregs
= & cpu
.asregs
.alt_gregs
[0];
864 cpu
.asregs
.active_gregs
= & cpu
.asregs
.gregs
[0];
869 /* We must not rely solely upon the native shift operations, since they
870 may not match the M*Core's behaviour on boundary conditions. */
872 cpu
.gr
[RD
] = ((long) cpu
.gr
[RD
]) < 0 ? -1 : 0;
874 cpu
.gr
[RD
] = (long) cpu
.gr
[RD
] >> cpu
.gr
[RS
];
878 /* We must not rely solely upon the native shift operations, since they
879 may not match the M*Core's behaviour on boundary conditions. */
880 cpu
.gr
[RD
] = cpu
.gr
[RS
] > 31 ? 0 : cpu
.gr
[RD
] << cpu
.gr
[RS
];
883 case 0x1C: /* addu */
884 cpu
.gr
[RD
] += cpu
.gr
[RS
];
888 cpu
.gr
[RD
] += cpu
.gr
[RS
] << 1;
892 cpu
.gr
[RD
] |= cpu
.gr
[RS
];
895 case 0x1F: /* andn */
896 cpu
.gr
[RD
] &= ~cpu
.gr
[RS
];
898 case 0x20: case 0x21: /* addi */
900 cpu
.gr
[RD
] + (IMM5
+ 1);
902 case 0x22: case 0x23: /* cmplti */
904 int tmp
= (IMM5
+ 1);
905 if (cpu
.gr
[RD
] < tmp
)
915 case 0x24: case 0x25: /* subi */
917 cpu
.gr
[RD
] - (IMM5
+ 1);
919 case 0x26: case 0x27: /* illegal */
920 cpu
.asregs
.exception
= SIGILL
;
922 case 0x28: case 0x29: /* rsubi */
926 case 0x2A: case 0x2B: /* cmpnei */
927 if (cpu
.gr
[RD
] != IMM5
)
937 case 0x2C: case 0x2D: /* bmaski, divu */
951 /* unsigned divide */
952 cpu
.gr
[RD
] = (word
) ((unsigned int) cpu
.gr
[RD
] / (unsigned int)cpu
.gr
[1] );
954 /* compute bonus_cycles for divu */
955 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32); r1nlz
++)
958 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32); rxnlz
++)
964 exe
+= 5 + r1nlz
- rxnlz
;
966 if (exe
>= (2 * memcycles
- 1))
968 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
971 else if (imm
== 0 || imm
>= 8)
977 cpu
.gr
[RD
] = (1 << imm
) - 1;
982 cpu
.asregs
.exception
= SIGILL
;
986 case 0x2E: case 0x2F: /* andi */
987 cpu
.gr
[RD
] = cpu
.gr
[RD
] & IMM5
;
989 case 0x30: case 0x31: /* bclri */
990 cpu
.gr
[RD
] = cpu
.gr
[RD
] & ~(1<<IMM5
);
992 case 0x32: case 0x33: /* bgeni, divs */
1001 /* compute bonus_cycles for divu */
1006 if (((rx
< 0) && (r1
> 0)) || ((rx
>= 0) && (r1
< 0)))
1014 /* signed divide, general registers are of type int, so / op is OK */
1015 cpu
.gr
[RD
] = cpu
.gr
[RD
] / cpu
.gr
[1];
1017 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32) ; r1nlz
++ )
1020 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32) ; rxnlz
++ )
1026 exe
+= 6 + r1nlz
- rxnlz
+ sc
;
1028 if (exe
>= (2 * memcycles
- 1))
1030 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
1036 cpu
.gr
[RD
] = (1 << IMM5
);
1041 cpu
.asregs
.exception
= SIGILL
;
1045 case 0x34: case 0x35: /* bseti */
1046 cpu
.gr
[RD
] = cpu
.gr
[RD
] | (1 << IMM5
);
1048 case 0x36: case 0x37: /* btsti */
1049 NEW_C (cpu
.gr
[RD
] >> IMM5
);
1051 case 0x38: case 0x39: /* xsr, rotli */
1053 unsigned imm
= IMM5
;
1054 unsigned long tmp
= cpu
.gr
[RD
];
1060 cpu
.gr
[RD
] = (cbit
<< 31) | (tmp
>> 1);
1063 cpu
.gr
[RD
] = (tmp
<< imm
) | (tmp
>> (32 - imm
));
1066 case 0x3A: case 0x3B: /* asrc, asri */
1068 unsigned imm
= IMM5
;
1069 long tmp
= cpu
.gr
[RD
];
1073 cpu
.gr
[RD
] = tmp
>> 1;
1076 cpu
.gr
[RD
] = tmp
>> imm
;
1079 case 0x3C: case 0x3D: /* lslc, lsli */
1081 unsigned imm
= IMM5
;
1082 unsigned long tmp
= cpu
.gr
[RD
];
1086 cpu
.gr
[RD
] = tmp
<< 1;
1089 cpu
.gr
[RD
] = tmp
<< imm
;
1092 case 0x3E: case 0x3F: /* lsrc, lsri */
1094 unsigned imm
= IMM5
;
1095 unsigned long tmp
= cpu
.gr
[RD
];
1099 cpu
.gr
[RD
] = tmp
>> 1;
1102 cpu
.gr
[RD
] = tmp
>> imm
;
1105 case 0x40: case 0x41: case 0x42: case 0x43:
1106 case 0x44: case 0x45: case 0x46: case 0x47:
1107 case 0x48: case 0x49: case 0x4A: case 0x4B:
1108 case 0x4C: case 0x4D: case 0x4E: case 0x4F:
1109 cpu
.asregs
.exception
= SIGILL
;
1112 util (sd
, inst
& 0xFF);
1114 case 0x51: case 0x52: case 0x53:
1115 case 0x54: case 0x55: case 0x56: case 0x57:
1116 case 0x58: case 0x59: case 0x5A: case 0x5B:
1117 case 0x5C: case 0x5D: case 0x5E: case 0x5F:
1118 cpu
.asregs
.exception
= SIGILL
;
1120 case 0x60: case 0x61: case 0x62: case 0x63: /* movi */
1121 case 0x64: case 0x65: case 0x66: case 0x67:
1122 cpu
.gr
[RD
] = (inst
>> 4) & 0x7F;
1124 case 0x68: case 0x69: case 0x6A: case 0x6B:
1125 case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */
1126 cpu
.asregs
.exception
= SIGILL
;
1128 case 0x71: case 0x72: case 0x73:
1129 case 0x74: case 0x75: case 0x76: case 0x77:
1130 case 0x78: case 0x79: case 0x7A: case 0x7B:
1131 case 0x7C: case 0x7D: case 0x7E: /* lrw */
1132 cpu
.gr
[RX
] = rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1134 fprintf (stderr
, "LRW of 0x%x from 0x%lx to reg %d",
1135 rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC),
1136 (pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC, RX
);
1139 case 0x7F: /* jsri */
1143 "func call: r2 = %lx r3 = %lx r4 = %lx r5 = %lx r6 = %lx r7 = %lx\n",
1144 cpu
.gr
[2], cpu
.gr
[3], cpu
.gr
[4], cpu
.gr
[5], cpu
.gr
[6], cpu
.gr
[7]);
1145 case 0x70: /* jmpi */
1146 pc
= rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1152 case 0x80: case 0x81: case 0x82: case 0x83:
1153 case 0x84: case 0x85: case 0x86: case 0x87:
1154 case 0x88: case 0x89: case 0x8A: case 0x8B:
1155 case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */
1156 cpu
.gr
[RX
] = rlat (cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C));
1158 fprintf (stderr
, "load reg %d from 0x%lx with 0x%lx",
1160 cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C), cpu
.gr
[RX
]);
1163 case 0x90: case 0x91: case 0x92: case 0x93:
1164 case 0x94: case 0x95: case 0x96: case 0x97:
1165 case 0x98: case 0x99: case 0x9A: case 0x9B:
1166 case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */
1167 wlat (cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C), cpu
.gr
[RX
]);
1169 fprintf (stderr
, "store reg %d (containing 0x%lx) to 0x%lx",
1171 cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C));
1174 case 0xA0: case 0xA1: case 0xA2: case 0xA3:
1175 case 0xA4: case 0xA5: case 0xA6: case 0xA7:
1176 case 0xA8: case 0xA9: case 0xAA: case 0xAB:
1177 case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */
1178 cpu
.gr
[RX
] = rbat (cpu
.gr
[RD
] + RS
);
1181 case 0xB0: case 0xB1: case 0xB2: case 0xB3:
1182 case 0xB4: case 0xB5: case 0xB6: case 0xB7:
1183 case 0xB8: case 0xB9: case 0xBA: case 0xBB:
1184 case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */
1185 wbat (cpu
.gr
[RD
] + RS
, cpu
.gr
[RX
]);
1188 case 0xC0: case 0xC1: case 0xC2: case 0xC3:
1189 case 0xC4: case 0xC5: case 0xC6: case 0xC7:
1190 case 0xC8: case 0xC9: case 0xCA: case 0xCB:
1191 case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */
1192 cpu
.gr
[RX
] = rhat (cpu
.gr
[RD
] + ((inst
>> 3) & 0x001E));
1195 case 0xD0: case 0xD1: case 0xD2: case 0xD3:
1196 case 0xD4: case 0xD5: case 0xD6: case 0xD7:
1197 case 0xD8: case 0xD9: case 0xDA: case 0xDB:
1198 case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */
1199 what (cpu
.gr
[RD
] + ((inst
>> 3) & 0x001E), cpu
.gr
[RX
]);
1202 case 0xE8: case 0xE9: case 0xEA: case 0xEB:
1203 case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */
1207 disp
= inst
& 0x03FF;
1215 case 0xE0: case 0xE1: case 0xE2: case 0xE3:
1216 case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */
1220 disp
= inst
& 0x03FF;
1229 case 0xF8: case 0xF9: case 0xFA: case 0xFB:
1230 case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */
1232 case 0xF0: case 0xF1: case 0xF2: case 0xF3:
1233 case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */
1236 disp
= inst
& 0x03FF;
1248 fprintf (stderr
, "\n");
1252 ibuf
= rlat (pc
& 0xFFFFFFFC);
1256 while (!cpu
.asregs
.exception
);
1258 /* Hide away the things we've cached while executing. */
1259 CPU_PC_SET (scpu
, pc
);
1260 cpu
.asregs
.insts
+= insts
; /* instructions done ... */
1261 cpu
.asregs
.cycles
+= insts
; /* and each takes a cycle */
1262 cpu
.asregs
.cycles
+= bonus_cycles
; /* and extra cycles for branches */
1263 cpu
.asregs
.cycles
+= memops
* memcycles
; /* and memop cycle delays */
1267 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1269 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1275 /* misalignment safe */
1276 ival
= mcore_extract_unsigned_integer (memory
, 4);
1277 cpu
.asints
[rn
] = ival
;
1287 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1289 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1293 long ival
= cpu
.asints
[rn
];
1295 /* misalignment-safe */
1296 mcore_store_unsigned_integer (memory
, 4, ival
);
1306 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
1308 if (cpu
.asregs
.exception
== SIGQUIT
)
1310 * reason
= sim_exited
;
1311 * sigrc
= cpu
.gr
[PARM1
];
1315 * reason
= sim_stopped
;
1316 * sigrc
= cpu
.asregs
.exception
;
1321 sim_info (SIM_DESC sd
, int verbose
)
1323 #ifdef WATCHFUNCTIONS
1326 double virttime
= cpu
.asregs
.cycles
/ 36.0e6
;
1327 host_callback
*callback
= STATE_CALLBACK (sd
);
1329 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
1331 callback
->printf_filtered (callback
, "# cycles %10d\n",
1333 callback
->printf_filtered (callback
, "# pipeline stalls %10d\n",
1335 callback
->printf_filtered (callback
, "# virtual time taken %10.4f\n",
1338 #ifdef WATCHFUNCTIONS
1339 callback
->printf_filtered (callback
, "\nNumber of watched functions: %d\n",
1344 for (w
= 1; w
<= ENDWL
; w
++)
1346 callback
->printf_filtered (callback
, "WL = %s %8x\n",WLstr
[w
],WL
[w
]);
1347 callback
->printf_filtered (callback
, " calls = %d, cycles = %d\n",
1348 WLcnts
[w
],WLcyc
[w
]);
1351 callback
->printf_filtered (callback
,
1352 " maxcpc = %d, mincpc = %d, avecpc = %d\n",
1353 WLmax
[w
],WLmin
[w
],WLcyc
[w
]/WLcnts
[w
]);
1357 callback
->printf_filtered (callback
,
1358 "Total cycles for watched functions: %d\n",wcyc
);
1363 mcore_pc_get (sim_cpu
*cpu
)
1369 mcore_pc_set (sim_cpu
*cpu
, sim_cia pc
)
1375 free_state (SIM_DESC sd
)
1377 if (STATE_MODULES (sd
) != NULL
)
1378 sim_module_uninstall (sd
);
1379 sim_cpu_free_all (sd
);
1380 sim_state_free (sd
);
1384 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
, struct bfd
*abfd
, char **argv
)
1387 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
1388 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1390 /* The cpu data is kept in a separately allocated chunk of memory. */
1391 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
1397 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
1403 /* getopt will print the error message so we just have to exit if this fails.
1404 FIXME: Hmmm... in the case of gdb we need getopt to call
1406 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
1412 /* Check for/establish the a reference program image. */
1413 if (sim_analyze_program (sd
,
1414 (STATE_PROG_ARGV (sd
) != NULL
1415 ? *STATE_PROG_ARGV (sd
)
1416 : NULL
), abfd
) != SIM_RC_OK
)
1422 /* Configure/verify the target byte order and other runtime
1423 configuration options. */
1424 if (sim_config (sd
) != SIM_RC_OK
)
1426 sim_module_uninstall (sd
);
1430 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
1432 /* Uninstall the modules to avoid memory leaks,
1433 file descriptor leaks, etc. */
1434 sim_module_uninstall (sd
);
1438 /* CPU specific initialization. */
1439 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
1441 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
1443 CPU_PC_FETCH (cpu
) = mcore_pc_get
;
1444 CPU_PC_STORE (cpu
) = mcore_pc_set
;
1446 set_initial_gprs (cpu
); /* Reset the GPR registers. */
1449 /* Default to a 8 Mbyte (== 2^23) memory space. */
1450 sim_do_commandf (sd
, "memory-size %#x", DEFAULT_MEMORY_SIZE
);
1456 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
, char **argv
, char **env
)
1458 SIM_CPU
*scpu
= STATE_CPU (sd
, 0);
1464 unsigned long strings
;
1465 unsigned long pointers
;
1466 unsigned long hi_stack
;
1469 /* Set the initial register set. */
1470 set_initial_gprs (scpu
);
1472 hi_stack
= DEFAULT_MEMORY_SIZE
- 4;
1473 CPU_PC_SET (scpu
, bfd_get_start_address (prog_bfd
));
1475 /* Calculate the argument and environment strings. */
1481 l
= strlen (*avp
) + 1; /* include the null */
1482 s_length
+= (l
+ 3) & ~3; /* make it a 4 byte boundary */
1490 l
= strlen (*avp
) + 1; /* include the null */
1491 s_length
+= (l
+ 3) & ~ 3;/* make it a 4 byte boundary */
1495 /* Claim some memory for the pointers and strings. */
1496 pointers
= hi_stack
- sizeof(word
) * (nenv
+1+nargs
+1);
1497 pointers
&= ~3; /* must be 4-byte aligned */
1498 cpu
.gr
[0] = pointers
;
1500 strings
= cpu
.gr
[0] - s_length
;
1501 strings
&= ~3; /* want to make it 4-byte aligned */
1502 cpu
.gr
[0] = strings
;
1503 /* dac fix, the stack address must be 8-byte aligned! */
1504 cpu
.gr
[0] = cpu
.gr
[0] - cpu
.gr
[0] % 8;
1506 /* Loop through the arguments and fill them in. */
1507 cpu
.gr
[PARM1
] = nargs
;
1510 /* No strings to fill in. */
1515 cpu
.gr
[PARM2
] = pointers
;
1519 /* Save where we're putting it. */
1520 wlat (pointers
, strings
);
1522 /* Copy the string. */
1523 l
= strlen (* avp
) + 1;
1524 sim_core_write_buffer (sd
, scpu
, write_map
, *avp
, strings
, l
);
1526 /* Bump the pointers. */
1532 /* A null to finish the list. */
1537 /* Now do the environment pointers. */
1540 /* No strings to fill in. */
1545 cpu
.gr
[PARM3
] = pointers
;
1550 /* Save where we're putting it. */
1551 wlat (pointers
, strings
);
1553 /* Copy the string. */
1554 l
= strlen (* avp
) + 1;
1555 sim_core_write_buffer (sd
, scpu
, write_map
, *avp
, strings
, l
);
1557 /* Bump the pointers. */
1563 /* A null to finish the list. */
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