b7810d20e18a8f3e0761e4d37a18e6a65788f314
1 /* Simulator for Motorola's MCore processor
2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include <sys/times.h>
25 #include <sys/param.h>
28 #include "gdb/callback.h"
29 #include "libiberty.h"
30 #include "gdb/remote-sim.h"
34 #include "sim-options.h"
36 #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
40 mcore_extract_unsigned_integer (unsigned char *addr
, int len
)
44 unsigned char * startaddr
= (unsigned char *)addr
;
45 unsigned char * endaddr
= startaddr
+ len
;
47 if (len
> (int) sizeof (unsigned long))
48 printf ("That operation is not available on integers of more than %zu bytes.",
49 sizeof (unsigned long));
51 /* Start at the most significant end of the integer, and work towards
52 the least significant. */
55 if (! target_big_endian
)
57 for (p
= endaddr
; p
> startaddr
;)
58 retval
= (retval
<< 8) | * -- p
;
62 for (p
= startaddr
; p
< endaddr
;)
63 retval
= (retval
<< 8) | * p
++;
70 mcore_store_unsigned_integer (unsigned char *addr
, int len
, unsigned long val
)
73 unsigned char * startaddr
= (unsigned char *)addr
;
74 unsigned char * endaddr
= startaddr
+ len
;
76 if (! target_big_endian
)
78 for (p
= startaddr
; p
< endaddr
;)
86 for (p
= endaddr
; p
> startaddr
;)
95 This state is maintained in host byte order. The
96 fetch/store register functions must translate between host
97 byte order and the target processor byte order.
98 Keeping this data in target byte order simplifies the register
99 read/write functions. Keeping this data in native order improves
100 the performance of the simulator. Simulation speed is deemed more
102 /* TODO: Should be moved to sim-main.h:sim_cpu. */
104 /* The ordering of the mcore_regset structure is matched in the
105 gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
108 word gregs
[16]; /* primary registers */
109 word alt_gregs
[16]; /* alt register file */
110 word cregs
[32]; /* control registers */
117 unsigned char * memory
;
123 struct mcore_regset asregs
;
124 word asints
[1]; /* but accessed larger... */
127 #define LAST_VALID_CREG 32 /* only 0..12 implemented */
128 #define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
130 static int memcycles
= 1;
132 static int issue_messages
= 0;
134 #define gr asregs.active_gregs
135 #define cr asregs.cregs
136 #define sr asregs.cregs[0]
137 #define vbr asregs.cregs[1]
138 #define esr asregs.cregs[2]
139 #define fsr asregs.cregs[3]
140 #define epc asregs.cregs[4]
141 #define fpc asregs.cregs[5]
142 #define ss0 asregs.cregs[6]
143 #define ss1 asregs.cregs[7]
144 #define ss2 asregs.cregs[8]
145 #define ss3 asregs.cregs[9]
146 #define ss4 asregs.cregs[10]
147 #define gcr asregs.cregs[11]
148 #define gsr asregs.cregs[12]
149 #define mem asregs.memory
151 /* maniuplate the carry bit */
152 #define C_ON() (cpu.sr & 1)
153 #define C_VALUE() (cpu.sr & 1)
154 #define C_OFF() ((cpu.sr & 1) == 0)
155 #define SET_C() {cpu.sr |= 1;}
156 #define CLR_C() {cpu.sr &= 0xfffffffe;}
157 #define NEW_C(v) {CLR_C(); cpu.sr |= ((v) & 1);}
159 #define SR_AF() ((cpu.sr >> 1) & 1)
161 #define TRAPCODE 1 /* r1 holds which function we want */
162 #define PARM1 2 /* first parameter */
166 #define RET1 2 /* register for return values. */
169 wbat (word x
, word v
)
171 if (((uword
)x
) >= cpu
.asregs
.msize
)
174 fprintf (stderr
, "byte write to 0x%x outside memory range\n", x
);
176 cpu
.asregs
.exception
= SIGSEGV
;
180 unsigned char *p
= cpu
.mem
+ x
;
186 wlat (word x
, word v
)
188 if (((uword
)x
) >= cpu
.asregs
.msize
)
191 fprintf (stderr
, "word write to 0x%x outside memory range\n", x
);
193 cpu
.asregs
.exception
= SIGSEGV
;
200 fprintf (stderr
, "word write to unaligned memory address: 0x%x\n", x
);
202 cpu
.asregs
.exception
= SIGBUS
;
204 else if (! target_big_endian
)
206 unsigned char * p
= cpu
.mem
+ x
;
214 unsigned char * p
= cpu
.mem
+ x
;
224 what (word x
, word v
)
226 if (((uword
)x
) >= cpu
.asregs
.msize
)
229 fprintf (stderr
, "short write to 0x%x outside memory range\n", x
);
231 cpu
.asregs
.exception
= SIGSEGV
;
238 fprintf (stderr
, "short write to unaligned memory address: 0x%x\n",
241 cpu
.asregs
.exception
= SIGBUS
;
243 else if (! target_big_endian
)
245 unsigned char * p
= cpu
.mem
+ x
;
251 unsigned char * p
= cpu
.mem
+ x
;
258 /* Read functions. */
262 if (((uword
)x
) >= cpu
.asregs
.msize
)
265 fprintf (stderr
, "byte read from 0x%x outside memory range\n", x
);
267 cpu
.asregs
.exception
= SIGSEGV
;
272 unsigned char * p
= cpu
.mem
+ x
;
280 if (((uword
) x
) >= cpu
.asregs
.msize
)
283 fprintf (stderr
, "word read from 0x%x outside memory range\n", x
);
285 cpu
.asregs
.exception
= SIGSEGV
;
293 fprintf (stderr
, "word read from unaligned address: 0x%x\n", x
);
295 cpu
.asregs
.exception
= SIGBUS
;
298 else if (! target_big_endian
)
300 unsigned char * p
= cpu
.mem
+ x
;
301 return (p
[3] << 24) | (p
[2] << 16) | (p
[1] << 8) | p
[0];
305 unsigned char * p
= cpu
.mem
+ x
;
306 return (p
[0] << 24) | (p
[1] << 16) | (p
[2] << 8) | p
[3];
314 if (((uword
)x
) >= cpu
.asregs
.msize
)
317 fprintf (stderr
, "short read from 0x%x outside memory range\n", x
);
319 cpu
.asregs
.exception
= SIGSEGV
;
327 fprintf (stderr
, "short read from unaligned address: 0x%x\n", x
);
329 cpu
.asregs
.exception
= SIGBUS
;
332 else if (! target_big_endian
)
334 unsigned char * p
= cpu
.mem
+ x
;
335 return (p
[1] << 8) | p
[0];
339 unsigned char * p
= cpu
.mem
+ x
;
340 return (p
[0] << 8) | p
[1];
346 /* Default to a 8 Mbyte (== 2^23) memory space. */
347 /* TODO: Delete all this custom memory logic and move to common sim helpers. */
348 static int sim_memory_size
= 23;
350 #define MEM_SIZE_FLOOR 64
354 sim_memory_size
= power
;
355 cpu
.asregs
.msize
= 1 << sim_memory_size
;
360 /* Watch out for the '0 count' problem. There's probably a better
361 way.. e.g., why do we use 64 here? */
362 if (cpu
.asregs
.msize
< 64) /* Ensure a boundary. */
363 cpu
.mem
= (unsigned char *) calloc (64, (64 + cpu
.asregs
.msize
) / 64);
365 cpu
.mem
= (unsigned char *) calloc (64, cpu
.asregs
.msize
/ 64);
371 "Not enough VM for simulation of %lu bytes of RAM\n",
374 cpu
.asregs
.msize
= 1;
375 cpu
.mem
= (unsigned char *) calloc (1, 1);
382 if (cpu
.asregs
.msize
!= (1 << sim_memory_size
))
383 sim_size (sim_memory_size
);
387 set_initial_gprs (SIM_CPU
*scpu
)
391 unsigned long memsize
;
395 /* Set up machine just out of reset. */
396 CPU_PC_SET (scpu
, 0);
399 memsize
= cpu
.asregs
.msize
/ (1024 * 1024);
401 if (issue_messages
> 1)
402 fprintf (stderr
, "Simulated memory of %lu Mbytes (0x0 .. 0x%08lx)\n",
403 memsize
, cpu
.asregs
.msize
- 1);
405 /* Clean out the GPRs and alternate GPRs. */
406 for (i
= 0; i
< 16; i
++)
408 cpu
.asregs
.gregs
[i
] = 0;
409 cpu
.asregs
.alt_gregs
[i
] = 0;
412 /* Make our register set point to the right place. */
414 cpu
.asregs
.active_gregs
= &cpu
.asregs
.alt_gregs
[0];
416 cpu
.asregs
.active_gregs
= &cpu
.asregs
.gregs
[0];
418 /* ABI specifies initial values for these registers. */
419 cpu
.gr
[0] = cpu
.asregs
.msize
- 4;
421 /* dac fix, the stack address must be 8-byte aligned! */
422 cpu
.gr
[0] = cpu
.gr
[0] - cpu
.gr
[0] % 8;
426 cpu
.gr
[PARM4
] = cpu
.gr
[0];
429 /* Read/write functions for system call interface. */
432 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
433 unsigned long taddr
, char *buf
, int bytes
)
435 memcpy (buf
, cpu
.mem
+ taddr
, bytes
);
440 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
441 unsigned long taddr
, const char *buf
, int bytes
)
443 memcpy (cpu
.mem
+ taddr
, buf
, bytes
);
447 /* Simulate a monitor trap. */
450 handle_trap1 (SIM_DESC sd
)
452 host_callback
*cb
= STATE_CALLBACK (sd
);
455 CB_SYSCALL_INIT (&sc
);
457 sc
.func
= cpu
.gr
[TRAPCODE
];
458 sc
.arg1
= cpu
.gr
[PARM1
];
459 sc
.arg2
= cpu
.gr
[PARM2
];
460 sc
.arg3
= cpu
.gr
[PARM3
];
461 sc
.arg4
= cpu
.gr
[PARM4
];
464 sc
.p2
= (PTR
) STATE_CPU (sd
, 0);
465 sc
.read_mem
= syscall_read_mem
;
466 sc
.write_mem
= syscall_write_mem
;
468 cb_syscall (cb
, &sc
);
470 /* XXX: We don't pass back the actual errno value. */
471 cpu
.gr
[RET1
] = sc
.result
;
475 process_stub (SIM_DESC sd
, int what
)
477 /* These values should match those in libgloss/mcore/syscalls.s. */
484 case 10: /* _unlink */
485 case 19: /* _lseek */
486 case 43: /* _times */
487 cpu
.gr
[TRAPCODE
] = what
;
493 fprintf (stderr
, "Unhandled stub opcode: %d\n", what
);
499 util (SIM_DESC sd
, unsigned what
)
504 cpu
.asregs
.exception
= SIGQUIT
;
513 a
[0] = (unsigned long)(cpu
.mem
+ cpu
.gr
[PARM1
]);
515 for (s
= (unsigned char *)a
[0], i
= 1 ; *s
&& i
< 6 ; s
++)
520 a
[i
] = (unsigned long)(cpu
.mem
+ cpu
.gr
[PARM1
+i
]);
522 a
[i
] = cpu
.gr
[i
+PARM1
];
527 cpu
.gr
[RET1
] = printf ((char *)a
[0], a
[1], a
[2], a
[3], a
[4], a
[5]);
533 fprintf (stderr
, "WARNING: scanf unimplemented\n");
537 cpu
.gr
[RET1
] = cpu
.asregs
.insts
;
541 process_stub (sd
, cpu
.gr
[1]);
546 fprintf (stderr
, "Unhandled util code: %x\n", what
);
551 /* For figuring out whether we carried; addc/subc use this. */
553 iu_carry (unsigned long a
, unsigned long b
, int cin
)
557 x
= (a
& 0xffff) + (b
& 0xffff) + cin
;
558 x
= (x
>> 16) + (a
>> 16) + (b
>> 16);
564 #define WATCHFUNCTIONS 1
565 #ifdef WATCHFUNCTIONS
582 #define RD (inst & 0xF)
583 #define RS ((inst >> 4) & 0xF)
584 #define RX ((inst >> 8) & 0xF)
585 #define IMM5 ((inst >> 4) & 0x1F)
586 #define IMM4 ((inst) & 0xF)
588 static int tracing
= 0;
591 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
593 SIM_CPU
*scpu
= STATE_CPU (sd
, 0);
605 cpu
.asregs
.exception
= step
? SIGTRAP
: 0;
606 pc
= CPU_PC_GET (scpu
);
608 /* Fetch the initial instructions that we'll decode. */
609 ibuf
= rlat (pc
& 0xFFFFFFFC);
616 /* make our register set point to the right place */
618 cpu
.asregs
.active_gregs
= & cpu
.asregs
.alt_gregs
[0];
620 cpu
.asregs
.active_gregs
= & cpu
.asregs
.gregs
[0];
622 /* make a hash to speed exec loop, hope it's nonzero */
625 for (w
= 1; w
<= ENDWL
; w
++)
626 WLhash
= WLhash
& WL
[w
];
636 if (! target_big_endian
)
639 inst
= ibuf
& 0xFFFF;
644 if (! target_big_endian
)
645 inst
= ibuf
& 0xFFFF;
650 #ifdef WATCHFUNCTIONS
651 /* now scan list of watch addresses, if match, count it and
652 note return address and count cycles until pc=return address */
654 if ((WLincyc
== 1) && (pc
== WLendpc
))
656 cycs
= (cpu
.asregs
.cycles
+ (insts
+ bonus_cycles
+
657 (memops
* memcycles
)) - WLbcyc
);
659 if (WLcnts
[WLW
] == 1)
666 if (cycs
> WLmax
[WLW
])
671 if (cycs
< WLmin
[WLW
])
681 /* Optimize with a hash to speed loop. */
684 if ((WLhash
== 0) || ((WLhash
& pc
) != 0))
686 for (w
=1; w
<= ENDWL
; w
++)
691 WLbcyc
= cpu
.asregs
.cycles
+ insts
692 + bonus_cycles
+ (memops
* memcycles
);
693 WLendpc
= cpu
.gr
[15];
704 fprintf (stderr
, "%.4x: inst = %.4x ", pc
, inst
);
719 cpu
.asregs
.exception
= SIGTRAP
;
732 cpu
.asregs
.active_gregs
= & cpu
.asregs
.alt_gregs
[0];
734 cpu
.asregs
.active_gregs
= & cpu
.asregs
.gregs
[0];
743 cpu
.asregs
.active_gregs
= &cpu
.asregs
.alt_gregs
[0];
745 cpu
.asregs
.active_gregs
= &cpu
.asregs
.gregs
[0];
750 fprintf (stderr
, "WARNING: stop unimplemented\n");
755 fprintf (stderr
, "WARNING: wait unimplemented\n");
760 fprintf (stderr
, "WARNING: doze unimplemented\n");
764 cpu
.asregs
.exception
= SIGILL
; /* illegal */
767 case 0x8: /* trap 0 */
768 case 0xA: /* trap 2 */
769 case 0xB: /* trap 3 */
770 cpu
.asregs
.exception
= SIGTRAP
;
773 case 0xC: /* trap 4 */
774 case 0xD: /* trap 5 */
775 case 0xE: /* trap 6 */
776 cpu
.asregs
.exception
= SIGILL
; /* illegal */
779 case 0xF: /* trap 7 */
780 cpu
.asregs
.exception
= SIGTRAP
; /* integer div-by-0 */
783 case 0x9: /* trap 1 */
790 cpu
.asregs
.exception
= SIGILL
; /* illegal */
794 cpu
.gr
[RD
] = C_VALUE();
797 cpu
.gr
[RD
] = C_OFF();
801 word addr
= cpu
.gr
[RD
];
802 int regno
= 4; /* always r4-r7 */
808 cpu
.gr
[regno
] = rlat(addr
);
812 while ((regno
&0x3) != 0);
817 word addr
= cpu
.gr
[RD
];
818 int regno
= 4; /* always r4-r7 */
824 wlat(addr
, cpu
.gr
[regno
]);
828 while ((regno
& 0x3) != 0);
833 word addr
= cpu
.gr
[0];
836 /* bonus cycle is really only needed if
837 the next insn shifts the last reg loaded.
844 cpu
.gr
[regno
] = rlat(addr
);
852 word addr
= cpu
.gr
[0];
855 /* this should be removed! */
856 /* bonus_cycles ++; */
858 memops
+= 16 - regno
;
861 wlat(addr
, cpu
.gr
[regno
]);
869 cpu
.gr
[RD
] -= C_VALUE();
872 cpu
.gr
[RD
] -= C_OFF();
875 cpu
.gr
[RD
] += C_VALUE();
878 cpu
.gr
[RD
] += C_OFF();
882 if (tracing
&& RD
== 15)
883 fprintf (stderr
, "Func return, r2 = %x, r3 = %x\n",
884 cpu
.gr
[2], cpu
.gr
[3]);
898 for (i
= 0; !(tmp
& 0x80000000) && i
< 32; i
++)
907 tmp
= ((tmp
& 0xaaaaaaaa) >> 1) | ((tmp
& 0x55555555) << 1);
908 tmp
= ((tmp
& 0xcccccccc) >> 2) | ((tmp
& 0x33333333) << 2);
909 tmp
= ((tmp
& 0xf0f0f0f0) >> 4) | ((tmp
& 0x0f0f0f0f) << 4);
910 tmp
= ((tmp
& 0xff00ff00) >> 8) | ((tmp
& 0x00ff00ff) << 8);
911 cpu
.gr
[RD
] = ((tmp
& 0xffff0000) >> 16) | ((tmp
& 0x0000ffff) << 16);
919 case 0x0: /* xtrb3 */
920 cpu
.gr
[1] = (cpu
.gr
[RD
]) & 0xFF;
921 NEW_C (cpu
.gr
[RD
] != 0);
923 case 0x1: /* xtrb2 */
924 cpu
.gr
[1] = (cpu
.gr
[RD
]>>8) & 0xFF;
925 NEW_C (cpu
.gr
[RD
] != 0);
927 case 0x2: /* xtrb1 */
928 cpu
.gr
[1] = (cpu
.gr
[RD
]>>16) & 0xFF;
929 NEW_C (cpu
.gr
[RD
] != 0);
931 case 0x3: /* xtrb0 */
932 cpu
.gr
[1] = (cpu
.gr
[RD
]>>24) & 0xFF;
933 NEW_C (cpu
.gr
[RD
] != 0);
935 case 0x4: /* zextb */
936 cpu
.gr
[RD
] &= 0x000000FF;
938 case 0x5: /* sextb */
947 case 0x6: /* zexth */
948 cpu
.gr
[RD
] &= 0x0000FFFF;
950 case 0x7: /* sexth */
959 case 0x8: /* declt */
961 NEW_C ((long)cpu
.gr
[RD
] < 0);
963 case 0x9: /* tstnbz */
965 word tmp
= cpu
.gr
[RD
];
966 NEW_C ((tmp
& 0xFF000000) != 0 &&
967 (tmp
& 0x00FF0000) != 0 && (tmp
& 0x0000FF00) != 0 &&
968 (tmp
& 0x000000FF) != 0);
971 case 0xA: /* decgt */
973 NEW_C ((long)cpu
.gr
[RD
] > 0);
975 case 0xB: /* decne */
977 NEW_C ((long)cpu
.gr
[RD
] != 0);
988 if (cpu
.gr
[RD
] & 0x80000000)
989 cpu
.gr
[RD
] = ~cpu
.gr
[RD
] + 1;
992 cpu
.gr
[RD
] = ~cpu
.gr
[RD
];
996 case 0x02: /* movt */
998 cpu
.gr
[RD
] = cpu
.gr
[RS
];
1000 case 0x03: /* mult */
1001 /* consume 2 bits per cycle from rs, until rs is 0 */
1003 unsigned int t
= cpu
.gr
[RS
];
1005 for (ticks
= 0; t
!= 0 ; t
>>= 2)
1007 bonus_cycles
+= ticks
;
1009 bonus_cycles
+= 2; /* min. is 3, so add 2, plus ticks above */
1011 fprintf (stderr
, " mult %x by %x to give %x",
1012 cpu
.gr
[RD
], cpu
.gr
[RS
], cpu
.gr
[RD
] * cpu
.gr
[RS
]);
1013 cpu
.gr
[RD
] = cpu
.gr
[RD
] * cpu
.gr
[RS
];
1015 case 0x04: /* loopt */
1018 pc
+= (IMM4
<< 1) - 32;
1022 --cpu
.gr
[RS
]; /* not RD! */
1023 NEW_C (((long)cpu
.gr
[RS
]) > 0);
1025 case 0x05: /* subu */
1026 cpu
.gr
[RD
] -= cpu
.gr
[RS
];
1028 case 0x06: /* addc */
1030 unsigned long tmp
, a
, b
;
1033 cpu
.gr
[RD
] = a
+ b
+ C_VALUE ();
1034 tmp
= iu_carry (a
, b
, C_VALUE ());
1038 case 0x07: /* subc */
1040 unsigned long tmp
, a
, b
;
1043 cpu
.gr
[RD
] = a
- b
+ C_VALUE () - 1;
1044 tmp
= iu_carry (a
,~b
, C_VALUE ());
1048 case 0x08: /* illegal */
1049 case 0x09: /* illegal*/
1050 cpu
.asregs
.exception
= SIGILL
;
1052 case 0x0A: /* movf */
1054 cpu
.gr
[RD
] = cpu
.gr
[RS
];
1056 case 0x0B: /* lsr */
1058 unsigned long dst
, src
;
1061 /* We must not rely solely upon the native shift operations, since they
1062 may not match the M*Core's behaviour on boundary conditions. */
1063 dst
= src
> 31 ? 0 : dst
>> src
;
1067 case 0x0C: /* cmphs */
1068 NEW_C ((unsigned long )cpu
.gr
[RD
] >=
1069 (unsigned long)cpu
.gr
[RS
]);
1071 case 0x0D: /* cmplt */
1072 NEW_C ((long)cpu
.gr
[RD
] < (long)cpu
.gr
[RS
]);
1074 case 0x0E: /* tst */
1075 NEW_C ((cpu
.gr
[RD
] & cpu
.gr
[RS
]) != 0);
1077 case 0x0F: /* cmpne */
1078 NEW_C (cpu
.gr
[RD
] != cpu
.gr
[RS
]);
1080 case 0x10: case 0x11: /* mfcr */
1084 if (r
<= LAST_VALID_CREG
)
1085 cpu
.gr
[RD
] = cpu
.cr
[r
];
1087 cpu
.asregs
.exception
= SIGILL
;
1091 case 0x12: /* mov */
1092 cpu
.gr
[RD
] = cpu
.gr
[RS
];
1094 fprintf (stderr
, "MOV %x into reg %d", cpu
.gr
[RD
], RD
);
1097 case 0x13: /* bgenr */
1098 if (cpu
.gr
[RS
] & 0x20)
1101 cpu
.gr
[RD
] = 1 << (cpu
.gr
[RS
] & 0x1F);
1104 case 0x14: /* rsub */
1105 cpu
.gr
[RD
] = cpu
.gr
[RS
] - cpu
.gr
[RD
];
1108 case 0x15: /* ixw */
1109 cpu
.gr
[RD
] += cpu
.gr
[RS
]<<2;
1112 case 0x16: /* and */
1113 cpu
.gr
[RD
] &= cpu
.gr
[RS
];
1116 case 0x17: /* xor */
1117 cpu
.gr
[RD
] ^= cpu
.gr
[RS
];
1120 case 0x18: case 0x19: /* mtcr */
1124 if (r
<= LAST_VALID_CREG
)
1125 cpu
.cr
[r
] = cpu
.gr
[RD
];
1127 cpu
.asregs
.exception
= SIGILL
;
1129 /* we might have changed register sets... */
1131 cpu
.asregs
.active_gregs
= & cpu
.asregs
.alt_gregs
[0];
1133 cpu
.asregs
.active_gregs
= & cpu
.asregs
.gregs
[0];
1137 case 0x1A: /* asr */
1138 /* We must not rely solely upon the native shift operations, since they
1139 may not match the M*Core's behaviour on boundary conditions. */
1140 if (cpu
.gr
[RS
] > 30)
1141 cpu
.gr
[RD
] = ((long) cpu
.gr
[RD
]) < 0 ? -1 : 0;
1143 cpu
.gr
[RD
] = (long) cpu
.gr
[RD
] >> cpu
.gr
[RS
];
1146 case 0x1B: /* lsl */
1147 /* We must not rely solely upon the native shift operations, since they
1148 may not match the M*Core's behaviour on boundary conditions. */
1149 cpu
.gr
[RD
] = cpu
.gr
[RS
] > 31 ? 0 : cpu
.gr
[RD
] << cpu
.gr
[RS
];
1152 case 0x1C: /* addu */
1153 cpu
.gr
[RD
] += cpu
.gr
[RS
];
1156 case 0x1D: /* ixh */
1157 cpu
.gr
[RD
] += cpu
.gr
[RS
] << 1;
1161 cpu
.gr
[RD
] |= cpu
.gr
[RS
];
1164 case 0x1F: /* andn */
1165 cpu
.gr
[RD
] &= ~cpu
.gr
[RS
];
1167 case 0x20: case 0x21: /* addi */
1169 cpu
.gr
[RD
] + (IMM5
+ 1);
1171 case 0x22: case 0x23: /* cmplti */
1173 int tmp
= (IMM5
+ 1);
1174 if (cpu
.gr
[RD
] < tmp
)
1184 case 0x24: case 0x25: /* subi */
1186 cpu
.gr
[RD
] - (IMM5
+ 1);
1188 case 0x26: case 0x27: /* illegal */
1189 cpu
.asregs
.exception
= SIGILL
;
1191 case 0x28: case 0x29: /* rsubi */
1195 case 0x2A: case 0x2B: /* cmpnei */
1196 if (cpu
.gr
[RD
] != IMM5
)
1206 case 0x2C: case 0x2D: /* bmaski, divu */
1208 unsigned imm
= IMM5
;
1214 unsigned int rx
, r1
;
1220 /* unsigned divide */
1221 cpu
.gr
[RD
] = (word
) ((unsigned int) cpu
.gr
[RD
] / (unsigned int)cpu
.gr
[1] );
1223 /* compute bonus_cycles for divu */
1224 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32); r1nlz
++)
1227 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32); rxnlz
++)
1233 exe
+= 5 + r1nlz
- rxnlz
;
1235 if (exe
>= (2 * memcycles
- 1))
1237 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
1240 else if (imm
== 0 || imm
>= 8)
1246 cpu
.gr
[RD
] = (1 << imm
) - 1;
1251 cpu
.asregs
.exception
= SIGILL
;
1255 case 0x2E: case 0x2F: /* andi */
1256 cpu
.gr
[RD
] = cpu
.gr
[RD
] & IMM5
;
1258 case 0x30: case 0x31: /* bclri */
1259 cpu
.gr
[RD
] = cpu
.gr
[RD
] & ~(1<<IMM5
);
1261 case 0x32: case 0x33: /* bgeni, divs */
1263 unsigned imm
= IMM5
;
1270 /* compute bonus_cycles for divu */
1275 if (((rx
< 0) && (r1
> 0)) || ((rx
>= 0) && (r1
< 0)))
1283 /* signed divide, general registers are of type int, so / op is OK */
1284 cpu
.gr
[RD
] = cpu
.gr
[RD
] / cpu
.gr
[1];
1286 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32) ; r1nlz
++ )
1289 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32) ; rxnlz
++ )
1295 exe
+= 6 + r1nlz
- rxnlz
+ sc
;
1297 if (exe
>= (2 * memcycles
- 1))
1299 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
1305 cpu
.gr
[RD
] = (1 << IMM5
);
1310 cpu
.asregs
.exception
= SIGILL
;
1314 case 0x34: case 0x35: /* bseti */
1315 cpu
.gr
[RD
] = cpu
.gr
[RD
] | (1 << IMM5
);
1317 case 0x36: case 0x37: /* btsti */
1318 NEW_C (cpu
.gr
[RD
] >> IMM5
);
1320 case 0x38: case 0x39: /* xsr, rotli */
1322 unsigned imm
= IMM5
;
1323 unsigned long tmp
= cpu
.gr
[RD
];
1329 cpu
.gr
[RD
] = (cbit
<< 31) | (tmp
>> 1);
1332 cpu
.gr
[RD
] = (tmp
<< imm
) | (tmp
>> (32 - imm
));
1335 case 0x3A: case 0x3B: /* asrc, asri */
1337 unsigned imm
= IMM5
;
1338 long tmp
= cpu
.gr
[RD
];
1342 cpu
.gr
[RD
] = tmp
>> 1;
1345 cpu
.gr
[RD
] = tmp
>> imm
;
1348 case 0x3C: case 0x3D: /* lslc, lsli */
1350 unsigned imm
= IMM5
;
1351 unsigned long tmp
= cpu
.gr
[RD
];
1355 cpu
.gr
[RD
] = tmp
<< 1;
1358 cpu
.gr
[RD
] = tmp
<< imm
;
1361 case 0x3E: case 0x3F: /* lsrc, lsri */
1363 unsigned imm
= IMM5
;
1364 unsigned long tmp
= cpu
.gr
[RD
];
1368 cpu
.gr
[RD
] = tmp
>> 1;
1371 cpu
.gr
[RD
] = tmp
>> imm
;
1374 case 0x40: case 0x41: case 0x42: case 0x43:
1375 case 0x44: case 0x45: case 0x46: case 0x47:
1376 case 0x48: case 0x49: case 0x4A: case 0x4B:
1377 case 0x4C: case 0x4D: case 0x4E: case 0x4F:
1378 cpu
.asregs
.exception
= SIGILL
;
1381 util (sd
, inst
& 0xFF);
1383 case 0x51: case 0x52: case 0x53:
1384 case 0x54: case 0x55: case 0x56: case 0x57:
1385 case 0x58: case 0x59: case 0x5A: case 0x5B:
1386 case 0x5C: case 0x5D: case 0x5E: case 0x5F:
1387 cpu
.asregs
.exception
= SIGILL
;
1389 case 0x60: case 0x61: case 0x62: case 0x63: /* movi */
1390 case 0x64: case 0x65: case 0x66: case 0x67:
1391 cpu
.gr
[RD
] = (inst
>> 4) & 0x7F;
1393 case 0x68: case 0x69: case 0x6A: case 0x6B:
1394 case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */
1395 cpu
.asregs
.exception
= SIGILL
;
1397 case 0x71: case 0x72: case 0x73:
1398 case 0x74: case 0x75: case 0x76: case 0x77:
1399 case 0x78: case 0x79: case 0x7A: case 0x7B:
1400 case 0x7C: case 0x7D: case 0x7E: /* lrw */
1401 cpu
.gr
[RX
] = rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1403 fprintf (stderr
, "LRW of 0x%x from 0x%x to reg %d",
1404 rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC),
1405 (pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC, RX
);
1408 case 0x7F: /* jsri */
1411 fprintf (stderr
, "func call: r2 = %x r3 = %x r4 = %x r5 = %x r6 = %x r7 = %x\n",
1412 cpu
.gr
[2], cpu
.gr
[3], cpu
.gr
[4], cpu
.gr
[5], cpu
.gr
[6], cpu
.gr
[7]);
1413 case 0x70: /* jmpi */
1414 pc
= rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1420 case 0x80: case 0x81: case 0x82: case 0x83:
1421 case 0x84: case 0x85: case 0x86: case 0x87:
1422 case 0x88: case 0x89: case 0x8A: case 0x8B:
1423 case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */
1424 cpu
.gr
[RX
] = rlat (cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C));
1426 fprintf (stderr
, "load reg %d from 0x%x with 0x%x",
1428 cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C), cpu
.gr
[RX
]);
1431 case 0x90: case 0x91: case 0x92: case 0x93:
1432 case 0x94: case 0x95: case 0x96: case 0x97:
1433 case 0x98: case 0x99: case 0x9A: case 0x9B:
1434 case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */
1435 wlat (cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C), cpu
.gr
[RX
]);
1437 fprintf (stderr
, "store reg %d (containing 0x%x) to 0x%x",
1439 cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C));
1442 case 0xA0: case 0xA1: case 0xA2: case 0xA3:
1443 case 0xA4: case 0xA5: case 0xA6: case 0xA7:
1444 case 0xA8: case 0xA9: case 0xAA: case 0xAB:
1445 case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */
1446 cpu
.gr
[RX
] = rbat (cpu
.gr
[RD
] + RS
);
1449 case 0xB0: case 0xB1: case 0xB2: case 0xB3:
1450 case 0xB4: case 0xB5: case 0xB6: case 0xB7:
1451 case 0xB8: case 0xB9: case 0xBA: case 0xBB:
1452 case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */
1453 wbat (cpu
.gr
[RD
] + RS
, cpu
.gr
[RX
]);
1456 case 0xC0: case 0xC1: case 0xC2: case 0xC3:
1457 case 0xC4: case 0xC5: case 0xC6: case 0xC7:
1458 case 0xC8: case 0xC9: case 0xCA: case 0xCB:
1459 case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */
1460 cpu
.gr
[RX
] = rhat (cpu
.gr
[RD
] + ((inst
>> 3) & 0x001E));
1463 case 0xD0: case 0xD1: case 0xD2: case 0xD3:
1464 case 0xD4: case 0xD5: case 0xD6: case 0xD7:
1465 case 0xD8: case 0xD9: case 0xDA: case 0xDB:
1466 case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */
1467 what (cpu
.gr
[RD
] + ((inst
>> 3) & 0x001E), cpu
.gr
[RX
]);
1470 case 0xE8: case 0xE9: case 0xEA: case 0xEB:
1471 case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */
1475 disp
= inst
& 0x03FF;
1483 case 0xE0: case 0xE1: case 0xE2: case 0xE3:
1484 case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */
1488 disp
= inst
& 0x03FF;
1497 case 0xF8: case 0xF9: case 0xFA: case 0xFB:
1498 case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */
1500 case 0xF0: case 0xF1: case 0xF2: case 0xF3:
1501 case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */
1504 disp
= inst
& 0x03FF;
1516 fprintf (stderr
, "\n");
1520 /* Do not let him fetch from a bad address! */
1521 if (((uword
)pc
) >= cpu
.asregs
.msize
)
1524 fprintf (stderr
, "PC loaded at 0x%x is outside of available memory! (0x%x)\n", oldpc
, pc
);
1526 cpu
.asregs
.exception
= SIGSEGV
;
1530 ibuf
= rlat (pc
& 0xFFFFFFFC);
1535 while (!cpu
.asregs
.exception
);
1537 /* Hide away the things we've cached while executing. */
1538 CPU_PC_SET (scpu
, pc
);
1539 cpu
.asregs
.insts
+= insts
; /* instructions done ... */
1540 cpu
.asregs
.cycles
+= insts
; /* and each takes a cycle */
1541 cpu
.asregs
.cycles
+= bonus_cycles
; /* and extra cycles for branches */
1542 cpu
.asregs
.cycles
+= memops
* memcycles
; /* and memop cycle delays */
1547 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
1552 memcpy (& cpu
.mem
[addr
], buffer
, size
);
1558 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
1563 memcpy (buffer
, & cpu
.mem
[addr
], size
);
1570 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1574 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1580 /* misalignment safe */
1581 ival
= mcore_extract_unsigned_integer (memory
, 4);
1582 cpu
.asints
[rn
] = ival
;
1592 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1596 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1600 long ival
= cpu
.asints
[rn
];
1602 /* misalignment-safe */
1603 mcore_store_unsigned_integer (memory
, 4, ival
);
1613 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
1615 if (cpu
.asregs
.exception
== SIGQUIT
)
1617 * reason
= sim_exited
;
1618 * sigrc
= cpu
.gr
[PARM1
];
1622 * reason
= sim_stopped
;
1623 * sigrc
= cpu
.asregs
.exception
;
1628 sim_info (SIM_DESC sd
, int verbose
)
1630 #ifdef WATCHFUNCTIONS
1633 double virttime
= cpu
.asregs
.cycles
/ 36.0e6
;
1634 host_callback
*callback
= STATE_CALLBACK (sd
);
1636 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
1638 callback
->printf_filtered (callback
, "# cycles %10d\n",
1640 callback
->printf_filtered (callback
, "# pipeline stalls %10d\n",
1642 callback
->printf_filtered (callback
, "# virtual time taken %10.4f\n",
1645 #ifdef WATCHFUNCTIONS
1646 callback
->printf_filtered (callback
, "\nNumber of watched functions: %d\n",
1651 for (w
= 1; w
<= ENDWL
; w
++)
1653 callback
->printf_filtered (callback
, "WL = %s %8x\n",WLstr
[w
],WL
[w
]);
1654 callback
->printf_filtered (callback
, " calls = %d, cycles = %d\n",
1655 WLcnts
[w
],WLcyc
[w
]);
1658 callback
->printf_filtered (callback
,
1659 " maxcpc = %d, mincpc = %d, avecpc = %d\n",
1660 WLmax
[w
],WLmin
[w
],WLcyc
[w
]/WLcnts
[w
]);
1664 callback
->printf_filtered (callback
,
1665 "Total cycles for watched functions: %d\n",wcyc
);
1670 mcore_pc_get (sim_cpu
*cpu
)
1676 mcore_pc_set (sim_cpu
*cpu
, sim_cia pc
)
1682 free_state (SIM_DESC sd
)
1684 if (STATE_MODULES (sd
) != NULL
)
1685 sim_module_uninstall (sd
);
1686 sim_cpu_free_all (sd
);
1687 sim_state_free (sd
);
1691 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
, struct bfd
*abfd
, char **argv
)
1693 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
1695 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1697 /* The cpu data is kept in a separately allocated chunk of memory. */
1698 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
1704 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
1710 /* getopt will print the error message so we just have to exit if this fails.
1711 FIXME: Hmmm... in the case of gdb we need getopt to call
1713 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
1719 /* Check for/establish the a reference program image. */
1720 if (sim_analyze_program (sd
,
1721 (STATE_PROG_ARGV (sd
) != NULL
1722 ? *STATE_PROG_ARGV (sd
)
1723 : NULL
), abfd
) != SIM_RC_OK
)
1729 /* Configure/verify the target byte order and other runtime
1730 configuration options. */
1731 if (sim_config (sd
) != SIM_RC_OK
)
1733 sim_module_uninstall (sd
);
1737 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
1739 /* Uninstall the modules to avoid memory leaks,
1740 file descriptor leaks, etc. */
1741 sim_module_uninstall (sd
);
1745 osize
= sim_memory_size
;
1747 if (kind
== SIM_OPEN_STANDALONE
)
1750 /* Discard and reacquire memory -- start with a clean slate. */
1751 sim_size (1); /* small */
1752 sim_size (osize
); /* and back again */
1754 /* CPU specific initialization. */
1755 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
1757 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
1759 CPU_PC_FETCH (cpu
) = mcore_pc_get
;
1760 CPU_PC_STORE (cpu
) = mcore_pc_set
;
1762 set_initial_gprs (cpu
); /* Reset the GPR registers. */
1769 sim_close (SIM_DESC sd
, int quitting
)
1775 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
, char **argv
, char **env
)
1777 SIM_CPU
*scpu
= STATE_CPU (sd
, 0);
1783 unsigned long strings
;
1784 unsigned long pointers
;
1785 unsigned long hi_stack
;
1788 /* Set the initial register set. */
1791 set_initial_gprs (scpu
);
1794 hi_stack
= cpu
.asregs
.msize
- 4;
1795 CPU_PC_SET (scpu
, bfd_get_start_address (prog_bfd
));
1797 /* Calculate the argument and environment strings. */
1803 l
= strlen (*avp
) + 1; /* include the null */
1804 s_length
+= (l
+ 3) & ~3; /* make it a 4 byte boundary */
1812 l
= strlen (*avp
) + 1; /* include the null */
1813 s_length
+= (l
+ 3) & ~ 3;/* make it a 4 byte boundary */
1817 /* Claim some memory for the pointers and strings. */
1818 pointers
= hi_stack
- sizeof(word
) * (nenv
+1+nargs
+1);
1819 pointers
&= ~3; /* must be 4-byte aligned */
1820 cpu
.gr
[0] = pointers
;
1822 strings
= cpu
.gr
[0] - s_length
;
1823 strings
&= ~3; /* want to make it 4-byte aligned */
1824 cpu
.gr
[0] = strings
;
1825 /* dac fix, the stack address must be 8-byte aligned! */
1826 cpu
.gr
[0] = cpu
.gr
[0] - cpu
.gr
[0] % 8;
1828 /* Loop through the arguments and fill them in. */
1829 cpu
.gr
[PARM1
] = nargs
;
1832 /* No strings to fill in. */
1837 cpu
.gr
[PARM2
] = pointers
;
1841 /* Save where we're putting it. */
1842 wlat (pointers
, strings
);
1844 /* Copy the string. */
1845 l
= strlen (* avp
) + 1;
1846 strcpy ((char *)(cpu
.mem
+ strings
), *avp
);
1848 /* Bump the pointers. */
1854 /* A null to finish the list. */
1859 /* Now do the environment pointers. */
1862 /* No strings to fill in. */
1867 cpu
.gr
[PARM3
] = pointers
;
1872 /* Save where we're putting it. */
1873 wlat (pointers
, strings
);
1875 /* Copy the string. */
1876 l
= strlen (* avp
) + 1;
1877 strcpy ((char *)(cpu
.mem
+ strings
), *avp
);
1879 /* Bump the pointers. */
1885 /* A null to finish the list. */
1894 sim_do_command (SIM_DESC sd
, const char *cmd
)
1896 /* Nothing there yet; it's all an error. */
1900 char ** simargv
= buildargv (cmd
);
1902 if (strcmp (simargv
[0], "watch") == 0)
1904 if ((simargv
[1] == NULL
) || (simargv
[2] == NULL
))
1906 fprintf (stderr
, "Error: missing argument to watch cmd.\n");
1913 WL
[ENDWL
] = strtol (simargv
[2], NULL
, 0);
1914 WLstr
[ENDWL
] = strdup (simargv
[1]);
1915 fprintf (stderr
, "Added %s (%x) to watchlist, #%d\n",WLstr
[ENDWL
],
1919 else if (strcmp (simargv
[0], "dumpmem") == 0)
1924 if (simargv
[1] == NULL
)
1925 fprintf (stderr
, "Error: missing argument to dumpmem cmd.\n");
1927 fprintf (stderr
, "Writing dumpfile %s...",simargv
[1]);
1929 dumpfile
= fopen (simargv
[1], "w");
1931 fwrite (p
, cpu
.asregs
.msize
-1, 1, dumpfile
);
1934 fprintf (stderr
, "done.\n");
1936 else if (strcmp (simargv
[0], "clearstats") == 0)
1938 cpu
.asregs
.cycles
= 0;
1939 cpu
.asregs
.insts
= 0;
1940 cpu
.asregs
.stalls
= 0;
1943 else if (strcmp (simargv
[0], "verbose") == 0)
1949 fprintf (stderr
,"Error: \"%s\" is not a valid M.CORE simulator command.\n",
1957 fprintf (stderr
, "M.CORE sim commands: \n");
1958 fprintf (stderr
, " watch <funcname> <addr>\n");
1959 fprintf (stderr
, " dumpmem <filename>\n");
1960 fprintf (stderr
, " clearstats\n");
1961 fprintf (stderr
, " verbose\n");
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