1 /* Simulator for Motorola's MCore processor
2 Copyright (C) 1999-2015 Free Software Foundation, Inc.
3 Contributed by Cygnus Solutions.
5 This file is part of GDB, the GNU debugger.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #include <sys/times.h>
25 #include <sys/param.h>
28 #include "gdb/callback.h"
29 #include "libiberty.h"
30 #include "gdb/remote-sim.h"
34 #include "sim-options.h"
36 #define target_big_endian (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
40 mcore_extract_unsigned_integer (unsigned char *addr
, int len
)
44 unsigned char * startaddr
= (unsigned char *)addr
;
45 unsigned char * endaddr
= startaddr
+ len
;
47 if (len
> (int) sizeof (unsigned long))
48 printf ("That operation is not available on integers of more than %zu bytes.",
49 sizeof (unsigned long));
51 /* Start at the most significant end of the integer, and work towards
52 the least significant. */
55 if (! target_big_endian
)
57 for (p
= endaddr
; p
> startaddr
;)
58 retval
= (retval
<< 8) | * -- p
;
62 for (p
= startaddr
; p
< endaddr
;)
63 retval
= (retval
<< 8) | * p
++;
70 mcore_store_unsigned_integer (unsigned char *addr
, int len
, unsigned long val
)
73 unsigned char * startaddr
= (unsigned char *)addr
;
74 unsigned char * endaddr
= startaddr
+ len
;
76 if (! target_big_endian
)
78 for (p
= startaddr
; p
< endaddr
;)
86 for (p
= endaddr
; p
> startaddr
;)
95 This state is maintained in host byte order. The
96 fetch/store register functions must translate between host
97 byte order and the target processor byte order.
98 Keeping this data in target byte order simplifies the register
99 read/write functions. Keeping this data in native order improves
100 the performance of the simulator. Simulation speed is deemed more
102 /* TODO: Should be moved to sim-main.h:sim_cpu. */
104 /* The ordering of the mcore_regset structure is matched in the
105 gdb/config/mcore/tm-mcore.h file in the REGISTER_NAMES macro. */
108 word gregs
[16]; /* primary registers */
109 word alt_gregs
[16]; /* alt register file */
110 word cregs
[32]; /* control registers */
121 struct mcore_regset asregs
;
122 word asints
[1]; /* but accessed larger... */
125 #define LAST_VALID_CREG 32 /* only 0..12 implemented */
126 #define NUM_MCORE_REGS (16 + 16 + LAST_VALID_CREG + 1)
128 static int memcycles
= 1;
130 #define gr asregs.active_gregs
131 #define cr asregs.cregs
132 #define sr asregs.cregs[0]
133 #define vbr asregs.cregs[1]
134 #define esr asregs.cregs[2]
135 #define fsr asregs.cregs[3]
136 #define epc asregs.cregs[4]
137 #define fpc asregs.cregs[5]
138 #define ss0 asregs.cregs[6]
139 #define ss1 asregs.cregs[7]
140 #define ss2 asregs.cregs[8]
141 #define ss3 asregs.cregs[9]
142 #define ss4 asregs.cregs[10]
143 #define gcr asregs.cregs[11]
144 #define gsr asregs.cregs[12]
146 /* maniuplate the carry bit */
147 #define C_ON() (cpu.sr & 1)
148 #define C_VALUE() (cpu.sr & 1)
149 #define C_OFF() ((cpu.sr & 1) == 0)
150 #define SET_C() {cpu.sr |= 1;}
151 #define CLR_C() {cpu.sr &= 0xfffffffe;}
152 #define NEW_C(v) {CLR_C(); cpu.sr |= ((v) & 1);}
154 #define SR_AF() ((cpu.sr >> 1) & 1)
156 #define TRAPCODE 1 /* r1 holds which function we want */
157 #define PARM1 2 /* first parameter */
161 #define RET1 2 /* register for return values. */
163 /* Default to a 8 Mbyte (== 2^23) memory space. */
164 #define DEFAULT_MEMORY_SIZE 0x800000
167 set_initial_gprs (SIM_CPU
*scpu
)
172 /* Set up machine just out of reset. */
173 CPU_PC_SET (scpu
, 0);
176 /* Clean out the GPRs and alternate GPRs. */
177 for (i
= 0; i
< 16; i
++)
179 cpu
.asregs
.gregs
[i
] = 0;
180 cpu
.asregs
.alt_gregs
[i
] = 0;
183 /* Make our register set point to the right place. */
185 cpu
.asregs
.active_gregs
= &cpu
.asregs
.alt_gregs
[0];
187 cpu
.asregs
.active_gregs
= &cpu
.asregs
.gregs
[0];
189 /* ABI specifies initial values for these registers. */
190 cpu
.gr
[0] = DEFAULT_MEMORY_SIZE
- 4;
192 /* dac fix, the stack address must be 8-byte aligned! */
193 cpu
.gr
[0] = cpu
.gr
[0] - cpu
.gr
[0] % 8;
197 cpu
.gr
[PARM4
] = cpu
.gr
[0];
200 /* Read/write functions for system call interface. */
203 syscall_read_mem (host_callback
*cb
, struct cb_syscall
*sc
,
204 unsigned long taddr
, char *buf
, int bytes
)
206 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
207 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
209 return sim_core_read_buffer (sd
, cpu
, read_map
, buf
, taddr
, bytes
);
213 syscall_write_mem (host_callback
*cb
, struct cb_syscall
*sc
,
214 unsigned long taddr
, const char *buf
, int bytes
)
216 SIM_DESC sd
= (SIM_DESC
) sc
->p1
;
217 SIM_CPU
*cpu
= (SIM_CPU
*) sc
->p2
;
219 return sim_core_write_buffer (sd
, cpu
, write_map
, buf
, taddr
, bytes
);
222 /* Simulate a monitor trap. */
225 handle_trap1 (SIM_DESC sd
)
227 host_callback
*cb
= STATE_CALLBACK (sd
);
230 CB_SYSCALL_INIT (&sc
);
232 sc
.func
= cpu
.gr
[TRAPCODE
];
233 sc
.arg1
= cpu
.gr
[PARM1
];
234 sc
.arg2
= cpu
.gr
[PARM2
];
235 sc
.arg3
= cpu
.gr
[PARM3
];
236 sc
.arg4
= cpu
.gr
[PARM4
];
239 sc
.p2
= (PTR
) STATE_CPU (sd
, 0);
240 sc
.read_mem
= syscall_read_mem
;
241 sc
.write_mem
= syscall_write_mem
;
243 cb_syscall (cb
, &sc
);
245 /* XXX: We don't pass back the actual errno value. */
246 cpu
.gr
[RET1
] = sc
.result
;
250 process_stub (SIM_DESC sd
, int what
)
252 /* These values should match those in libgloss/mcore/syscalls.s. */
259 case 10: /* _unlink */
260 case 19: /* _lseek */
261 case 43: /* _times */
262 cpu
.gr
[TRAPCODE
] = what
;
267 if (STATE_VERBOSE_P (sd
))
268 fprintf (stderr
, "Unhandled stub opcode: %d\n", what
);
274 util (SIM_DESC sd
, unsigned what
)
279 cpu
.asregs
.exception
= SIGQUIT
;
283 if (STATE_VERBOSE_P (sd
))
284 fprintf (stderr
, "WARNING: printf unimplemented\n");
288 if (STATE_VERBOSE_P (sd
))
289 fprintf (stderr
, "WARNING: scanf unimplemented\n");
293 cpu
.gr
[RET1
] = cpu
.asregs
.insts
;
297 process_stub (sd
, cpu
.gr
[1]);
301 if (STATE_VERBOSE_P (sd
))
302 fprintf (stderr
, "Unhandled util code: %x\n", what
);
307 /* For figuring out whether we carried; addc/subc use this. */
309 iu_carry (unsigned long a
, unsigned long b
, int cin
)
313 x
= (a
& 0xffff) + (b
& 0xffff) + cin
;
314 x
= (x
>> 16) + (a
>> 16) + (b
>> 16);
320 /* TODO: Convert to common watchpoints. */
321 #undef WATCHFUNCTIONS
322 #ifdef WATCHFUNCTIONS
339 #define RD (inst & 0xF)
340 #define RS ((inst >> 4) & 0xF)
341 #define RX ((inst >> 8) & 0xF)
342 #define IMM5 ((inst >> 4) & 0x1F)
343 #define IMM4 ((inst) & 0xF)
345 #define rbat(X) sim_core_read_1 (scpu, 0, read_map, X)
346 #define rhat(X) sim_core_read_2 (scpu, 0, read_map, X)
347 #define rlat(X) sim_core_read_4 (scpu, 0, read_map, X)
348 #define wbat(X, D) sim_core_write_1 (scpu, 0, write_map, X, D)
349 #define what(X, D) sim_core_write_2 (scpu, 0, write_map, X, D)
350 #define wlat(X, D) sim_core_write_4 (scpu, 0, write_map, X, D)
352 static int tracing
= 0;
355 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
357 SIM_CPU
*scpu
= STATE_CPU (sd
, 0);
367 #ifdef WATCHFUNCTIONS
371 cpu
.asregs
.exception
= step
? SIGTRAP
: 0;
372 pc
= CPU_PC_GET (scpu
);
374 /* Fetch the initial instructions that we'll decode. */
375 ibuf
= rlat (pc
& 0xFFFFFFFC);
382 /* make our register set point to the right place */
384 cpu
.asregs
.active_gregs
= & cpu
.asregs
.alt_gregs
[0];
386 cpu
.asregs
.active_gregs
= & cpu
.asregs
.gregs
[0];
388 #ifdef WATCHFUNCTIONS
389 /* make a hash to speed exec loop, hope it's nonzero */
392 for (w
= 1; w
<= ENDWL
; w
++)
393 WLhash
= WLhash
& WL
[w
];
404 if (! target_big_endian
)
407 inst
= ibuf
& 0xFFFF;
412 if (! target_big_endian
)
413 inst
= ibuf
& 0xFFFF;
418 #ifdef WATCHFUNCTIONS
419 /* now scan list of watch addresses, if match, count it and
420 note return address and count cycles until pc=return address */
422 if ((WLincyc
== 1) && (pc
== WLendpc
))
424 cycs
= (cpu
.asregs
.cycles
+ (insts
+ bonus_cycles
+
425 (memops
* memcycles
)) - WLbcyc
);
427 if (WLcnts
[WLW
] == 1)
434 if (cycs
> WLmax
[WLW
])
439 if (cycs
< WLmin
[WLW
])
449 /* Optimize with a hash to speed loop. */
452 if ((WLhash
== 0) || ((WLhash
& pc
) != 0))
454 for (w
=1; w
<= ENDWL
; w
++)
459 WLbcyc
= cpu
.asregs
.cycles
+ insts
460 + bonus_cycles
+ (memops
* memcycles
);
461 WLendpc
= cpu
.gr
[15];
472 fprintf (stderr
, "%.4lx: inst = %.4x ", pc
, inst
);
487 cpu
.asregs
.exception
= SIGTRAP
;
500 cpu
.asregs
.active_gregs
= & cpu
.asregs
.alt_gregs
[0];
502 cpu
.asregs
.active_gregs
= & cpu
.asregs
.gregs
[0];
511 cpu
.asregs
.active_gregs
= &cpu
.asregs
.alt_gregs
[0];
513 cpu
.asregs
.active_gregs
= &cpu
.asregs
.gregs
[0];
517 if (STATE_VERBOSE_P (sd
))
518 fprintf (stderr
, "WARNING: stop unimplemented\n");
522 if (STATE_VERBOSE_P (sd
))
523 fprintf (stderr
, "WARNING: wait unimplemented\n");
527 if (STATE_VERBOSE_P (sd
))
528 fprintf (stderr
, "WARNING: doze unimplemented\n");
532 cpu
.asregs
.exception
= SIGILL
; /* illegal */
535 case 0x8: /* trap 0 */
536 case 0xA: /* trap 2 */
537 case 0xB: /* trap 3 */
538 cpu
.asregs
.exception
= SIGTRAP
;
541 case 0xC: /* trap 4 */
542 case 0xD: /* trap 5 */
543 case 0xE: /* trap 6 */
544 cpu
.asregs
.exception
= SIGILL
; /* illegal */
547 case 0xF: /* trap 7 */
548 cpu
.asregs
.exception
= SIGTRAP
; /* integer div-by-0 */
551 case 0x9: /* trap 1 */
558 cpu
.asregs
.exception
= SIGILL
; /* illegal */
562 cpu
.gr
[RD
] = C_VALUE();
565 cpu
.gr
[RD
] = C_OFF();
569 word addr
= cpu
.gr
[RD
];
570 int regno
= 4; /* always r4-r7 */
576 cpu
.gr
[regno
] = rlat(addr
);
580 while ((regno
&0x3) != 0);
585 word addr
= cpu
.gr
[RD
];
586 int regno
= 4; /* always r4-r7 */
592 wlat(addr
, cpu
.gr
[regno
]);
596 while ((regno
& 0x3) != 0);
601 word addr
= cpu
.gr
[0];
604 /* bonus cycle is really only needed if
605 the next insn shifts the last reg loaded.
612 cpu
.gr
[regno
] = rlat(addr
);
620 word addr
= cpu
.gr
[0];
623 /* this should be removed! */
624 /* bonus_cycles ++; */
626 memops
+= 16 - regno
;
629 wlat(addr
, cpu
.gr
[regno
]);
637 cpu
.gr
[RD
] -= C_VALUE();
640 cpu
.gr
[RD
] -= C_OFF();
643 cpu
.gr
[RD
] += C_VALUE();
646 cpu
.gr
[RD
] += C_OFF();
650 if (tracing
&& RD
== 15)
651 fprintf (stderr
, "Func return, r2 = %lxx, r3 = %lx\n",
652 cpu
.gr
[2], cpu
.gr
[3]);
666 for (i
= 0; !(tmp
& 0x80000000) && i
< 32; i
++)
675 tmp
= ((tmp
& 0xaaaaaaaa) >> 1) | ((tmp
& 0x55555555) << 1);
676 tmp
= ((tmp
& 0xcccccccc) >> 2) | ((tmp
& 0x33333333) << 2);
677 tmp
= ((tmp
& 0xf0f0f0f0) >> 4) | ((tmp
& 0x0f0f0f0f) << 4);
678 tmp
= ((tmp
& 0xff00ff00) >> 8) | ((tmp
& 0x00ff00ff) << 8);
679 cpu
.gr
[RD
] = ((tmp
& 0xffff0000) >> 16) | ((tmp
& 0x0000ffff) << 16);
687 case 0x0: /* xtrb3 */
688 cpu
.gr
[1] = (cpu
.gr
[RD
]) & 0xFF;
689 NEW_C (cpu
.gr
[RD
] != 0);
691 case 0x1: /* xtrb2 */
692 cpu
.gr
[1] = (cpu
.gr
[RD
]>>8) & 0xFF;
693 NEW_C (cpu
.gr
[RD
] != 0);
695 case 0x2: /* xtrb1 */
696 cpu
.gr
[1] = (cpu
.gr
[RD
]>>16) & 0xFF;
697 NEW_C (cpu
.gr
[RD
] != 0);
699 case 0x3: /* xtrb0 */
700 cpu
.gr
[1] = (cpu
.gr
[RD
]>>24) & 0xFF;
701 NEW_C (cpu
.gr
[RD
] != 0);
703 case 0x4: /* zextb */
704 cpu
.gr
[RD
] &= 0x000000FF;
706 case 0x5: /* sextb */
715 case 0x6: /* zexth */
716 cpu
.gr
[RD
] &= 0x0000FFFF;
718 case 0x7: /* sexth */
727 case 0x8: /* declt */
729 NEW_C ((long)cpu
.gr
[RD
] < 0);
731 case 0x9: /* tstnbz */
733 word tmp
= cpu
.gr
[RD
];
734 NEW_C ((tmp
& 0xFF000000) != 0 &&
735 (tmp
& 0x00FF0000) != 0 && (tmp
& 0x0000FF00) != 0 &&
736 (tmp
& 0x000000FF) != 0);
739 case 0xA: /* decgt */
741 NEW_C ((long)cpu
.gr
[RD
] > 0);
743 case 0xB: /* decne */
745 NEW_C ((long)cpu
.gr
[RD
] != 0);
756 if (cpu
.gr
[RD
] & 0x80000000)
757 cpu
.gr
[RD
] = ~cpu
.gr
[RD
] + 1;
760 cpu
.gr
[RD
] = ~cpu
.gr
[RD
];
764 case 0x02: /* movt */
766 cpu
.gr
[RD
] = cpu
.gr
[RS
];
768 case 0x03: /* mult */
769 /* consume 2 bits per cycle from rs, until rs is 0 */
771 unsigned int t
= cpu
.gr
[RS
];
773 for (ticks
= 0; t
!= 0 ; t
>>= 2)
775 bonus_cycles
+= ticks
;
777 bonus_cycles
+= 2; /* min. is 3, so add 2, plus ticks above */
779 fprintf (stderr
, " mult %lx by %lx to give %lx",
780 cpu
.gr
[RD
], cpu
.gr
[RS
], cpu
.gr
[RD
] * cpu
.gr
[RS
]);
781 cpu
.gr
[RD
] = cpu
.gr
[RD
] * cpu
.gr
[RS
];
783 case 0x04: /* loopt */
786 pc
+= (IMM4
<< 1) - 32;
790 --cpu
.gr
[RS
]; /* not RD! */
791 NEW_C (((long)cpu
.gr
[RS
]) > 0);
793 case 0x05: /* subu */
794 cpu
.gr
[RD
] -= cpu
.gr
[RS
];
796 case 0x06: /* addc */
798 unsigned long tmp
, a
, b
;
801 cpu
.gr
[RD
] = a
+ b
+ C_VALUE ();
802 tmp
= iu_carry (a
, b
, C_VALUE ());
806 case 0x07: /* subc */
808 unsigned long tmp
, a
, b
;
811 cpu
.gr
[RD
] = a
- b
+ C_VALUE () - 1;
812 tmp
= iu_carry (a
,~b
, C_VALUE ());
816 case 0x08: /* illegal */
817 case 0x09: /* illegal*/
818 cpu
.asregs
.exception
= SIGILL
;
820 case 0x0A: /* movf */
822 cpu
.gr
[RD
] = cpu
.gr
[RS
];
826 unsigned long dst
, src
;
829 /* We must not rely solely upon the native shift operations, since they
830 may not match the M*Core's behaviour on boundary conditions. */
831 dst
= src
> 31 ? 0 : dst
>> src
;
835 case 0x0C: /* cmphs */
836 NEW_C ((unsigned long )cpu
.gr
[RD
] >=
837 (unsigned long)cpu
.gr
[RS
]);
839 case 0x0D: /* cmplt */
840 NEW_C ((long)cpu
.gr
[RD
] < (long)cpu
.gr
[RS
]);
843 NEW_C ((cpu
.gr
[RD
] & cpu
.gr
[RS
]) != 0);
845 case 0x0F: /* cmpne */
846 NEW_C (cpu
.gr
[RD
] != cpu
.gr
[RS
]);
848 case 0x10: case 0x11: /* mfcr */
852 if (r
<= LAST_VALID_CREG
)
853 cpu
.gr
[RD
] = cpu
.cr
[r
];
855 cpu
.asregs
.exception
= SIGILL
;
860 cpu
.gr
[RD
] = cpu
.gr
[RS
];
862 fprintf (stderr
, "MOV %lx into reg %d", cpu
.gr
[RD
], RD
);
865 case 0x13: /* bgenr */
866 if (cpu
.gr
[RS
] & 0x20)
869 cpu
.gr
[RD
] = 1 << (cpu
.gr
[RS
] & 0x1F);
872 case 0x14: /* rsub */
873 cpu
.gr
[RD
] = cpu
.gr
[RS
] - cpu
.gr
[RD
];
877 cpu
.gr
[RD
] += cpu
.gr
[RS
]<<2;
881 cpu
.gr
[RD
] &= cpu
.gr
[RS
];
885 cpu
.gr
[RD
] ^= cpu
.gr
[RS
];
888 case 0x18: case 0x19: /* mtcr */
892 if (r
<= LAST_VALID_CREG
)
893 cpu
.cr
[r
] = cpu
.gr
[RD
];
895 cpu
.asregs
.exception
= SIGILL
;
897 /* we might have changed register sets... */
899 cpu
.asregs
.active_gregs
= & cpu
.asregs
.alt_gregs
[0];
901 cpu
.asregs
.active_gregs
= & cpu
.asregs
.gregs
[0];
906 /* We must not rely solely upon the native shift operations, since they
907 may not match the M*Core's behaviour on boundary conditions. */
909 cpu
.gr
[RD
] = ((long) cpu
.gr
[RD
]) < 0 ? -1 : 0;
911 cpu
.gr
[RD
] = (long) cpu
.gr
[RD
] >> cpu
.gr
[RS
];
915 /* We must not rely solely upon the native shift operations, since they
916 may not match the M*Core's behaviour on boundary conditions. */
917 cpu
.gr
[RD
] = cpu
.gr
[RS
] > 31 ? 0 : cpu
.gr
[RD
] << cpu
.gr
[RS
];
920 case 0x1C: /* addu */
921 cpu
.gr
[RD
] += cpu
.gr
[RS
];
925 cpu
.gr
[RD
] += cpu
.gr
[RS
] << 1;
929 cpu
.gr
[RD
] |= cpu
.gr
[RS
];
932 case 0x1F: /* andn */
933 cpu
.gr
[RD
] &= ~cpu
.gr
[RS
];
935 case 0x20: case 0x21: /* addi */
937 cpu
.gr
[RD
] + (IMM5
+ 1);
939 case 0x22: case 0x23: /* cmplti */
941 int tmp
= (IMM5
+ 1);
942 if (cpu
.gr
[RD
] < tmp
)
952 case 0x24: case 0x25: /* subi */
954 cpu
.gr
[RD
] - (IMM5
+ 1);
956 case 0x26: case 0x27: /* illegal */
957 cpu
.asregs
.exception
= SIGILL
;
959 case 0x28: case 0x29: /* rsubi */
963 case 0x2A: case 0x2B: /* cmpnei */
964 if (cpu
.gr
[RD
] != IMM5
)
974 case 0x2C: case 0x2D: /* bmaski, divu */
988 /* unsigned divide */
989 cpu
.gr
[RD
] = (word
) ((unsigned int) cpu
.gr
[RD
] / (unsigned int)cpu
.gr
[1] );
991 /* compute bonus_cycles for divu */
992 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32); r1nlz
++)
995 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32); rxnlz
++)
1001 exe
+= 5 + r1nlz
- rxnlz
;
1003 if (exe
>= (2 * memcycles
- 1))
1005 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
1008 else if (imm
== 0 || imm
>= 8)
1014 cpu
.gr
[RD
] = (1 << imm
) - 1;
1019 cpu
.asregs
.exception
= SIGILL
;
1023 case 0x2E: case 0x2F: /* andi */
1024 cpu
.gr
[RD
] = cpu
.gr
[RD
] & IMM5
;
1026 case 0x30: case 0x31: /* bclri */
1027 cpu
.gr
[RD
] = cpu
.gr
[RD
] & ~(1<<IMM5
);
1029 case 0x32: case 0x33: /* bgeni, divs */
1031 unsigned imm
= IMM5
;
1038 /* compute bonus_cycles for divu */
1043 if (((rx
< 0) && (r1
> 0)) || ((rx
>= 0) && (r1
< 0)))
1051 /* signed divide, general registers are of type int, so / op is OK */
1052 cpu
.gr
[RD
] = cpu
.gr
[RD
] / cpu
.gr
[1];
1054 for (r1nlz
= 0; ((r1
& 0x80000000) == 0) && (r1nlz
< 32) ; r1nlz
++ )
1057 for (rxnlz
= 0; ((rx
& 0x80000000) == 0) && (rxnlz
< 32) ; rxnlz
++ )
1063 exe
+= 6 + r1nlz
- rxnlz
+ sc
;
1065 if (exe
>= (2 * memcycles
- 1))
1067 bonus_cycles
+= exe
- (2 * memcycles
) + 1;
1073 cpu
.gr
[RD
] = (1 << IMM5
);
1078 cpu
.asregs
.exception
= SIGILL
;
1082 case 0x34: case 0x35: /* bseti */
1083 cpu
.gr
[RD
] = cpu
.gr
[RD
] | (1 << IMM5
);
1085 case 0x36: case 0x37: /* btsti */
1086 NEW_C (cpu
.gr
[RD
] >> IMM5
);
1088 case 0x38: case 0x39: /* xsr, rotli */
1090 unsigned imm
= IMM5
;
1091 unsigned long tmp
= cpu
.gr
[RD
];
1097 cpu
.gr
[RD
] = (cbit
<< 31) | (tmp
>> 1);
1100 cpu
.gr
[RD
] = (tmp
<< imm
) | (tmp
>> (32 - imm
));
1103 case 0x3A: case 0x3B: /* asrc, asri */
1105 unsigned imm
= IMM5
;
1106 long tmp
= cpu
.gr
[RD
];
1110 cpu
.gr
[RD
] = tmp
>> 1;
1113 cpu
.gr
[RD
] = tmp
>> imm
;
1116 case 0x3C: case 0x3D: /* lslc, lsli */
1118 unsigned imm
= IMM5
;
1119 unsigned long tmp
= cpu
.gr
[RD
];
1123 cpu
.gr
[RD
] = tmp
<< 1;
1126 cpu
.gr
[RD
] = tmp
<< imm
;
1129 case 0x3E: case 0x3F: /* lsrc, lsri */
1131 unsigned imm
= IMM5
;
1132 unsigned long tmp
= cpu
.gr
[RD
];
1136 cpu
.gr
[RD
] = tmp
>> 1;
1139 cpu
.gr
[RD
] = tmp
>> imm
;
1142 case 0x40: case 0x41: case 0x42: case 0x43:
1143 case 0x44: case 0x45: case 0x46: case 0x47:
1144 case 0x48: case 0x49: case 0x4A: case 0x4B:
1145 case 0x4C: case 0x4D: case 0x4E: case 0x4F:
1146 cpu
.asregs
.exception
= SIGILL
;
1149 util (sd
, inst
& 0xFF);
1151 case 0x51: case 0x52: case 0x53:
1152 case 0x54: case 0x55: case 0x56: case 0x57:
1153 case 0x58: case 0x59: case 0x5A: case 0x5B:
1154 case 0x5C: case 0x5D: case 0x5E: case 0x5F:
1155 cpu
.asregs
.exception
= SIGILL
;
1157 case 0x60: case 0x61: case 0x62: case 0x63: /* movi */
1158 case 0x64: case 0x65: case 0x66: case 0x67:
1159 cpu
.gr
[RD
] = (inst
>> 4) & 0x7F;
1161 case 0x68: case 0x69: case 0x6A: case 0x6B:
1162 case 0x6C: case 0x6D: case 0x6E: case 0x6F: /* illegal */
1163 cpu
.asregs
.exception
= SIGILL
;
1165 case 0x71: case 0x72: case 0x73:
1166 case 0x74: case 0x75: case 0x76: case 0x77:
1167 case 0x78: case 0x79: case 0x7A: case 0x7B:
1168 case 0x7C: case 0x7D: case 0x7E: /* lrw */
1169 cpu
.gr
[RX
] = rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1171 fprintf (stderr
, "LRW of 0x%x from 0x%lx to reg %d",
1172 rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC),
1173 (pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC, RX
);
1176 case 0x7F: /* jsri */
1180 "func call: r2 = %lx r3 = %lx r4 = %lx r5 = %lx r6 = %lx r7 = %lx\n",
1181 cpu
.gr
[2], cpu
.gr
[3], cpu
.gr
[4], cpu
.gr
[5], cpu
.gr
[6], cpu
.gr
[7]);
1182 case 0x70: /* jmpi */
1183 pc
= rlat ((pc
+ ((inst
& 0xFF) << 2)) & 0xFFFFFFFC);
1189 case 0x80: case 0x81: case 0x82: case 0x83:
1190 case 0x84: case 0x85: case 0x86: case 0x87:
1191 case 0x88: case 0x89: case 0x8A: case 0x8B:
1192 case 0x8C: case 0x8D: case 0x8E: case 0x8F: /* ld */
1193 cpu
.gr
[RX
] = rlat (cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C));
1195 fprintf (stderr
, "load reg %d from 0x%lx with 0x%lx",
1197 cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C), cpu
.gr
[RX
]);
1200 case 0x90: case 0x91: case 0x92: case 0x93:
1201 case 0x94: case 0x95: case 0x96: case 0x97:
1202 case 0x98: case 0x99: case 0x9A: case 0x9B:
1203 case 0x9C: case 0x9D: case 0x9E: case 0x9F: /* st */
1204 wlat (cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C), cpu
.gr
[RX
]);
1206 fprintf (stderr
, "store reg %d (containing 0x%lx) to 0x%lx",
1208 cpu
.gr
[RD
] + ((inst
>> 2) & 0x003C));
1211 case 0xA0: case 0xA1: case 0xA2: case 0xA3:
1212 case 0xA4: case 0xA5: case 0xA6: case 0xA7:
1213 case 0xA8: case 0xA9: case 0xAA: case 0xAB:
1214 case 0xAC: case 0xAD: case 0xAE: case 0xAF: /* ld.b */
1215 cpu
.gr
[RX
] = rbat (cpu
.gr
[RD
] + RS
);
1218 case 0xB0: case 0xB1: case 0xB2: case 0xB3:
1219 case 0xB4: case 0xB5: case 0xB6: case 0xB7:
1220 case 0xB8: case 0xB9: case 0xBA: case 0xBB:
1221 case 0xBC: case 0xBD: case 0xBE: case 0xBF: /* st.b */
1222 wbat (cpu
.gr
[RD
] + RS
, cpu
.gr
[RX
]);
1225 case 0xC0: case 0xC1: case 0xC2: case 0xC3:
1226 case 0xC4: case 0xC5: case 0xC6: case 0xC7:
1227 case 0xC8: case 0xC9: case 0xCA: case 0xCB:
1228 case 0xCC: case 0xCD: case 0xCE: case 0xCF: /* ld.h */
1229 cpu
.gr
[RX
] = rhat (cpu
.gr
[RD
] + ((inst
>> 3) & 0x001E));
1232 case 0xD0: case 0xD1: case 0xD2: case 0xD3:
1233 case 0xD4: case 0xD5: case 0xD6: case 0xD7:
1234 case 0xD8: case 0xD9: case 0xDA: case 0xDB:
1235 case 0xDC: case 0xDD: case 0xDE: case 0xDF: /* st.h */
1236 what (cpu
.gr
[RD
] + ((inst
>> 3) & 0x001E), cpu
.gr
[RX
]);
1239 case 0xE8: case 0xE9: case 0xEA: case 0xEB:
1240 case 0xEC: case 0xED: case 0xEE: case 0xEF: /* bf */
1244 disp
= inst
& 0x03FF;
1252 case 0xE0: case 0xE1: case 0xE2: case 0xE3:
1253 case 0xE4: case 0xE5: case 0xE6: case 0xE7: /* bt */
1257 disp
= inst
& 0x03FF;
1266 case 0xF8: case 0xF9: case 0xFA: case 0xFB:
1267 case 0xFC: case 0xFD: case 0xFE: case 0xFF: /* bsr */
1269 case 0xF0: case 0xF1: case 0xF2: case 0xF3:
1270 case 0xF4: case 0xF5: case 0xF6: case 0xF7: /* br */
1273 disp
= inst
& 0x03FF;
1285 fprintf (stderr
, "\n");
1289 ibuf
= rlat (pc
& 0xFFFFFFFC);
1293 while (!cpu
.asregs
.exception
);
1295 /* Hide away the things we've cached while executing. */
1296 CPU_PC_SET (scpu
, pc
);
1297 cpu
.asregs
.insts
+= insts
; /* instructions done ... */
1298 cpu
.asregs
.cycles
+= insts
; /* and each takes a cycle */
1299 cpu
.asregs
.cycles
+= bonus_cycles
; /* and extra cycles for branches */
1300 cpu
.asregs
.cycles
+= memops
* memcycles
; /* and memop cycle delays */
1304 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1306 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1312 /* misalignment safe */
1313 ival
= mcore_extract_unsigned_integer (memory
, 4);
1314 cpu
.asints
[rn
] = ival
;
1324 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
1326 if (rn
< NUM_MCORE_REGS
&& rn
>= 0)
1330 long ival
= cpu
.asints
[rn
];
1332 /* misalignment-safe */
1333 mcore_store_unsigned_integer (memory
, 4, ival
);
1343 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
1345 if (cpu
.asregs
.exception
== SIGQUIT
)
1347 * reason
= sim_exited
;
1348 * sigrc
= cpu
.gr
[PARM1
];
1352 * reason
= sim_stopped
;
1353 * sigrc
= cpu
.asregs
.exception
;
1358 sim_info (SIM_DESC sd
, int verbose
)
1360 #ifdef WATCHFUNCTIONS
1363 double virttime
= cpu
.asregs
.cycles
/ 36.0e6
;
1364 host_callback
*callback
= STATE_CALLBACK (sd
);
1366 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
1368 callback
->printf_filtered (callback
, "# cycles %10d\n",
1370 callback
->printf_filtered (callback
, "# pipeline stalls %10d\n",
1372 callback
->printf_filtered (callback
, "# virtual time taken %10.4f\n",
1375 #ifdef WATCHFUNCTIONS
1376 callback
->printf_filtered (callback
, "\nNumber of watched functions: %d\n",
1381 for (w
= 1; w
<= ENDWL
; w
++)
1383 callback
->printf_filtered (callback
, "WL = %s %8x\n",WLstr
[w
],WL
[w
]);
1384 callback
->printf_filtered (callback
, " calls = %d, cycles = %d\n",
1385 WLcnts
[w
],WLcyc
[w
]);
1388 callback
->printf_filtered (callback
,
1389 " maxcpc = %d, mincpc = %d, avecpc = %d\n",
1390 WLmax
[w
],WLmin
[w
],WLcyc
[w
]/WLcnts
[w
]);
1394 callback
->printf_filtered (callback
,
1395 "Total cycles for watched functions: %d\n",wcyc
);
1400 mcore_pc_get (sim_cpu
*cpu
)
1406 mcore_pc_set (sim_cpu
*cpu
, sim_cia pc
)
1412 free_state (SIM_DESC sd
)
1414 if (STATE_MODULES (sd
) != NULL
)
1415 sim_module_uninstall (sd
);
1416 sim_cpu_free_all (sd
);
1417 sim_state_free (sd
);
1421 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
, struct bfd
*abfd
, char **argv
)
1424 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
1425 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
1427 /* The cpu data is kept in a separately allocated chunk of memory. */
1428 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
1434 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
1440 /* getopt will print the error message so we just have to exit if this fails.
1441 FIXME: Hmmm... in the case of gdb we need getopt to call
1443 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
1449 /* Check for/establish the a reference program image. */
1450 if (sim_analyze_program (sd
,
1451 (STATE_PROG_ARGV (sd
) != NULL
1452 ? *STATE_PROG_ARGV (sd
)
1453 : NULL
), abfd
) != SIM_RC_OK
)
1459 /* Configure/verify the target byte order and other runtime
1460 configuration options. */
1461 if (sim_config (sd
) != SIM_RC_OK
)
1463 sim_module_uninstall (sd
);
1467 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
1469 /* Uninstall the modules to avoid memory leaks,
1470 file descriptor leaks, etc. */
1471 sim_module_uninstall (sd
);
1475 /* CPU specific initialization. */
1476 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
1478 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
1480 CPU_PC_FETCH (cpu
) = mcore_pc_get
;
1481 CPU_PC_STORE (cpu
) = mcore_pc_set
;
1483 set_initial_gprs (cpu
); /* Reset the GPR registers. */
1486 /* Default to a 8 Mbyte (== 2^23) memory space. */
1487 sim_do_commandf (sd
, "memory-size %#x", DEFAULT_MEMORY_SIZE
);
1493 sim_close (SIM_DESC sd
, int quitting
)
1499 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
, char **argv
, char **env
)
1501 SIM_CPU
*scpu
= STATE_CPU (sd
, 0);
1507 unsigned long strings
;
1508 unsigned long pointers
;
1509 unsigned long hi_stack
;
1512 /* Set the initial register set. */
1513 set_initial_gprs (scpu
);
1515 hi_stack
= DEFAULT_MEMORY_SIZE
- 4;
1516 CPU_PC_SET (scpu
, bfd_get_start_address (prog_bfd
));
1518 /* Calculate the argument and environment strings. */
1524 l
= strlen (*avp
) + 1; /* include the null */
1525 s_length
+= (l
+ 3) & ~3; /* make it a 4 byte boundary */
1533 l
= strlen (*avp
) + 1; /* include the null */
1534 s_length
+= (l
+ 3) & ~ 3;/* make it a 4 byte boundary */
1538 /* Claim some memory for the pointers and strings. */
1539 pointers
= hi_stack
- sizeof(word
) * (nenv
+1+nargs
+1);
1540 pointers
&= ~3; /* must be 4-byte aligned */
1541 cpu
.gr
[0] = pointers
;
1543 strings
= cpu
.gr
[0] - s_length
;
1544 strings
&= ~3; /* want to make it 4-byte aligned */
1545 cpu
.gr
[0] = strings
;
1546 /* dac fix, the stack address must be 8-byte aligned! */
1547 cpu
.gr
[0] = cpu
.gr
[0] - cpu
.gr
[0] % 8;
1549 /* Loop through the arguments and fill them in. */
1550 cpu
.gr
[PARM1
] = nargs
;
1553 /* No strings to fill in. */
1558 cpu
.gr
[PARM2
] = pointers
;
1562 /* Save where we're putting it. */
1563 wlat (pointers
, strings
);
1565 /* Copy the string. */
1566 l
= strlen (* avp
) + 1;
1567 sim_core_write_buffer (sd
, scpu
, write_map
, *avp
, strings
, l
);
1569 /* Bump the pointers. */
1575 /* A null to finish the list. */
1580 /* Now do the environment pointers. */
1583 /* No strings to fill in. */
1588 cpu
.gr
[PARM3
] = pointers
;
1593 /* Save where we're putting it. */
1594 wlat (pointers
, strings
);
1596 /* Copy the string. */
1597 l
= strlen (* avp
) + 1;
1598 sim_core_write_buffer (sd
, scpu
, write_map
, *avp
, strings
, l
);
1600 /* Bump the pointers. */
1606 /* A null to finish the list. */
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