1 /* Simulator for Xilinx MicroBlaze processor
2 Copyright 2009-2015 Free Software Foundation, Inc.
4 This file is part of GDB, the GNU debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, see <http://www.gnu.org/licenses/>. */
23 #include <sys/times.h>
24 #include <sys/param.h>
27 #include "gdb/callback.h"
28 #include "libiberty.h"
29 #include "gdb/remote-sim.h"
32 #include "sim-utils.h"
33 #include "microblaze-dis.h"
37 #define NUM_ELEM(A) (sizeof (A) / sizeof (A)[0])
40 static int target_big_endian
= 1;
41 static unsigned long heap_ptr
= 0;
42 static unsigned long stack_ptr
= 0;
43 host_callback
*callback
;
46 microblaze_extract_unsigned_integer (unsigned char *addr
, int len
)
50 unsigned char *startaddr
= (unsigned char *)addr
;
51 unsigned char *endaddr
= startaddr
+ len
;
53 if (len
> (int) sizeof (unsigned long))
54 printf ("That operation is not available on integers of more than "
55 "%zu bytes.", sizeof (unsigned long));
57 /* Start at the most significant end of the integer, and work towards
58 the least significant. */
61 if (!target_big_endian
)
63 for (p
= endaddr
; p
> startaddr
;)
64 retval
= (retval
<< 8) | * -- p
;
68 for (p
= startaddr
; p
< endaddr
;)
69 retval
= (retval
<< 8) | * p
++;
76 microblaze_store_unsigned_integer (unsigned char *addr
, int len
,
80 unsigned char *startaddr
= (unsigned char *)addr
;
81 unsigned char *endaddr
= startaddr
+ len
;
83 if (!target_big_endian
)
85 for (p
= startaddr
; p
< endaddr
;)
93 for (p
= endaddr
; p
> startaddr
;)
101 struct sim_state microblaze_state
;
105 static SIM_OPEN_KIND sim_kind
;
108 static int issue_messages
= 0;
110 static void /* INLINE */
111 wbat (word x
, word v
)
113 if (((uword
)x
) >= CPU
.msize
)
116 fprintf (stderr
, "byte write to 0x%x outside memory range\n", x
);
118 CPU
.exception
= SIGSEGV
;
122 unsigned char *p
= CPU
.memory
+ x
;
127 static void /* INLINE */
128 wlat (word x
, word v
)
130 if (((uword
)x
) >= CPU
.msize
)
133 fprintf (stderr
, "word write to 0x%x outside memory range\n", x
);
135 CPU
.exception
= SIGSEGV
;
142 fprintf (stderr
, "word write to unaligned memory address: 0x%x\n", x
);
144 CPU
.exception
= SIGBUS
;
146 else if (!target_big_endian
)
148 unsigned char *p
= CPU
.memory
+ x
;
156 unsigned char *p
= CPU
.memory
+ x
;
165 static void /* INLINE */
166 what (word x
, word v
)
168 if (((uword
)x
) >= CPU
.msize
)
171 fprintf (stderr
, "short write to 0x%x outside memory range\n", x
);
173 CPU
.exception
= SIGSEGV
;
180 fprintf (stderr
, "short write to unaligned memory address: 0x%x\n",
183 CPU
.exception
= SIGBUS
;
185 else if (!target_big_endian
)
187 unsigned char *p
= CPU
.memory
+ x
;
193 unsigned char *p
= CPU
.memory
+ x
;
200 /* Read functions. */
201 static int /* INLINE */
204 if (((uword
)x
) >= CPU
.msize
)
207 fprintf (stderr
, "byte read from 0x%x outside memory range\n", x
);
209 CPU
.exception
= SIGSEGV
;
214 unsigned char *p
= CPU
.memory
+ x
;
219 static int /* INLINE */
222 if (((uword
) x
) >= CPU
.msize
)
225 fprintf (stderr
, "word read from 0x%x outside memory range\n", x
);
227 CPU
.exception
= SIGSEGV
;
235 fprintf (stderr
, "word read from unaligned address: 0x%x\n", x
);
237 CPU
.exception
= SIGBUS
;
240 else if (! target_big_endian
)
242 unsigned char *p
= CPU
.memory
+ x
;
243 return (p
[3] << 24) | (p
[2] << 16) | (p
[1] << 8) | p
[0];
247 unsigned char *p
= CPU
.memory
+ x
;
248 return (p
[0] << 24) | (p
[1] << 16) | (p
[2] << 8) | p
[3];
253 static int /* INLINE */
256 if (((uword
)x
) >= CPU
.msize
)
259 fprintf (stderr
, "short read from 0x%x outside memory range\n", x
);
261 CPU
.exception
= SIGSEGV
;
269 fprintf (stderr
, "short read from unaligned address: 0x%x\n", x
);
271 CPU
.exception
= SIGBUS
;
274 else if (!target_big_endian
)
276 unsigned char *p
= CPU
.memory
+ x
;
277 return (p
[1] << 8) | p
[0];
281 unsigned char *p
= CPU
.memory
+ x
;
282 return (p
[0] << 8) | p
[1];
287 /* Default to a 8 Mbyte (== 2^23) memory space. */
288 static int sim_memory_size
= 1 << 23;
290 #define MEM_SIZE_FLOOR 64
294 sim_memory_size
= size
;
295 CPU
.msize
= sim_memory_size
;
300 CPU
.memory
= (unsigned char *) calloc (1, CPU
.msize
);
306 "Not enough VM for simulation of %ld bytes of RAM\n",
310 CPU
.memory
= (unsigned char *) calloc (1, 1);
317 if (CPU
.msize
!= (sim_memory_size
))
318 sim_size (sim_memory_size
);
322 set_initial_gprs (void)
326 unsigned long memsize
;
330 /* Set up machine just out of reset. */
334 memsize
= CPU
.msize
/ (1024 * 1024);
336 if (issue_messages
> 1)
337 fprintf (stderr
, "Simulated memory of %ld Mbytes (0x0 .. 0x%08lx)\n",
338 memsize
, CPU
.msize
- 1);
340 /* Clean out the GPRs */
341 for (i
= 0; i
< 32; i
++)
348 #define WATCHFUNCTIONS 1
349 #ifdef WATCHFUNCTIONS
366 static int tracing
= 0;
369 sim_resume (SIM_DESC sd
, int step
, int siggnal
)
373 enum microblaze_instr op
;
385 short delay_slot_enable
;
387 short num_delay_slot
; /* UNUSED except as reqd parameter */
388 enum microblaze_instr_type insn_type
;
390 CPU
.exception
= step
? SIGTRAP
: 0;
398 /* Fetch the initial instructions that we'll decode. */
399 inst
= rlat (PC
& 0xFFFFFFFC);
401 op
= get_insn_microblaze (inst
, &imm_unsigned
, &insn_type
,
404 if (op
== invalid_inst
)
405 fprintf (stderr
, "Unknown instruction 0x%04x", inst
);
408 fprintf (stderr
, "%.4x: inst = %.4x ", PC
, inst
);
413 /* immword = IMM_W; */
416 delay_slot_enable
= 0;
418 if (op
== microblaze_brk
)
419 CPU
.exception
= SIGTRAP
;
420 else if (inst
== MICROBLAZE_HALT_INST
)
422 CPU
.exception
= SIGQUIT
;
430 #define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
434 #include "microblaze.isa"
438 CPU
.exception
= SIGILL
;
439 fprintf (stderr
, "ERROR: Unknown opcode\n");
441 /* Make R0 consistent */
444 /* Check for imm instr */
450 /* Update cycle counts */
452 if (insn_type
== memory_store_inst
|| insn_type
== memory_load_inst
)
454 if (insn_type
== mult_inst
)
456 if (insn_type
== barrel_shift_inst
)
458 if (insn_type
== anyware_inst
)
460 if (insn_type
== div_inst
)
463 if ((insn_type
== branch_inst
|| insn_type
== return_inst
)
466 /* Add an extra cycle for taken branches */
468 /* For branch instructions handle the instruction in the delay slot */
469 if (delay_slot_enable
)
472 PC
= oldpc
+ INST_SIZE
;
473 inst
= rlat (PC
& 0xFFFFFFFC);
474 op
= get_insn_microblaze (inst
, &imm_unsigned
, &insn_type
,
476 if (op
== invalid_inst
)
477 fprintf (stderr
, "Unknown instruction 0x%04x", inst
);
479 fprintf (stderr
, "%.4x: inst = %.4x ", PC
, inst
);
483 /* immword = IMM_W; */
484 if (op
== microblaze_brk
)
487 fprintf (stderr
, "Breakpoint set in delay slot "
488 "(at address 0x%x) will not be honored\n", PC
);
489 /* ignore the breakpoint */
491 else if (insn_type
== branch_inst
|| insn_type
== return_inst
)
494 fprintf (stderr
, "Cannot have branch or return instructions "
495 "in delay slot (at address 0x%x)\n", PC
);
496 CPU
.exception
= SIGILL
;
502 #define INSTRUCTION(NAME, OPCODE, TYPE, ACTION) \
506 #include "microblaze.isa"
510 CPU
.exception
= SIGILL
;
511 fprintf (stderr
, "ERROR: Unknown opcode at 0x%x\n", PC
);
513 /* Update cycle counts */
515 if (insn_type
== memory_store_inst
516 || insn_type
== memory_load_inst
)
518 if (insn_type
== mult_inst
)
520 if (insn_type
== barrel_shift_inst
)
522 if (insn_type
== anyware_inst
)
524 if (insn_type
== div_inst
)
529 /* Make R0 consistent */
531 /* Check for imm instr */
538 /* no delay slot: increment cycle count */
544 fprintf (stderr
, "\n");
546 while (!CPU
.exception
);
548 /* Hide away the things we've cached while executing. */
550 CPU
.insts
+= insts
; /* instructions done ... */
551 CPU
.cycles
+= insts
; /* and each takes a cycle */
552 CPU
.cycles
+= bonus_cycles
; /* and extra cycles for branches */
553 CPU
.cycles
+= memops
; /* and memop cycle delays */
558 sim_write (SIM_DESC sd
, SIM_ADDR addr
, const unsigned char *buffer
, int size
)
563 memcpy (&CPU
.memory
[addr
], buffer
, size
);
569 sim_read (SIM_DESC sd
, SIM_ADDR addr
, unsigned char *buffer
, int size
)
574 memcpy (buffer
, &CPU
.memory
[addr
], size
);
581 sim_store_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
585 if (rn
< NUM_REGS
+ NUM_SPECIAL
&& rn
>= 0)
589 /* misalignment safe */
590 long ival
= microblaze_extract_unsigned_integer (memory
, 4);
594 CPU
.spregs
[rn
-NUM_REGS
] = ival
;
605 sim_fetch_register (SIM_DESC sd
, int rn
, unsigned char *memory
, int length
)
610 if (rn
< NUM_REGS
+ NUM_SPECIAL
&& rn
>= 0)
617 ival
= CPU
.spregs
[rn
-NUM_REGS
];
619 /* misalignment-safe */
620 microblaze_store_unsigned_integer (memory
, 4, ival
);
632 sim_trace (SIM_DESC sd
)
636 sim_resume (sd
, 0, 0);
644 sim_stop_reason (SIM_DESC sd
, enum sim_stop
*reason
, int *sigrc
)
646 if (CPU
.exception
== SIGQUIT
)
648 *reason
= sim_exited
;
653 *reason
= sim_stopped
;
654 *sigrc
= CPU
.exception
;
660 sim_stop (SIM_DESC sd
)
662 CPU
.exception
= SIGINT
;
668 sim_info (SIM_DESC sd
, int verbose
)
670 #ifdef WATCHFUNCTIONS
674 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
676 callback
->printf_filtered (callback
, "# cycles %10d\n",
677 (CPU
.cycles
) ? CPU
.cycles
+2 : 0);
679 #ifdef WATCHFUNCTIONS
680 callback
->printf_filtered (callback
, "\nNumber of watched functions: %d\n",
685 for (w
= 1; w
<= ENDWL
; w
++)
687 callback
->printf_filtered (callback
, "WL = %s %8x\n",WLstr
[w
],WL
[w
]);
688 callback
->printf_filtered (callback
, " calls = %d, cycles = %d\n",
692 callback
->printf_filtered (callback
,
693 " maxcpc = %d, mincpc = %d, avecpc = %d\n",
694 WLmax
[w
],WLmin
[w
],WLcyc
[w
]/WLcnts
[w
]);
698 callback
->printf_filtered (callback
,
699 "Total cycles for watched functions: %d\n",wcyc
);
705 unsigned char sa_machtype
[2];
706 unsigned char sa_magic
[2];
707 unsigned char sa_tsize
[4];
708 unsigned char sa_dsize
[4];
709 unsigned char sa_bsize
[4];
710 unsigned char sa_syms
[4];
711 unsigned char sa_entry
[4];
712 unsigned char sa_trelo
[4];
713 unsigned char sa_drelo
[4];
716 #define LONG(x) (((x)[0]<<24)|((x)[1]<<16)|((x)[2]<<8)|(x)[3])
717 #define SHORT(x) (((x)[0]<<8)|(x)[1])
720 sim_open (SIM_OPEN_KIND kind
, host_callback
*cb
, struct bfd
*abfd
, char **argv
)
722 /* SIM_DESC sd = sim_state_alloc(kind, alloc);*/
724 int osize
= sim_memory_size
;
728 if (kind
== SIM_OPEN_STANDALONE
)
731 /* Discard and reacquire memory -- start with a clean slate. */
732 sim_size (1); /* small */
733 sim_size (osize
); /* and back again */
735 set_initial_gprs (); /* Reset the GPR registers. */
737 return ((SIM_DESC
) 1);
741 sim_close (SIM_DESC sd
, int quitting
)
752 sim_load (SIM_DESC sd
, const char *prog
, bfd
*abfd
, int from_tty
)
754 /* Do the right thing for ELF executables; this turns out to be
755 just about the right thing for any object format that:
756 - we crack using BFD routines
757 - follows the traditional UNIX text/data/bss layout
758 - calls the bss section ".bss". */
760 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
766 int found_loadable_section
= 0;
767 bfd_vma max_addr
= 0;
768 handle
= bfd_openr (prog
, 0);
772 printf("``%s'' could not be opened.\n", prog
);
776 /* Makes sure that we have an object file, also cleans gets the
777 section headers in place. */
778 if (!bfd_check_format (handle
, bfd_object
))
780 /* wasn't an object file */
782 printf ("``%s'' is not appropriate object file.\n", prog
);
786 for (s
= handle
->sections
; s
; s
= s
->next
)
788 if (s
->flags
& SEC_ALLOC
)
791 int size
= bfd_get_section_size (s
);
794 vma
= bfd_section_vma (handle
, s
);
797 max_addr
= vma
+ size
;
800 if (s
->flags
& SEC_LOAD
)
801 found_loadable_section
= 1;
805 if (!found_loadable_section
)
807 /* No loadable sections */
809 printf("No loadable sections in file %s\n", prog
);
813 sim_memory_size
= (unsigned long) max_addr
;
815 /* Clean up after ourselves. */
821 prog_bfd
= sim_load_file (sd
, myname
, callback
, prog
, abfd
,
822 /* sim_kind == SIM_OPEN_DEBUG, */
825 if (prog_bfd
== NULL
)
828 target_big_endian
= bfd_big_endian (prog_bfd
);
829 PC
= bfd_get_start_address (prog_bfd
);
832 bfd_close (prog_bfd
);
838 sim_create_inferior (SIM_DESC sd
, struct bfd
*prog_bfd
, char **argv
, char **env
)
845 unsigned long strings
;
846 unsigned long pointers
;
847 unsigned long hi_stack
;
850 /* Set the initial register set. */
856 hi_stack
= CPU
.msize
- 4;
857 PC
= bfd_get_start_address (prog_bfd
);
859 /* For now ignore all parameters to the program */
865 sim_do_command (SIM_DESC sd
, const char *cmd
)
867 /* Nothing there yet; it's all an error. */
871 char ** simargv
= buildargv (cmd
);
873 if (strcmp (simargv
[0], "watch") == 0)
875 if ((simargv
[1] == NULL
) || (simargv
[2] == NULL
))
877 fprintf (stderr
, "Error: missing argument to watch cmd.\n");
884 WL
[ENDWL
] = strtol (simargv
[2], NULL
, 0);
885 WLstr
[ENDWL
] = strdup (simargv
[1]);
886 fprintf (stderr
, "Added %s (%x) to watchlist, #%d\n",WLstr
[ENDWL
],
890 else if (strcmp (simargv
[0], "dumpmem") == 0)
895 if (simargv
[1] == NULL
)
896 fprintf (stderr
, "Error: missing argument to dumpmem cmd.\n");
898 fprintf (stderr
, "Writing dumpfile %s...",simargv
[1]);
900 dumpfile
= fopen (simargv
[1], "w");
902 fwrite (p
, CPU
.msize
-1, 1, dumpfile
);
905 fprintf (stderr
, "done.\n");
907 else if (strcmp (simargv
[0], "clearstats") == 0)
913 else if (strcmp (simargv
[0], "verbose") == 0)
919 fprintf (stderr
,"Error: \"%s\" is not a valid M.CORE simulator command.\n",
927 fprintf (stderr
, "M.CORE sim commands: \n");
928 fprintf (stderr
, " watch <funcname> <addr>\n");
929 fprintf (stderr
, " dumpmem <filename>\n");
930 fprintf (stderr
, " clearstats\n");
931 fprintf (stderr
, " verbose\n");
936 sim_set_callbacks (host_callback
*ptr
)
942 sim_complete_command (SIM_DESC sd
, const char *text
, const char *word
)