sim/mips/ChangeLog

   1 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * mips.igen (mipsV): New model name.  Also, add it to
   4         all instructions and functions where it is appropriate.
   5
   6 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
   7
   8         * mips.igen: For all functions and instructions, list model
   9         names that support that instruction one per line.
  10
  11 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
  12
  13         * mips.igen: Add some additional comments about supported
  14         models, and about which instructions go where.
  15         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
  16         order as is used in the rest of the file.
  17
  18 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
  19
  20         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
  21         indicating that ALU32_END or ALU64_END are there to check
  22         for overflow.
  23         (DADD): Likewise, but also remove previous comment about
  24         overflow checking.
  25
  26 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
  27
  28         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
  29         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
  30         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
  31         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
  32         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
  33         fields (i.e., add and move commas) so that they more closely
  34         match the MIPS ISA documentation opcode partitioning.
  35
  36 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
  37
  38         * mips.igen (ADDI): Print immediate value.
  39         (BREAK): Print code.
  40         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
  41         (SLL): Print "nop" specially, and don't run the code
  42         that does the shift for the "nop" case.
  43
  44 2001-11-17  Fred Fish  <fnf@redhat.com>
  45
  46         * sim-main.h (float_operation): Move enum declaration outside
  47         of _sim_cpu struct declaration.
  48
  49 2001-04-12  Jim Blandy  <jimb@redhat.com>
  50
  51         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
  52         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
  53         set of the FCSR.
  54         * sim-main.h (COCIDX): Remove definition; this isn't supported by
  55         PENDING_FILL, and you can get the intended effect gracefully by
  56         calling PENDING_SCHED directly.
  57
  58 2001-02-23  Ben Elliston  <bje@redhat.com>
  59
  60         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
  61         already defined elsewhere.
  62
  63 2001-02-19  Ben Elliston  <bje@redhat.com>
  64
  65         * sim-main.h (sim_monitor): Return an int.
  66         * interp.c (sim_monitor): Add return values.
  67         (signal_exception): Handle error conditions from sim_monitor.
  68
  69 2001-02-08  Ben Elliston  <bje@redhat.com>
  70
  71         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
  72         (store_memory): Likewise, pass cia to sim_core_write*.
  73
  74 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
  75
  76         On advice from Chris G. Demetriou <cgd@sibyte.com>:
  77         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
  78
  79 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
  80
  81         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
  82         * Makefile.in: Don't delete *.igen when cleaning directory.
  83
  84 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
  85
  86         * m16.igen (break): Call SignalException not sim_engine_halt.
  87
  88 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
  89
  90         From Jason Eckhardt:
  91         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
  92
  93 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
  94
  95         * mips.igen (MxC1, DMxC1): Fix printf formatting.
  96
  97 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
  98
  99         * mips.igen (do_dmultx): Fix typo.
 100
 101 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 102
 103         * configure: Regenerated to track ../common/aclocal.m4 changes.
 104
 105 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 106
 107         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 108
 109 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 110
 111         * sim-main.h (GPR_CLEAR): Define macro.
 112
 113 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 114
 115         * interp.c (decode_coproc): Output long using %lx and not %s.
 116
 117 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 118
 119         * interp.c (sim_open): Sort & extend dummy memory regions for
 120         --board=jmr3904 for eCos.
 121
 122 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 123
 124         * configure: Regenerated.
 125
 126 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 127
 128         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 129         calls, conditional on the simulator being in verbose mode.
 130
 131 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 132
 133         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 134         cache don't get ReservedInstruction traps.
 135
 136 1999-11-29  Mark Salter  <msalter@cygnus.com>
 137
 138         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 139         to clear status bits in sdisr register. This is how the hardware works.
 140
 141         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 142         being used by cygmon.
 143
 144 1999-11-11  Andrew Haley  <aph@cygnus.com>
 145
 146         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 147         instructions.
 148
 149 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 150
 151         * mips.igen (MULT): Correct previous mis-applied patch.
 152
 153 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 154
 155         * mips.igen (delayslot32): Handle sequence like
 156         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 157         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 158         (MULT): Actually pass the third register...
 159
 160 1999-09-03  Mark Salter  <msalter@cygnus.com>
 161
 162         * interp.c (sim_open): Added more memory aliases for additional
 163         hardware being touched by cygmon on jmr3904 board.
 164
 165 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 166
 167         * configure: Regenerated to track ../common/aclocal.m4 changes.
 168
 169 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 170
 171         * interp.c (sim_store_register): Handle case where client - GDB -
 172         specifies that a 4 byte register is 8 bytes in size.
 173         (sim_fetch_register): Ditto.
 174
 175 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 176
 177         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 178         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 179         (idt_monitor_base): Base address for IDT monitor traps.
 180         (pmon_monitor_base): Ditto for PMON.
 181         (lsipmon_monitor_base): Ditto for LSI PMON.
 182         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 183         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 184         (sim_firmware_command): New function.
 185         (mips_option_handler): Call it for OPTION_FIRMWARE.
 186         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 187         option was given, add no monitor by default.  Add BREAK hooks only if
 188         monitors are also there.
 189
 190 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 191
 192         * interp.c (sim_monitor): Flush output before reading input.
 193
 194 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 195
 196         * tconfig.in (SIM_HANDLES_LMA): Always define.
 197
 198 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 199
 200         From Mark Salter <msalter@cygnus.com>:
 201         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 202         (sim_open): Add setup for BSP board.
 203
 204 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 205
 206         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 207         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 208         them as unimplemented.
 209
 210 1999-05-08  Felix Lee  <flee@cygnus.com>
 211
 212         * configure: Regenerated to track ../common/aclocal.m4 changes.
 213
 214 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 215
 216         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 217
 218 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 219
 220         * configure.in: Any mips64vr5*-*-* target should have
 221         -DTARGET_ENABLE_FR=1.
 222         (default_endian): Any mips64vr*el-*-* target should default to
 223         LITTLE_ENDIAN.
 224         * configure: Re-generate.
 225
 226 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 227
 228         * mips.igen (ldl): Extend from _16_, not 32.
 229
 230 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 231
 232         * interp.c (sim_store_register): Force registers written to by GDB
 233         into an un-interpreted state.
 234
 235 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 236
 237         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 238         CPU, start periodic background I/O polls.
 239         (tx3904sio_poll): New function: periodic I/O poller.
 240
 241 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 242
 243         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 244
 245 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 246
 247         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 248         case statement.
 249
 250 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 251
 252         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 253         (load_word): Call SIM_CORE_SIGNAL hook on error.
 254         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 255         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 256         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 257         * sim-main.h (COP0_BADVADDR): Define.
 258         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 259         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 260         (_sim_cpu): Add exc_* fields to store register value snapshots.
 261         * mips.igen (*): Replace memory-related SignalException* calls
 262         with references to SIM_CORE_SIGNAL hook.
 263
 264         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 265         fix.
 266         * sim-main.c (*): Minor warning cleanups.
 267
 268 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 269
 270         * m16.igen (DADDIU5): Correct type-o.
 271
 272 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 273
 274         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 275         variables.
 276
 277 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 278
 279         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 280         to include path.
 281         (interp.o): Add dependency on itable.h
 282         (oengine.c, gencode): Delete remaining references.
 283         (BUILT_SRC_FROM_GEN): Clean up.
 284
 285 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 286
 287         * vr4run.c: New.
 288         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 289         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 290         tmp-run-hack) : New.
 291         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 292         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 293         Drop the "64" qualifier to get the HACK generator working.
 294         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 295         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 296         qualifier to get the hack generator working.
 297         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 298         (DSLL): Use do_dsll.
 299         (DSLLV): Use do_dsllv.
 300         (DSRA): Use do_dsra.
 301         (DSRL): Use do_dsrl.
 302         (DSRLV): Use do_dsrlv.
 303         (BC1): Move *vr4100 to get the HACK generator working.
 304         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 305         get the HACK generator working.
 306         (MACC) Rename to get the HACK generator working.
 307         (DMACC,MACCS,DMACCS): Add the 64.
 308
 309 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 310
 311         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 312         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 313
 314 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 315
 316     * mips/interp.c (DEBUG): Cleanups.
 317
 318 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 319
 320         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 321         (tx3904sio_tickle): fflush after a stdout character output.
 322
 323 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 324
 325         * interp.c (sim_close): Uninstall modules.
 326
 327 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 328
 329         * sim-main.h, interp.c (sim_monitor): Change to global
 330         function.
 331
 332 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 333
 334         * configure.in (vr4100): Only include vr4100 instructions in
 335         simulator.
 336         * configure: Re-generate.
 337         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 338
 339 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 340
 341         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 342         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 343         true alternative.
 344
 345         * configure.in (sim_default_gen, sim_use_gen): Replace with
 346         sim_gen.
 347         (--enable-sim-igen): Delete config option. Always using IGEN.
 348         * configure: Re-generate.
 349
 350         * Makefile.in (gencode): Kill, kill, kill.
 351         * gencode.c: Ditto.
 352
 353 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 354
 355         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 356         bit mips16 igen simulator.
 357         * configure: Re-generate.
 358
 359         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 360         as part of vr4100 ISA.
 361         * vr.igen: Mark all instructions as 64 bit only.
 362
 363 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 364
 365         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 366         Pacify GCC.
 367
 368 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 369
 370         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 371         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 372         * configure: Re-generate.
 373
 374         * m16.igen (BREAK): Define breakpoint instruction.
 375         (JALX32): Mark instruction as mips16 and not r3900.
 376         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 377
 378         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 379
 380 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 381
 382         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 383         insn as a debug breakpoint.
 384
 385         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 386         pending.slot_size.
 387         (PENDING_SCHED): Clean up trace statement.
 388         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 389         (PENDING_FILL): Delay write by only one cycle.
 390         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 391
 392         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 393         of pending writes.
 394         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 395         32 & 64.
 396         (pending_tick): Move incrementing of index to FOR statement.
 397         (pending_tick): Only update PENDING_OUT after a write has occured.
 398
 399         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 400         build simulator.
 401         * configure: Re-generate.
 402
 403         * interp.c (sim_engine_run OLD): Delete explicit call to
 404         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 405
 406 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 407
 408         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 409         interrupt level number to match changed SignalExceptionInterrupt
 410         macro.
 411
 412 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 413
 414         * interp.c: #include "itable.h" if WITH_IGEN.
 415         (get_insn_name): New function.
 416         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 417         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 418
 419 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 420
 421         * configure: Rebuilt to inhale new common/aclocal.m4.
 422
 423 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 424
 425         * dv-tx3904sio.c: Include sim-assert.h.
 426
 427 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 428
 429         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 430         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 431         Reorganize target-specific sim-hardware checks.
 432         * configure: rebuilt.
 433         * interp.c (sim_open): For tx39 target boards, set
 434         OPERATING_ENVIRONMENT, add tx3904sio devices.
 435         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 436         ROM executables.  Install dv-sockser into sim-modules list.
 437
 438         * dv-tx3904irc.c: Compiler warning clean-up.
 439         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 440         frequent hw-trace messages.
 441
 442 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 443
 444         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 445
 446 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 447
 448         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 449
 450         * vr.igen: New file.
 451         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 452         * mips.igen: Define vr4100 model. Include vr.igen.
 453 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 454
 455         * mips.igen (check_mf_hilo): Correct check.
 456
 457 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 458
 459         * sim-main.h (interrupt_event): Add prototype.
 460
 461         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 462         register_ptr, register_value.
 463         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 464
 465         * sim-main.h (tracefh): Make extern.
 466
 467 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 468
 469         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 470         Reduce unnecessarily high timer event frequency.
 471         * dv-tx3904cpu.c: Ditto for interrupt event.
 472
 473 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 474
 475         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 476         to allay warnings.
 477         (interrupt_event): Made non-static.
 478
 479         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 480         interchange of configuration values for external vs. internal
 481         clock dividers.
 482
 483 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 484
 485         * mips.igen (BREAK): Moved code to here for
 486         simulator-reserved break instructions.
 487         * gencode.c (build_instruction): Ditto.
 488         * interp.c (signal_exception): Code moved from here.  Non-
 489         reserved instructions now use exception vector, rather
 490         than halting sim.
 491         * sim-main.h: Moved magic constants to here.
 492
 493 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 494
 495         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 496         register upon non-zero interrupt event level, clear upon zero
 497         event value.
 498         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 499         by passing zero event value.
 500         (*_io_{read,write}_buffer): Endianness fixes.
 501         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 502         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 503
 504         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 505         serial I/O and timer module at base address 0xFFFF0000.
 506
 507 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 508
 509         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 510         and BigEndianCPU.
 511
 512 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 513
 514         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 515         parts.
 516         * configure: Update.
 517
 518 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 519
 520         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 521         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 522         * configure.in: Include tx3904tmr in hw_device list.
 523         * configure: Rebuilt.
 524         * interp.c (sim_open): Instantiate three timer instances.
 525         Fix address typo of tx3904irc instance.
 526
 527 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 528
 529         * interp.c (signal_exception): SystemCall exception now uses
 530         the exception vector.
 531
 532 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 533
 534         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 535         to allay warnings.
 536
 537 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 538
 539         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 540
 541 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 542
 543         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 544
 545         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 546         sim-main.h. Declare a struct hw_descriptor instead of struct
 547         hw_device_descriptor.
 548
 549 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 550
 551         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 552         right bits and then re-align left hand bytes to correct byte
 553         lanes.  Fix incorrect computation in do_store_left when loading
 554         bytes from second word.
 555
 556 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 557
 558         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 559         * interp.c (sim_open): Only create a device tree when HW is
 560         enabled.
 561
 562         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 563         * interp.c (signal_exception): Ditto.
 564
 565 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 566
 567         * gencode.c: Mark BEGEZALL as LIKELY.
 568
 569 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 570
 571         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 572         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 573
 574 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 575
 576         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 577         modules.  Recognize TX39 target with "mips*tx39" pattern.
 578         * configure: Rebuilt.
 579         * sim-main.h (*): Added many macros defining bits in
 580         TX39 control registers.
 581         (SignalInterrupt): Send actual PC instead of NULL.
 582         (SignalNMIReset): New exception type.
 583         * interp.c (board): New variable for future use to identify
 584         a particular board being simulated.
 585         (mips_option_handler,mips_options): Added "--board" option.
 586         (interrupt_event): Send actual PC.
 587         (sim_open): Make memory layout conditional on board setting.
 588         (signal_exception): Initial implementation of hardware interrupt
 589         handling.  Accept another break instruction variant for simulator
 590         exit.
 591         (decode_coproc): Implement RFE instruction for TX39.
 592         (mips.igen): Decode RFE instruction as such.
 593         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 594         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 595         bbegin to implement memory map.
 596         * dv-tx3904cpu.c: New file.
 597         * dv-tx3904irc.c: New file.
 598
 599 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 600
 601         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 602
 603 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 604
 605         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 606         with calls to check_div_hilo.
 607
 608 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 609
 610         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 611         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 612         Add special r3900 version of do_mult_hilo.
 613         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 614         with calls to check_mult_hilo.
 615         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 616         with calls to check_div_hilo.
 617
 618 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 619
 620         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 621         Document a replacement.
 622
 623 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 624
 625         * interp.c (sim_monitor): Make mon_printf work.
 626
 627 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 628
 629         * sim-main.h (INSN_NAME): New arg `cpu'.
 630
 631 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 632
 633         * configure: Regenerated to track ../common/aclocal.m4 changes.
 634
 635 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 636
 637         * configure: Regenerated to track ../common/aclocal.m4 changes.
 638         * config.in: Ditto.
 639
 640 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 641
 642         * acconfig.h: New file.
 643         * configure.in: Reverted change of Apr 24; use sinclude again.
 644
 645 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 646
 647         * configure: Regenerated to track ../common/aclocal.m4 changes.
 648         * config.in: Ditto.
 649
 650 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 651
 652         * configure.in: Don't call sinclude.
 653
 654 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 655
 656         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 657
 658 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 659
 660         * mips.igen (ERET): Implement.
 661
 662         * interp.c (decode_coproc): Return sign-extended EPC.
 663
 664         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 665
 666         * interp.c (signal_exception): Do not ignore Trap.
 667         (signal_exception): On TRAP, restart at exception address.
 668         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 669         (signal_exception): Update.
 670         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 671         so that TRAP instructions are caught.
 672
 673 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 674
 675         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 676         contains HI/LO access history.
 677         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 678         (HIACCESS, LOACCESS): Delete, replace with
 679         (HIHISTORY, LOHISTORY): New macros.
 680         (CHECKHILO): Delete all, moved to mips.igen
 681
 682         * gencode.c (build_instruction): Do not generate checks for
 683         correct HI/LO register usage.
 684
 685         * interp.c (old_engine_run): Delete checks for correct HI/LO
 686         register usage.
 687
 688         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 689         check_mf_cycles): New functions.
 690         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 691         do_divu, domultx, do_mult, do_multu): Use.
 692
 693         * tx.igen ("madd", "maddu"): Use.
 694
 695 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 696
 697         * mips.igen (DSRAV): Use function do_dsrav.
 698         (SRAV): Use new function do_srav.
 699
 700         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 701         (B): Sign extend 11 bit immediate.
 702         (EXT-B*): Shift 16 bit immediate left by 1.
 703         (ADDIU*): Don't sign extend immediate value.
 704
 705 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 706
 707         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 708
 709         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 710         functions.
 711
 712         * mips.igen (delayslot32, nullify_next_insn): New functions.
 713         (m16.igen): Always include.
 714         (do_*): Add more tracing.
 715
 716         * m16.igen (delayslot16): Add NIA argument, could be called by a
 717         32 bit MIPS16 instruction.
 718
 719         * interp.c (ifetch16): Move function from here.
 720         * sim-main.c (ifetch16): To here.
 721
 722         * sim-main.c (ifetch16, ifetch32): Update to match current
 723         implementations of LH, LW.
 724         (signal_exception): Don't print out incorrect hex value of illegal
 725         instruction.
 726
 727 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 728
 729         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 730         instruction.
 731
 732         * m16.igen: Implement MIPS16 instructions.
 733
 734         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 735         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 736         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 737         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 738         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 739         bodies of corresponding code from 32 bit insn to these.  Also used
 740         by MIPS16 versions of functions.
 741
 742         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 743         (IMEM16): Drop NR argument from macro.
 744
 745 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 746
 747         * Makefile.in (SIM_OBJS): Add sim-main.o.
 748
 749         * sim-main.h (address_translation, load_memory, store_memory,
 750         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 751         as INLINE_SIM_MAIN.
 752         (pr_addr, pr_uword64): Declare.
 753         (sim-main.c): Include when H_REVEALS_MODULE_P.
 754
 755         * interp.c (address_translation, load_memory, store_memory,
 756         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 757         from here.
 758         * sim-main.c: To here. Fix compilation problems.
 759
 760         * configure.in: Enable inlining.
 761         * configure: Re-config.
 762
 763 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 764
 765         * configure: Regenerated to track ../common/aclocal.m4 changes.
 766
 767 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 768
 769         * mips.igen: Include tx.igen.
 770         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 771         * tx.igen: New file, contains MADD and MADDU.
 772
 773         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 774         the hardwired constant `7'.
 775         (store_memory): Ditto.
 776         (LOADDRMASK): Move definition to sim-main.h.
 777
 778         mips.igen (MTC0): Enable for r3900.
 779         (ADDU): Add trace.
 780
 781         mips.igen (do_load_byte): Delete.
 782         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 783         do_store_right): New functions.
 784         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 785
 786         configure.in: Let the tx39 use igen again.
 787         configure: Update.
 788
 789 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 790
 791         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 792         not an address sized quantity.  Return zero for cache sizes.
 793
 794 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 795
 796         * mips.igen (r3900): r3900 does not support 64 bit integer
 797         operations.
 798
 799 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 800
 801         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 802         than igen one.
 803         * configure : Rebuild.
 804
 805 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 806
 807         * configure: Regenerated to track ../common/aclocal.m4 changes.
 808
 809 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 810
 811         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
 812
 813 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
 814
 815         * configure: Regenerated to track ../common/aclocal.m4 changes.
 816         * config.in: Regenerated to track ../common/aclocal.m4 changes.
 817
 818 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 819
 820         * configure: Regenerated to track ../common/aclocal.m4 changes.
 821
 822 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 823
 824         * interp.c (Max, Min): Comment out functions. Not yet used.
 825
 826 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 827
 828         * configure: Regenerated to track ../common/aclocal.m4 changes.
 829
 830 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
 831
 832         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 833         configurable settings for stand-alone simulator.
 834
 835         * configure.in: Added X11 search, just in case.
 836
 837         * configure: Regenerated.
 838
 839 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 840
 841         * interp.c (sim_write, sim_read, load_memory, store_memory):
 842         Replace sim_core_*_map with read_map, write_map, exec_map resp.
 843
 844 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 845
 846         * sim-main.h (GETFCC): Return an unsigned value.
 847
 848 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 849
 850         * mips.igen (DIV): Fix check for -1 / MIN_INT.
 851         (DADD): Result destination is RD not RT.
 852
 853 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 854
 855         * sim-main.h (HIACCESS, LOACCESS): Always define.
 856
 857         * mdmx.igen (Maxi, Mini): Rename Max, Min.
 858
 859         * interp.c (sim_info): Delete.
 860
 861 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
 862
 863         * interp.c (DECLARE_OPTION_HANDLER): Use it.
 864         (mips_option_handler): New argument `cpu'.
 865         (sim_open): Update call to sim_add_option_table.
 866
 867 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 868
 869         * mips.igen (CxC1): Add tracing.
 870
 871 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 872
 873         * sim-main.h (Max, Min): Declare.
 874
 875         * interp.c (Max, Min): New functions.
 876
 877         * mips.igen (BC1): Add tracing.
 878
 879 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
 880
 881         * interp.c Added memory map for stack in vr4100
 882
 883 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
 884
 885         * interp.c (load_memory): Add missing "break"'s.
 886
 887 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 888
 889         * interp.c (sim_store_register, sim_fetch_register): Pass in
 890         length parameter.  Return -1.
 891
 892 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
 893
 894         * interp.c: Added hardware init hook, fixed warnings.
 895
 896 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 897
 898         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
 899
 900 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 901
 902         * interp.c (ifetch16): New function.
 903
 904         * sim-main.h (IMEM32): Rename IMEM.
 905         (IMEM16_IMMED): Define.
 906         (IMEM16): Define.
 907         (DELAY_SLOT): Update.
 908
 909         * m16run.c (sim_engine_run): New file.
 910
 911         * m16.igen: All instructions except LB.
 912         (LB): Call do_load_byte.
 913         * mips.igen (do_load_byte): New function.
 914         (LB): Call do_load_byte.
 915
 916         * mips.igen: Move spec for insn bit size and high bit from here.
 917         * Makefile.in (tmp-igen, tmp-m16): To here.
 918
 919         * m16.dc: New file, decode mips16 instructions.
 920
 921         * Makefile.in (SIM_NO_ALL): Define.
 922         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
 923
 924 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 925
 926         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
 927         point unit to 32 bit registers.
 928         * configure: Re-generate.
 929
 930 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 931
 932         * configure.in (sim_use_gen): Make IGEN the default simulator
 933         generator for generic 32 and 64 bit mips targets.
 934         * configure: Re-generate.
 935
 936 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 937
 938         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
 939         bitsize.
 940
 941         * interp.c (sim_fetch_register, sim_store_register): Read/write
 942         FGR from correct location.
 943         (sim_open): Set size of FGR's according to
 944         WITH_TARGET_FLOATING_POINT_BITSIZE.
 945
 946         * sim-main.h (FGR): Store floating point registers in a separate
 947         array.
 948
 949 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 950
 951         * configure: Regenerated to track ../common/aclocal.m4 changes.
 952
 953 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 954
 955         * interp.c (ColdReset): Call PENDING_INVALIDATE.
 956
 957         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
 958
 959         * interp.c (pending_tick): New function.  Deliver pending writes.
 960
 961         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
 962         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
 963         it can handle mixed sized quantites and single bits.
 964
 965 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 966
 967         * interp.c (oengine.h): Do not include when building with IGEN.
 968         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
 969         (sim_info): Ditto for PROCESSOR_64BIT.
 970         (sim_monitor): Replace ut_reg with unsigned_word.
 971         (*): Ditto for t_reg.
 972         (LOADDRMASK): Define.
 973         (sim_open): Remove defunct check that host FP is IEEE compliant,
 974         using software to emulate floating point.
 975         (value_fpr, ...): Always compile, was conditional on HASFPU.
 976
 977 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 978
 979         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
 980         size.
 981
 982         * interp.c (SD, CPU): Define.
 983         (mips_option_handler): Set flags in each CPU.
 984         (interrupt_event): Assume CPU 0 is the one being iterrupted.
 985         (sim_close): Do not clear STATE, deleted anyway.
 986         (sim_write, sim_read): Assume CPU zero's vm should be used for
 987         data transfers.
 988         (sim_create_inferior): Set the PC for all processors.
 989         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
 990         argument.
 991         (mips16_entry): Pass correct nr of args to store_word, load_word.
 992         (ColdReset): Cold reset all cpu's.
 993         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
 994         (sim_monitor, load_memory, store_memory, signal_exception): Use
 995         `CPU' instead of STATE_CPU.
 996
 997
 998         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
 999         SD or CPU_.
1000
1001         * sim-main.h (signal_exception): Add sim_cpu arg.
1002         (SignalException*): Pass both SD and CPU to signal_exception.
1003         * interp.c (signal_exception): Update.
1004
1005         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1006         Ditto
1007         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1008         address_translation): Ditto
1009         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1010
1011 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1012
1013         * configure: Regenerated to track ../common/aclocal.m4 changes.
1014
1015 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1016
1017         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1018
1019         * mips.igen (model): Map processor names onto BFD name.
1020
1021         * sim-main.h (CPU_CIA): Delete.
1022         (SET_CIA, GET_CIA): Define
1023
1024 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1025
1026         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1027         regiser.
1028
1029         * configure.in (default_endian): Configure a big-endian simulator
1030         by default.
1031         * configure: Re-generate.
1032
1033 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1034
1035         * configure: Regenerated to track ../common/aclocal.m4 changes.
1036
1037 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1038
1039         * interp.c (sim_monitor): Handle Densan monitor outbyte
1040         and inbyte functions.
1041
1042 1997-12-29  Felix Lee  <flee@cygnus.com>
1043
1044         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1045
1046 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1047
1048         * Makefile.in (tmp-igen): Arrange for $zero to always be
1049         reset to zero after every instruction.
1050
1051 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1052
1053         * configure: Regenerated to track ../common/aclocal.m4 changes.
1054         * config.in: Ditto.
1055
1056 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1057
1058         * mips.igen (MSUB): Fix to work like MADD.
1059         * gencode.c (MSUB): Similarly.
1060
1061 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1062
1063         * configure: Regenerated to track ../common/aclocal.m4 changes.
1064
1065 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1066
1067         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1068
1069 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1070
1071         * sim-main.h (sim-fpu.h): Include.
1072
1073         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1074         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1075         using host independant sim_fpu module.
1076
1077 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1078
1079         * interp.c (signal_exception): Report internal errors with SIGABRT
1080         not SIGQUIT.
1081
1082         * sim-main.h (C0_CONFIG): New register.
1083         (signal.h): No longer include.
1084
1085         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1086
1087 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1088
1089         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1090
1091 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1092
1093         * mips.igen: Tag vr5000 instructions.
1094         (ANDI): Was missing mipsIV model, fix assembler syntax.
1095         (do_c_cond_fmt): New function.
1096         (C.cond.fmt): Handle mips I-III which do not support CC field
1097         separatly.
1098         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1099         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1100         in IV3.2 spec.
1101         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1102         vr5000 which saves LO in a GPR separatly.
1103
1104         * configure.in (enable-sim-igen): For vr5000, select vr5000
1105         specific instructions.
1106         * configure: Re-generate.
1107
1108 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1109
1110         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1111
1112         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1113         fmt_uninterpreted_64 bit cases to switch.  Convert to
1114         fmt_formatted,
1115
1116         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1117
1118         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1119         as specified in IV3.2 spec.
1120         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1121
1122 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1123
1124         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1125         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1126         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1127         PENDING_FILL versions of instructions.  Simplify.
1128         (X): New function.
1129         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1130         instructions.
1131         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1132         a signed value.
1133         (MTHI, MFHI): Disable code checking HI-LO.
1134
1135         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1136         global.
1137         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1138
1139 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1140
1141         * gencode.c (build_mips16_operands): Replace IPC with cia.
1142
1143         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1144         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1145         IPC to `cia'.
1146         (UndefinedResult): Replace function with macro/function
1147         combination.
1148         (sim_engine_run): Don't save PC in IPC.
1149
1150         * sim-main.h (IPC): Delete.
1151
1152
1153         * interp.c (signal_exception, store_word, load_word,
1154         address_translation, load_memory, store_memory, cache_op,
1155         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1156         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1157         current instruction address - cia - argument.
1158         (sim_read, sim_write): Call address_translation directly.
1159         (sim_engine_run): Rename variable vaddr to cia.
1160         (signal_exception): Pass cia to sim_monitor
1161
1162         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1163         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1164         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1165
1166         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1167         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1168         SIM_ASSERT.
1169
1170         * interp.c (signal_exception): Pass restart address to
1171         sim_engine_restart.
1172
1173         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1174         idecode.o): Add dependency.
1175
1176         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1177         Delete definitions
1178         (DELAY_SLOT): Update NIA not PC with branch address.
1179         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1180
1181         * mips.igen: Use CIA not PC in branch calculations.
1182         (illegal): Call SignalException.
1183         (BEQ, ADDIU): Fix assembler.
1184
1185 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1186
1187         * m16.igen (JALX): Was missing.
1188
1189         * configure.in (enable-sim-igen): New configuration option.
1190         * configure: Re-generate.
1191
1192         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1193
1194         * interp.c (load_memory, store_memory): Delete parameter RAW.
1195         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1196         bypassing {load,store}_memory.
1197
1198         * sim-main.h (ByteSwapMem): Delete definition.
1199
1200         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1201
1202         * interp.c (sim_do_command, sim_commands): Delete mips specific
1203         commands.  Handled by module sim-options.
1204
1205         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1206         (WITH_MODULO_MEMORY): Define.
1207
1208         * interp.c (sim_info): Delete code printing memory size.
1209
1210         * interp.c (mips_size): Nee sim_size, delete function.
1211         (power2): Delete.
1212         (monitor, monitor_base, monitor_size): Delete global variables.
1213         (sim_open, sim_close): Delete code creating monitor and other
1214         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1215         manage memory regions.
1216         (load_memory, store_memory): Use sim-core for memory model.
1217
1218         * interp.c (address_translation): Delete all memory map code
1219         except line forcing 32 bit addresses.
1220
1221 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1222
1223         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1224         trace options.
1225
1226         * interp.c (logfh, logfile): Delete globals.
1227         (sim_open, sim_close): Delete code opening & closing log file.
1228         (mips_option_handler): Delete -l and -n options.
1229         (OPTION mips_options): Ditto.
1230
1231         * interp.c (OPTION mips_options): Rename option trace to dinero.
1232         (mips_option_handler): Update.
1233
1234 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1235
1236         * interp.c (fetch_str): New function.
1237         (sim_monitor): Rewrite using sim_read & sim_write.
1238         (sim_open): Check magic number.
1239         (sim_open): Write monitor vectors into memory using sim_write.
1240         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1241         (sim_read, sim_write): Simplify - transfer data one byte at a
1242         time.
1243         (load_memory, store_memory): Clarify meaning of parameter RAW.
1244
1245         * sim-main.h (isHOST): Defete definition.
1246         (isTARGET): Mark as depreciated.
1247         (address_translation): Delete parameter HOST.
1248
1249         * interp.c (address_translation): Delete parameter HOST.
1250
1251 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1252
1253         * mips.igen:
1254
1255         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1256         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1257
1258 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1259
1260         * mips.igen: Add model filter field to records.
1261
1262 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1263
1264         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1265
1266         interp.c (sim_engine_run): Do not compile function sim_engine_run
1267         when WITH_IGEN == 1.
1268
1269         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1270         target architecture.
1271
1272         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1273         igen. Replace with configuration variables sim_igen_flags /
1274         sim_m16_flags.
1275
1276         * m16.igen: New file.  Copy mips16 insns here.
1277         * mips.igen: From here.
1278
1279 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1280
1281         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1282         to top.
1283         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1284
1285 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1286
1287         * gencode.c (build_instruction): Follow sim_write's lead in using
1288         BigEndianMem instead of !ByteSwapMem.
1289
1290 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1291
1292         * configure.in (sim_gen): Dependent on target, select type of
1293         generator.  Always select old style generator.
1294
1295         configure: Re-generate.
1296
1297         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1298         targets.
1299         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1300         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1301         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1302         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1303         SIM_@sim_gen@_*, set by autoconf.
1304
1305 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1306
1307         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1308
1309         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1310         CURRENT_FLOATING_POINT instead.
1311
1312         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1313         (address_translation): Raise exception InstructionFetch when
1314         translation fails and isINSTRUCTION.
1315
1316         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1317         sim_engine_run): Change type of of vaddr and paddr to
1318         address_word.
1319         (address_translation, prefetch, load_memory, store_memory,
1320         cache_op): Change type of vAddr and pAddr to address_word.
1321
1322         * gencode.c (build_instruction): Change type of vaddr and paddr to
1323         address_word.
1324
1325 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1326
1327         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1328         macro to obtain result of ALU op.
1329
1330 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1331
1332         * interp.c (sim_info): Call profile_print.
1333
1334 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1335
1336         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1337
1338         * sim-main.h (WITH_PROFILE): Do not define, defined in
1339         common/sim-config.h.  Use sim-profile module.
1340         (simPROFILE): Delete defintion.
1341
1342         * interp.c (PROFILE): Delete definition.
1343         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1344         (sim_close): Delete code writing profile histogram.
1345         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1346         Delete.
1347         (sim_engine_run): Delete code profiling the PC.
1348
1349 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1350
1351         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1352
1353         * interp.c (sim_monitor): Make register pointers of type
1354         unsigned_word*.
1355
1356         * sim-main.h: Make registers of type unsigned_word not
1357         signed_word.
1358
1359 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1360
1361         * interp.c (sync_operation): Rename from SyncOperation, make
1362         global, add SD argument.
1363         (prefetch): Rename from Prefetch, make global, add SD argument.
1364         (decode_coproc): Make global.
1365
1366         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1367
1368         * gencode.c (build_instruction): Generate DecodeCoproc not
1369         decode_coproc calls.
1370
1371         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1372         (SizeFGR): Move to sim-main.h
1373         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1374         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1375         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1376         sim-main.h.
1377         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1378         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1379         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1380         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1381         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1382         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1383
1384         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1385         exception.
1386         (sim-alu.h): Include.
1387         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1388         (sim_cia): Typedef to instruction_address.
1389
1390 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1391
1392         * Makefile.in (interp.o): Rename generated file engine.c to
1393         oengine.c.
1394
1395         * interp.c: Update.
1396
1397 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1398
1399         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1400
1401 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1402
1403         * gencode.c (build_instruction): For "FPSQRT", output correct
1404         number of arguments to Recip.
1405
1406 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1407
1408         * Makefile.in (interp.o): Depends on sim-main.h
1409
1410         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1411
1412         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1413         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1414         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1415         STATE, DSSTATE): Define
1416         (GPR, FGRIDX, ..): Define.
1417
1418         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1419         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1420         (GPR, FGRIDX, ...): Delete macros.
1421
1422         * interp.c: Update names to match defines from sim-main.h
1423
1424 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1425
1426         * interp.c (sim_monitor): Add SD argument.
1427         (sim_warning): Delete.  Replace calls with calls to
1428         sim_io_eprintf.
1429         (sim_error): Delete. Replace calls with sim_io_error.
1430         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1431         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1432         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1433         argument.
1434         (mips_size): Rename from sim_size. Add SD argument.
1435
1436         * interp.c (simulator): Delete global variable.
1437         (callback): Delete global variable.
1438         (mips_option_handler, sim_open, sim_write, sim_read,
1439         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1440         sim_size,sim_monitor): Use sim_io_* not callback->*.
1441         (sim_open): ZALLOC simulator struct.
1442         (PROFILE): Do not define.
1443
1444 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1445
1446         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1447         support.h with corresponding code.
1448
1449         * sim-main.h (word64, uword64), support.h: Move definition to
1450         sim-main.h.
1451         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1452
1453         * support.h: Delete
1454         * Makefile.in: Update dependencies
1455         * interp.c: Do not include.
1456
1457 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1458
1459         * interp.c (address_translation, load_memory, store_memory,
1460         cache_op): Rename to from AddressTranslation et.al., make global,
1461         add SD argument
1462
1463         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1464         CacheOp): Define.
1465
1466         * interp.c (SignalException): Rename to signal_exception, make
1467         global.
1468
1469         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1470
1471         * sim-main.h (SignalException, SignalExceptionInterrupt,
1472         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1473         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1474         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1475         Define.
1476
1477         * interp.c, support.h: Use.
1478
1479 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1480
1481         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1482         to value_fpr / store_fpr. Add SD argument.
1483         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1484         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1485
1486         * sim-main.h (ValueFPR, StoreFPR): Define.
1487
1488 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1489
1490         * interp.c (sim_engine_run): Check consistency between configure
1491         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1492         and HASFPU.
1493
1494         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1495         (mips_fpu): Configure WITH_FLOATING_POINT.
1496         (mips_endian): Configure WITH_TARGET_ENDIAN.
1497         * configure: Update.
1498
1499 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1500
1501         * configure: Regenerated to track ../common/aclocal.m4 changes.
1502
1503 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1504
1505         * configure: Regenerated.
1506
1507 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1508
1509         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1510
1511 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1512
1513         * gencode.c (print_igen_insn_models): Assume certain architectures
1514         include all mips* instructions.
1515         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1516         instruction.
1517
1518         * Makefile.in (tmp.igen): Add target. Generate igen input from
1519         gencode file.
1520
1521         * gencode.c (FEATURE_IGEN): Define.
1522         (main): Add --igen option.  Generate output in igen format.
1523         (process_instructions): Format output according to igen option.
1524         (print_igen_insn_format): New function.
1525         (print_igen_insn_models): New function.
1526         (process_instructions): Only issue warnings and ignore
1527         instructions when no FEATURE_IGEN.
1528
1529 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1530
1531         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1532         MIPS targets.
1533
1534 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1535
1536         * configure: Regenerated to track ../common/aclocal.m4 changes.
1537
1538 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1539
1540         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1541         SIM_RESERVED_BITS): Delete, moved to common.
1542         (SIM_EXTRA_CFLAGS): Update.
1543
1544 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1545
1546         * configure.in: Configure non-strict memory alignment.
1547         * configure: Regenerated to track ../common/aclocal.m4 changes.
1548
1549 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1550
1551         * configure: Regenerated to track ../common/aclocal.m4 changes.
1552
1553 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1554
1555         * gencode.c (SDBBP,DERET): Added (3900) insns.
1556         (RFE): Turn on for 3900.
1557         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1558         (dsstate): Made global.
1559         (SUBTARGET_R3900): Added.
1560         (CANCELDELAYSLOT): New.
1561         (SignalException): Ignore SystemCall rather than ignore and
1562         terminate.  Add DebugBreakPoint handling.
1563         (decode_coproc): New insns RFE, DERET; and new registers Debug
1564         and DEPC protected by SUBTARGET_R3900.
1565         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1566         bits explicitly.
1567         * Makefile.in,configure.in: Add mips subtarget option.
1568         * configure: Update.
1569
1570 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1571
1572         * gencode.c: Add r3900 (tx39).
1573
1574
1575 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1576
1577         * gencode.c (build_instruction): Don't need to subtract 4 for
1578         JALR, just 2.
1579
1580 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1581
1582         * interp.c: Correct some HASFPU problems.
1583
1584 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1585
1586         * configure: Regenerated to track ../common/aclocal.m4 changes.
1587
1588 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1589
1590         * interp.c (mips_options): Fix samples option short form, should
1591         be `x'.
1592
1593 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1594
1595         * interp.c (sim_info): Enable info code.  Was just returning.
1596
1597 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1598
1599         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1600         MFC0.
1601
1602 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1603
1604         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1605         constants.
1606         (build_instruction): Ditto for LL.
1607
1608 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1609
1610         * configure: Regenerated to track ../common/aclocal.m4 changes.
1611
1612 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1613
1614         * configure: Regenerated to track ../common/aclocal.m4 changes.
1615         * config.in: Ditto.
1616
1617 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1618
1619         * interp.c (sim_open): Add call to sim_analyze_program, update
1620         call to sim_config.
1621
1622 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1623
1624         * interp.c (sim_kill): Delete.
1625         (sim_create_inferior): Add ABFD argument. Set PC from same.
1626         (sim_load): Move code initializing trap handlers from here.
1627         (sim_open): To here.
1628         (sim_load): Delete, use sim-hload.c.
1629
1630         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1631
1632 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1633
1634         * configure: Regenerated to track ../common/aclocal.m4 changes.
1635         * config.in: Ditto.
1636
1637 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1638
1639         * interp.c (sim_open): Add ABFD argument.
1640         (sim_load): Move call to sim_config from here.
1641         (sim_open): To here.  Check return status.
1642
1643 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1644
1645         * gencode.c (build_instruction): Two arg MADD should
1646         not assign result to $0.
1647
1648 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1649
1650         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1651         * sim/mips/configure.in: Regenerate.
1652
1653 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1654
1655         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1656         signed8, unsigned8 et.al. types.
1657
1658         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1659         hosts when selecting subreg.
1660
1661 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1662
1663         * interp.c (sim_engine_run): Reset the ZERO register to zero
1664         regardless of FEATURE_WARN_ZERO.
1665         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1666
1667 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1668
1669         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1670         (SignalException): For BreakPoints ignore any mode bits and just
1671         save the PC.
1672         (SignalException): Always set the CAUSE register.
1673
1674 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1675
1676         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1677         exception has been taken.
1678
1679         * interp.c: Implement the ERET and mt/f sr instructions.
1680
1681 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1682
1683         * interp.c (SignalException): Don't bother restarting an
1684         interrupt.
1685
1686 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1687
1688         * interp.c (SignalException): Really take an interrupt.
1689         (interrupt_event): Only deliver interrupts when enabled.
1690
1691 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1692
1693         * interp.c (sim_info): Only print info when verbose.
1694         (sim_info) Use sim_io_printf for output.
1695
1696 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1697
1698         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1699         mips architectures.
1700
1701 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1702
1703         * interp.c (sim_do_command): Check for common commands if a
1704         simulator specific command fails.
1705
1706 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1707
1708         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1709         and simBE when DEBUG is defined.
1710
1711 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1712
1713         * interp.c (interrupt_event): New function.  Pass exception event
1714         onto exception handler.
1715
1716         * configure.in: Check for stdlib.h.
1717         * configure: Regenerate.
1718
1719         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1720         variable declaration.
1721         (build_instruction): Initialize memval1.
1722         (build_instruction): Add UNUSED attribute to byte, bigend,
1723         reverse.
1724         (build_operands): Ditto.
1725
1726         * interp.c: Fix GCC warnings.
1727         (sim_get_quit_code): Delete.
1728
1729         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1730         * Makefile.in: Ditto.
1731         * configure: Re-generate.
1732
1733         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1734
1735 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1736
1737         * interp.c (mips_option_handler): New function parse argumes using
1738         sim-options.
1739         (myname): Replace with STATE_MY_NAME.
1740         (sim_open): Delete check for host endianness - performed by
1741         sim_config.
1742         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1743         (sim_open): Move much of the initialization from here.
1744         (sim_load): To here.  After the image has been loaded and
1745         endianness set.
1746         (sim_open): Move ColdReset from here.
1747         (sim_create_inferior): To here.
1748         (sim_open): Make FP check less dependant on host endianness.
1749
1750         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1751         run.
1752         * interp.c (sim_set_callbacks): Delete.
1753
1754         * interp.c (membank, membank_base, membank_size): Replace with
1755         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1756         (sim_open): Remove call to callback->init. gdb/run do this.
1757
1758         * interp.c: Update
1759
1760         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1761
1762         * interp.c (big_endian_p): Delete, replaced by
1763         current_target_byte_order.
1764
1765 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1766
1767         * interp.c (host_read_long, host_read_word, host_swap_word,
1768         host_swap_long): Delete. Using common sim-endian.
1769         (sim_fetch_register, sim_store_register): Use H2T.
1770         (pipeline_ticks): Delete.  Handled by sim-events.
1771         (sim_info): Update.
1772         (sim_engine_run): Update.
1773
1774 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1775
1776         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1777         reason from here.
1778         (SignalException): To here. Signal using sim_engine_halt.
1779         (sim_stop_reason): Delete, moved to common.
1780
1781 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
1782
1783         * interp.c (sim_open): Add callback argument.
1784         (sim_set_callbacks): Delete SIM_DESC argument.
1785         (sim_size): Ditto.
1786
1787 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1788
1789         * Makefile.in (SIM_OBJS): Add common modules.
1790
1791         * interp.c (sim_set_callbacks): Also set SD callback.
1792         (set_endianness, xfer_*, swap_*): Delete.
1793         (host_read_word, host_read_long, host_swap_word, host_swap_long):
1794         Change to functions using sim-endian macros.
1795         (control_c, sim_stop): Delete, use common version.
1796         (simulate): Convert into.
1797         (sim_engine_run): This function.
1798         (sim_resume): Delete.
1799
1800         * interp.c (simulation): New variable - the simulator object.
1801         (sim_kind): Delete global - merged into simulation.
1802         (sim_load): Cleanup.  Move PC assignment from here.
1803         (sim_create_inferior): To here.
1804
1805         * sim-main.h: New file.
1806         * interp.c (sim-main.h): Include.
1807
1808 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
1809
1810         * configure: Regenerated to track ../common/aclocal.m4 changes.
1811
1812 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
1813
1814         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1815
1816 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
1817
1818         * gencode.c (build_instruction): DIV instructions: check
1819         for division by zero and integer overflow before using
1820         host's division operation.
1821
1822 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
1823
1824         * Makefile.in (SIM_OBJS): Add sim-load.o.
1825         * interp.c: #include bfd.h.
1826         (target_byte_order): Delete.
1827         (sim_kind, myname, big_endian_p): New static locals.
1828         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
1829         after argument parsing.  Recognize -E arg, set endianness accordingly.
1830         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
1831         load file into simulator.  Set PC from bfd.
1832         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
1833         (set_endianness): Use big_endian_p instead of target_byte_order.
1834
1835 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1836
1837         * interp.c (sim_size): Delete prototype - conflicts with
1838         definition in remote-sim.h.  Correct definition.
1839
1840 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1841
1842         * configure: Regenerated to track ../common/aclocal.m4 changes.
1843         * config.in: Ditto.
1844
1845 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
1846
1847         * interp.c (sim_open): New arg `kind'.
1848
1849         * configure: Regenerated to track ../common/aclocal.m4 changes.
1850
1851 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1852
1853         * configure: Regenerated to track ../common/aclocal.m4 changes.
1854
1855 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
1856
1857         * interp.c (sim_open): Set optind to 0 before calling getopt.
1858
1859 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1860
1861         * configure: Regenerated to track ../common/aclocal.m4 changes.
1862
1863 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
1864
1865         * interp.c : Replace uses of pr_addr with pr_uword64
1866         where the bit length is always 64 independent of SIM_ADDR.
1867         (pr_uword64) : added.
1868
1869 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1870
1871         * configure: Re-generate.
1872
1873 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
1874
1875         * configure: Regenerate to track ../common/aclocal.m4 changes.
1876
1877 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
1878
1879         * interp.c (sim_open): New SIM_DESC result.  Argument is now
1880         in argv form.
1881         (other sim_*): New SIM_DESC argument.
1882
1883 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
1884
1885         * interp.c: Fix printing of addresses for non-64-bit targets.
1886         (pr_addr): Add function to print address based on size.
1887
1888 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
1889
1890         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1891
1892 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
1893
1894         * gencode.c (build_mips16_operands): Correct computation of base
1895         address for extended PC relative instruction.
1896
1897 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
1898
1899         * interp.c (mips16_entry): Add support for floating point cases.
1900         (SignalException): Pass floating point cases to mips16_entry.
1901         (ValueFPR): Don't restrict fmt_single and fmt_word to even
1902         registers.
1903         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
1904         or fmt_word.
1905         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1906         and then set the state to fmt_uninterpreted.
1907         (COP_SW): Temporarily set the state to fmt_word while calling
1908         ValueFPR.
1909
1910 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
1911
1912         * gencode.c (build_instruction): The high order may be set in the
1913         comparison flags at any ISA level, not just ISA 4.
1914
1915 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
1916
1917         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1918         COMMON_{PRE,POST}_CONFIG_FRAG instead.
1919         * configure.in: sinclude ../common/aclocal.m4.
1920         * configure: Regenerated.
1921
1922 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
1923
1924         * configure: Rebuild after change to aclocal.m4.
1925
1926 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
1927
1928         * configure configure.in Makefile.in:  Update to new configure
1929         scheme which is more compatible with WinGDB builds.
1930         * configure.in:  Improve comment on how to run autoconf.
1931         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
1932         * Makefile.in:  Use autoconf substitution to install common
1933         makefile fragment.
1934
1935 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
1936
1937         * gencode.c (build_instruction): Use BigEndianCPU instead of
1938         ByteSwapMem.
1939
1940 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
1941
1942         * interp.c (sim_monitor): Make output to stdout visible in
1943         wingdb's I/O log window.
1944
1945 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
1946
1947         * support.h: Undo previous change to SIGTRAP
1948         and SIGQUIT values.
1949
1950 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
1951
1952         * interp.c (store_word, load_word): New static functions.
1953         (mips16_entry): New static function.
1954         (SignalException): Look for mips16 entry and exit instructions.
1955         (simulate): Use the correct index when setting fpr_state after
1956         doing a pending move.
1957
1958 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
1959
1960         * interp.c: Fix byte-swapping code throughout to work on
1961         both little- and big-endian hosts.
1962
1963 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
1964
1965         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1966         with gdb/config/i386/xm-windows.h.
1967
1968 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
1969
1970         * gencode.c (build_instruction): Work around MSVC++ code gen bug
1971         that messes up arithmetic shifts.
1972
1973 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
1974
1975         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
1976         SIGTRAP and SIGQUIT for _WIN32.
1977
1978 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
1979
1980         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1981         force a 64 bit multiplication.
1982         (build_instruction) [OR]: In mips16 mode, don't do anything if the
1983         destination register is 0, since that is the default mips16 nop
1984         instruction.
1985
1986 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
1987
1988         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1989         (build_endian_shift): Don't check proc64.
1990         (build_instruction): Always set memval to uword64.  Cast op2 to
1991         uword64 when shifting it left in memory instructions.  Always use
1992         the same code for stores--don't special case proc64.
1993
1994         * gencode.c (build_mips16_operands): Fix base PC value for PC
1995         relative operands.
1996         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1997         jal instruction.
1998         * interp.c (simJALDELAYSLOT): Define.
1999         (JALDELAYSLOT): Define.
2000         (INDELAYSLOT, INJALDELAYSLOT): Define.
2001         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2002
2003 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2004
2005         * interp.c (sim_open): add flush_cache as a PMON routine
2006         (sim_monitor): handle flush_cache by ignoring it
2007
2008 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2009
2010         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2011         BigEndianMem.
2012         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2013         (BigEndianMem): Rename to ByteSwapMem and change sense.
2014         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2015         BigEndianMem references to !ByteSwapMem.
2016         (set_endianness): New function, with prototype.
2017         (sim_open): Call set_endianness.
2018         (sim_info): Use simBE instead of BigEndianMem.
2019         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2020         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2021         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2022         ifdefs, keeping the prototype declaration.
2023         (swap_word): Rewrite correctly.
2024         (ColdReset): Delete references to CONFIG.  Delete endianness related
2025         code; moved to set_endianness.
2026
2027 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2028
2029         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2030         * interp.c (CHECKHILO): Define away.
2031         (simSIGINT): New macro.
2032         (membank_size): Increase from 1MB to 2MB.
2033         (control_c): New function.
2034         (sim_resume): Rename parameter signal to signal_number.  Add local
2035         variable prev.  Call signal before and after simulate.
2036         (sim_stop_reason): Add simSIGINT support.
2037         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2038         functions always.
2039         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2040         if logfh is NULL.
2041         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2042         a call to sim_warning.
2043
2044 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2045
2046         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2047         16 bit instructions.
2048
2049 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2050
2051         Add support for mips16 (16 bit MIPS implementation):
2052         * gencode.c (inst_type): Add mips16 instruction encoding types.
2053         (GETDATASIZEINSN): Define.
2054         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2055         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2056         mtlo.
2057         (MIPS16_DECODE): New table, for mips16 instructions.
2058         (bitmap_val): New static function.
2059         (struct mips16_op): Define.
2060         (mips16_op_table): New table, for mips16 operands.
2061         (build_mips16_operands): New static function.
2062         (process_instructions): If PC is odd, decode a mips16
2063         instruction.  Break out instruction handling into new
2064         build_instruction function.
2065         (build_instruction): New static function, broken out of
2066         process_instructions.  Check modifiers rather than flags for SHIFT
2067         bit count and m[ft]{hi,lo} direction.
2068         (usage): Pass program name to fprintf.
2069         (main): Remove unused variable this_option_optind.  Change
2070         ``*loptarg++'' to ``loptarg++''.
2071         (my_strtoul): Parenthesize && within ||.
2072         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2073         (simulate): If PC is odd, fetch a 16 bit instruction, and
2074         increment PC by 2 rather than 4.
2075         * configure.in: Add case for mips16*-*-*.
2076         * configure: Rebuild.
2077
2078 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2079
2080         * interp.c: Allow -t to enable tracing in standalone simulator.
2081         Fix garbage output in trace file and error messages.
2082
2083 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2084
2085         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2086         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2087         * configure.in: Simplify using macros in ../common/aclocal.m4.
2088         * configure: Regenerated.
2089         * tconfig.in: New file.
2090
2091 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2092
2093         * interp.c: Fix bugs in 64-bit port.
2094         Use ansi function declarations for msvc compiler.
2095         Initialize and test file pointer in trace code.
2096         Prevent duplicate definition of LAST_EMED_REGNUM.
2097
2098 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2099
2100         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2101
2102 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2103
2104         * interp.c (SignalException): Check for explicit terminating
2105         breakpoint value.
2106         * gencode.c: Pass instruction value through SignalException()
2107         calls for Trap, Breakpoint and Syscall.
2108
2109 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2110
2111         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2112         only used on those hosts that provide it.
2113         * configure.in: Add sqrt() to list of functions to be checked for.
2114         * config.in: Re-generated.
2115         * configure: Re-generated.
2116
2117 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2118
2119         * gencode.c (process_instructions): Call build_endian_shift when
2120         expanding STORE RIGHT, to fix swr.
2121         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2122         clear the high bits.
2123         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2124         Fix float to int conversions to produce signed values.
2125
2126 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2127
2128         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2129         (process_instructions): Correct handling of nor instruction.
2130         Correct shift count for 32 bit shift instructions. Correct sign
2131         extension for arithmetic shifts to not shift the number of bits in
2132         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2133         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2134         Fix madd.
2135         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2136         It's OK to have a mult follow a mult.  What's not OK is to have a
2137         mult follow an mfhi.
2138         (Convert): Comment out incorrect rounding code.
2139
2140 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2141
2142         * interp.c (sim_monitor): Improved monitor printf
2143         simulation. Tidied up simulator warnings, and added "--log" option
2144         for directing warning message output.
2145         * gencode.c: Use sim_warning() rather than WARNING macro.
2146
2147 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2148
2149         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2150         getopt1.o, rather than on gencode.c.  Link objects together.
2151         Don't link against -liberty.
2152         (gencode.o, getopt.o, getopt1.o): New targets.
2153         * gencode.c: Include <ctype.h> and "ansidecl.h".
2154         (AND): Undefine after including "ansidecl.h".
2155         (ULONG_MAX): Define if not defined.
2156         (OP_*): Don't define macros; now defined in opcode/mips.h.
2157         (main): Call my_strtoul rather than strtoul.
2158         (my_strtoul): New static function.
2159
2160 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2161
2162         * gencode.c (process_instructions):  Generate word64 and uword64
2163         instead of `long long' and `unsigned long long' data types.
2164         * interp.c:  #include sysdep.h to get signals, and define default
2165         for SIGBUS.
2166         * (Convert):  Work around for Visual-C++ compiler bug with type
2167         conversion.
2168         * support.h:  Make things compile under Visual-C++ by using
2169         __int64 instead of `long long'.  Change many refs to long long
2170         into word64/uword64 typedefs.
2171
2172 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2173
2174         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2175         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2176         (docdir): Removed.
2177         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2178         (AC_PROG_INSTALL): Added.
2179         (AC_PROG_CC): Moved to before configure.host call.
2180         * configure: Rebuilt.
2181
2182 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2183
2184         * configure.in: Define @SIMCONF@ depending on mips target.
2185         * configure: Rebuild.
2186         * Makefile.in (run): Add @SIMCONF@ to control simulator
2187         construction.
2188         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2189         * interp.c: Remove some debugging, provide more detailed error
2190         messages, update memory accesses to use LOADDRMASK.
2191
2192 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2193
2194         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2195         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2196         stamp-h.
2197         * configure: Rebuild.
2198         * config.in: New file, generated by autoheader.
2199         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2200         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2201         HAVE_ANINT and HAVE_AINT, as appropriate.
2202         * Makefile.in (run): Use @LIBS@ rather than -lm.
2203         (interp.o): Depend upon config.h.
2204         (Makefile): Just rebuild Makefile.
2205         (clean): Remove stamp-h.
2206         (mostlyclean): Make the same as clean, not as distclean.
2207         (config.h, stamp-h): New targets.
2208
2209 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2210
2211         * interp.c (ColdReset): Fix boolean test. Make all simulator
2212         globals static.
2213
2214 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2215
2216         * interp.c (xfer_direct_word, xfer_direct_long,
2217         swap_direct_word, swap_direct_long, xfer_big_word,
2218         xfer_big_long, xfer_little_word, xfer_little_long,
2219         swap_word,swap_long): Added.
2220         * interp.c (ColdReset): Provide function indirection to
2221         host<->simulated_target transfer routines.
2222         * interp.c (sim_store_register, sim_fetch_register): Updated to
2223         make use of indirected transfer routines.
2224
2225 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2226
2227         * gencode.c (process_instructions): Ensure FP ABS instruction
2228         recognised.
2229         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2230         system call support.
2231
2232 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2233
2234         * interp.c (sim_do_command): Complain if callback structure not
2235         initialised.
2236
2237 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2238
2239         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2240         support for Sun hosts.
2241         * Makefile.in (gencode): Ensure the host compiler and libraries
2242         used for cross-hosted build.
2243
2244 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2245
2246         * interp.c, gencode.c: Some more (TODO) tidying.
2247
2248 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2249
2250         * gencode.c, interp.c: Replaced explicit long long references with
2251         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2252         * support.h (SET64LO, SET64HI): Macros added.
2253
2254 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2255
2256         * configure: Regenerate with autoconf 2.7.
2257
2258 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2259
2260         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2261         * support.h: Remove superfluous "1" from #if.
2262         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2263
2264 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2265
2266         * interp.c (StoreFPR): Control UndefinedResult() call on
2267         WARN_RESULT manifest.
2268
2269 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2270
2271         * gencode.c: Tidied instruction decoding, and added FP instruction
2272         support.
2273
2274         * interp.c: Added dineroIII, and BSD profiling support. Also
2275         run-time FP handling.
2276
2277 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2278
2279         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2280         gencode.c, interp.c, support.h: created.