sim/mips/ChangeLog

   1 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
   4         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
   5         (status_CU3): New definitions.
   6
   7         * sim-main.h (ExceptionCause): Add new values for MIPS32
   8         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
   9         for DebugBreakPoint and NMIReset to note their status in
  10         MIPS32 and MIPS64.
  11         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
  12         (SignalExceptionCacheErr): New exception macros.
  13
  14 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  15
  16         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
  17         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
  18         is always enabled.
  19         (SignalExceptionCoProcessorUnusable): Take as argument the
  20         unusable coprocessor number.
  21
  22 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  23
  24         * mips.igen: Fix formatting of all SignalException calls.
  25
  26 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  27
  28         * sim-main.h (SIGNEXTEND): Remove.
  29
  30 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
  31
  32         * mips.igen: Remove gencode comment from top of file, fix
  33         spelling in another comment.
  34
  35 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
  36
  37         * mips.igen (check_fmt, check_fmt_p): New functions to check
  38         whether specific floating point formats are usable.
  39         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
  40         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
  41         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
  42         Use the new functions.
  43         (do_c_cond_fmt): Remove format checks...
  44         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
  45
  46 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
  47
  48         * mips.igen: Fix formatting of check_fpu calls.
  49
  50 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
  51
  52         * mips.igen (FLOOR.L.fmt): Store correct destination register.
  53
  54 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
  55
  56         * mips.igen: Remove whitespace at end of lines.
  57
  58 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  59
  60         * mips.igen (loadstore_ea): New function to do effective
  61         address calculations.
  62         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
  63         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
  64         CACHE): Use loadstore_ea to do effective address computations.
  65
  66 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  67
  68         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
  69         * mips.igen (LL, CxC1, MxC1): Likewise.
  70
  71 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  72
  73         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
  74         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
  75         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
  76         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
  77         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
  78         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
  79         Don't split opcode fields by hand, use the opcode field values
  80         provided by igen.
  81
  82 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  83
  84         * mips.igen (do_divu): Fix spacing.
  85
  86         * mips.igen (do_dsllv): Move to be right before DSLLV,
  87         to match the rest of the do_<shift> functions.
  88
  89 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  90
  91         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
  92         DSRL32, do_dsrlv): Trace inputs and results.
  93
  94 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  95
  96         * mips.igen (CACHE): Provide instruction-printing string.
  97
  98         * interp.c (signal_exception): Comment tokens after #endif.
  99
 100 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 101
 102         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 103         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 104         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 105         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 106         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 107         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 108         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 109         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 110
 111 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 112
 113         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 114         instruction-printing string.
 115         (LWU): Use '64' as the filter flag.
 116
 117 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 118
 119         * mips.igen (SDXC1): Fix instruction-printing string.
 120
 121 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 122
 123         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 124         filter flags "32,f".
 125
 126 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 127
 128         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 129         as the filter flag.
 130
 131 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 132
 133         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 134         add a comma) so that it more closely match the MIPS ISA
 135         documentation opcode partitioning.
 136         (PREF): Put useful names on opcode fields, and include
 137         instruction-printing string.
 138
 139 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 140
 141         * mips.igen (check_u64): New function which in the future will
 142         check whether 64-bit instructions are usable and signal an
 143         exception if not.  Currently a no-op.
 144         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 145         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 146         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 147         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 148
 149         * mips.igen (check_fpu): New function which in the future will
 150         check whether FPU instructions are usable and signal an exception
 151         if not.  Currently a no-op.
 152         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 153         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 154         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 155         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 156         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 157         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 158         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 159         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 160
 161 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 162
 163         * mips.igen (do_load_left, do_load_right): Move to be immediately
 164         following do_load.
 165         (do_store_left, do_store_right): Move to be immediately following
 166         do_store.
 167
 168 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 169
 170         * mips.igen (mipsV): New model name.  Also, add it to
 171         all instructions and functions where it is appropriate.
 172
 173 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 174
 175         * mips.igen: For all functions and instructions, list model
 176         names that support that instruction one per line.
 177
 178 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 179
 180         * mips.igen: Add some additional comments about supported
 181         models, and about which instructions go where.
 182         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 183         order as is used in the rest of the file.
 184
 185 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 186
 187         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 188         indicating that ALU32_END or ALU64_END are there to check
 189         for overflow.
 190         (DADD): Likewise, but also remove previous comment about
 191         overflow checking.
 192
 193 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 194
 195         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 196         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 197         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 198         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 199         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 200         fields (i.e., add and move commas) so that they more closely
 201         match the MIPS ISA documentation opcode partitioning.
 202
 203 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 204
 205         * mips.igen (ADDI): Print immediate value.
 206         (BREAK): Print code.
 207         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 208         (SLL): Print "nop" specially, and don't run the code
 209         that does the shift for the "nop" case.
 210
 211 2001-11-17  Fred Fish  <fnf@redhat.com>
 212
 213         * sim-main.h (float_operation): Move enum declaration outside
 214         of _sim_cpu struct declaration.
 215
 216 2001-04-12  Jim Blandy  <jimb@redhat.com>
 217
 218         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 219         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 220         set of the FCSR.
 221         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 222         PENDING_FILL, and you can get the intended effect gracefully by
 223         calling PENDING_SCHED directly.
 224
 225 2001-02-23  Ben Elliston  <bje@redhat.com>
 226
 227         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 228         already defined elsewhere.
 229
 230 2001-02-19  Ben Elliston  <bje@redhat.com>
 231
 232         * sim-main.h (sim_monitor): Return an int.
 233         * interp.c (sim_monitor): Add return values.
 234         (signal_exception): Handle error conditions from sim_monitor.
 235
 236 2001-02-08  Ben Elliston  <bje@redhat.com>
 237
 238         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 239         (store_memory): Likewise, pass cia to sim_core_write*.
 240
 241 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 242
 243         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 244         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 245
 246 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 247
 248         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 249         * Makefile.in: Don't delete *.igen when cleaning directory.
 250
 251 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 252
 253         * m16.igen (break): Call SignalException not sim_engine_halt.
 254
 255 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 256
 257         From Jason Eckhardt:
 258         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 259
 260 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 261
 262         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 263
 264 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 265
 266         * mips.igen (do_dmultx): Fix typo.
 267
 268 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 269
 270         * configure: Regenerated to track ../common/aclocal.m4 changes.
 271
 272 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 273
 274         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 275
 276 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 277
 278         * sim-main.h (GPR_CLEAR): Define macro.
 279
 280 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 281
 282         * interp.c (decode_coproc): Output long using %lx and not %s.
 283
 284 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 285
 286         * interp.c (sim_open): Sort & extend dummy memory regions for
 287         --board=jmr3904 for eCos.
 288
 289 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 290
 291         * configure: Regenerated.
 292
 293 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 294
 295         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 296         calls, conditional on the simulator being in verbose mode.
 297
 298 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 299
 300         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 301         cache don't get ReservedInstruction traps.
 302
 303 1999-11-29  Mark Salter  <msalter@cygnus.com>
 304
 305         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 306         to clear status bits in sdisr register. This is how the hardware works.
 307
 308         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 309         being used by cygmon.
 310
 311 1999-11-11  Andrew Haley  <aph@cygnus.com>
 312
 313         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 314         instructions.
 315
 316 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 317
 318         * mips.igen (MULT): Correct previous mis-applied patch.
 319
 320 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 321
 322         * mips.igen (delayslot32): Handle sequence like
 323         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 324         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 325         (MULT): Actually pass the third register...
 326
 327 1999-09-03  Mark Salter  <msalter@cygnus.com>
 328
 329         * interp.c (sim_open): Added more memory aliases for additional
 330         hardware being touched by cygmon on jmr3904 board.
 331
 332 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 333
 334         * configure: Regenerated to track ../common/aclocal.m4 changes.
 335
 336 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 337
 338         * interp.c (sim_store_register): Handle case where client - GDB -
 339         specifies that a 4 byte register is 8 bytes in size.
 340         (sim_fetch_register): Ditto.
 341
 342 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 343
 344         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 345         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 346         (idt_monitor_base): Base address for IDT monitor traps.
 347         (pmon_monitor_base): Ditto for PMON.
 348         (lsipmon_monitor_base): Ditto for LSI PMON.
 349         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 350         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 351         (sim_firmware_command): New function.
 352         (mips_option_handler): Call it for OPTION_FIRMWARE.
 353         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 354         option was given, add no monitor by default.  Add BREAK hooks only if
 355         monitors are also there.
 356
 357 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 358
 359         * interp.c (sim_monitor): Flush output before reading input.
 360
 361 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 362
 363         * tconfig.in (SIM_HANDLES_LMA): Always define.
 364
 365 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 366
 367         From Mark Salter <msalter@cygnus.com>:
 368         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 369         (sim_open): Add setup for BSP board.
 370
 371 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 372
 373         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 374         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 375         them as unimplemented.
 376
 377 1999-05-08  Felix Lee  <flee@cygnus.com>
 378
 379         * configure: Regenerated to track ../common/aclocal.m4 changes.
 380
 381 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 382
 383         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 384
 385 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 386
 387         * configure.in: Any mips64vr5*-*-* target should have
 388         -DTARGET_ENABLE_FR=1.
 389         (default_endian): Any mips64vr*el-*-* target should default to
 390         LITTLE_ENDIAN.
 391         * configure: Re-generate.
 392
 393 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 394
 395         * mips.igen (ldl): Extend from _16_, not 32.
 396
 397 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 398
 399         * interp.c (sim_store_register): Force registers written to by GDB
 400         into an un-interpreted state.
 401
 402 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 403
 404         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 405         CPU, start periodic background I/O polls.
 406         (tx3904sio_poll): New function: periodic I/O poller.
 407
 408 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 409
 410         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 411
 412 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 413
 414         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 415         case statement.
 416
 417 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 418
 419         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 420         (load_word): Call SIM_CORE_SIGNAL hook on error.
 421         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 422         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 423         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 424         * sim-main.h (COP0_BADVADDR): Define.
 425         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 426         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 427         (_sim_cpu): Add exc_* fields to store register value snapshots.
 428         * mips.igen (*): Replace memory-related SignalException* calls
 429         with references to SIM_CORE_SIGNAL hook.
 430
 431         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 432         fix.
 433         * sim-main.c (*): Minor warning cleanups.
 434
 435 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 436
 437         * m16.igen (DADDIU5): Correct type-o.
 438
 439 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 440
 441         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 442         variables.
 443
 444 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 445
 446         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 447         to include path.
 448         (interp.o): Add dependency on itable.h
 449         (oengine.c, gencode): Delete remaining references.
 450         (BUILT_SRC_FROM_GEN): Clean up.
 451
 452 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 453
 454         * vr4run.c: New.
 455         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 456         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 457         tmp-run-hack) : New.
 458         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 459         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 460         Drop the "64" qualifier to get the HACK generator working.
 461         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 462         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 463         qualifier to get the hack generator working.
 464         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 465         (DSLL): Use do_dsll.
 466         (DSLLV): Use do_dsllv.
 467         (DSRA): Use do_dsra.
 468         (DSRL): Use do_dsrl.
 469         (DSRLV): Use do_dsrlv.
 470         (BC1): Move *vr4100 to get the HACK generator working.
 471         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 472         get the HACK generator working.
 473         (MACC) Rename to get the HACK generator working.
 474         (DMACC,MACCS,DMACCS): Add the 64.
 475
 476 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 477
 478         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 479         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 480
 481 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 482
 483     * mips/interp.c (DEBUG): Cleanups.
 484
 485 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 486
 487         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 488         (tx3904sio_tickle): fflush after a stdout character output.
 489
 490 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 491
 492         * interp.c (sim_close): Uninstall modules.
 493
 494 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 495
 496         * sim-main.h, interp.c (sim_monitor): Change to global
 497         function.
 498
 499 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 500
 501         * configure.in (vr4100): Only include vr4100 instructions in
 502         simulator.
 503         * configure: Re-generate.
 504         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 505
 506 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 507
 508         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 509         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 510         true alternative.
 511
 512         * configure.in (sim_default_gen, sim_use_gen): Replace with
 513         sim_gen.
 514         (--enable-sim-igen): Delete config option. Always using IGEN.
 515         * configure: Re-generate.
 516
 517         * Makefile.in (gencode): Kill, kill, kill.
 518         * gencode.c: Ditto.
 519
 520 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 521
 522         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 523         bit mips16 igen simulator.
 524         * configure: Re-generate.
 525
 526         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 527         as part of vr4100 ISA.
 528         * vr.igen: Mark all instructions as 64 bit only.
 529
 530 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 531
 532         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 533         Pacify GCC.
 534
 535 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 536
 537         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 538         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 539         * configure: Re-generate.
 540
 541         * m16.igen (BREAK): Define breakpoint instruction.
 542         (JALX32): Mark instruction as mips16 and not r3900.
 543         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 544
 545         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 546
 547 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 548
 549         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 550         insn as a debug breakpoint.
 551
 552         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 553         pending.slot_size.
 554         (PENDING_SCHED): Clean up trace statement.
 555         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 556         (PENDING_FILL): Delay write by only one cycle.
 557         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 558
 559         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 560         of pending writes.
 561         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 562         32 & 64.
 563         (pending_tick): Move incrementing of index to FOR statement.
 564         (pending_tick): Only update PENDING_OUT after a write has occured.
 565
 566         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 567         build simulator.
 568         * configure: Re-generate.
 569
 570         * interp.c (sim_engine_run OLD): Delete explicit call to
 571         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 572
 573 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 574
 575         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 576         interrupt level number to match changed SignalExceptionInterrupt
 577         macro.
 578
 579 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 580
 581         * interp.c: #include "itable.h" if WITH_IGEN.
 582         (get_insn_name): New function.
 583         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 584         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 585
 586 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 587
 588         * configure: Rebuilt to inhale new common/aclocal.m4.
 589
 590 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 591
 592         * dv-tx3904sio.c: Include sim-assert.h.
 593
 594 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 595
 596         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 597         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 598         Reorganize target-specific sim-hardware checks.
 599         * configure: rebuilt.
 600         * interp.c (sim_open): For tx39 target boards, set
 601         OPERATING_ENVIRONMENT, add tx3904sio devices.
 602         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 603         ROM executables.  Install dv-sockser into sim-modules list.
 604
 605         * dv-tx3904irc.c: Compiler warning clean-up.
 606         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 607         frequent hw-trace messages.
 608
 609 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 610
 611         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 612
 613 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 614
 615         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 616
 617         * vr.igen: New file.
 618         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 619         * mips.igen: Define vr4100 model. Include vr.igen.
 620 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 621
 622         * mips.igen (check_mf_hilo): Correct check.
 623
 624 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 625
 626         * sim-main.h (interrupt_event): Add prototype.
 627
 628         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 629         register_ptr, register_value.
 630         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 631
 632         * sim-main.h (tracefh): Make extern.
 633
 634 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 635
 636         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 637         Reduce unnecessarily high timer event frequency.
 638         * dv-tx3904cpu.c: Ditto for interrupt event.
 639
 640 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 641
 642         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 643         to allay warnings.
 644         (interrupt_event): Made non-static.
 645
 646         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 647         interchange of configuration values for external vs. internal
 648         clock dividers.
 649
 650 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 651
 652         * mips.igen (BREAK): Moved code to here for
 653         simulator-reserved break instructions.
 654         * gencode.c (build_instruction): Ditto.
 655         * interp.c (signal_exception): Code moved from here.  Non-
 656         reserved instructions now use exception vector, rather
 657         than halting sim.
 658         * sim-main.h: Moved magic constants to here.
 659
 660 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 661
 662         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 663         register upon non-zero interrupt event level, clear upon zero
 664         event value.
 665         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 666         by passing zero event value.
 667         (*_io_{read,write}_buffer): Endianness fixes.
 668         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 669         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 670
 671         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 672         serial I/O and timer module at base address 0xFFFF0000.
 673
 674 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 675
 676         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 677         and BigEndianCPU.
 678
 679 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 680
 681         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 682         parts.
 683         * configure: Update.
 684
 685 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 686
 687         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 688         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 689         * configure.in: Include tx3904tmr in hw_device list.
 690         * configure: Rebuilt.
 691         * interp.c (sim_open): Instantiate three timer instances.
 692         Fix address typo of tx3904irc instance.
 693
 694 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 695
 696         * interp.c (signal_exception): SystemCall exception now uses
 697         the exception vector.
 698
 699 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 700
 701         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 702         to allay warnings.
 703
 704 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 705
 706         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 707
 708 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 709
 710         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 711
 712         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 713         sim-main.h. Declare a struct hw_descriptor instead of struct
 714         hw_device_descriptor.
 715
 716 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 717
 718         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 719         right bits and then re-align left hand bytes to correct byte
 720         lanes.  Fix incorrect computation in do_store_left when loading
 721         bytes from second word.
 722
 723 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 724
 725         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 726         * interp.c (sim_open): Only create a device tree when HW is
 727         enabled.
 728
 729         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 730         * interp.c (signal_exception): Ditto.
 731
 732 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 733
 734         * gencode.c: Mark BEGEZALL as LIKELY.
 735
 736 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 737
 738         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 739         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 740
 741 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 742
 743         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 744         modules.  Recognize TX39 target with "mips*tx39" pattern.
 745         * configure: Rebuilt.
 746         * sim-main.h (*): Added many macros defining bits in
 747         TX39 control registers.
 748         (SignalInterrupt): Send actual PC instead of NULL.
 749         (SignalNMIReset): New exception type.
 750         * interp.c (board): New variable for future use to identify
 751         a particular board being simulated.
 752         (mips_option_handler,mips_options): Added "--board" option.
 753         (interrupt_event): Send actual PC.
 754         (sim_open): Make memory layout conditional on board setting.
 755         (signal_exception): Initial implementation of hardware interrupt
 756         handling.  Accept another break instruction variant for simulator
 757         exit.
 758         (decode_coproc): Implement RFE instruction for TX39.
 759         (mips.igen): Decode RFE instruction as such.
 760         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 761         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 762         bbegin to implement memory map.
 763         * dv-tx3904cpu.c: New file.
 764         * dv-tx3904irc.c: New file.
 765
 766 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 767
 768         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 769
 770 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 771
 772         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 773         with calls to check_div_hilo.
 774
 775 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 776
 777         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 778         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 779         Add special r3900 version of do_mult_hilo.
 780         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 781         with calls to check_mult_hilo.
 782         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 783         with calls to check_div_hilo.
 784
 785 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 786
 787         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 788         Document a replacement.
 789
 790 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 791
 792         * interp.c (sim_monitor): Make mon_printf work.
 793
 794 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 795
 796         * sim-main.h (INSN_NAME): New arg `cpu'.
 797
 798 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 799
 800         * configure: Regenerated to track ../common/aclocal.m4 changes.
 801
 802 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 803
 804         * configure: Regenerated to track ../common/aclocal.m4 changes.
 805         * config.in: Ditto.
 806
 807 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 808
 809         * acconfig.h: New file.
 810         * configure.in: Reverted change of Apr 24; use sinclude again.
 811
 812 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 813
 814         * configure: Regenerated to track ../common/aclocal.m4 changes.
 815         * config.in: Ditto.
 816
 817 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 818
 819         * configure.in: Don't call sinclude.
 820
 821 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 822
 823         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 824
 825 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 826
 827         * mips.igen (ERET): Implement.
 828
 829         * interp.c (decode_coproc): Return sign-extended EPC.
 830
 831         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 832
 833         * interp.c (signal_exception): Do not ignore Trap.
 834         (signal_exception): On TRAP, restart at exception address.
 835         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 836         (signal_exception): Update.
 837         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 838         so that TRAP instructions are caught.
 839
 840 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 841
 842         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 843         contains HI/LO access history.
 844         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 845         (HIACCESS, LOACCESS): Delete, replace with
 846         (HIHISTORY, LOHISTORY): New macros.
 847         (CHECKHILO): Delete all, moved to mips.igen
 848
 849         * gencode.c (build_instruction): Do not generate checks for
 850         correct HI/LO register usage.
 851
 852         * interp.c (old_engine_run): Delete checks for correct HI/LO
 853         register usage.
 854
 855         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 856         check_mf_cycles): New functions.
 857         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 858         do_divu, domultx, do_mult, do_multu): Use.
 859
 860         * tx.igen ("madd", "maddu"): Use.
 861
 862 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 863
 864         * mips.igen (DSRAV): Use function do_dsrav.
 865         (SRAV): Use new function do_srav.
 866
 867         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 868         (B): Sign extend 11 bit immediate.
 869         (EXT-B*): Shift 16 bit immediate left by 1.
 870         (ADDIU*): Don't sign extend immediate value.
 871
 872 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 873
 874         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 875
 876         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 877         functions.
 878
 879         * mips.igen (delayslot32, nullify_next_insn): New functions.
 880         (m16.igen): Always include.
 881         (do_*): Add more tracing.
 882
 883         * m16.igen (delayslot16): Add NIA argument, could be called by a
 884         32 bit MIPS16 instruction.
 885
 886         * interp.c (ifetch16): Move function from here.
 887         * sim-main.c (ifetch16): To here.
 888
 889         * sim-main.c (ifetch16, ifetch32): Update to match current
 890         implementations of LH, LW.
 891         (signal_exception): Don't print out incorrect hex value of illegal
 892         instruction.
 893
 894 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 895
 896         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 897         instruction.
 898
 899         * m16.igen: Implement MIPS16 instructions.
 900
 901         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 902         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 903         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 904         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 905         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 906         bodies of corresponding code from 32 bit insn to these.  Also used
 907         by MIPS16 versions of functions.
 908
 909         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 910         (IMEM16): Drop NR argument from macro.
 911
 912 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 913
 914         * Makefile.in (SIM_OBJS): Add sim-main.o.
 915
 916         * sim-main.h (address_translation, load_memory, store_memory,
 917         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 918         as INLINE_SIM_MAIN.
 919         (pr_addr, pr_uword64): Declare.
 920         (sim-main.c): Include when H_REVEALS_MODULE_P.
 921
 922         * interp.c (address_translation, load_memory, store_memory,
 923         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 924         from here.
 925         * sim-main.c: To here. Fix compilation problems.
 926
 927         * configure.in: Enable inlining.
 928         * configure: Re-config.
 929
 930 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 931
 932         * configure: Regenerated to track ../common/aclocal.m4 changes.
 933
 934 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 935
 936         * mips.igen: Include tx.igen.
 937         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 938         * tx.igen: New file, contains MADD and MADDU.
 939
 940         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 941         the hardwired constant `7'.
 942         (store_memory): Ditto.
 943         (LOADDRMASK): Move definition to sim-main.h.
 944
 945         mips.igen (MTC0): Enable for r3900.
 946         (ADDU): Add trace.
 947
 948         mips.igen (do_load_byte): Delete.
 949         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 950         do_store_right): New functions.
 951         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 952
 953         configure.in: Let the tx39 use igen again.
 954         configure: Update.
 955
 956 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 957
 958         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 959         not an address sized quantity.  Return zero for cache sizes.
 960
 961 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 962
 963         * mips.igen (r3900): r3900 does not support 64 bit integer
 964         operations.
 965
 966 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 967
 968         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 969         than igen one.
 970         * configure : Rebuild.
 971
 972 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 973
 974         * configure: Regenerated to track ../common/aclocal.m4 changes.
 975
 976 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 977
 978         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
 979
 980 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
 981
 982         * configure: Regenerated to track ../common/aclocal.m4 changes.
 983         * config.in: Regenerated to track ../common/aclocal.m4 changes.
 984
 985 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 986
 987         * configure: Regenerated to track ../common/aclocal.m4 changes.
 988
 989 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 990
 991         * interp.c (Max, Min): Comment out functions. Not yet used.
 992
 993 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 994
 995         * configure: Regenerated to track ../common/aclocal.m4 changes.
 996
 997 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
 998
 999         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1000         configurable settings for stand-alone simulator.
1001
1002         * configure.in: Added X11 search, just in case.
1003
1004         * configure: Regenerated.
1005
1006 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1007
1008         * interp.c (sim_write, sim_read, load_memory, store_memory):
1009         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1010
1011 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1012
1013         * sim-main.h (GETFCC): Return an unsigned value.
1014
1015 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1016
1017         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1018         (DADD): Result destination is RD not RT.
1019
1020 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1021
1022         * sim-main.h (HIACCESS, LOACCESS): Always define.
1023
1024         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1025
1026         * interp.c (sim_info): Delete.
1027
1028 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1029
1030         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1031         (mips_option_handler): New argument `cpu'.
1032         (sim_open): Update call to sim_add_option_table.
1033
1034 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1035
1036         * mips.igen (CxC1): Add tracing.
1037
1038 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1039
1040         * sim-main.h (Max, Min): Declare.
1041
1042         * interp.c (Max, Min): New functions.
1043
1044         * mips.igen (BC1): Add tracing.
1045
1046 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1047
1048         * interp.c Added memory map for stack in vr4100
1049
1050 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1051
1052         * interp.c (load_memory): Add missing "break"'s.
1053
1054 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1055
1056         * interp.c (sim_store_register, sim_fetch_register): Pass in
1057         length parameter.  Return -1.
1058
1059 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1060
1061         * interp.c: Added hardware init hook, fixed warnings.
1062
1063 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1064
1065         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1066
1067 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1068
1069         * interp.c (ifetch16): New function.
1070
1071         * sim-main.h (IMEM32): Rename IMEM.
1072         (IMEM16_IMMED): Define.
1073         (IMEM16): Define.
1074         (DELAY_SLOT): Update.
1075
1076         * m16run.c (sim_engine_run): New file.
1077
1078         * m16.igen: All instructions except LB.
1079         (LB): Call do_load_byte.
1080         * mips.igen (do_load_byte): New function.
1081         (LB): Call do_load_byte.
1082
1083         * mips.igen: Move spec for insn bit size and high bit from here.
1084         * Makefile.in (tmp-igen, tmp-m16): To here.
1085
1086         * m16.dc: New file, decode mips16 instructions.
1087
1088         * Makefile.in (SIM_NO_ALL): Define.
1089         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1090
1091 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1092
1093         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1094         point unit to 32 bit registers.
1095         * configure: Re-generate.
1096
1097 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1098
1099         * configure.in (sim_use_gen): Make IGEN the default simulator
1100         generator for generic 32 and 64 bit mips targets.
1101         * configure: Re-generate.
1102
1103 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1104
1105         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1106         bitsize.
1107
1108         * interp.c (sim_fetch_register, sim_store_register): Read/write
1109         FGR from correct location.
1110         (sim_open): Set size of FGR's according to
1111         WITH_TARGET_FLOATING_POINT_BITSIZE.
1112
1113         * sim-main.h (FGR): Store floating point registers in a separate
1114         array.
1115
1116 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1117
1118         * configure: Regenerated to track ../common/aclocal.m4 changes.
1119
1120 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1121
1122         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1123
1124         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1125
1126         * interp.c (pending_tick): New function.  Deliver pending writes.
1127
1128         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1129         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1130         it can handle mixed sized quantites and single bits.
1131
1132 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1133
1134         * interp.c (oengine.h): Do not include when building with IGEN.
1135         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1136         (sim_info): Ditto for PROCESSOR_64BIT.
1137         (sim_monitor): Replace ut_reg with unsigned_word.
1138         (*): Ditto for t_reg.
1139         (LOADDRMASK): Define.
1140         (sim_open): Remove defunct check that host FP is IEEE compliant,
1141         using software to emulate floating point.
1142         (value_fpr, ...): Always compile, was conditional on HASFPU.
1143
1144 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1145
1146         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1147         size.
1148
1149         * interp.c (SD, CPU): Define.
1150         (mips_option_handler): Set flags in each CPU.
1151         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1152         (sim_close): Do not clear STATE, deleted anyway.
1153         (sim_write, sim_read): Assume CPU zero's vm should be used for
1154         data transfers.
1155         (sim_create_inferior): Set the PC for all processors.
1156         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1157         argument.
1158         (mips16_entry): Pass correct nr of args to store_word, load_word.
1159         (ColdReset): Cold reset all cpu's.
1160         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1161         (sim_monitor, load_memory, store_memory, signal_exception): Use
1162         `CPU' instead of STATE_CPU.
1163
1164
1165         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1166         SD or CPU_.
1167
1168         * sim-main.h (signal_exception): Add sim_cpu arg.
1169         (SignalException*): Pass both SD and CPU to signal_exception.
1170         * interp.c (signal_exception): Update.
1171
1172         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1173         Ditto
1174         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1175         address_translation): Ditto
1176         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1177
1178 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1179
1180         * configure: Regenerated to track ../common/aclocal.m4 changes.
1181
1182 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1183
1184         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1185
1186         * mips.igen (model): Map processor names onto BFD name.
1187
1188         * sim-main.h (CPU_CIA): Delete.
1189         (SET_CIA, GET_CIA): Define
1190
1191 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1192
1193         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1194         regiser.
1195
1196         * configure.in (default_endian): Configure a big-endian simulator
1197         by default.
1198         * configure: Re-generate.
1199
1200 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1201
1202         * configure: Regenerated to track ../common/aclocal.m4 changes.
1203
1204 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1205
1206         * interp.c (sim_monitor): Handle Densan monitor outbyte
1207         and inbyte functions.
1208
1209 1997-12-29  Felix Lee  <flee@cygnus.com>
1210
1211         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1212
1213 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1214
1215         * Makefile.in (tmp-igen): Arrange for $zero to always be
1216         reset to zero after every instruction.
1217
1218 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1219
1220         * configure: Regenerated to track ../common/aclocal.m4 changes.
1221         * config.in: Ditto.
1222
1223 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1224
1225         * mips.igen (MSUB): Fix to work like MADD.
1226         * gencode.c (MSUB): Similarly.
1227
1228 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1229
1230         * configure: Regenerated to track ../common/aclocal.m4 changes.
1231
1232 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1233
1234         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1235
1236 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1237
1238         * sim-main.h (sim-fpu.h): Include.
1239
1240         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1241         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1242         using host independant sim_fpu module.
1243
1244 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1245
1246         * interp.c (signal_exception): Report internal errors with SIGABRT
1247         not SIGQUIT.
1248
1249         * sim-main.h (C0_CONFIG): New register.
1250         (signal.h): No longer include.
1251
1252         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1253
1254 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1255
1256         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1257
1258 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1259
1260         * mips.igen: Tag vr5000 instructions.
1261         (ANDI): Was missing mipsIV model, fix assembler syntax.
1262         (do_c_cond_fmt): New function.
1263         (C.cond.fmt): Handle mips I-III which do not support CC field
1264         separatly.
1265         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1266         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1267         in IV3.2 spec.
1268         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1269         vr5000 which saves LO in a GPR separatly.
1270
1271         * configure.in (enable-sim-igen): For vr5000, select vr5000
1272         specific instructions.
1273         * configure: Re-generate.
1274
1275 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1276
1277         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1278
1279         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1280         fmt_uninterpreted_64 bit cases to switch.  Convert to
1281         fmt_formatted,
1282
1283         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1284
1285         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1286         as specified in IV3.2 spec.
1287         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1288
1289 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1290
1291         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1292         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1293         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1294         PENDING_FILL versions of instructions.  Simplify.
1295         (X): New function.
1296         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1297         instructions.
1298         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1299         a signed value.
1300         (MTHI, MFHI): Disable code checking HI-LO.
1301
1302         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1303         global.
1304         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1305
1306 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1307
1308         * gencode.c (build_mips16_operands): Replace IPC with cia.
1309
1310         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1311         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1312         IPC to `cia'.
1313         (UndefinedResult): Replace function with macro/function
1314         combination.
1315         (sim_engine_run): Don't save PC in IPC.
1316
1317         * sim-main.h (IPC): Delete.
1318
1319
1320         * interp.c (signal_exception, store_word, load_word,
1321         address_translation, load_memory, store_memory, cache_op,
1322         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1323         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1324         current instruction address - cia - argument.
1325         (sim_read, sim_write): Call address_translation directly.
1326         (sim_engine_run): Rename variable vaddr to cia.
1327         (signal_exception): Pass cia to sim_monitor
1328
1329         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1330         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1331         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1332
1333         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1334         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1335         SIM_ASSERT.
1336
1337         * interp.c (signal_exception): Pass restart address to
1338         sim_engine_restart.
1339
1340         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1341         idecode.o): Add dependency.
1342
1343         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1344         Delete definitions
1345         (DELAY_SLOT): Update NIA not PC with branch address.
1346         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1347
1348         * mips.igen: Use CIA not PC in branch calculations.
1349         (illegal): Call SignalException.
1350         (BEQ, ADDIU): Fix assembler.
1351
1352 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1353
1354         * m16.igen (JALX): Was missing.
1355
1356         * configure.in (enable-sim-igen): New configuration option.
1357         * configure: Re-generate.
1358
1359         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1360
1361         * interp.c (load_memory, store_memory): Delete parameter RAW.
1362         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1363         bypassing {load,store}_memory.
1364
1365         * sim-main.h (ByteSwapMem): Delete definition.
1366
1367         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1368
1369         * interp.c (sim_do_command, sim_commands): Delete mips specific
1370         commands.  Handled by module sim-options.
1371
1372         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1373         (WITH_MODULO_MEMORY): Define.
1374
1375         * interp.c (sim_info): Delete code printing memory size.
1376
1377         * interp.c (mips_size): Nee sim_size, delete function.
1378         (power2): Delete.
1379         (monitor, monitor_base, monitor_size): Delete global variables.
1380         (sim_open, sim_close): Delete code creating monitor and other
1381         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1382         manage memory regions.
1383         (load_memory, store_memory): Use sim-core for memory model.
1384
1385         * interp.c (address_translation): Delete all memory map code
1386         except line forcing 32 bit addresses.
1387
1388 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1389
1390         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1391         trace options.
1392
1393         * interp.c (logfh, logfile): Delete globals.
1394         (sim_open, sim_close): Delete code opening & closing log file.
1395         (mips_option_handler): Delete -l and -n options.
1396         (OPTION mips_options): Ditto.
1397
1398         * interp.c (OPTION mips_options): Rename option trace to dinero.
1399         (mips_option_handler): Update.
1400
1401 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1402
1403         * interp.c (fetch_str): New function.
1404         (sim_monitor): Rewrite using sim_read & sim_write.
1405         (sim_open): Check magic number.
1406         (sim_open): Write monitor vectors into memory using sim_write.
1407         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1408         (sim_read, sim_write): Simplify - transfer data one byte at a
1409         time.
1410         (load_memory, store_memory): Clarify meaning of parameter RAW.
1411
1412         * sim-main.h (isHOST): Defete definition.
1413         (isTARGET): Mark as depreciated.
1414         (address_translation): Delete parameter HOST.
1415
1416         * interp.c (address_translation): Delete parameter HOST.
1417
1418 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1419
1420         * mips.igen:
1421
1422         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1423         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1424
1425 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1426
1427         * mips.igen: Add model filter field to records.
1428
1429 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1430
1431         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1432
1433         interp.c (sim_engine_run): Do not compile function sim_engine_run
1434         when WITH_IGEN == 1.
1435
1436         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1437         target architecture.
1438
1439         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1440         igen. Replace with configuration variables sim_igen_flags /
1441         sim_m16_flags.
1442
1443         * m16.igen: New file.  Copy mips16 insns here.
1444         * mips.igen: From here.
1445
1446 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1447
1448         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1449         to top.
1450         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1451
1452 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1453
1454         * gencode.c (build_instruction): Follow sim_write's lead in using
1455         BigEndianMem instead of !ByteSwapMem.
1456
1457 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1458
1459         * configure.in (sim_gen): Dependent on target, select type of
1460         generator.  Always select old style generator.
1461
1462         configure: Re-generate.
1463
1464         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1465         targets.
1466         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1467         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1468         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1469         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1470         SIM_@sim_gen@_*, set by autoconf.
1471
1472 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1473
1474         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1475
1476         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1477         CURRENT_FLOATING_POINT instead.
1478
1479         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1480         (address_translation): Raise exception InstructionFetch when
1481         translation fails and isINSTRUCTION.
1482
1483         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1484         sim_engine_run): Change type of of vaddr and paddr to
1485         address_word.
1486         (address_translation, prefetch, load_memory, store_memory,
1487         cache_op): Change type of vAddr and pAddr to address_word.
1488
1489         * gencode.c (build_instruction): Change type of vaddr and paddr to
1490         address_word.
1491
1492 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1493
1494         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1495         macro to obtain result of ALU op.
1496
1497 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1498
1499         * interp.c (sim_info): Call profile_print.
1500
1501 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1502
1503         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1504
1505         * sim-main.h (WITH_PROFILE): Do not define, defined in
1506         common/sim-config.h.  Use sim-profile module.
1507         (simPROFILE): Delete defintion.
1508
1509         * interp.c (PROFILE): Delete definition.
1510         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1511         (sim_close): Delete code writing profile histogram.
1512         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1513         Delete.
1514         (sim_engine_run): Delete code profiling the PC.
1515
1516 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1517
1518         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1519
1520         * interp.c (sim_monitor): Make register pointers of type
1521         unsigned_word*.
1522
1523         * sim-main.h: Make registers of type unsigned_word not
1524         signed_word.
1525
1526 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1527
1528         * interp.c (sync_operation): Rename from SyncOperation, make
1529         global, add SD argument.
1530         (prefetch): Rename from Prefetch, make global, add SD argument.
1531         (decode_coproc): Make global.
1532
1533         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1534
1535         * gencode.c (build_instruction): Generate DecodeCoproc not
1536         decode_coproc calls.
1537
1538         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1539         (SizeFGR): Move to sim-main.h
1540         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1541         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1542         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1543         sim-main.h.
1544         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1545         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1546         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1547         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1548         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1549         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1550
1551         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1552         exception.
1553         (sim-alu.h): Include.
1554         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1555         (sim_cia): Typedef to instruction_address.
1556
1557 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1558
1559         * Makefile.in (interp.o): Rename generated file engine.c to
1560         oengine.c.
1561
1562         * interp.c: Update.
1563
1564 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1565
1566         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1567
1568 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1569
1570         * gencode.c (build_instruction): For "FPSQRT", output correct
1571         number of arguments to Recip.
1572
1573 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1574
1575         * Makefile.in (interp.o): Depends on sim-main.h
1576
1577         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1578
1579         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1580         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1581         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1582         STATE, DSSTATE): Define
1583         (GPR, FGRIDX, ..): Define.
1584
1585         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1586         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1587         (GPR, FGRIDX, ...): Delete macros.
1588
1589         * interp.c: Update names to match defines from sim-main.h
1590
1591 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1592
1593         * interp.c (sim_monitor): Add SD argument.
1594         (sim_warning): Delete.  Replace calls with calls to
1595         sim_io_eprintf.
1596         (sim_error): Delete. Replace calls with sim_io_error.
1597         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1598         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1599         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1600         argument.
1601         (mips_size): Rename from sim_size. Add SD argument.
1602
1603         * interp.c (simulator): Delete global variable.
1604         (callback): Delete global variable.
1605         (mips_option_handler, sim_open, sim_write, sim_read,
1606         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1607         sim_size,sim_monitor): Use sim_io_* not callback->*.
1608         (sim_open): ZALLOC simulator struct.
1609         (PROFILE): Do not define.
1610
1611 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1612
1613         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1614         support.h with corresponding code.
1615
1616         * sim-main.h (word64, uword64), support.h: Move definition to
1617         sim-main.h.
1618         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1619
1620         * support.h: Delete
1621         * Makefile.in: Update dependencies
1622         * interp.c: Do not include.
1623
1624 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1625
1626         * interp.c (address_translation, load_memory, store_memory,
1627         cache_op): Rename to from AddressTranslation et.al., make global,
1628         add SD argument
1629
1630         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1631         CacheOp): Define.
1632
1633         * interp.c (SignalException): Rename to signal_exception, make
1634         global.
1635
1636         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1637
1638         * sim-main.h (SignalException, SignalExceptionInterrupt,
1639         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1640         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1641         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1642         Define.
1643
1644         * interp.c, support.h: Use.
1645
1646 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1647
1648         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1649         to value_fpr / store_fpr. Add SD argument.
1650         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1651         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1652
1653         * sim-main.h (ValueFPR, StoreFPR): Define.
1654
1655 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1656
1657         * interp.c (sim_engine_run): Check consistency between configure
1658         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1659         and HASFPU.
1660
1661         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1662         (mips_fpu): Configure WITH_FLOATING_POINT.
1663         (mips_endian): Configure WITH_TARGET_ENDIAN.
1664         * configure: Update.
1665
1666 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1667
1668         * configure: Regenerated to track ../common/aclocal.m4 changes.
1669
1670 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1671
1672         * configure: Regenerated.
1673
1674 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1675
1676         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1677
1678 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1679
1680         * gencode.c (print_igen_insn_models): Assume certain architectures
1681         include all mips* instructions.
1682         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1683         instruction.
1684
1685         * Makefile.in (tmp.igen): Add target. Generate igen input from
1686         gencode file.
1687
1688         * gencode.c (FEATURE_IGEN): Define.
1689         (main): Add --igen option.  Generate output in igen format.
1690         (process_instructions): Format output according to igen option.
1691         (print_igen_insn_format): New function.
1692         (print_igen_insn_models): New function.
1693         (process_instructions): Only issue warnings and ignore
1694         instructions when no FEATURE_IGEN.
1695
1696 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1697
1698         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1699         MIPS targets.
1700
1701 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1702
1703         * configure: Regenerated to track ../common/aclocal.m4 changes.
1704
1705 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1706
1707         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1708         SIM_RESERVED_BITS): Delete, moved to common.
1709         (SIM_EXTRA_CFLAGS): Update.
1710
1711 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1712
1713         * configure.in: Configure non-strict memory alignment.
1714         * configure: Regenerated to track ../common/aclocal.m4 changes.
1715
1716 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1717
1718         * configure: Regenerated to track ../common/aclocal.m4 changes.
1719
1720 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1721
1722         * gencode.c (SDBBP,DERET): Added (3900) insns.
1723         (RFE): Turn on for 3900.
1724         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1725         (dsstate): Made global.
1726         (SUBTARGET_R3900): Added.
1727         (CANCELDELAYSLOT): New.
1728         (SignalException): Ignore SystemCall rather than ignore and
1729         terminate.  Add DebugBreakPoint handling.
1730         (decode_coproc): New insns RFE, DERET; and new registers Debug
1731         and DEPC protected by SUBTARGET_R3900.
1732         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1733         bits explicitly.
1734         * Makefile.in,configure.in: Add mips subtarget option.
1735         * configure: Update.
1736
1737 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1738
1739         * gencode.c: Add r3900 (tx39).
1740
1741
1742 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1743
1744         * gencode.c (build_instruction): Don't need to subtract 4 for
1745         JALR, just 2.
1746
1747 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1748
1749         * interp.c: Correct some HASFPU problems.
1750
1751 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1752
1753         * configure: Regenerated to track ../common/aclocal.m4 changes.
1754
1755 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1756
1757         * interp.c (mips_options): Fix samples option short form, should
1758         be `x'.
1759
1760 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1761
1762         * interp.c (sim_info): Enable info code.  Was just returning.
1763
1764 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1765
1766         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1767         MFC0.
1768
1769 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1770
1771         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1772         constants.
1773         (build_instruction): Ditto for LL.
1774
1775 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1776
1777         * configure: Regenerated to track ../common/aclocal.m4 changes.
1778
1779 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1780
1781         * configure: Regenerated to track ../common/aclocal.m4 changes.
1782         * config.in: Ditto.
1783
1784 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1785
1786         * interp.c (sim_open): Add call to sim_analyze_program, update
1787         call to sim_config.
1788
1789 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1790
1791         * interp.c (sim_kill): Delete.
1792         (sim_create_inferior): Add ABFD argument. Set PC from same.
1793         (sim_load): Move code initializing trap handlers from here.
1794         (sim_open): To here.
1795         (sim_load): Delete, use sim-hload.c.
1796
1797         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1798
1799 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1800
1801         * configure: Regenerated to track ../common/aclocal.m4 changes.
1802         * config.in: Ditto.
1803
1804 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1805
1806         * interp.c (sim_open): Add ABFD argument.
1807         (sim_load): Move call to sim_config from here.
1808         (sim_open): To here.  Check return status.
1809
1810 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1811
1812         * gencode.c (build_instruction): Two arg MADD should
1813         not assign result to $0.
1814
1815 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1816
1817         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1818         * sim/mips/configure.in: Regenerate.
1819
1820 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1821
1822         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1823         signed8, unsigned8 et.al. types.
1824
1825         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1826         hosts when selecting subreg.
1827
1828 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1829
1830         * interp.c (sim_engine_run): Reset the ZERO register to zero
1831         regardless of FEATURE_WARN_ZERO.
1832         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1833
1834 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1835
1836         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1837         (SignalException): For BreakPoints ignore any mode bits and just
1838         save the PC.
1839         (SignalException): Always set the CAUSE register.
1840
1841 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1842
1843         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1844         exception has been taken.
1845
1846         * interp.c: Implement the ERET and mt/f sr instructions.
1847
1848 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1849
1850         * interp.c (SignalException): Don't bother restarting an
1851         interrupt.
1852
1853 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1854
1855         * interp.c (SignalException): Really take an interrupt.
1856         (interrupt_event): Only deliver interrupts when enabled.
1857
1858 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1859
1860         * interp.c (sim_info): Only print info when verbose.
1861         (sim_info) Use sim_io_printf for output.
1862
1863 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1864
1865         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1866         mips architectures.
1867
1868 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1869
1870         * interp.c (sim_do_command): Check for common commands if a
1871         simulator specific command fails.
1872
1873 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1874
1875         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1876         and simBE when DEBUG is defined.
1877
1878 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1879
1880         * interp.c (interrupt_event): New function.  Pass exception event
1881         onto exception handler.
1882
1883         * configure.in: Check for stdlib.h.
1884         * configure: Regenerate.
1885
1886         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1887         variable declaration.
1888         (build_instruction): Initialize memval1.
1889         (build_instruction): Add UNUSED attribute to byte, bigend,
1890         reverse.
1891         (build_operands): Ditto.
1892
1893         * interp.c: Fix GCC warnings.
1894         (sim_get_quit_code): Delete.
1895
1896         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1897         * Makefile.in: Ditto.
1898         * configure: Re-generate.
1899
1900         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1901
1902 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1903
1904         * interp.c (mips_option_handler): New function parse argumes using
1905         sim-options.
1906         (myname): Replace with STATE_MY_NAME.
1907         (sim_open): Delete check for host endianness - performed by
1908         sim_config.
1909         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1910         (sim_open): Move much of the initialization from here.
1911         (sim_load): To here.  After the image has been loaded and
1912         endianness set.
1913         (sim_open): Move ColdReset from here.
1914         (sim_create_inferior): To here.
1915         (sim_open): Make FP check less dependant on host endianness.
1916
1917         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1918         run.
1919         * interp.c (sim_set_callbacks): Delete.
1920
1921         * interp.c (membank, membank_base, membank_size): Replace with
1922         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1923         (sim_open): Remove call to callback->init. gdb/run do this.
1924
1925         * interp.c: Update
1926
1927         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1928
1929         * interp.c (big_endian_p): Delete, replaced by
1930         current_target_byte_order.
1931
1932 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * interp.c (host_read_long, host_read_word, host_swap_word,
1935         host_swap_long): Delete. Using common sim-endian.
1936         (sim_fetch_register, sim_store_register): Use H2T.
1937         (pipeline_ticks): Delete.  Handled by sim-events.
1938         (sim_info): Update.
1939         (sim_engine_run): Update.
1940
1941 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1942
1943         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1944         reason from here.
1945         (SignalException): To here. Signal using sim_engine_halt.
1946         (sim_stop_reason): Delete, moved to common.
1947
1948 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
1949
1950         * interp.c (sim_open): Add callback argument.
1951         (sim_set_callbacks): Delete SIM_DESC argument.
1952         (sim_size): Ditto.
1953
1954 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1955
1956         * Makefile.in (SIM_OBJS): Add common modules.
1957
1958         * interp.c (sim_set_callbacks): Also set SD callback.
1959         (set_endianness, xfer_*, swap_*): Delete.
1960         (host_read_word, host_read_long, host_swap_word, host_swap_long):
1961         Change to functions using sim-endian macros.
1962         (control_c, sim_stop): Delete, use common version.
1963         (simulate): Convert into.
1964         (sim_engine_run): This function.
1965         (sim_resume): Delete.
1966
1967         * interp.c (simulation): New variable - the simulator object.
1968         (sim_kind): Delete global - merged into simulation.
1969         (sim_load): Cleanup.  Move PC assignment from here.
1970         (sim_create_inferior): To here.
1971
1972         * sim-main.h: New file.
1973         * interp.c (sim-main.h): Include.
1974
1975 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
1976
1977         * configure: Regenerated to track ../common/aclocal.m4 changes.
1978
1979 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
1980
1981         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1982
1983 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
1984
1985         * gencode.c (build_instruction): DIV instructions: check
1986         for division by zero and integer overflow before using
1987         host's division operation.
1988
1989 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
1990
1991         * Makefile.in (SIM_OBJS): Add sim-load.o.
1992         * interp.c: #include bfd.h.
1993         (target_byte_order): Delete.
1994         (sim_kind, myname, big_endian_p): New static locals.
1995         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
1996         after argument parsing.  Recognize -E arg, set endianness accordingly.
1997         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
1998         load file into simulator.  Set PC from bfd.
1999         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2000         (set_endianness): Use big_endian_p instead of target_byte_order.
2001
2002 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2003
2004         * interp.c (sim_size): Delete prototype - conflicts with
2005         definition in remote-sim.h.  Correct definition.
2006
2007 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2008
2009         * configure: Regenerated to track ../common/aclocal.m4 changes.
2010         * config.in: Ditto.
2011
2012 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2013
2014         * interp.c (sim_open): New arg `kind'.
2015
2016         * configure: Regenerated to track ../common/aclocal.m4 changes.
2017
2018 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2019
2020         * configure: Regenerated to track ../common/aclocal.m4 changes.
2021
2022 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2023
2024         * interp.c (sim_open): Set optind to 0 before calling getopt.
2025
2026 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2027
2028         * configure: Regenerated to track ../common/aclocal.m4 changes.
2029
2030 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2031
2032         * interp.c : Replace uses of pr_addr with pr_uword64
2033         where the bit length is always 64 independent of SIM_ADDR.
2034         (pr_uword64) : added.
2035
2036 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2037
2038         * configure: Re-generate.
2039
2040 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2041
2042         * configure: Regenerate to track ../common/aclocal.m4 changes.
2043
2044 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2045
2046         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2047         in argv form.
2048         (other sim_*): New SIM_DESC argument.
2049
2050 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2051
2052         * interp.c: Fix printing of addresses for non-64-bit targets.
2053         (pr_addr): Add function to print address based on size.
2054
2055 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2056
2057         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2058
2059 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2060
2061         * gencode.c (build_mips16_operands): Correct computation of base
2062         address for extended PC relative instruction.
2063
2064 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2065
2066         * interp.c (mips16_entry): Add support for floating point cases.
2067         (SignalException): Pass floating point cases to mips16_entry.
2068         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2069         registers.
2070         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2071         or fmt_word.
2072         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2073         and then set the state to fmt_uninterpreted.
2074         (COP_SW): Temporarily set the state to fmt_word while calling
2075         ValueFPR.
2076
2077 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2078
2079         * gencode.c (build_instruction): The high order may be set in the
2080         comparison flags at any ISA level, not just ISA 4.
2081
2082 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2083
2084         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2085         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2086         * configure.in: sinclude ../common/aclocal.m4.
2087         * configure: Regenerated.
2088
2089 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2090
2091         * configure: Rebuild after change to aclocal.m4.
2092
2093 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2094
2095         * configure configure.in Makefile.in:  Update to new configure
2096         scheme which is more compatible with WinGDB builds.
2097         * configure.in:  Improve comment on how to run autoconf.
2098         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2099         * Makefile.in:  Use autoconf substitution to install common
2100         makefile fragment.
2101
2102 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2103
2104         * gencode.c (build_instruction): Use BigEndianCPU instead of
2105         ByteSwapMem.
2106
2107 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2108
2109         * interp.c (sim_monitor): Make output to stdout visible in
2110         wingdb's I/O log window.
2111
2112 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2113
2114         * support.h: Undo previous change to SIGTRAP
2115         and SIGQUIT values.
2116
2117 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2118
2119         * interp.c (store_word, load_word): New static functions.
2120         (mips16_entry): New static function.
2121         (SignalException): Look for mips16 entry and exit instructions.
2122         (simulate): Use the correct index when setting fpr_state after
2123         doing a pending move.
2124
2125 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2126
2127         * interp.c: Fix byte-swapping code throughout to work on
2128         both little- and big-endian hosts.
2129
2130 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2131
2132         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2133         with gdb/config/i386/xm-windows.h.
2134
2135 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2136
2137         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2138         that messes up arithmetic shifts.
2139
2140 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2141
2142         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2143         SIGTRAP and SIGQUIT for _WIN32.
2144
2145 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2146
2147         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2148         force a 64 bit multiplication.
2149         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2150         destination register is 0, since that is the default mips16 nop
2151         instruction.
2152
2153 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2154
2155         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2156         (build_endian_shift): Don't check proc64.
2157         (build_instruction): Always set memval to uword64.  Cast op2 to
2158         uword64 when shifting it left in memory instructions.  Always use
2159         the same code for stores--don't special case proc64.
2160
2161         * gencode.c (build_mips16_operands): Fix base PC value for PC
2162         relative operands.
2163         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2164         jal instruction.
2165         * interp.c (simJALDELAYSLOT): Define.
2166         (JALDELAYSLOT): Define.
2167         (INDELAYSLOT, INJALDELAYSLOT): Define.
2168         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2169
2170 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2171
2172         * interp.c (sim_open): add flush_cache as a PMON routine
2173         (sim_monitor): handle flush_cache by ignoring it
2174
2175 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2176
2177         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2178         BigEndianMem.
2179         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2180         (BigEndianMem): Rename to ByteSwapMem and change sense.
2181         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2182         BigEndianMem references to !ByteSwapMem.
2183         (set_endianness): New function, with prototype.
2184         (sim_open): Call set_endianness.
2185         (sim_info): Use simBE instead of BigEndianMem.
2186         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2187         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2188         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2189         ifdefs, keeping the prototype declaration.
2190         (swap_word): Rewrite correctly.
2191         (ColdReset): Delete references to CONFIG.  Delete endianness related
2192         code; moved to set_endianness.
2193
2194 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2195
2196         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2197         * interp.c (CHECKHILO): Define away.
2198         (simSIGINT): New macro.
2199         (membank_size): Increase from 1MB to 2MB.
2200         (control_c): New function.
2201         (sim_resume): Rename parameter signal to signal_number.  Add local
2202         variable prev.  Call signal before and after simulate.
2203         (sim_stop_reason): Add simSIGINT support.
2204         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2205         functions always.
2206         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2207         if logfh is NULL.
2208         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2209         a call to sim_warning.
2210
2211 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2212
2213         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2214         16 bit instructions.
2215
2216 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2217
2218         Add support for mips16 (16 bit MIPS implementation):
2219         * gencode.c (inst_type): Add mips16 instruction encoding types.
2220         (GETDATASIZEINSN): Define.
2221         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2222         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2223         mtlo.
2224         (MIPS16_DECODE): New table, for mips16 instructions.
2225         (bitmap_val): New static function.
2226         (struct mips16_op): Define.
2227         (mips16_op_table): New table, for mips16 operands.
2228         (build_mips16_operands): New static function.
2229         (process_instructions): If PC is odd, decode a mips16
2230         instruction.  Break out instruction handling into new
2231         build_instruction function.
2232         (build_instruction): New static function, broken out of
2233         process_instructions.  Check modifiers rather than flags for SHIFT
2234         bit count and m[ft]{hi,lo} direction.
2235         (usage): Pass program name to fprintf.
2236         (main): Remove unused variable this_option_optind.  Change
2237         ``*loptarg++'' to ``loptarg++''.
2238         (my_strtoul): Parenthesize && within ||.
2239         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2240         (simulate): If PC is odd, fetch a 16 bit instruction, and
2241         increment PC by 2 rather than 4.
2242         * configure.in: Add case for mips16*-*-*.
2243         * configure: Rebuild.
2244
2245 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2246
2247         * interp.c: Allow -t to enable tracing in standalone simulator.
2248         Fix garbage output in trace file and error messages.
2249
2250 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2251
2252         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2253         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2254         * configure.in: Simplify using macros in ../common/aclocal.m4.
2255         * configure: Regenerated.
2256         * tconfig.in: New file.
2257
2258 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2259
2260         * interp.c: Fix bugs in 64-bit port.
2261         Use ansi function declarations for msvc compiler.
2262         Initialize and test file pointer in trace code.
2263         Prevent duplicate definition of LAST_EMED_REGNUM.
2264
2265 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2266
2267         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2268
2269 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2270
2271         * interp.c (SignalException): Check for explicit terminating
2272         breakpoint value.
2273         * gencode.c: Pass instruction value through SignalException()
2274         calls for Trap, Breakpoint and Syscall.
2275
2276 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2277
2278         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2279         only used on those hosts that provide it.
2280         * configure.in: Add sqrt() to list of functions to be checked for.
2281         * config.in: Re-generated.
2282         * configure: Re-generated.
2283
2284 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2285
2286         * gencode.c (process_instructions): Call build_endian_shift when
2287         expanding STORE RIGHT, to fix swr.
2288         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2289         clear the high bits.
2290         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2291         Fix float to int conversions to produce signed values.
2292
2293 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2294
2295         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2296         (process_instructions): Correct handling of nor instruction.
2297         Correct shift count for 32 bit shift instructions. Correct sign
2298         extension for arithmetic shifts to not shift the number of bits in
2299         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2300         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2301         Fix madd.
2302         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2303         It's OK to have a mult follow a mult.  What's not OK is to have a
2304         mult follow an mfhi.
2305         (Convert): Comment out incorrect rounding code.
2306
2307 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2308
2309         * interp.c (sim_monitor): Improved monitor printf
2310         simulation. Tidied up simulator warnings, and added "--log" option
2311         for directing warning message output.
2312         * gencode.c: Use sim_warning() rather than WARNING macro.
2313
2314 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2315
2316         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2317         getopt1.o, rather than on gencode.c.  Link objects together.
2318         Don't link against -liberty.
2319         (gencode.o, getopt.o, getopt1.o): New targets.
2320         * gencode.c: Include <ctype.h> and "ansidecl.h".
2321         (AND): Undefine after including "ansidecl.h".
2322         (ULONG_MAX): Define if not defined.
2323         (OP_*): Don't define macros; now defined in opcode/mips.h.
2324         (main): Call my_strtoul rather than strtoul.
2325         (my_strtoul): New static function.
2326
2327 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2328
2329         * gencode.c (process_instructions):  Generate word64 and uword64
2330         instead of `long long' and `unsigned long long' data types.
2331         * interp.c:  #include sysdep.h to get signals, and define default
2332         for SIGBUS.
2333         * (Convert):  Work around for Visual-C++ compiler bug with type
2334         conversion.
2335         * support.h:  Make things compile under Visual-C++ by using
2336         __int64 instead of `long long'.  Change many refs to long long
2337         into word64/uword64 typedefs.
2338
2339 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2340
2341         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2342         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2343         (docdir): Removed.
2344         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2345         (AC_PROG_INSTALL): Added.
2346         (AC_PROG_CC): Moved to before configure.host call.
2347         * configure: Rebuilt.
2348
2349 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2350
2351         * configure.in: Define @SIMCONF@ depending on mips target.
2352         * configure: Rebuild.
2353         * Makefile.in (run): Add @SIMCONF@ to control simulator
2354         construction.
2355         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2356         * interp.c: Remove some debugging, provide more detailed error
2357         messages, update memory accesses to use LOADDRMASK.
2358
2359 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2360
2361         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2362         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2363         stamp-h.
2364         * configure: Rebuild.
2365         * config.in: New file, generated by autoheader.
2366         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2367         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2368         HAVE_ANINT and HAVE_AINT, as appropriate.
2369         * Makefile.in (run): Use @LIBS@ rather than -lm.
2370         (interp.o): Depend upon config.h.
2371         (Makefile): Just rebuild Makefile.
2372         (clean): Remove stamp-h.
2373         (mostlyclean): Make the same as clean, not as distclean.
2374         (config.h, stamp-h): New targets.
2375
2376 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2377
2378         * interp.c (ColdReset): Fix boolean test. Make all simulator
2379         globals static.
2380
2381 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2382
2383         * interp.c (xfer_direct_word, xfer_direct_long,
2384         swap_direct_word, swap_direct_long, xfer_big_word,
2385         xfer_big_long, xfer_little_word, xfer_little_long,
2386         swap_word,swap_long): Added.
2387         * interp.c (ColdReset): Provide function indirection to
2388         host<->simulated_target transfer routines.
2389         * interp.c (sim_store_register, sim_fetch_register): Updated to
2390         make use of indirected transfer routines.
2391
2392 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2393
2394         * gencode.c (process_instructions): Ensure FP ABS instruction
2395         recognised.
2396         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2397         system call support.
2398
2399 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2400
2401         * interp.c (sim_do_command): Complain if callback structure not
2402         initialised.
2403
2404 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2405
2406         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2407         support for Sun hosts.
2408         * Makefile.in (gencode): Ensure the host compiler and libraries
2409         used for cross-hosted build.
2410
2411 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2412
2413         * interp.c, gencode.c: Some more (TODO) tidying.
2414
2415 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2416
2417         * gencode.c, interp.c: Replaced explicit long long references with
2418         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2419         * support.h (SET64LO, SET64HI): Macros added.
2420
2421 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2422
2423         * configure: Regenerate with autoconf 2.7.
2424
2425 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2426
2427         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2428         * support.h: Remove superfluous "1" from #if.
2429         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2430
2431 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2432
2433         * interp.c (StoreFPR): Control UndefinedResult() call on
2434         WARN_RESULT manifest.
2435
2436 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2437
2438         * gencode.c: Tidied instruction decoding, and added FP instruction
2439         support.
2440
2441         * interp.c: Added dineroIII, and BSD profiling support. Also
2442         run-time FP handling.
2443
2444 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2445
2446         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2447         gencode.c, interp.c, support.h: created.