sim/mips/ChangeLog

   1 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
   2             Ed Satterthwaite  <ehs@broadcom.com>
   3
   4         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
   5         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
   6         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
   7         (fp_nmsub): New prototypes.
   8         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
   9         (NegMultiplySub): New defines.
  10         * mips.igen (RSQRT.fmt): Use RSquareRoot().
  11         (MADD.D, MADD.S): Replace with...
  12         (MADD.fmt): New instruction.
  13         (MSUB.D, MSUB.S): Replace with...
  14         (MSUB.fmt): New instruction.
  15         (NMADD.D, NMADD.S): Replace with...
  16         (NMADD.fmt): New instruction.
  17         (NMSUB.D, MSUB.S): Replace with...
  18         (NMSUB.fmt): New instruction.
  19
  20 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  21             Ed Satterthwaite  <ehs@broadcom.com>
  22
  23         * cp1.c: Fix more comment spelling and formatting.
  24         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
  25         (denorm_mode): New function.
  26         (fpu_unary, fpu_binary): Round results after operation, collect
  27         status from rounding operations, and update the FCSR.
  28         (convert): Collect status from integer conversions and rounding
  29         operations, and update the FCSR.  Adjust NaN values that result
  30         from conversions.  Convert to use sim_io_eprintf rather than
  31         fprintf, and remove some debugging code.
  32         * cp1.h (fenr_FS): New define.
  33
  34 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  35
  36         * cp1.c (convert): Remove unusable debugging code, and move MIPS
  37         rounding mode to sim FP rounding mode flag conversion code into...
  38         (rounding_mode): New function.
  39
  40 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
  41
  42         * cp1.c: Clean up formatting of a few comments.
  43         (value_fpr): Reformat switch statement.
  44
  45 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
  46             Ed Satterthwaite  <ehs@broadcom.com>
  47
  48         * cp1.h: New file.
  49         * sim-main.h: Include cp1.h.
  50         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
  51         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
  52         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
  53         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
  54         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
  55         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
  56         * cp1.c: Don't include sim-fpu.h; already included by
  57         sim-main.h.  Clean up formatting of some comments.
  58         (NaN, Equal, Less): Remove.
  59         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
  60         (fp_cmp): New functions.
  61         * mips.igen (do_c_cond_fmt): Remove.
  62         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
  63         Compare.  Add result tracing.
  64         (CxC1): Remove, replace with...
  65         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
  66         (DMxC1): Remove, replace with...
  67         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
  68         (MxC1): Remove, replace with...
  69         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
  70
  71 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
  72
  73         * sim-main.h (FGRIDX): Remove, replace all uses with...
  74         (FGR_BASE): New macro.
  75         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
  76         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
  77         (NR_FGR, FGR): Likewise.
  78         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
  79         * mips.igen: Likewise.
  80
  81 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
  82
  83         * cp1.c: Add an FSF Copyright notice to this file.
  84
  85 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
  86             Ed Satterthwaite  <ehs@broadcom.com>
  87
  88         * cp1.c (Infinity): Remove.
  89         * sim-main.h (Infinity): Likewise.
  90
  91         * cp1.c (fp_unary, fp_binary): New functions.
  92         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
  93         (fp_sqrt): New functions, implemented in terms of the above.
  94         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
  95         (Recip, SquareRoot): Remove (replaced by functions above).
  96         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
  97         (fp_recip, fp_sqrt): New prototypes.
  98         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
  99         (Recip, SquareRoot): Replace prototypes with #defines which
 100         invoke the functions above.
 101
 102 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 103
 104         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 105         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 106         file, remove PARAMS from prototypes.
 107         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 108         simulator state arguments.
 109         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 110         pass simulator state arguments.
 111         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 112         (store_fpr, convert): Remove 'sd' argument.
 113         (value_fpr): Likewise.  Convert to use 'SD' instead.
 114
 115 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 116
 117         * cp1.c (Min, Max): Remove #if 0'd functions.
 118         * sim-main.h (Min, Max): Remove.
 119
 120 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 121
 122         * cp1.c: fix formatting of switch case and default labels.
 123         * interp.c: Likewise.
 124         * sim-main.c: Likewise.
 125
 126 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 127
 128         * cp1.c: Clean up comments which describe FP formats.
 129          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 130
 131 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 132             Ed Satterthwaite  <ehs@broadcom.com>
 133
 134         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 135         Broadcom SiByte SB-1 processor configurations.
 136         * configure: Regenerate.
 137         * sb1.igen: New file.
 138         * mips.igen: Include sb1.igen.
 139         (sb1): New model.
 140         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 141         * mdmx.igen: Add "sb1" model to all appropriate functions and
 142         instructions.
 143         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 144         (ob_func, ob_acc): Reference the above.
 145         (qh_acc): Adjust to keep the same size as ob_acc.
 146         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 147         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 148
 149 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 150
 151         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 152
 153 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 154             Ed Satterthwaite  <ehs@broadcom.com>
 155
 156         * mips.igen (mdmx): New (pseudo-)model.
 157         * mdmx.c, mdmx.igen: New files.
 158         * Makefile.in (SIM_OBJS): Add mdmx.o.
 159         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 160         New typedefs.
 161         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 162         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 163         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 164         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 165         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 166         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 167         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 168         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 169         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 170         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 171         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 172         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 173         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 174         (qh_fmtsel): New macros.
 175         (_sim_cpu): New member "acc".
 176         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 177         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 178
 179 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 180
 181         * interp.c: Use 'deprecated' rather than 'depreciated.'
 182         * sim-main.h: Likewise.
 183
 184 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 185
 186         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 187         which wouldn't compile anyway.
 188         * sim-main.h (unpredictable_action): New function prototype.
 189         (Unpredictable): Define to call igen function unpredictable().
 190         (NotWordValue): New macro to call igen function not_word_value().
 191         (UndefinedResult): Remove.
 192         * interp.c (undefined_result): Remove.
 193         (unpredictable_action): New function.
 194         * mips.igen (not_word_value, unpredictable): New functions.
 195         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 196         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 197         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 198         NotWordValue() to check for unpredictable inputs, then
 199         Unpredictable() to handle them.
 200
 201 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 202
 203         * mips.igen: Fix formatting of calls to Unpredictable().
 204
 205 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 206
 207         * interp.c (sim_open): Revert previous change.
 208
 209 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 210
 211         * interp.c (sim_open): Disable chunk of code that wrote code in
 212         vector table entries.
 213
 214 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 215
 216         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 217         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 218         unused definitions.
 219
 220 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 221
 222         * cp1.c: Fix many formatting issues.
 223
 224 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 225
 226         * cp1.c (fpu_format_name): New function to replace...
 227         (DOFMT): This.  Delete, and update all callers.
 228         (fpu_rounding_mode_name): New function to replace...
 229         (RMMODE): This.  Delete, and update all callers.
 230
 231 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 232
 233         * interp.c: Move FPU support routines from here to...
 234         * cp1.c: Here.  New file.
 235         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 236         (cp1.o): New target.
 237
 238 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 239
 240         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 241         * mips.igen (mips32, mips64): New models, add to all instructions
 242         and functions as appropriate.
 243         (loadstore_ea, check_u64): New variant for model mips64.
 244         (check_fmt_p): New variant for models mipsV and mips64, remove
 245         mipsV model marking fro other variant.
 246         (SLL) Rename to...
 247         (SLLa) this.
 248         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 249         for mips32 and mips64.
 250         (DCLO, DCLZ): New instructions for mips64.
 251
 252 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 253
 254         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 255         immediate or code as a hex value with the "%#lx" format.
 256         (ANDI): Likewise, and fix printed instruction name.
 257
 258 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 259
 260         * sim-main.h (UndefinedResult, Unpredictable): New macros
 261         which currently do nothing.
 262
 263 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 264
 265         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 266         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 267         (status_CU3): New definitions.
 268
 269         * sim-main.h (ExceptionCause): Add new values for MIPS32
 270         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 271         for DebugBreakPoint and NMIReset to note their status in
 272         MIPS32 and MIPS64.
 273         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 274         (SignalExceptionCacheErr): New exception macros.
 275
 276 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 277
 278         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 279         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 280         is always enabled.
 281         (SignalExceptionCoProcessorUnusable): Take as argument the
 282         unusable coprocessor number.
 283
 284 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 285
 286         * mips.igen: Fix formatting of all SignalException calls.
 287
 288 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 289
 290         * sim-main.h (SIGNEXTEND): Remove.
 291
 292 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 293
 294         * mips.igen: Remove gencode comment from top of file, fix
 295         spelling in another comment.
 296
 297 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 298
 299         * mips.igen (check_fmt, check_fmt_p): New functions to check
 300         whether specific floating point formats are usable.
 301         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 302         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 303         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 304         Use the new functions.
 305         (do_c_cond_fmt): Remove format checks...
 306         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 307
 308 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 309
 310         * mips.igen: Fix formatting of check_fpu calls.
 311
 312 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 313
 314         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 315
 316 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 317
 318         * mips.igen: Remove whitespace at end of lines.
 319
 320 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 321
 322         * mips.igen (loadstore_ea): New function to do effective
 323         address calculations.
 324         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 325         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 326         CACHE): Use loadstore_ea to do effective address computations.
 327
 328 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 329
 330         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 331         * mips.igen (LL, CxC1, MxC1): Likewise.
 332
 333 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 334
 335         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 336         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 337         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 338         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 339         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 340         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 341         Don't split opcode fields by hand, use the opcode field values
 342         provided by igen.
 343
 344 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 345
 346         * mips.igen (do_divu): Fix spacing.
 347
 348         * mips.igen (do_dsllv): Move to be right before DSLLV,
 349         to match the rest of the do_<shift> functions.
 350
 351 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 352
 353         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 354         DSRL32, do_dsrlv): Trace inputs and results.
 355
 356 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 357
 358         * mips.igen (CACHE): Provide instruction-printing string.
 359
 360         * interp.c (signal_exception): Comment tokens after #endif.
 361
 362 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 363
 364         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 365         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 366         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 367         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 368         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 369         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 370         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 371         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 372
 373 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 374
 375         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 376         instruction-printing string.
 377         (LWU): Use '64' as the filter flag.
 378
 379 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 380
 381         * mips.igen (SDXC1): Fix instruction-printing string.
 382
 383 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 384
 385         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 386         filter flags "32,f".
 387
 388 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 389
 390         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 391         as the filter flag.
 392
 393 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 394
 395         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 396         add a comma) so that it more closely match the MIPS ISA
 397         documentation opcode partitioning.
 398         (PREF): Put useful names on opcode fields, and include
 399         instruction-printing string.
 400
 401 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 402
 403         * mips.igen (check_u64): New function which in the future will
 404         check whether 64-bit instructions are usable and signal an
 405         exception if not.  Currently a no-op.
 406         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 407         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 408         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 409         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 410
 411         * mips.igen (check_fpu): New function which in the future will
 412         check whether FPU instructions are usable and signal an exception
 413         if not.  Currently a no-op.
 414         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 415         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 416         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 417         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 418         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 419         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 420         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 421         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 422
 423 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 424
 425         * mips.igen (do_load_left, do_load_right): Move to be immediately
 426         following do_load.
 427         (do_store_left, do_store_right): Move to be immediately following
 428         do_store.
 429
 430 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 431
 432         * mips.igen (mipsV): New model name.  Also, add it to
 433         all instructions and functions where it is appropriate.
 434
 435 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 436
 437         * mips.igen: For all functions and instructions, list model
 438         names that support that instruction one per line.
 439
 440 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 441
 442         * mips.igen: Add some additional comments about supported
 443         models, and about which instructions go where.
 444         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 445         order as is used in the rest of the file.
 446
 447 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 448
 449         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 450         indicating that ALU32_END or ALU64_END are there to check
 451         for overflow.
 452         (DADD): Likewise, but also remove previous comment about
 453         overflow checking.
 454
 455 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 456
 457         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 458         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 459         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 460         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 461         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 462         fields (i.e., add and move commas) so that they more closely
 463         match the MIPS ISA documentation opcode partitioning.
 464
 465 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 466
 467         * mips.igen (ADDI): Print immediate value.
 468         (BREAK): Print code.
 469         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 470         (SLL): Print "nop" specially, and don't run the code
 471         that does the shift for the "nop" case.
 472
 473 2001-11-17  Fred Fish  <fnf@redhat.com>
 474
 475         * sim-main.h (float_operation): Move enum declaration outside
 476         of _sim_cpu struct declaration.
 477
 478 2001-04-12  Jim Blandy  <jimb@redhat.com>
 479
 480         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 481         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 482         set of the FCSR.
 483         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 484         PENDING_FILL, and you can get the intended effect gracefully by
 485         calling PENDING_SCHED directly.
 486
 487 2001-02-23  Ben Elliston  <bje@redhat.com>
 488
 489         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 490         already defined elsewhere.
 491
 492 2001-02-19  Ben Elliston  <bje@redhat.com>
 493
 494         * sim-main.h (sim_monitor): Return an int.
 495         * interp.c (sim_monitor): Add return values.
 496         (signal_exception): Handle error conditions from sim_monitor.
 497
 498 2001-02-08  Ben Elliston  <bje@redhat.com>
 499
 500         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 501         (store_memory): Likewise, pass cia to sim_core_write*.
 502
 503 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 504
 505         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 506         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 507
 508 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 509
 510         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 511         * Makefile.in: Don't delete *.igen when cleaning directory.
 512
 513 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 514
 515         * m16.igen (break): Call SignalException not sim_engine_halt.
 516
 517 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 518
 519         From Jason Eckhardt:
 520         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 521
 522 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 523
 524         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 525
 526 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 527
 528         * mips.igen (do_dmultx): Fix typo.
 529
 530 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 531
 532         * configure: Regenerated to track ../common/aclocal.m4 changes.
 533
 534 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 535
 536         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 537
 538 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 539
 540         * sim-main.h (GPR_CLEAR): Define macro.
 541
 542 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 543
 544         * interp.c (decode_coproc): Output long using %lx and not %s.
 545
 546 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 547
 548         * interp.c (sim_open): Sort & extend dummy memory regions for
 549         --board=jmr3904 for eCos.
 550
 551 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 552
 553         * configure: Regenerated.
 554
 555 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 556
 557         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 558         calls, conditional on the simulator being in verbose mode.
 559
 560 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 561
 562         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 563         cache don't get ReservedInstruction traps.
 564
 565 1999-11-29  Mark Salter  <msalter@cygnus.com>
 566
 567         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 568         to clear status bits in sdisr register. This is how the hardware works.
 569
 570         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 571         being used by cygmon.
 572
 573 1999-11-11  Andrew Haley  <aph@cygnus.com>
 574
 575         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 576         instructions.
 577
 578 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 579
 580         * mips.igen (MULT): Correct previous mis-applied patch.
 581
 582 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 583
 584         * mips.igen (delayslot32): Handle sequence like
 585         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 586         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 587         (MULT): Actually pass the third register...
 588
 589 1999-09-03  Mark Salter  <msalter@cygnus.com>
 590
 591         * interp.c (sim_open): Added more memory aliases for additional
 592         hardware being touched by cygmon on jmr3904 board.
 593
 594 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 595
 596         * configure: Regenerated to track ../common/aclocal.m4 changes.
 597
 598 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 599
 600         * interp.c (sim_store_register): Handle case where client - GDB -
 601         specifies that a 4 byte register is 8 bytes in size.
 602         (sim_fetch_register): Ditto.
 603
 604 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 605
 606         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 607         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 608         (idt_monitor_base): Base address for IDT monitor traps.
 609         (pmon_monitor_base): Ditto for PMON.
 610         (lsipmon_monitor_base): Ditto for LSI PMON.
 611         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 612         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 613         (sim_firmware_command): New function.
 614         (mips_option_handler): Call it for OPTION_FIRMWARE.
 615         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 616         option was given, add no monitor by default.  Add BREAK hooks only if
 617         monitors are also there.
 618
 619 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 620
 621         * interp.c (sim_monitor): Flush output before reading input.
 622
 623 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 624
 625         * tconfig.in (SIM_HANDLES_LMA): Always define.
 626
 627 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 628
 629         From Mark Salter <msalter@cygnus.com>:
 630         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 631         (sim_open): Add setup for BSP board.
 632
 633 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 634
 635         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 636         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 637         them as unimplemented.
 638
 639 1999-05-08  Felix Lee  <flee@cygnus.com>
 640
 641         * configure: Regenerated to track ../common/aclocal.m4 changes.
 642
 643 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 644
 645         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 646
 647 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 648
 649         * configure.in: Any mips64vr5*-*-* target should have
 650         -DTARGET_ENABLE_FR=1.
 651         (default_endian): Any mips64vr*el-*-* target should default to
 652         LITTLE_ENDIAN.
 653         * configure: Re-generate.
 654
 655 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 656
 657         * mips.igen (ldl): Extend from _16_, not 32.
 658
 659 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 660
 661         * interp.c (sim_store_register): Force registers written to by GDB
 662         into an un-interpreted state.
 663
 664 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 665
 666         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 667         CPU, start periodic background I/O polls.
 668         (tx3904sio_poll): New function: periodic I/O poller.
 669
 670 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 671
 672         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 673
 674 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 675
 676         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 677         case statement.
 678
 679 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 680
 681         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 682         (load_word): Call SIM_CORE_SIGNAL hook on error.
 683         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 684         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 685         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 686         * sim-main.h (COP0_BADVADDR): Define.
 687         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 688         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 689         (_sim_cpu): Add exc_* fields to store register value snapshots.
 690         * mips.igen (*): Replace memory-related SignalException* calls
 691         with references to SIM_CORE_SIGNAL hook.
 692
 693         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 694         fix.
 695         * sim-main.c (*): Minor warning cleanups.
 696
 697 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 698
 699         * m16.igen (DADDIU5): Correct type-o.
 700
 701 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 702
 703         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 704         variables.
 705
 706 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 707
 708         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 709         to include path.
 710         (interp.o): Add dependency on itable.h
 711         (oengine.c, gencode): Delete remaining references.
 712         (BUILT_SRC_FROM_GEN): Clean up.
 713
 714 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 715
 716         * vr4run.c: New.
 717         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 718         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 719         tmp-run-hack) : New.
 720         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 721         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 722         Drop the "64" qualifier to get the HACK generator working.
 723         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 724         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 725         qualifier to get the hack generator working.
 726         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 727         (DSLL): Use do_dsll.
 728         (DSLLV): Use do_dsllv.
 729         (DSRA): Use do_dsra.
 730         (DSRL): Use do_dsrl.
 731         (DSRLV): Use do_dsrlv.
 732         (BC1): Move *vr4100 to get the HACK generator working.
 733         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 734         get the HACK generator working.
 735         (MACC) Rename to get the HACK generator working.
 736         (DMACC,MACCS,DMACCS): Add the 64.
 737
 738 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 739
 740         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 741         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 742
 743 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 744
 745     * mips/interp.c (DEBUG): Cleanups.
 746
 747 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 748
 749         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 750         (tx3904sio_tickle): fflush after a stdout character output.
 751
 752 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 753
 754         * interp.c (sim_close): Uninstall modules.
 755
 756 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 757
 758         * sim-main.h, interp.c (sim_monitor): Change to global
 759         function.
 760
 761 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 762
 763         * configure.in (vr4100): Only include vr4100 instructions in
 764         simulator.
 765         * configure: Re-generate.
 766         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 767
 768 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 769
 770         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 771         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 772         true alternative.
 773
 774         * configure.in (sim_default_gen, sim_use_gen): Replace with
 775         sim_gen.
 776         (--enable-sim-igen): Delete config option. Always using IGEN.
 777         * configure: Re-generate.
 778
 779         * Makefile.in (gencode): Kill, kill, kill.
 780         * gencode.c: Ditto.
 781
 782 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 783
 784         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 785         bit mips16 igen simulator.
 786         * configure: Re-generate.
 787
 788         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 789         as part of vr4100 ISA.
 790         * vr.igen: Mark all instructions as 64 bit only.
 791
 792 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 793
 794         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 795         Pacify GCC.
 796
 797 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 798
 799         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 800         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 801         * configure: Re-generate.
 802
 803         * m16.igen (BREAK): Define breakpoint instruction.
 804         (JALX32): Mark instruction as mips16 and not r3900.
 805         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 806
 807         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 808
 809 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 810
 811         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 812         insn as a debug breakpoint.
 813
 814         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 815         pending.slot_size.
 816         (PENDING_SCHED): Clean up trace statement.
 817         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 818         (PENDING_FILL): Delay write by only one cycle.
 819         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 820
 821         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 822         of pending writes.
 823         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 824         32 & 64.
 825         (pending_tick): Move incrementing of index to FOR statement.
 826         (pending_tick): Only update PENDING_OUT after a write has occured.
 827
 828         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 829         build simulator.
 830         * configure: Re-generate.
 831
 832         * interp.c (sim_engine_run OLD): Delete explicit call to
 833         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 834
 835 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 836
 837         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 838         interrupt level number to match changed SignalExceptionInterrupt
 839         macro.
 840
 841 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 842
 843         * interp.c: #include "itable.h" if WITH_IGEN.
 844         (get_insn_name): New function.
 845         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 846         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 847
 848 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 849
 850         * configure: Rebuilt to inhale new common/aclocal.m4.
 851
 852 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 853
 854         * dv-tx3904sio.c: Include sim-assert.h.
 855
 856 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 857
 858         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 859         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 860         Reorganize target-specific sim-hardware checks.
 861         * configure: rebuilt.
 862         * interp.c (sim_open): For tx39 target boards, set
 863         OPERATING_ENVIRONMENT, add tx3904sio devices.
 864         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 865         ROM executables.  Install dv-sockser into sim-modules list.
 866
 867         * dv-tx3904irc.c: Compiler warning clean-up.
 868         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 869         frequent hw-trace messages.
 870
 871 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 872
 873         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 874
 875 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 876
 877         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 878
 879         * vr.igen: New file.
 880         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 881         * mips.igen: Define vr4100 model. Include vr.igen.
 882 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 883
 884         * mips.igen (check_mf_hilo): Correct check.
 885
 886 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 887
 888         * sim-main.h (interrupt_event): Add prototype.
 889
 890         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 891         register_ptr, register_value.
 892         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 893
 894         * sim-main.h (tracefh): Make extern.
 895
 896 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 897
 898         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 899         Reduce unnecessarily high timer event frequency.
 900         * dv-tx3904cpu.c: Ditto for interrupt event.
 901
 902 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 903
 904         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 905         to allay warnings.
 906         (interrupt_event): Made non-static.
 907
 908         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 909         interchange of configuration values for external vs. internal
 910         clock dividers.
 911
 912 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 913
 914         * mips.igen (BREAK): Moved code to here for
 915         simulator-reserved break instructions.
 916         * gencode.c (build_instruction): Ditto.
 917         * interp.c (signal_exception): Code moved from here.  Non-
 918         reserved instructions now use exception vector, rather
 919         than halting sim.
 920         * sim-main.h: Moved magic constants to here.
 921
 922 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 923
 924         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 925         register upon non-zero interrupt event level, clear upon zero
 926         event value.
 927         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 928         by passing zero event value.
 929         (*_io_{read,write}_buffer): Endianness fixes.
 930         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 931         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 932
 933         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 934         serial I/O and timer module at base address 0xFFFF0000.
 935
 936 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 937
 938         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 939         and BigEndianCPU.
 940
 941 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 942
 943         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 944         parts.
 945         * configure: Update.
 946
 947 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 948
 949         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 950         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 951         * configure.in: Include tx3904tmr in hw_device list.
 952         * configure: Rebuilt.
 953         * interp.c (sim_open): Instantiate three timer instances.
 954         Fix address typo of tx3904irc instance.
 955
 956 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 957
 958         * interp.c (signal_exception): SystemCall exception now uses
 959         the exception vector.
 960
 961 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 962
 963         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 964         to allay warnings.
 965
 966 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 967
 968         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 969
 970 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 971
 972         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 973
 974         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 975         sim-main.h. Declare a struct hw_descriptor instead of struct
 976         hw_device_descriptor.
 977
 978 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 979
 980         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 981         right bits and then re-align left hand bytes to correct byte
 982         lanes.  Fix incorrect computation in do_store_left when loading
 983         bytes from second word.
 984
 985 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 986
 987         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 988         * interp.c (sim_open): Only create a device tree when HW is
 989         enabled.
 990
 991         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 992         * interp.c (signal_exception): Ditto.
 993
 994 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 995
 996         * gencode.c: Mark BEGEZALL as LIKELY.
 997
 998 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 999
1000         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1001         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1002
1003 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1004
1005         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1006         modules.  Recognize TX39 target with "mips*tx39" pattern.
1007         * configure: Rebuilt.
1008         * sim-main.h (*): Added many macros defining bits in
1009         TX39 control registers.
1010         (SignalInterrupt): Send actual PC instead of NULL.
1011         (SignalNMIReset): New exception type.
1012         * interp.c (board): New variable for future use to identify
1013         a particular board being simulated.
1014         (mips_option_handler,mips_options): Added "--board" option.
1015         (interrupt_event): Send actual PC.
1016         (sim_open): Make memory layout conditional on board setting.
1017         (signal_exception): Initial implementation of hardware interrupt
1018         handling.  Accept another break instruction variant for simulator
1019         exit.
1020         (decode_coproc): Implement RFE instruction for TX39.
1021         (mips.igen): Decode RFE instruction as such.
1022         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1023         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1024         bbegin to implement memory map.
1025         * dv-tx3904cpu.c: New file.
1026         * dv-tx3904irc.c: New file.
1027
1028 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1029
1030         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1031
1032 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1033
1034         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1035         with calls to check_div_hilo.
1036
1037 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1038
1039         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1040         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1041         Add special r3900 version of do_mult_hilo.
1042         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1043         with calls to check_mult_hilo.
1044         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1045         with calls to check_div_hilo.
1046
1047 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1048
1049         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1050         Document a replacement.
1051
1052 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1053
1054         * interp.c (sim_monitor): Make mon_printf work.
1055
1056 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1057
1058         * sim-main.h (INSN_NAME): New arg `cpu'.
1059
1060 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1061
1062         * configure: Regenerated to track ../common/aclocal.m4 changes.
1063
1064 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1065
1066         * configure: Regenerated to track ../common/aclocal.m4 changes.
1067         * config.in: Ditto.
1068
1069 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1070
1071         * acconfig.h: New file.
1072         * configure.in: Reverted change of Apr 24; use sinclude again.
1073
1074 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1075
1076         * configure: Regenerated to track ../common/aclocal.m4 changes.
1077         * config.in: Ditto.
1078
1079 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1080
1081         * configure.in: Don't call sinclude.
1082
1083 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1084
1085         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1086
1087 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1088
1089         * mips.igen (ERET): Implement.
1090
1091         * interp.c (decode_coproc): Return sign-extended EPC.
1092
1093         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1094
1095         * interp.c (signal_exception): Do not ignore Trap.
1096         (signal_exception): On TRAP, restart at exception address.
1097         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1098         (signal_exception): Update.
1099         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1100         so that TRAP instructions are caught.
1101
1102 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1103
1104         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1105         contains HI/LO access history.
1106         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1107         (HIACCESS, LOACCESS): Delete, replace with
1108         (HIHISTORY, LOHISTORY): New macros.
1109         (CHECKHILO): Delete all, moved to mips.igen
1110
1111         * gencode.c (build_instruction): Do not generate checks for
1112         correct HI/LO register usage.
1113
1114         * interp.c (old_engine_run): Delete checks for correct HI/LO
1115         register usage.
1116
1117         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1118         check_mf_cycles): New functions.
1119         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1120         do_divu, domultx, do_mult, do_multu): Use.
1121
1122         * tx.igen ("madd", "maddu"): Use.
1123
1124 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1125
1126         * mips.igen (DSRAV): Use function do_dsrav.
1127         (SRAV): Use new function do_srav.
1128
1129         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1130         (B): Sign extend 11 bit immediate.
1131         (EXT-B*): Shift 16 bit immediate left by 1.
1132         (ADDIU*): Don't sign extend immediate value.
1133
1134 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1135
1136         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1137
1138         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1139         functions.
1140
1141         * mips.igen (delayslot32, nullify_next_insn): New functions.
1142         (m16.igen): Always include.
1143         (do_*): Add more tracing.
1144
1145         * m16.igen (delayslot16): Add NIA argument, could be called by a
1146         32 bit MIPS16 instruction.
1147
1148         * interp.c (ifetch16): Move function from here.
1149         * sim-main.c (ifetch16): To here.
1150
1151         * sim-main.c (ifetch16, ifetch32): Update to match current
1152         implementations of LH, LW.
1153         (signal_exception): Don't print out incorrect hex value of illegal
1154         instruction.
1155
1156 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1157
1158         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1159         instruction.
1160
1161         * m16.igen: Implement MIPS16 instructions.
1162
1163         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1164         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1165         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1166         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1167         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1168         bodies of corresponding code from 32 bit insn to these.  Also used
1169         by MIPS16 versions of functions.
1170
1171         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1172         (IMEM16): Drop NR argument from macro.
1173
1174 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1175
1176         * Makefile.in (SIM_OBJS): Add sim-main.o.
1177
1178         * sim-main.h (address_translation, load_memory, store_memory,
1179         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1180         as INLINE_SIM_MAIN.
1181         (pr_addr, pr_uword64): Declare.
1182         (sim-main.c): Include when H_REVEALS_MODULE_P.
1183
1184         * interp.c (address_translation, load_memory, store_memory,
1185         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1186         from here.
1187         * sim-main.c: To here. Fix compilation problems.
1188
1189         * configure.in: Enable inlining.
1190         * configure: Re-config.
1191
1192 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1193
1194         * configure: Regenerated to track ../common/aclocal.m4 changes.
1195
1196 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1197
1198         * mips.igen: Include tx.igen.
1199         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1200         * tx.igen: New file, contains MADD and MADDU.
1201
1202         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1203         the hardwired constant `7'.
1204         (store_memory): Ditto.
1205         (LOADDRMASK): Move definition to sim-main.h.
1206
1207         mips.igen (MTC0): Enable for r3900.
1208         (ADDU): Add trace.
1209
1210         mips.igen (do_load_byte): Delete.
1211         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1212         do_store_right): New functions.
1213         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1214
1215         configure.in: Let the tx39 use igen again.
1216         configure: Update.
1217
1218 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1219
1220         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1221         not an address sized quantity.  Return zero for cache sizes.
1222
1223 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1224
1225         * mips.igen (r3900): r3900 does not support 64 bit integer
1226         operations.
1227
1228 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1229
1230         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1231         than igen one.
1232         * configure : Rebuild.
1233
1234 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1235
1236         * configure: Regenerated to track ../common/aclocal.m4 changes.
1237
1238 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1239
1240         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1241
1242 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1243
1244         * configure: Regenerated to track ../common/aclocal.m4 changes.
1245         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1246
1247 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1248
1249         * configure: Regenerated to track ../common/aclocal.m4 changes.
1250
1251 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1252
1253         * interp.c (Max, Min): Comment out functions. Not yet used.
1254
1255 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1256
1257         * configure: Regenerated to track ../common/aclocal.m4 changes.
1258
1259 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1260
1261         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1262         configurable settings for stand-alone simulator.
1263
1264         * configure.in: Added X11 search, just in case.
1265
1266         * configure: Regenerated.
1267
1268 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1269
1270         * interp.c (sim_write, sim_read, load_memory, store_memory):
1271         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1272
1273 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1274
1275         * sim-main.h (GETFCC): Return an unsigned value.
1276
1277 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1278
1279         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1280         (DADD): Result destination is RD not RT.
1281
1282 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1283
1284         * sim-main.h (HIACCESS, LOACCESS): Always define.
1285
1286         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1287
1288         * interp.c (sim_info): Delete.
1289
1290 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1291
1292         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1293         (mips_option_handler): New argument `cpu'.
1294         (sim_open): Update call to sim_add_option_table.
1295
1296 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1297
1298         * mips.igen (CxC1): Add tracing.
1299
1300 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1301
1302         * sim-main.h (Max, Min): Declare.
1303
1304         * interp.c (Max, Min): New functions.
1305
1306         * mips.igen (BC1): Add tracing.
1307
1308 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1309
1310         * interp.c Added memory map for stack in vr4100
1311
1312 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1313
1314         * interp.c (load_memory): Add missing "break"'s.
1315
1316 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1317
1318         * interp.c (sim_store_register, sim_fetch_register): Pass in
1319         length parameter.  Return -1.
1320
1321 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1322
1323         * interp.c: Added hardware init hook, fixed warnings.
1324
1325 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1326
1327         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1328
1329 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1330
1331         * interp.c (ifetch16): New function.
1332
1333         * sim-main.h (IMEM32): Rename IMEM.
1334         (IMEM16_IMMED): Define.
1335         (IMEM16): Define.
1336         (DELAY_SLOT): Update.
1337
1338         * m16run.c (sim_engine_run): New file.
1339
1340         * m16.igen: All instructions except LB.
1341         (LB): Call do_load_byte.
1342         * mips.igen (do_load_byte): New function.
1343         (LB): Call do_load_byte.
1344
1345         * mips.igen: Move spec for insn bit size and high bit from here.
1346         * Makefile.in (tmp-igen, tmp-m16): To here.
1347
1348         * m16.dc: New file, decode mips16 instructions.
1349
1350         * Makefile.in (SIM_NO_ALL): Define.
1351         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1352
1353 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1354
1355         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1356         point unit to 32 bit registers.
1357         * configure: Re-generate.
1358
1359 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1360
1361         * configure.in (sim_use_gen): Make IGEN the default simulator
1362         generator for generic 32 and 64 bit mips targets.
1363         * configure: Re-generate.
1364
1365 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1366
1367         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1368         bitsize.
1369
1370         * interp.c (sim_fetch_register, sim_store_register): Read/write
1371         FGR from correct location.
1372         (sim_open): Set size of FGR's according to
1373         WITH_TARGET_FLOATING_POINT_BITSIZE.
1374
1375         * sim-main.h (FGR): Store floating point registers in a separate
1376         array.
1377
1378 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1379
1380         * configure: Regenerated to track ../common/aclocal.m4 changes.
1381
1382 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1383
1384         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1385
1386         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1387
1388         * interp.c (pending_tick): New function.  Deliver pending writes.
1389
1390         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1391         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1392         it can handle mixed sized quantites and single bits.
1393
1394 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1395
1396         * interp.c (oengine.h): Do not include when building with IGEN.
1397         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1398         (sim_info): Ditto for PROCESSOR_64BIT.
1399         (sim_monitor): Replace ut_reg with unsigned_word.
1400         (*): Ditto for t_reg.
1401         (LOADDRMASK): Define.
1402         (sim_open): Remove defunct check that host FP is IEEE compliant,
1403         using software to emulate floating point.
1404         (value_fpr, ...): Always compile, was conditional on HASFPU.
1405
1406 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1407
1408         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1409         size.
1410
1411         * interp.c (SD, CPU): Define.
1412         (mips_option_handler): Set flags in each CPU.
1413         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1414         (sim_close): Do not clear STATE, deleted anyway.
1415         (sim_write, sim_read): Assume CPU zero's vm should be used for
1416         data transfers.
1417         (sim_create_inferior): Set the PC for all processors.
1418         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1419         argument.
1420         (mips16_entry): Pass correct nr of args to store_word, load_word.
1421         (ColdReset): Cold reset all cpu's.
1422         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1423         (sim_monitor, load_memory, store_memory, signal_exception): Use
1424         `CPU' instead of STATE_CPU.
1425
1426
1427         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1428         SD or CPU_.
1429
1430         * sim-main.h (signal_exception): Add sim_cpu arg.
1431         (SignalException*): Pass both SD and CPU to signal_exception.
1432         * interp.c (signal_exception): Update.
1433
1434         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1435         Ditto
1436         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1437         address_translation): Ditto
1438         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1439
1440 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1441
1442         * configure: Regenerated to track ../common/aclocal.m4 changes.
1443
1444 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1445
1446         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1447
1448         * mips.igen (model): Map processor names onto BFD name.
1449
1450         * sim-main.h (CPU_CIA): Delete.
1451         (SET_CIA, GET_CIA): Define
1452
1453 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1454
1455         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1456         regiser.
1457
1458         * configure.in (default_endian): Configure a big-endian simulator
1459         by default.
1460         * configure: Re-generate.
1461
1462 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1463
1464         * configure: Regenerated to track ../common/aclocal.m4 changes.
1465
1466 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1467
1468         * interp.c (sim_monitor): Handle Densan monitor outbyte
1469         and inbyte functions.
1470
1471 1997-12-29  Felix Lee  <flee@cygnus.com>
1472
1473         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1474
1475 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1476
1477         * Makefile.in (tmp-igen): Arrange for $zero to always be
1478         reset to zero after every instruction.
1479
1480 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1481
1482         * configure: Regenerated to track ../common/aclocal.m4 changes.
1483         * config.in: Ditto.
1484
1485 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1486
1487         * mips.igen (MSUB): Fix to work like MADD.
1488         * gencode.c (MSUB): Similarly.
1489
1490 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1491
1492         * configure: Regenerated to track ../common/aclocal.m4 changes.
1493
1494 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1495
1496         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1497
1498 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1499
1500         * sim-main.h (sim-fpu.h): Include.
1501
1502         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1503         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1504         using host independant sim_fpu module.
1505
1506 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1507
1508         * interp.c (signal_exception): Report internal errors with SIGABRT
1509         not SIGQUIT.
1510
1511         * sim-main.h (C0_CONFIG): New register.
1512         (signal.h): No longer include.
1513
1514         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1515
1516 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1517
1518         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1519
1520 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1521
1522         * mips.igen: Tag vr5000 instructions.
1523         (ANDI): Was missing mipsIV model, fix assembler syntax.
1524         (do_c_cond_fmt): New function.
1525         (C.cond.fmt): Handle mips I-III which do not support CC field
1526         separatly.
1527         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1528         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1529         in IV3.2 spec.
1530         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1531         vr5000 which saves LO in a GPR separatly.
1532
1533         * configure.in (enable-sim-igen): For vr5000, select vr5000
1534         specific instructions.
1535         * configure: Re-generate.
1536
1537 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1538
1539         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1540
1541         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1542         fmt_uninterpreted_64 bit cases to switch.  Convert to
1543         fmt_formatted,
1544
1545         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1546
1547         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1548         as specified in IV3.2 spec.
1549         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1550
1551 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1552
1553         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1554         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1555         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1556         PENDING_FILL versions of instructions.  Simplify.
1557         (X): New function.
1558         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1559         instructions.
1560         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1561         a signed value.
1562         (MTHI, MFHI): Disable code checking HI-LO.
1563
1564         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1565         global.
1566         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1567
1568 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1569
1570         * gencode.c (build_mips16_operands): Replace IPC with cia.
1571
1572         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1573         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1574         IPC to `cia'.
1575         (UndefinedResult): Replace function with macro/function
1576         combination.
1577         (sim_engine_run): Don't save PC in IPC.
1578
1579         * sim-main.h (IPC): Delete.
1580
1581
1582         * interp.c (signal_exception, store_word, load_word,
1583         address_translation, load_memory, store_memory, cache_op,
1584         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1585         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1586         current instruction address - cia - argument.
1587         (sim_read, sim_write): Call address_translation directly.
1588         (sim_engine_run): Rename variable vaddr to cia.
1589         (signal_exception): Pass cia to sim_monitor
1590
1591         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1592         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1593         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1594
1595         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1596         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1597         SIM_ASSERT.
1598
1599         * interp.c (signal_exception): Pass restart address to
1600         sim_engine_restart.
1601
1602         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1603         idecode.o): Add dependency.
1604
1605         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1606         Delete definitions
1607         (DELAY_SLOT): Update NIA not PC with branch address.
1608         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1609
1610         * mips.igen: Use CIA not PC in branch calculations.
1611         (illegal): Call SignalException.
1612         (BEQ, ADDIU): Fix assembler.
1613
1614 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1615
1616         * m16.igen (JALX): Was missing.
1617
1618         * configure.in (enable-sim-igen): New configuration option.
1619         * configure: Re-generate.
1620
1621         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1622
1623         * interp.c (load_memory, store_memory): Delete parameter RAW.
1624         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1625         bypassing {load,store}_memory.
1626
1627         * sim-main.h (ByteSwapMem): Delete definition.
1628
1629         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1630
1631         * interp.c (sim_do_command, sim_commands): Delete mips specific
1632         commands.  Handled by module sim-options.
1633
1634         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1635         (WITH_MODULO_MEMORY): Define.
1636
1637         * interp.c (sim_info): Delete code printing memory size.
1638
1639         * interp.c (mips_size): Nee sim_size, delete function.
1640         (power2): Delete.
1641         (monitor, monitor_base, monitor_size): Delete global variables.
1642         (sim_open, sim_close): Delete code creating monitor and other
1643         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1644         manage memory regions.
1645         (load_memory, store_memory): Use sim-core for memory model.
1646
1647         * interp.c (address_translation): Delete all memory map code
1648         except line forcing 32 bit addresses.
1649
1650 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1651
1652         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1653         trace options.
1654
1655         * interp.c (logfh, logfile): Delete globals.
1656         (sim_open, sim_close): Delete code opening & closing log file.
1657         (mips_option_handler): Delete -l and -n options.
1658         (OPTION mips_options): Ditto.
1659
1660         * interp.c (OPTION mips_options): Rename option trace to dinero.
1661         (mips_option_handler): Update.
1662
1663 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1664
1665         * interp.c (fetch_str): New function.
1666         (sim_monitor): Rewrite using sim_read & sim_write.
1667         (sim_open): Check magic number.
1668         (sim_open): Write monitor vectors into memory using sim_write.
1669         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1670         (sim_read, sim_write): Simplify - transfer data one byte at a
1671         time.
1672         (load_memory, store_memory): Clarify meaning of parameter RAW.
1673
1674         * sim-main.h (isHOST): Defete definition.
1675         (isTARGET): Mark as depreciated.
1676         (address_translation): Delete parameter HOST.
1677
1678         * interp.c (address_translation): Delete parameter HOST.
1679
1680 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1681
1682         * mips.igen:
1683
1684         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1685         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1686
1687 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1688
1689         * mips.igen: Add model filter field to records.
1690
1691 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1692
1693         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1694
1695         interp.c (sim_engine_run): Do not compile function sim_engine_run
1696         when WITH_IGEN == 1.
1697
1698         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1699         target architecture.
1700
1701         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1702         igen. Replace with configuration variables sim_igen_flags /
1703         sim_m16_flags.
1704
1705         * m16.igen: New file.  Copy mips16 insns here.
1706         * mips.igen: From here.
1707
1708 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1709
1710         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1711         to top.
1712         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1713
1714 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1715
1716         * gencode.c (build_instruction): Follow sim_write's lead in using
1717         BigEndianMem instead of !ByteSwapMem.
1718
1719 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1720
1721         * configure.in (sim_gen): Dependent on target, select type of
1722         generator.  Always select old style generator.
1723
1724         configure: Re-generate.
1725
1726         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1727         targets.
1728         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1729         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1730         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1731         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1732         SIM_@sim_gen@_*, set by autoconf.
1733
1734 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1735
1736         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1737
1738         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1739         CURRENT_FLOATING_POINT instead.
1740
1741         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1742         (address_translation): Raise exception InstructionFetch when
1743         translation fails and isINSTRUCTION.
1744
1745         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1746         sim_engine_run): Change type of of vaddr and paddr to
1747         address_word.
1748         (address_translation, prefetch, load_memory, store_memory,
1749         cache_op): Change type of vAddr and pAddr to address_word.
1750
1751         * gencode.c (build_instruction): Change type of vaddr and paddr to
1752         address_word.
1753
1754 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1755
1756         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1757         macro to obtain result of ALU op.
1758
1759 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1760
1761         * interp.c (sim_info): Call profile_print.
1762
1763 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1764
1765         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1766
1767         * sim-main.h (WITH_PROFILE): Do not define, defined in
1768         common/sim-config.h.  Use sim-profile module.
1769         (simPROFILE): Delete defintion.
1770
1771         * interp.c (PROFILE): Delete definition.
1772         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1773         (sim_close): Delete code writing profile histogram.
1774         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1775         Delete.
1776         (sim_engine_run): Delete code profiling the PC.
1777
1778 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1779
1780         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1781
1782         * interp.c (sim_monitor): Make register pointers of type
1783         unsigned_word*.
1784
1785         * sim-main.h: Make registers of type unsigned_word not
1786         signed_word.
1787
1788 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1789
1790         * interp.c (sync_operation): Rename from SyncOperation, make
1791         global, add SD argument.
1792         (prefetch): Rename from Prefetch, make global, add SD argument.
1793         (decode_coproc): Make global.
1794
1795         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1796
1797         * gencode.c (build_instruction): Generate DecodeCoproc not
1798         decode_coproc calls.
1799
1800         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1801         (SizeFGR): Move to sim-main.h
1802         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1803         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1804         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1805         sim-main.h.
1806         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1807         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1808         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1809         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1810         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1811         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1812
1813         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1814         exception.
1815         (sim-alu.h): Include.
1816         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1817         (sim_cia): Typedef to instruction_address.
1818
1819 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1820
1821         * Makefile.in (interp.o): Rename generated file engine.c to
1822         oengine.c.
1823
1824         * interp.c: Update.
1825
1826 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1827
1828         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1829
1830 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1831
1832         * gencode.c (build_instruction): For "FPSQRT", output correct
1833         number of arguments to Recip.
1834
1835 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1836
1837         * Makefile.in (interp.o): Depends on sim-main.h
1838
1839         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1840
1841         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1842         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1843         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1844         STATE, DSSTATE): Define
1845         (GPR, FGRIDX, ..): Define.
1846
1847         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1848         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1849         (GPR, FGRIDX, ...): Delete macros.
1850
1851         * interp.c: Update names to match defines from sim-main.h
1852
1853 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1854
1855         * interp.c (sim_monitor): Add SD argument.
1856         (sim_warning): Delete.  Replace calls with calls to
1857         sim_io_eprintf.
1858         (sim_error): Delete. Replace calls with sim_io_error.
1859         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1860         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1861         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1862         argument.
1863         (mips_size): Rename from sim_size. Add SD argument.
1864
1865         * interp.c (simulator): Delete global variable.
1866         (callback): Delete global variable.
1867         (mips_option_handler, sim_open, sim_write, sim_read,
1868         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1869         sim_size,sim_monitor): Use sim_io_* not callback->*.
1870         (sim_open): ZALLOC simulator struct.
1871         (PROFILE): Do not define.
1872
1873 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1874
1875         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1876         support.h with corresponding code.
1877
1878         * sim-main.h (word64, uword64), support.h: Move definition to
1879         sim-main.h.
1880         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1881
1882         * support.h: Delete
1883         * Makefile.in: Update dependencies
1884         * interp.c: Do not include.
1885
1886 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1887
1888         * interp.c (address_translation, load_memory, store_memory,
1889         cache_op): Rename to from AddressTranslation et.al., make global,
1890         add SD argument
1891
1892         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1893         CacheOp): Define.
1894
1895         * interp.c (SignalException): Rename to signal_exception, make
1896         global.
1897
1898         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1899
1900         * sim-main.h (SignalException, SignalExceptionInterrupt,
1901         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1902         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1903         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1904         Define.
1905
1906         * interp.c, support.h: Use.
1907
1908 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1909
1910         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1911         to value_fpr / store_fpr. Add SD argument.
1912         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1913         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1914
1915         * sim-main.h (ValueFPR, StoreFPR): Define.
1916
1917 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1918
1919         * interp.c (sim_engine_run): Check consistency between configure
1920         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1921         and HASFPU.
1922
1923         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1924         (mips_fpu): Configure WITH_FLOATING_POINT.
1925         (mips_endian): Configure WITH_TARGET_ENDIAN.
1926         * configure: Update.
1927
1928 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1929
1930         * configure: Regenerated to track ../common/aclocal.m4 changes.
1931
1932 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1933
1934         * configure: Regenerated.
1935
1936 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1937
1938         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1939
1940 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1941
1942         * gencode.c (print_igen_insn_models): Assume certain architectures
1943         include all mips* instructions.
1944         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1945         instruction.
1946
1947         * Makefile.in (tmp.igen): Add target. Generate igen input from
1948         gencode file.
1949
1950         * gencode.c (FEATURE_IGEN): Define.
1951         (main): Add --igen option.  Generate output in igen format.
1952         (process_instructions): Format output according to igen option.
1953         (print_igen_insn_format): New function.
1954         (print_igen_insn_models): New function.
1955         (process_instructions): Only issue warnings and ignore
1956         instructions when no FEATURE_IGEN.
1957
1958 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1959
1960         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1961         MIPS targets.
1962
1963 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1964
1965         * configure: Regenerated to track ../common/aclocal.m4 changes.
1966
1967 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1968
1969         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1970         SIM_RESERVED_BITS): Delete, moved to common.
1971         (SIM_EXTRA_CFLAGS): Update.
1972
1973 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1974
1975         * configure.in: Configure non-strict memory alignment.
1976         * configure: Regenerated to track ../common/aclocal.m4 changes.
1977
1978 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1979
1980         * configure: Regenerated to track ../common/aclocal.m4 changes.
1981
1982 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1983
1984         * gencode.c (SDBBP,DERET): Added (3900) insns.
1985         (RFE): Turn on for 3900.
1986         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1987         (dsstate): Made global.
1988         (SUBTARGET_R3900): Added.
1989         (CANCELDELAYSLOT): New.
1990         (SignalException): Ignore SystemCall rather than ignore and
1991         terminate.  Add DebugBreakPoint handling.
1992         (decode_coproc): New insns RFE, DERET; and new registers Debug
1993         and DEPC protected by SUBTARGET_R3900.
1994         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1995         bits explicitly.
1996         * Makefile.in,configure.in: Add mips subtarget option.
1997         * configure: Update.
1998
1999 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2000
2001         * gencode.c: Add r3900 (tx39).
2002
2003
2004 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2005
2006         * gencode.c (build_instruction): Don't need to subtract 4 for
2007         JALR, just 2.
2008
2009 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2010
2011         * interp.c: Correct some HASFPU problems.
2012
2013 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2014
2015         * configure: Regenerated to track ../common/aclocal.m4 changes.
2016
2017 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2018
2019         * interp.c (mips_options): Fix samples option short form, should
2020         be `x'.
2021
2022 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2023
2024         * interp.c (sim_info): Enable info code.  Was just returning.
2025
2026 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2027
2028         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2029         MFC0.
2030
2031 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2032
2033         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2034         constants.
2035         (build_instruction): Ditto for LL.
2036
2037 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2038
2039         * configure: Regenerated to track ../common/aclocal.m4 changes.
2040
2041 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2042
2043         * configure: Regenerated to track ../common/aclocal.m4 changes.
2044         * config.in: Ditto.
2045
2046 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2047
2048         * interp.c (sim_open): Add call to sim_analyze_program, update
2049         call to sim_config.
2050
2051 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2052
2053         * interp.c (sim_kill): Delete.
2054         (sim_create_inferior): Add ABFD argument. Set PC from same.
2055         (sim_load): Move code initializing trap handlers from here.
2056         (sim_open): To here.
2057         (sim_load): Delete, use sim-hload.c.
2058
2059         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2060
2061 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2062
2063         * configure: Regenerated to track ../common/aclocal.m4 changes.
2064         * config.in: Ditto.
2065
2066 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2067
2068         * interp.c (sim_open): Add ABFD argument.
2069         (sim_load): Move call to sim_config from here.
2070         (sim_open): To here.  Check return status.
2071
2072 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2073
2074         * gencode.c (build_instruction): Two arg MADD should
2075         not assign result to $0.
2076
2077 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2078
2079         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2080         * sim/mips/configure.in: Regenerate.
2081
2082 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2083
2084         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2085         signed8, unsigned8 et.al. types.
2086
2087         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2088         hosts when selecting subreg.
2089
2090 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2091
2092         * interp.c (sim_engine_run): Reset the ZERO register to zero
2093         regardless of FEATURE_WARN_ZERO.
2094         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2095
2096 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2097
2098         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2099         (SignalException): For BreakPoints ignore any mode bits and just
2100         save the PC.
2101         (SignalException): Always set the CAUSE register.
2102
2103 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2104
2105         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2106         exception has been taken.
2107
2108         * interp.c: Implement the ERET and mt/f sr instructions.
2109
2110 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2111
2112         * interp.c (SignalException): Don't bother restarting an
2113         interrupt.
2114
2115 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2116
2117         * interp.c (SignalException): Really take an interrupt.
2118         (interrupt_event): Only deliver interrupts when enabled.
2119
2120 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2121
2122         * interp.c (sim_info): Only print info when verbose.
2123         (sim_info) Use sim_io_printf for output.
2124
2125 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2126
2127         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2128         mips architectures.
2129
2130 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2131
2132         * interp.c (sim_do_command): Check for common commands if a
2133         simulator specific command fails.
2134
2135 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2136
2137         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2138         and simBE when DEBUG is defined.
2139
2140 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2141
2142         * interp.c (interrupt_event): New function.  Pass exception event
2143         onto exception handler.
2144
2145         * configure.in: Check for stdlib.h.
2146         * configure: Regenerate.
2147
2148         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2149         variable declaration.
2150         (build_instruction): Initialize memval1.
2151         (build_instruction): Add UNUSED attribute to byte, bigend,
2152         reverse.
2153         (build_operands): Ditto.
2154
2155         * interp.c: Fix GCC warnings.
2156         (sim_get_quit_code): Delete.
2157
2158         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2159         * Makefile.in: Ditto.
2160         * configure: Re-generate.
2161
2162         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2163
2164 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2165
2166         * interp.c (mips_option_handler): New function parse argumes using
2167         sim-options.
2168         (myname): Replace with STATE_MY_NAME.
2169         (sim_open): Delete check for host endianness - performed by
2170         sim_config.
2171         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2172         (sim_open): Move much of the initialization from here.
2173         (sim_load): To here.  After the image has been loaded and
2174         endianness set.
2175         (sim_open): Move ColdReset from here.
2176         (sim_create_inferior): To here.
2177         (sim_open): Make FP check less dependant on host endianness.
2178
2179         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2180         run.
2181         * interp.c (sim_set_callbacks): Delete.
2182
2183         * interp.c (membank, membank_base, membank_size): Replace with
2184         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2185         (sim_open): Remove call to callback->init. gdb/run do this.
2186
2187         * interp.c: Update
2188
2189         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2190
2191         * interp.c (big_endian_p): Delete, replaced by
2192         current_target_byte_order.
2193
2194 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2195
2196         * interp.c (host_read_long, host_read_word, host_swap_word,
2197         host_swap_long): Delete. Using common sim-endian.
2198         (sim_fetch_register, sim_store_register): Use H2T.
2199         (pipeline_ticks): Delete.  Handled by sim-events.
2200         (sim_info): Update.
2201         (sim_engine_run): Update.
2202
2203 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2204
2205         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2206         reason from here.
2207         (SignalException): To here. Signal using sim_engine_halt.
2208         (sim_stop_reason): Delete, moved to common.
2209
2210 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2211
2212         * interp.c (sim_open): Add callback argument.
2213         (sim_set_callbacks): Delete SIM_DESC argument.
2214         (sim_size): Ditto.
2215
2216 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2217
2218         * Makefile.in (SIM_OBJS): Add common modules.
2219
2220         * interp.c (sim_set_callbacks): Also set SD callback.
2221         (set_endianness, xfer_*, swap_*): Delete.
2222         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2223         Change to functions using sim-endian macros.
2224         (control_c, sim_stop): Delete, use common version.
2225         (simulate): Convert into.
2226         (sim_engine_run): This function.
2227         (sim_resume): Delete.
2228
2229         * interp.c (simulation): New variable - the simulator object.
2230         (sim_kind): Delete global - merged into simulation.
2231         (sim_load): Cleanup.  Move PC assignment from here.
2232         (sim_create_inferior): To here.
2233
2234         * sim-main.h: New file.
2235         * interp.c (sim-main.h): Include.
2236
2237 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2238
2239         * configure: Regenerated to track ../common/aclocal.m4 changes.
2240
2241 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2242
2243         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2244
2245 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2246
2247         * gencode.c (build_instruction): DIV instructions: check
2248         for division by zero and integer overflow before using
2249         host's division operation.
2250
2251 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2252
2253         * Makefile.in (SIM_OBJS): Add sim-load.o.
2254         * interp.c: #include bfd.h.
2255         (target_byte_order): Delete.
2256         (sim_kind, myname, big_endian_p): New static locals.
2257         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2258         after argument parsing.  Recognize -E arg, set endianness accordingly.
2259         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2260         load file into simulator.  Set PC from bfd.
2261         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2262         (set_endianness): Use big_endian_p instead of target_byte_order.
2263
2264 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2265
2266         * interp.c (sim_size): Delete prototype - conflicts with
2267         definition in remote-sim.h.  Correct definition.
2268
2269 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2270
2271         * configure: Regenerated to track ../common/aclocal.m4 changes.
2272         * config.in: Ditto.
2273
2274 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2275
2276         * interp.c (sim_open): New arg `kind'.
2277
2278         * configure: Regenerated to track ../common/aclocal.m4 changes.
2279
2280 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2281
2282         * configure: Regenerated to track ../common/aclocal.m4 changes.
2283
2284 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2285
2286         * interp.c (sim_open): Set optind to 0 before calling getopt.
2287
2288 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2289
2290         * configure: Regenerated to track ../common/aclocal.m4 changes.
2291
2292 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2293
2294         * interp.c : Replace uses of pr_addr with pr_uword64
2295         where the bit length is always 64 independent of SIM_ADDR.
2296         (pr_uword64) : added.
2297
2298 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2299
2300         * configure: Re-generate.
2301
2302 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2303
2304         * configure: Regenerate to track ../common/aclocal.m4 changes.
2305
2306 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2307
2308         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2309         in argv form.
2310         (other sim_*): New SIM_DESC argument.
2311
2312 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2313
2314         * interp.c: Fix printing of addresses for non-64-bit targets.
2315         (pr_addr): Add function to print address based on size.
2316
2317 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2318
2319         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2320
2321 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2322
2323         * gencode.c (build_mips16_operands): Correct computation of base
2324         address for extended PC relative instruction.
2325
2326 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2327
2328         * interp.c (mips16_entry): Add support for floating point cases.
2329         (SignalException): Pass floating point cases to mips16_entry.
2330         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2331         registers.
2332         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2333         or fmt_word.
2334         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2335         and then set the state to fmt_uninterpreted.
2336         (COP_SW): Temporarily set the state to fmt_word while calling
2337         ValueFPR.
2338
2339 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2340
2341         * gencode.c (build_instruction): The high order may be set in the
2342         comparison flags at any ISA level, not just ISA 4.
2343
2344 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2345
2346         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2347         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2348         * configure.in: sinclude ../common/aclocal.m4.
2349         * configure: Regenerated.
2350
2351 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2352
2353         * configure: Rebuild after change to aclocal.m4.
2354
2355 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2356
2357         * configure configure.in Makefile.in:  Update to new configure
2358         scheme which is more compatible with WinGDB builds.
2359         * configure.in:  Improve comment on how to run autoconf.
2360         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2361         * Makefile.in:  Use autoconf substitution to install common
2362         makefile fragment.
2363
2364 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2365
2366         * gencode.c (build_instruction): Use BigEndianCPU instead of
2367         ByteSwapMem.
2368
2369 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2370
2371         * interp.c (sim_monitor): Make output to stdout visible in
2372         wingdb's I/O log window.
2373
2374 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2375
2376         * support.h: Undo previous change to SIGTRAP
2377         and SIGQUIT values.
2378
2379 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2380
2381         * interp.c (store_word, load_word): New static functions.
2382         (mips16_entry): New static function.
2383         (SignalException): Look for mips16 entry and exit instructions.
2384         (simulate): Use the correct index when setting fpr_state after
2385         doing a pending move.
2386
2387 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2388
2389         * interp.c: Fix byte-swapping code throughout to work on
2390         both little- and big-endian hosts.
2391
2392 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2393
2394         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2395         with gdb/config/i386/xm-windows.h.
2396
2397 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2398
2399         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2400         that messes up arithmetic shifts.
2401
2402 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2403
2404         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2405         SIGTRAP and SIGQUIT for _WIN32.
2406
2407 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2408
2409         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2410         force a 64 bit multiplication.
2411         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2412         destination register is 0, since that is the default mips16 nop
2413         instruction.
2414
2415 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2416
2417         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2418         (build_endian_shift): Don't check proc64.
2419         (build_instruction): Always set memval to uword64.  Cast op2 to
2420         uword64 when shifting it left in memory instructions.  Always use
2421         the same code for stores--don't special case proc64.
2422
2423         * gencode.c (build_mips16_operands): Fix base PC value for PC
2424         relative operands.
2425         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2426         jal instruction.
2427         * interp.c (simJALDELAYSLOT): Define.
2428         (JALDELAYSLOT): Define.
2429         (INDELAYSLOT, INJALDELAYSLOT): Define.
2430         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2431
2432 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2433
2434         * interp.c (sim_open): add flush_cache as a PMON routine
2435         (sim_monitor): handle flush_cache by ignoring it
2436
2437 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2438
2439         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2440         BigEndianMem.
2441         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2442         (BigEndianMem): Rename to ByteSwapMem and change sense.
2443         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2444         BigEndianMem references to !ByteSwapMem.
2445         (set_endianness): New function, with prototype.
2446         (sim_open): Call set_endianness.
2447         (sim_info): Use simBE instead of BigEndianMem.
2448         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2449         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2450         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2451         ifdefs, keeping the prototype declaration.
2452         (swap_word): Rewrite correctly.
2453         (ColdReset): Delete references to CONFIG.  Delete endianness related
2454         code; moved to set_endianness.
2455
2456 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2457
2458         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2459         * interp.c (CHECKHILO): Define away.
2460         (simSIGINT): New macro.
2461         (membank_size): Increase from 1MB to 2MB.
2462         (control_c): New function.
2463         (sim_resume): Rename parameter signal to signal_number.  Add local
2464         variable prev.  Call signal before and after simulate.
2465         (sim_stop_reason): Add simSIGINT support.
2466         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2467         functions always.
2468         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2469         if logfh is NULL.
2470         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2471         a call to sim_warning.
2472
2473 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2474
2475         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2476         16 bit instructions.
2477
2478 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2479
2480         Add support for mips16 (16 bit MIPS implementation):
2481         * gencode.c (inst_type): Add mips16 instruction encoding types.
2482         (GETDATASIZEINSN): Define.
2483         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2484         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2485         mtlo.
2486         (MIPS16_DECODE): New table, for mips16 instructions.
2487         (bitmap_val): New static function.
2488         (struct mips16_op): Define.
2489         (mips16_op_table): New table, for mips16 operands.
2490         (build_mips16_operands): New static function.
2491         (process_instructions): If PC is odd, decode a mips16
2492         instruction.  Break out instruction handling into new
2493         build_instruction function.
2494         (build_instruction): New static function, broken out of
2495         process_instructions.  Check modifiers rather than flags for SHIFT
2496         bit count and m[ft]{hi,lo} direction.
2497         (usage): Pass program name to fprintf.
2498         (main): Remove unused variable this_option_optind.  Change
2499         ``*loptarg++'' to ``loptarg++''.
2500         (my_strtoul): Parenthesize && within ||.
2501         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2502         (simulate): If PC is odd, fetch a 16 bit instruction, and
2503         increment PC by 2 rather than 4.
2504         * configure.in: Add case for mips16*-*-*.
2505         * configure: Rebuild.
2506
2507 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2508
2509         * interp.c: Allow -t to enable tracing in standalone simulator.
2510         Fix garbage output in trace file and error messages.
2511
2512 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2513
2514         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2515         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2516         * configure.in: Simplify using macros in ../common/aclocal.m4.
2517         * configure: Regenerated.
2518         * tconfig.in: New file.
2519
2520 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2521
2522         * interp.c: Fix bugs in 64-bit port.
2523         Use ansi function declarations for msvc compiler.
2524         Initialize and test file pointer in trace code.
2525         Prevent duplicate definition of LAST_EMED_REGNUM.
2526
2527 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2528
2529         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2530
2531 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2532
2533         * interp.c (SignalException): Check for explicit terminating
2534         breakpoint value.
2535         * gencode.c: Pass instruction value through SignalException()
2536         calls for Trap, Breakpoint and Syscall.
2537
2538 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2539
2540         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2541         only used on those hosts that provide it.
2542         * configure.in: Add sqrt() to list of functions to be checked for.
2543         * config.in: Re-generated.
2544         * configure: Re-generated.
2545
2546 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2547
2548         * gencode.c (process_instructions): Call build_endian_shift when
2549         expanding STORE RIGHT, to fix swr.
2550         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2551         clear the high bits.
2552         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2553         Fix float to int conversions to produce signed values.
2554
2555 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2556
2557         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2558         (process_instructions): Correct handling of nor instruction.
2559         Correct shift count for 32 bit shift instructions. Correct sign
2560         extension for arithmetic shifts to not shift the number of bits in
2561         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2562         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2563         Fix madd.
2564         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2565         It's OK to have a mult follow a mult.  What's not OK is to have a
2566         mult follow an mfhi.
2567         (Convert): Comment out incorrect rounding code.
2568
2569 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2570
2571         * interp.c (sim_monitor): Improved monitor printf
2572         simulation. Tidied up simulator warnings, and added "--log" option
2573         for directing warning message output.
2574         * gencode.c: Use sim_warning() rather than WARNING macro.
2575
2576 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2577
2578         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2579         getopt1.o, rather than on gencode.c.  Link objects together.
2580         Don't link against -liberty.
2581         (gencode.o, getopt.o, getopt1.o): New targets.
2582         * gencode.c: Include <ctype.h> and "ansidecl.h".
2583         (AND): Undefine after including "ansidecl.h".
2584         (ULONG_MAX): Define if not defined.
2585         (OP_*): Don't define macros; now defined in opcode/mips.h.
2586         (main): Call my_strtoul rather than strtoul.
2587         (my_strtoul): New static function.
2588
2589 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2590
2591         * gencode.c (process_instructions):  Generate word64 and uword64
2592         instead of `long long' and `unsigned long long' data types.
2593         * interp.c:  #include sysdep.h to get signals, and define default
2594         for SIGBUS.
2595         * (Convert):  Work around for Visual-C++ compiler bug with type
2596         conversion.
2597         * support.h:  Make things compile under Visual-C++ by using
2598         __int64 instead of `long long'.  Change many refs to long long
2599         into word64/uword64 typedefs.
2600
2601 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2602
2603         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2604         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2605         (docdir): Removed.
2606         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2607         (AC_PROG_INSTALL): Added.
2608         (AC_PROG_CC): Moved to before configure.host call.
2609         * configure: Rebuilt.
2610
2611 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2612
2613         * configure.in: Define @SIMCONF@ depending on mips target.
2614         * configure: Rebuild.
2615         * Makefile.in (run): Add @SIMCONF@ to control simulator
2616         construction.
2617         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2618         * interp.c: Remove some debugging, provide more detailed error
2619         messages, update memory accesses to use LOADDRMASK.
2620
2621 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2622
2623         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2624         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2625         stamp-h.
2626         * configure: Rebuild.
2627         * config.in: New file, generated by autoheader.
2628         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2629         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2630         HAVE_ANINT and HAVE_AINT, as appropriate.
2631         * Makefile.in (run): Use @LIBS@ rather than -lm.
2632         (interp.o): Depend upon config.h.
2633         (Makefile): Just rebuild Makefile.
2634         (clean): Remove stamp-h.
2635         (mostlyclean): Make the same as clean, not as distclean.
2636         (config.h, stamp-h): New targets.
2637
2638 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2639
2640         * interp.c (ColdReset): Fix boolean test. Make all simulator
2641         globals static.
2642
2643 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2644
2645         * interp.c (xfer_direct_word, xfer_direct_long,
2646         swap_direct_word, swap_direct_long, xfer_big_word,
2647         xfer_big_long, xfer_little_word, xfer_little_long,
2648         swap_word,swap_long): Added.
2649         * interp.c (ColdReset): Provide function indirection to
2650         host<->simulated_target transfer routines.
2651         * interp.c (sim_store_register, sim_fetch_register): Updated to
2652         make use of indirected transfer routines.
2653
2654 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2655
2656         * gencode.c (process_instructions): Ensure FP ABS instruction
2657         recognised.
2658         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2659         system call support.
2660
2661 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2662
2663         * interp.c (sim_do_command): Complain if callback structure not
2664         initialised.
2665
2666 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2667
2668         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2669         support for Sun hosts.
2670         * Makefile.in (gencode): Ensure the host compiler and libraries
2671         used for cross-hosted build.
2672
2673 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2674
2675         * interp.c, gencode.c: Some more (TODO) tidying.
2676
2677 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2678
2679         * gencode.c, interp.c: Replaced explicit long long references with
2680         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2681         * support.h (SET64LO, SET64HI): Macros added.
2682
2683 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2684
2685         * configure: Regenerate with autoconf 2.7.
2686
2687 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2688
2689         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2690         * support.h: Remove superfluous "1" from #if.
2691         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2692
2693 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2694
2695         * interp.c (StoreFPR): Control UndefinedResult() call on
2696         WARN_RESULT manifest.
2697
2698 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2699
2700         * gencode.c: Tidied instruction decoding, and added FP instruction
2701         support.
2702
2703         * interp.c: Added dineroIII, and BSD profiling support. Also
2704         run-time FP handling.
2705
2706 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2707
2708         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2709         gencode.c, interp.c, support.h: created.