1 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
3 * configure: Regenerated.
5 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
7 * configure: Regenerated.
9 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
11 * configure: Regenerated.
13 2006-05-15 Chao-ying Fu <fu@mips.com>
15 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
17 2006-04-18 Nick Clifton <nickc@redhat.com>
19 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
22 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
24 * configure: Regenerate.
26 2005-12-14 Chao-ying Fu <fu@mips.com>
28 * Makefile.in (SIM_OBJS): Add dsp.o.
29 (dsp.o): New dependency.
30 (IGEN_INCLUDE): Add dsp.igen.
31 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
32 mipsisa64*-*-*): Add dsp to sim_igen_machine.
33 * configure: Regenerate.
34 * mips.igen: Add dsp model and include dsp.igen.
35 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
36 because these instructions are extended in DSP ASE.
37 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
38 adding 6 DSP accumulator registers and 1 DSP control register.
39 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
40 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
41 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
42 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
43 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
44 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
45 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
46 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
47 DSPCR_CCOND_SMASK): New define.
48 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
49 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
51 2005-07-08 Ian Lance Taylor <ian@airs.com>
53 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
55 2005-06-16 David Ung <davidu@mips.com>
56 Nigel Stephens <nigel@mips.com>
58 * mips.igen: New mips16e model and include m16e.igen.
59 (check_u64): Add mips16e tag.
60 * m16e.igen: New file for MIPS16e instructions.
61 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
62 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
64 * configure: Regenerate.
66 2005-05-26 David Ung <davidu@mips.com>
68 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
69 tags to all instructions which are applicable to the new ISAs.
70 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
72 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
74 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
76 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
77 * configure: Regenerate.
79 2005-03-23 Mark Kettenis <kettenis@gnu.org>
81 * configure: Regenerate.
83 2005-01-14 Andrew Cagney <cagney@gnu.org>
85 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
86 explicit call to AC_CONFIG_HEADER.
87 * configure: Regenerate.
89 2005-01-12 Andrew Cagney <cagney@gnu.org>
91 * configure.ac: Update to use ../common/common.m4.
92 * configure: Re-generate.
94 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
96 * configure: Regenerated to track ../common/aclocal.m4 changes.
98 2005-01-07 Andrew Cagney <cagney@gnu.org>
100 * configure.ac: Rename configure.in, require autoconf 2.59.
101 * configure: Re-generate.
103 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
105 * configure: Regenerate for ../common/aclocal.m4 update.
107 2004-09-24 Monika Chaddha <monika@acmet.com>
109 Committed by Andrew Cagney.
110 * m16.igen (CMP, CMPI): Fix assembler.
112 2004-08-18 Chris Demetriou <cgd@broadcom.com>
114 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
115 * configure: Regenerate.
117 2004-06-25 Chris Demetriou <cgd@broadcom.com>
119 * configure.in (sim_m16_machine): Include mipsIII.
120 * configure: Regenerate.
122 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
124 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
126 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
128 2004-04-10 Chris Demetriou <cgd@broadcom.com>
130 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
132 2004-04-09 Chris Demetriou <cgd@broadcom.com>
134 * mips.igen (check_fmt): Remove.
135 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
136 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
137 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
138 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
139 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
140 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
141 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
142 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
143 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
144 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
146 2004-04-09 Chris Demetriou <cgd@broadcom.com>
148 * sb1.igen (check_sbx): New function.
149 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
151 2004-03-29 Chris Demetriou <cgd@broadcom.com>
152 Richard Sandiford <rsandifo@redhat.com>
154 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
155 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
156 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
157 separate implementations for mipsIV and mipsV. Use new macros to
158 determine whether the restrictions apply.
160 2004-01-19 Chris Demetriou <cgd@broadcom.com>
162 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
163 (check_mult_hilo): Improve comments.
164 (check_div_hilo): Likewise. Also, fork off a new version
165 to handle mips32/mips64 (since there are no hazards to check
168 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
170 * mips.igen (do_dmultx): Fix check for negative operands.
172 2003-05-16 Ian Lance Taylor <ian@airs.com>
174 * Makefile.in (SHELL): Make sure this is defined.
175 (various): Use $(SHELL) whenever we invoke move-if-change.
177 2003-05-03 Chris Demetriou <cgd@broadcom.com>
179 * cp1.c: Tweak attribution slightly.
182 * mdmx.igen: Likewise.
183 * mips3d.igen: Likewise.
184 * sb1.igen: Likewise.
186 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
188 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
191 2003-02-27 Andrew Cagney <cagney@redhat.com>
193 * interp.c (sim_open): Rename _bfd to bfd.
194 (sim_create_inferior): Ditto.
196 2003-01-14 Chris Demetriou <cgd@broadcom.com>
198 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
200 2003-01-14 Chris Demetriou <cgd@broadcom.com>
202 * mips.igen (EI, DI): Remove.
204 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
206 * Makefile.in (tmp-run-multi): Fix mips16 filter.
208 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
209 Andrew Cagney <ac131313@redhat.com>
210 Gavin Romig-Koch <gavin@redhat.com>
211 Graydon Hoare <graydon@redhat.com>
212 Aldy Hernandez <aldyh@redhat.com>
213 Dave Brolley <brolley@redhat.com>
214 Chris Demetriou <cgd@broadcom.com>
216 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
217 (sim_mach_default): New variable.
218 (mips64vr-*-*, mips64vrel-*-*): New configurations.
219 Add a new simulator generator, MULTI.
220 * configure: Regenerate.
221 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
222 (multi-run.o): New dependency.
223 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
224 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
225 (tmp-multi): Combine them.
226 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
227 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
228 (distclean-extra): New rule.
229 * sim-main.h: Include bfd.h.
230 (MIPS_MACH): New macro.
231 * mips.igen (vr4120, vr5400, vr5500): New models.
232 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
233 * vr.igen: Replace with new version.
235 2003-01-04 Chris Demetriou <cgd@broadcom.com>
237 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
238 * configure: Regenerate.
240 2002-12-31 Chris Demetriou <cgd@broadcom.com>
242 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
243 * mips.igen: Remove all invocations of check_branch_bug and
246 2002-12-16 Chris Demetriou <cgd@broadcom.com>
248 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
250 2002-07-30 Chris Demetriou <cgd@broadcom.com>
252 * mips.igen (do_load_double, do_store_double): New functions.
253 (LDC1, SDC1): Rename to...
254 (LDC1b, SDC1b): respectively.
255 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
257 2002-07-29 Michael Snyder <msnyder@redhat.com>
259 * cp1.c (fp_recip2): Modify initialization expression so that
260 GCC will recognize it as constant.
262 2002-06-18 Chris Demetriou <cgd@broadcom.com>
264 * mdmx.c (SD_): Delete.
265 (Unpredictable): Re-define, for now, to directly invoke
266 unpredictable_action().
267 (mdmx_acc_op): Fix error in .ob immediate handling.
269 2002-06-18 Andrew Cagney <cagney@redhat.com>
271 * interp.c (sim_firmware_command): Initialize `address'.
273 2002-06-16 Andrew Cagney <ac131313@redhat.com>
275 * configure: Regenerated to track ../common/aclocal.m4 changes.
277 2002-06-14 Chris Demetriou <cgd@broadcom.com>
278 Ed Satterthwaite <ehs@broadcom.com>
280 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
281 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
282 * mips.igen: Include mips3d.igen.
283 (mips3d): New model name for MIPS-3D ASE instructions.
284 (CVT.W.fmt): Don't use this instruction for word (source) format
286 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
287 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
288 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
289 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
290 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
291 (RSquareRoot1, RSquareRoot2): New macros.
292 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
293 (fp_rsqrt2): New functions.
294 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
295 * configure: Regenerate.
297 2002-06-13 Chris Demetriou <cgd@broadcom.com>
298 Ed Satterthwaite <ehs@broadcom.com>
300 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
301 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
302 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
303 (convert): Note that this function is not used for paired-single
305 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
306 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
307 (check_fmt_p): Enable paired-single support.
308 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
309 (PUU.PS): New instructions.
310 (CVT.S.fmt): Don't use this instruction for paired-single format
312 * sim-main.h (FP_formats): New value 'fmt_ps.'
313 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
314 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
316 2002-06-12 Chris Demetriou <cgd@broadcom.com>
318 * mips.igen: Fix formatting of function calls in
321 2002-06-12 Chris Demetriou <cgd@broadcom.com>
323 * mips.igen (MOVN, MOVZ): Trace result.
324 (TNEI): Print "tnei" as the opcode name in traces.
325 (CEIL.W): Add disassembly string for traces.
326 (RSQRT.fmt): Make location of disassembly string consistent
327 with other instructions.
329 2002-06-12 Chris Demetriou <cgd@broadcom.com>
331 * mips.igen (X): Delete unused function.
333 2002-06-08 Andrew Cagney <cagney@redhat.com>
335 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
337 2002-06-07 Chris Demetriou <cgd@broadcom.com>
338 Ed Satterthwaite <ehs@broadcom.com>
340 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
341 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
342 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
343 (fp_nmsub): New prototypes.
344 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
345 (NegMultiplySub): New defines.
346 * mips.igen (RSQRT.fmt): Use RSquareRoot().
347 (MADD.D, MADD.S): Replace with...
348 (MADD.fmt): New instruction.
349 (MSUB.D, MSUB.S): Replace with...
350 (MSUB.fmt): New instruction.
351 (NMADD.D, NMADD.S): Replace with...
352 (NMADD.fmt): New instruction.
353 (NMSUB.D, MSUB.S): Replace with...
354 (NMSUB.fmt): New instruction.
356 2002-06-07 Chris Demetriou <cgd@broadcom.com>
357 Ed Satterthwaite <ehs@broadcom.com>
359 * cp1.c: Fix more comment spelling and formatting.
360 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
361 (denorm_mode): New function.
362 (fpu_unary, fpu_binary): Round results after operation, collect
363 status from rounding operations, and update the FCSR.
364 (convert): Collect status from integer conversions and rounding
365 operations, and update the FCSR. Adjust NaN values that result
366 from conversions. Convert to use sim_io_eprintf rather than
367 fprintf, and remove some debugging code.
368 * cp1.h (fenr_FS): New define.
370 2002-06-07 Chris Demetriou <cgd@broadcom.com>
372 * cp1.c (convert): Remove unusable debugging code, and move MIPS
373 rounding mode to sim FP rounding mode flag conversion code into...
374 (rounding_mode): New function.
376 2002-06-07 Chris Demetriou <cgd@broadcom.com>
378 * cp1.c: Clean up formatting of a few comments.
379 (value_fpr): Reformat switch statement.
381 2002-06-06 Chris Demetriou <cgd@broadcom.com>
382 Ed Satterthwaite <ehs@broadcom.com>
385 * sim-main.h: Include cp1.h.
386 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
387 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
388 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
389 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
390 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
391 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
392 * cp1.c: Don't include sim-fpu.h; already included by
393 sim-main.h. Clean up formatting of some comments.
394 (NaN, Equal, Less): Remove.
395 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
396 (fp_cmp): New functions.
397 * mips.igen (do_c_cond_fmt): Remove.
398 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
399 Compare. Add result tracing.
400 (CxC1): Remove, replace with...
401 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
402 (DMxC1): Remove, replace with...
403 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
404 (MxC1): Remove, replace with...
405 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
407 2002-06-04 Chris Demetriou <cgd@broadcom.com>
409 * sim-main.h (FGRIDX): Remove, replace all uses with...
410 (FGR_BASE): New macro.
411 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
412 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
413 (NR_FGR, FGR): Likewise.
414 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
415 * mips.igen: Likewise.
417 2002-06-04 Chris Demetriou <cgd@broadcom.com>
419 * cp1.c: Add an FSF Copyright notice to this file.
421 2002-06-04 Chris Demetriou <cgd@broadcom.com>
422 Ed Satterthwaite <ehs@broadcom.com>
424 * cp1.c (Infinity): Remove.
425 * sim-main.h (Infinity): Likewise.
427 * cp1.c (fp_unary, fp_binary): New functions.
428 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
429 (fp_sqrt): New functions, implemented in terms of the above.
430 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
431 (Recip, SquareRoot): Remove (replaced by functions above).
432 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
433 (fp_recip, fp_sqrt): New prototypes.
434 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
435 (Recip, SquareRoot): Replace prototypes with #defines which
436 invoke the functions above.
438 2002-06-03 Chris Demetriou <cgd@broadcom.com>
440 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
441 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
442 file, remove PARAMS from prototypes.
443 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
444 simulator state arguments.
445 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
446 pass simulator state arguments.
447 * cp1.c (SD): Redefine as CPU_STATE(cpu).
448 (store_fpr, convert): Remove 'sd' argument.
449 (value_fpr): Likewise. Convert to use 'SD' instead.
451 2002-06-03 Chris Demetriou <cgd@broadcom.com>
453 * cp1.c (Min, Max): Remove #if 0'd functions.
454 * sim-main.h (Min, Max): Remove.
456 2002-06-03 Chris Demetriou <cgd@broadcom.com>
458 * cp1.c: fix formatting of switch case and default labels.
459 * interp.c: Likewise.
460 * sim-main.c: Likewise.
462 2002-06-03 Chris Demetriou <cgd@broadcom.com>
464 * cp1.c: Clean up comments which describe FP formats.
465 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
467 2002-06-03 Chris Demetriou <cgd@broadcom.com>
468 Ed Satterthwaite <ehs@broadcom.com>
470 * configure.in (mipsisa64sb1*-*-*): New target for supporting
471 Broadcom SiByte SB-1 processor configurations.
472 * configure: Regenerate.
473 * sb1.igen: New file.
474 * mips.igen: Include sb1.igen.
476 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
477 * mdmx.igen: Add "sb1" model to all appropriate functions and
479 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
480 (ob_func, ob_acc): Reference the above.
481 (qh_acc): Adjust to keep the same size as ob_acc.
482 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
483 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
485 2002-06-03 Chris Demetriou <cgd@broadcom.com>
487 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
489 2002-06-02 Chris Demetriou <cgd@broadcom.com>
490 Ed Satterthwaite <ehs@broadcom.com>
492 * mips.igen (mdmx): New (pseudo-)model.
493 * mdmx.c, mdmx.igen: New files.
494 * Makefile.in (SIM_OBJS): Add mdmx.o.
495 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
497 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
498 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
499 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
500 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
501 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
502 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
503 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
504 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
505 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
506 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
507 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
508 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
509 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
510 (qh_fmtsel): New macros.
511 (_sim_cpu): New member "acc".
512 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
513 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
515 2002-05-01 Chris Demetriou <cgd@broadcom.com>
517 * interp.c: Use 'deprecated' rather than 'depreciated.'
518 * sim-main.h: Likewise.
520 2002-05-01 Chris Demetriou <cgd@broadcom.com>
522 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
523 which wouldn't compile anyway.
524 * sim-main.h (unpredictable_action): New function prototype.
525 (Unpredictable): Define to call igen function unpredictable().
526 (NotWordValue): New macro to call igen function not_word_value().
527 (UndefinedResult): Remove.
528 * interp.c (undefined_result): Remove.
529 (unpredictable_action): New function.
530 * mips.igen (not_word_value, unpredictable): New functions.
531 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
532 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
533 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
534 NotWordValue() to check for unpredictable inputs, then
535 Unpredictable() to handle them.
537 2002-02-24 Chris Demetriou <cgd@broadcom.com>
539 * mips.igen: Fix formatting of calls to Unpredictable().
541 2002-04-20 Andrew Cagney <ac131313@redhat.com>
543 * interp.c (sim_open): Revert previous change.
545 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
547 * interp.c (sim_open): Disable chunk of code that wrote code in
548 vector table entries.
550 2002-03-19 Chris Demetriou <cgd@broadcom.com>
552 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
553 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
556 2002-03-19 Chris Demetriou <cgd@broadcom.com>
558 * cp1.c: Fix many formatting issues.
560 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
562 * cp1.c (fpu_format_name): New function to replace...
563 (DOFMT): This. Delete, and update all callers.
564 (fpu_rounding_mode_name): New function to replace...
565 (RMMODE): This. Delete, and update all callers.
567 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
569 * interp.c: Move FPU support routines from here to...
570 * cp1.c: Here. New file.
571 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
574 2002-03-12 Chris Demetriou <cgd@broadcom.com>
576 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
577 * mips.igen (mips32, mips64): New models, add to all instructions
578 and functions as appropriate.
579 (loadstore_ea, check_u64): New variant for model mips64.
580 (check_fmt_p): New variant for models mipsV and mips64, remove
581 mipsV model marking fro other variant.
584 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
585 for mips32 and mips64.
586 (DCLO, DCLZ): New instructions for mips64.
588 2002-03-07 Chris Demetriou <cgd@broadcom.com>
590 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
591 immediate or code as a hex value with the "%#lx" format.
592 (ANDI): Likewise, and fix printed instruction name.
594 2002-03-05 Chris Demetriou <cgd@broadcom.com>
596 * sim-main.h (UndefinedResult, Unpredictable): New macros
597 which currently do nothing.
599 2002-03-05 Chris Demetriou <cgd@broadcom.com>
601 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
602 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
603 (status_CU3): New definitions.
605 * sim-main.h (ExceptionCause): Add new values for MIPS32
606 and MIPS64: MDMX, MCheck, CacheErr. Update comments
607 for DebugBreakPoint and NMIReset to note their status in
609 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
610 (SignalExceptionCacheErr): New exception macros.
612 2002-03-05 Chris Demetriou <cgd@broadcom.com>
614 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
615 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
617 (SignalExceptionCoProcessorUnusable): Take as argument the
618 unusable coprocessor number.
620 2002-03-05 Chris Demetriou <cgd@broadcom.com>
622 * mips.igen: Fix formatting of all SignalException calls.
624 2002-03-05 Chris Demetriou <cgd@broadcom.com>
626 * sim-main.h (SIGNEXTEND): Remove.
628 2002-03-04 Chris Demetriou <cgd@broadcom.com>
630 * mips.igen: Remove gencode comment from top of file, fix
631 spelling in another comment.
633 2002-03-04 Chris Demetriou <cgd@broadcom.com>
635 * mips.igen (check_fmt, check_fmt_p): New functions to check
636 whether specific floating point formats are usable.
637 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
638 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
639 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
640 Use the new functions.
641 (do_c_cond_fmt): Remove format checks...
642 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
644 2002-03-03 Chris Demetriou <cgd@broadcom.com>
646 * mips.igen: Fix formatting of check_fpu calls.
648 2002-03-03 Chris Demetriou <cgd@broadcom.com>
650 * mips.igen (FLOOR.L.fmt): Store correct destination register.
652 2002-03-03 Chris Demetriou <cgd@broadcom.com>
654 * mips.igen: Remove whitespace at end of lines.
656 2002-03-02 Chris Demetriou <cgd@broadcom.com>
658 * mips.igen (loadstore_ea): New function to do effective
659 address calculations.
660 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
661 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
662 CACHE): Use loadstore_ea to do effective address computations.
664 2002-03-02 Chris Demetriou <cgd@broadcom.com>
666 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
667 * mips.igen (LL, CxC1, MxC1): Likewise.
669 2002-03-02 Chris Demetriou <cgd@broadcom.com>
671 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
672 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
673 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
674 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
675 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
676 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
677 Don't split opcode fields by hand, use the opcode field values
680 2002-03-01 Chris Demetriou <cgd@broadcom.com>
682 * mips.igen (do_divu): Fix spacing.
684 * mips.igen (do_dsllv): Move to be right before DSLLV,
685 to match the rest of the do_<shift> functions.
687 2002-03-01 Chris Demetriou <cgd@broadcom.com>
689 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
690 DSRL32, do_dsrlv): Trace inputs and results.
692 2002-03-01 Chris Demetriou <cgd@broadcom.com>
694 * mips.igen (CACHE): Provide instruction-printing string.
696 * interp.c (signal_exception): Comment tokens after #endif.
698 2002-02-28 Chris Demetriou <cgd@broadcom.com>
700 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
701 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
702 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
703 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
704 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
705 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
706 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
707 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
709 2002-02-28 Chris Demetriou <cgd@broadcom.com>
711 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
712 instruction-printing string.
713 (LWU): Use '64' as the filter flag.
715 2002-02-28 Chris Demetriou <cgd@broadcom.com>
717 * mips.igen (SDXC1): Fix instruction-printing string.
719 2002-02-28 Chris Demetriou <cgd@broadcom.com>
721 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
724 2002-02-27 Chris Demetriou <cgd@broadcom.com>
726 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
729 2002-02-27 Chris Demetriou <cgd@broadcom.com>
731 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
732 add a comma) so that it more closely match the MIPS ISA
733 documentation opcode partitioning.
734 (PREF): Put useful names on opcode fields, and include
735 instruction-printing string.
737 2002-02-27 Chris Demetriou <cgd@broadcom.com>
739 * mips.igen (check_u64): New function which in the future will
740 check whether 64-bit instructions are usable and signal an
741 exception if not. Currently a no-op.
742 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
743 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
744 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
745 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
747 * mips.igen (check_fpu): New function which in the future will
748 check whether FPU instructions are usable and signal an exception
749 if not. Currently a no-op.
750 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
751 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
752 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
753 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
754 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
755 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
756 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
757 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
759 2002-02-27 Chris Demetriou <cgd@broadcom.com>
761 * mips.igen (do_load_left, do_load_right): Move to be immediately
763 (do_store_left, do_store_right): Move to be immediately following
766 2002-02-27 Chris Demetriou <cgd@broadcom.com>
768 * mips.igen (mipsV): New model name. Also, add it to
769 all instructions and functions where it is appropriate.
771 2002-02-18 Chris Demetriou <cgd@broadcom.com>
773 * mips.igen: For all functions and instructions, list model
774 names that support that instruction one per line.
776 2002-02-11 Chris Demetriou <cgd@broadcom.com>
778 * mips.igen: Add some additional comments about supported
779 models, and about which instructions go where.
780 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
781 order as is used in the rest of the file.
783 2002-02-11 Chris Demetriou <cgd@broadcom.com>
785 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
786 indicating that ALU32_END or ALU64_END are there to check
788 (DADD): Likewise, but also remove previous comment about
791 2002-02-10 Chris Demetriou <cgd@broadcom.com>
793 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
794 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
795 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
796 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
797 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
798 fields (i.e., add and move commas) so that they more closely
799 match the MIPS ISA documentation opcode partitioning.
801 2002-02-10 Chris Demetriou <cgd@broadcom.com>
803 * mips.igen (ADDI): Print immediate value.
805 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
806 (SLL): Print "nop" specially, and don't run the code
807 that does the shift for the "nop" case.
809 2001-11-17 Fred Fish <fnf@redhat.com>
811 * sim-main.h (float_operation): Move enum declaration outside
812 of _sim_cpu struct declaration.
814 2001-04-12 Jim Blandy <jimb@redhat.com>
816 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
817 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
819 * sim-main.h (COCIDX): Remove definition; this isn't supported by
820 PENDING_FILL, and you can get the intended effect gracefully by
821 calling PENDING_SCHED directly.
823 2001-02-23 Ben Elliston <bje@redhat.com>
825 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
826 already defined elsewhere.
828 2001-02-19 Ben Elliston <bje@redhat.com>
830 * sim-main.h (sim_monitor): Return an int.
831 * interp.c (sim_monitor): Add return values.
832 (signal_exception): Handle error conditions from sim_monitor.
834 2001-02-08 Ben Elliston <bje@redhat.com>
836 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
837 (store_memory): Likewise, pass cia to sim_core_write*.
839 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
841 On advice from Chris G. Demetriou <cgd@sibyte.com>:
842 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
844 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
846 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
847 * Makefile.in: Don't delete *.igen when cleaning directory.
849 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
851 * m16.igen (break): Call SignalException not sim_engine_halt.
853 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
856 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
858 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
860 * mips.igen (MxC1, DMxC1): Fix printf formatting.
862 2000-05-24 Michael Hayes <mhayes@cygnus.com>
864 * mips.igen (do_dmultx): Fix typo.
866 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
868 * configure: Regenerated to track ../common/aclocal.m4 changes.
870 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
872 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
874 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
876 * sim-main.h (GPR_CLEAR): Define macro.
878 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
880 * interp.c (decode_coproc): Output long using %lx and not %s.
882 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
884 * interp.c (sim_open): Sort & extend dummy memory regions for
885 --board=jmr3904 for eCos.
887 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
889 * configure: Regenerated.
891 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
893 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
894 calls, conditional on the simulator being in verbose mode.
896 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
898 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
899 cache don't get ReservedInstruction traps.
901 1999-11-29 Mark Salter <msalter@cygnus.com>
903 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
904 to clear status bits in sdisr register. This is how the hardware works.
906 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
907 being used by cygmon.
909 1999-11-11 Andrew Haley <aph@cygnus.com>
911 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
914 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
916 * mips.igen (MULT): Correct previous mis-applied patch.
918 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
920 * mips.igen (delayslot32): Handle sequence like
921 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
922 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
923 (MULT): Actually pass the third register...
925 1999-09-03 Mark Salter <msalter@cygnus.com>
927 * interp.c (sim_open): Added more memory aliases for additional
928 hardware being touched by cygmon on jmr3904 board.
930 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
932 * configure: Regenerated to track ../common/aclocal.m4 changes.
934 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
936 * interp.c (sim_store_register): Handle case where client - GDB -
937 specifies that a 4 byte register is 8 bytes in size.
938 (sim_fetch_register): Ditto.
940 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
942 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
943 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
944 (idt_monitor_base): Base address for IDT monitor traps.
945 (pmon_monitor_base): Ditto for PMON.
946 (lsipmon_monitor_base): Ditto for LSI PMON.
947 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
948 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
949 (sim_firmware_command): New function.
950 (mips_option_handler): Call it for OPTION_FIRMWARE.
951 (sim_open): Allocate memory for idt_monitor region. If "--board"
952 option was given, add no monitor by default. Add BREAK hooks only if
953 monitors are also there.
955 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
957 * interp.c (sim_monitor): Flush output before reading input.
959 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
961 * tconfig.in (SIM_HANDLES_LMA): Always define.
963 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
965 From Mark Salter <msalter@cygnus.com>:
966 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
967 (sim_open): Add setup for BSP board.
969 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
971 * mips.igen (MULT, MULTU): Add syntax for two operand version.
972 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
973 them as unimplemented.
975 1999-05-08 Felix Lee <flee@cygnus.com>
977 * configure: Regenerated to track ../common/aclocal.m4 changes.
979 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
981 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
983 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
985 * configure.in: Any mips64vr5*-*-* target should have
986 -DTARGET_ENABLE_FR=1.
987 (default_endian): Any mips64vr*el-*-* target should default to
989 * configure: Re-generate.
991 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
993 * mips.igen (ldl): Extend from _16_, not 32.
995 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
997 * interp.c (sim_store_register): Force registers written to by GDB
998 into an un-interpreted state.
1000 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1002 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1003 CPU, start periodic background I/O polls.
1004 (tx3904sio_poll): New function: periodic I/O poller.
1006 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1008 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1010 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1012 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1015 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1017 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1018 (load_word): Call SIM_CORE_SIGNAL hook on error.
1019 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1020 starting. For exception dispatching, pass PC instead of NULL_CIA.
1021 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1022 * sim-main.h (COP0_BADVADDR): Define.
1023 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1024 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1025 (_sim_cpu): Add exc_* fields to store register value snapshots.
1026 * mips.igen (*): Replace memory-related SignalException* calls
1027 with references to SIM_CORE_SIGNAL hook.
1029 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1031 * sim-main.c (*): Minor warning cleanups.
1033 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1035 * m16.igen (DADDIU5): Correct type-o.
1037 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1039 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1042 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1044 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1046 (interp.o): Add dependency on itable.h
1047 (oengine.c, gencode): Delete remaining references.
1048 (BUILT_SRC_FROM_GEN): Clean up.
1050 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1053 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1054 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1055 tmp-run-hack) : New.
1056 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1057 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1058 Drop the "64" qualifier to get the HACK generator working.
1059 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1060 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1061 qualifier to get the hack generator working.
1062 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1063 (DSLL): Use do_dsll.
1064 (DSLLV): Use do_dsllv.
1065 (DSRA): Use do_dsra.
1066 (DSRL): Use do_dsrl.
1067 (DSRLV): Use do_dsrlv.
1068 (BC1): Move *vr4100 to get the HACK generator working.
1069 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1070 get the HACK generator working.
1071 (MACC) Rename to get the HACK generator working.
1072 (DMACC,MACCS,DMACCS): Add the 64.
1074 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1076 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1077 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1079 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1081 * mips/interp.c (DEBUG): Cleanups.
1083 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1085 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1086 (tx3904sio_tickle): fflush after a stdout character output.
1088 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1090 * interp.c (sim_close): Uninstall modules.
1092 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1094 * sim-main.h, interp.c (sim_monitor): Change to global
1097 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1099 * configure.in (vr4100): Only include vr4100 instructions in
1101 * configure: Re-generate.
1102 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1104 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1106 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1107 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1110 * configure.in (sim_default_gen, sim_use_gen): Replace with
1112 (--enable-sim-igen): Delete config option. Always using IGEN.
1113 * configure: Re-generate.
1115 * Makefile.in (gencode): Kill, kill, kill.
1118 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1120 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1121 bit mips16 igen simulator.
1122 * configure: Re-generate.
1124 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1125 as part of vr4100 ISA.
1126 * vr.igen: Mark all instructions as 64 bit only.
1128 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1130 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1133 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1135 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1136 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1137 * configure: Re-generate.
1139 * m16.igen (BREAK): Define breakpoint instruction.
1140 (JALX32): Mark instruction as mips16 and not r3900.
1141 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1143 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1145 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1147 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1148 insn as a debug breakpoint.
1150 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1152 (PENDING_SCHED): Clean up trace statement.
1153 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1154 (PENDING_FILL): Delay write by only one cycle.
1155 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1157 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1159 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1161 (pending_tick): Move incrementing of index to FOR statement.
1162 (pending_tick): Only update PENDING_OUT after a write has occured.
1164 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1166 * configure: Re-generate.
1168 * interp.c (sim_engine_run OLD): Delete explicit call to
1169 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1171 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1173 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1174 interrupt level number to match changed SignalExceptionInterrupt
1177 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1179 * interp.c: #include "itable.h" if WITH_IGEN.
1180 (get_insn_name): New function.
1181 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1182 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1184 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1186 * configure: Rebuilt to inhale new common/aclocal.m4.
1188 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1190 * dv-tx3904sio.c: Include sim-assert.h.
1192 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1194 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1195 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1196 Reorganize target-specific sim-hardware checks.
1197 * configure: rebuilt.
1198 * interp.c (sim_open): For tx39 target boards, set
1199 OPERATING_ENVIRONMENT, add tx3904sio devices.
1200 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1201 ROM executables. Install dv-sockser into sim-modules list.
1203 * dv-tx3904irc.c: Compiler warning clean-up.
1204 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1205 frequent hw-trace messages.
1207 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1209 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1211 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1213 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1215 * vr.igen: New file.
1216 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1217 * mips.igen: Define vr4100 model. Include vr.igen.
1218 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1220 * mips.igen (check_mf_hilo): Correct check.
1222 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1224 * sim-main.h (interrupt_event): Add prototype.
1226 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1227 register_ptr, register_value.
1228 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1230 * sim-main.h (tracefh): Make extern.
1232 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1234 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1235 Reduce unnecessarily high timer event frequency.
1236 * dv-tx3904cpu.c: Ditto for interrupt event.
1238 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1240 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1242 (interrupt_event): Made non-static.
1244 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1245 interchange of configuration values for external vs. internal
1248 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1250 * mips.igen (BREAK): Moved code to here for
1251 simulator-reserved break instructions.
1252 * gencode.c (build_instruction): Ditto.
1253 * interp.c (signal_exception): Code moved from here. Non-
1254 reserved instructions now use exception vector, rather
1256 * sim-main.h: Moved magic constants to here.
1258 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1260 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1261 register upon non-zero interrupt event level, clear upon zero
1263 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1264 by passing zero event value.
1265 (*_io_{read,write}_buffer): Endianness fixes.
1266 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1267 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1269 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1270 serial I/O and timer module at base address 0xFFFF0000.
1272 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1274 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1277 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1279 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1281 * configure: Update.
1283 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1285 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1286 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1287 * configure.in: Include tx3904tmr in hw_device list.
1288 * configure: Rebuilt.
1289 * interp.c (sim_open): Instantiate three timer instances.
1290 Fix address typo of tx3904irc instance.
1292 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1294 * interp.c (signal_exception): SystemCall exception now uses
1295 the exception vector.
1297 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1299 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1302 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1304 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1306 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1308 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1310 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1311 sim-main.h. Declare a struct hw_descriptor instead of struct
1312 hw_device_descriptor.
1314 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1316 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1317 right bits and then re-align left hand bytes to correct byte
1318 lanes. Fix incorrect computation in do_store_left when loading
1319 bytes from second word.
1321 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1323 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1324 * interp.c (sim_open): Only create a device tree when HW is
1327 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1328 * interp.c (signal_exception): Ditto.
1330 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1332 * gencode.c: Mark BEGEZALL as LIKELY.
1334 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1336 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1337 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1339 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1341 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1342 modules. Recognize TX39 target with "mips*tx39" pattern.
1343 * configure: Rebuilt.
1344 * sim-main.h (*): Added many macros defining bits in
1345 TX39 control registers.
1346 (SignalInterrupt): Send actual PC instead of NULL.
1347 (SignalNMIReset): New exception type.
1348 * interp.c (board): New variable for future use to identify
1349 a particular board being simulated.
1350 (mips_option_handler,mips_options): Added "--board" option.
1351 (interrupt_event): Send actual PC.
1352 (sim_open): Make memory layout conditional on board setting.
1353 (signal_exception): Initial implementation of hardware interrupt
1354 handling. Accept another break instruction variant for simulator
1356 (decode_coproc): Implement RFE instruction for TX39.
1357 (mips.igen): Decode RFE instruction as such.
1358 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1359 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1360 bbegin to implement memory map.
1361 * dv-tx3904cpu.c: New file.
1362 * dv-tx3904irc.c: New file.
1364 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1366 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1368 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1370 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1371 with calls to check_div_hilo.
1373 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1375 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1376 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1377 Add special r3900 version of do_mult_hilo.
1378 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1379 with calls to check_mult_hilo.
1380 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1381 with calls to check_div_hilo.
1383 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1385 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1386 Document a replacement.
1388 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1390 * interp.c (sim_monitor): Make mon_printf work.
1392 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1394 * sim-main.h (INSN_NAME): New arg `cpu'.
1396 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1398 * configure: Regenerated to track ../common/aclocal.m4 changes.
1400 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1402 * configure: Regenerated to track ../common/aclocal.m4 changes.
1405 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1407 * acconfig.h: New file.
1408 * configure.in: Reverted change of Apr 24; use sinclude again.
1410 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1412 * configure: Regenerated to track ../common/aclocal.m4 changes.
1415 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1417 * configure.in: Don't call sinclude.
1419 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1421 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1423 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1425 * mips.igen (ERET): Implement.
1427 * interp.c (decode_coproc): Return sign-extended EPC.
1429 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1431 * interp.c (signal_exception): Do not ignore Trap.
1432 (signal_exception): On TRAP, restart at exception address.
1433 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1434 (signal_exception): Update.
1435 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1436 so that TRAP instructions are caught.
1438 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1440 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1441 contains HI/LO access history.
1442 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1443 (HIACCESS, LOACCESS): Delete, replace with
1444 (HIHISTORY, LOHISTORY): New macros.
1445 (CHECKHILO): Delete all, moved to mips.igen
1447 * gencode.c (build_instruction): Do not generate checks for
1448 correct HI/LO register usage.
1450 * interp.c (old_engine_run): Delete checks for correct HI/LO
1453 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1454 check_mf_cycles): New functions.
1455 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1456 do_divu, domultx, do_mult, do_multu): Use.
1458 * tx.igen ("madd", "maddu"): Use.
1460 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1462 * mips.igen (DSRAV): Use function do_dsrav.
1463 (SRAV): Use new function do_srav.
1465 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1466 (B): Sign extend 11 bit immediate.
1467 (EXT-B*): Shift 16 bit immediate left by 1.
1468 (ADDIU*): Don't sign extend immediate value.
1470 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1472 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1474 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1477 * mips.igen (delayslot32, nullify_next_insn): New functions.
1478 (m16.igen): Always include.
1479 (do_*): Add more tracing.
1481 * m16.igen (delayslot16): Add NIA argument, could be called by a
1482 32 bit MIPS16 instruction.
1484 * interp.c (ifetch16): Move function from here.
1485 * sim-main.c (ifetch16): To here.
1487 * sim-main.c (ifetch16, ifetch32): Update to match current
1488 implementations of LH, LW.
1489 (signal_exception): Don't print out incorrect hex value of illegal
1492 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1494 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1497 * m16.igen: Implement MIPS16 instructions.
1499 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1500 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1501 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1502 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1503 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1504 bodies of corresponding code from 32 bit insn to these. Also used
1505 by MIPS16 versions of functions.
1507 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1508 (IMEM16): Drop NR argument from macro.
1510 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1512 * Makefile.in (SIM_OBJS): Add sim-main.o.
1514 * sim-main.h (address_translation, load_memory, store_memory,
1515 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1517 (pr_addr, pr_uword64): Declare.
1518 (sim-main.c): Include when H_REVEALS_MODULE_P.
1520 * interp.c (address_translation, load_memory, store_memory,
1521 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1523 * sim-main.c: To here. Fix compilation problems.
1525 * configure.in: Enable inlining.
1526 * configure: Re-config.
1528 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1530 * configure: Regenerated to track ../common/aclocal.m4 changes.
1532 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1534 * mips.igen: Include tx.igen.
1535 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1536 * tx.igen: New file, contains MADD and MADDU.
1538 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1539 the hardwired constant `7'.
1540 (store_memory): Ditto.
1541 (LOADDRMASK): Move definition to sim-main.h.
1543 mips.igen (MTC0): Enable for r3900.
1546 mips.igen (do_load_byte): Delete.
1547 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1548 do_store_right): New functions.
1549 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1551 configure.in: Let the tx39 use igen again.
1554 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1556 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1557 not an address sized quantity. Return zero for cache sizes.
1559 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1561 * mips.igen (r3900): r3900 does not support 64 bit integer
1564 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1566 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1568 * configure : Rebuild.
1570 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1572 * configure: Regenerated to track ../common/aclocal.m4 changes.
1574 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1576 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1578 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1580 * configure: Regenerated to track ../common/aclocal.m4 changes.
1581 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1583 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1585 * configure: Regenerated to track ../common/aclocal.m4 changes.
1587 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1589 * interp.c (Max, Min): Comment out functions. Not yet used.
1591 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1593 * configure: Regenerated to track ../common/aclocal.m4 changes.
1595 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1597 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1598 configurable settings for stand-alone simulator.
1600 * configure.in: Added X11 search, just in case.
1602 * configure: Regenerated.
1604 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1606 * interp.c (sim_write, sim_read, load_memory, store_memory):
1607 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1609 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1611 * sim-main.h (GETFCC): Return an unsigned value.
1613 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1615 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1616 (DADD): Result destination is RD not RT.
1618 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1620 * sim-main.h (HIACCESS, LOACCESS): Always define.
1622 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1624 * interp.c (sim_info): Delete.
1626 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1628 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1629 (mips_option_handler): New argument `cpu'.
1630 (sim_open): Update call to sim_add_option_table.
1632 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1634 * mips.igen (CxC1): Add tracing.
1636 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1638 * sim-main.h (Max, Min): Declare.
1640 * interp.c (Max, Min): New functions.
1642 * mips.igen (BC1): Add tracing.
1644 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1646 * interp.c Added memory map for stack in vr4100
1648 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1650 * interp.c (load_memory): Add missing "break"'s.
1652 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1654 * interp.c (sim_store_register, sim_fetch_register): Pass in
1655 length parameter. Return -1.
1657 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1659 * interp.c: Added hardware init hook, fixed warnings.
1661 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1663 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1665 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1667 * interp.c (ifetch16): New function.
1669 * sim-main.h (IMEM32): Rename IMEM.
1670 (IMEM16_IMMED): Define.
1672 (DELAY_SLOT): Update.
1674 * m16run.c (sim_engine_run): New file.
1676 * m16.igen: All instructions except LB.
1677 (LB): Call do_load_byte.
1678 * mips.igen (do_load_byte): New function.
1679 (LB): Call do_load_byte.
1681 * mips.igen: Move spec for insn bit size and high bit from here.
1682 * Makefile.in (tmp-igen, tmp-m16): To here.
1684 * m16.dc: New file, decode mips16 instructions.
1686 * Makefile.in (SIM_NO_ALL): Define.
1687 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1689 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1691 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1692 point unit to 32 bit registers.
1693 * configure: Re-generate.
1695 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1697 * configure.in (sim_use_gen): Make IGEN the default simulator
1698 generator for generic 32 and 64 bit mips targets.
1699 * configure: Re-generate.
1701 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1703 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1706 * interp.c (sim_fetch_register, sim_store_register): Read/write
1707 FGR from correct location.
1708 (sim_open): Set size of FGR's according to
1709 WITH_TARGET_FLOATING_POINT_BITSIZE.
1711 * sim-main.h (FGR): Store floating point registers in a separate
1714 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1716 * configure: Regenerated to track ../common/aclocal.m4 changes.
1718 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1720 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1722 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1724 * interp.c (pending_tick): New function. Deliver pending writes.
1726 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1727 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1728 it can handle mixed sized quantites and single bits.
1730 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1732 * interp.c (oengine.h): Do not include when building with IGEN.
1733 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1734 (sim_info): Ditto for PROCESSOR_64BIT.
1735 (sim_monitor): Replace ut_reg with unsigned_word.
1736 (*): Ditto for t_reg.
1737 (LOADDRMASK): Define.
1738 (sim_open): Remove defunct check that host FP is IEEE compliant,
1739 using software to emulate floating point.
1740 (value_fpr, ...): Always compile, was conditional on HASFPU.
1742 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1744 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1747 * interp.c (SD, CPU): Define.
1748 (mips_option_handler): Set flags in each CPU.
1749 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1750 (sim_close): Do not clear STATE, deleted anyway.
1751 (sim_write, sim_read): Assume CPU zero's vm should be used for
1753 (sim_create_inferior): Set the PC for all processors.
1754 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1756 (mips16_entry): Pass correct nr of args to store_word, load_word.
1757 (ColdReset): Cold reset all cpu's.
1758 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1759 (sim_monitor, load_memory, store_memory, signal_exception): Use
1760 `CPU' instead of STATE_CPU.
1763 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1766 * sim-main.h (signal_exception): Add sim_cpu arg.
1767 (SignalException*): Pass both SD and CPU to signal_exception.
1768 * interp.c (signal_exception): Update.
1770 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1772 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1773 address_translation): Ditto
1774 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1776 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1778 * configure: Regenerated to track ../common/aclocal.m4 changes.
1780 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1782 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1784 * mips.igen (model): Map processor names onto BFD name.
1786 * sim-main.h (CPU_CIA): Delete.
1787 (SET_CIA, GET_CIA): Define
1789 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1791 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1794 * configure.in (default_endian): Configure a big-endian simulator
1796 * configure: Re-generate.
1798 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1800 * configure: Regenerated to track ../common/aclocal.m4 changes.
1802 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1804 * interp.c (sim_monitor): Handle Densan monitor outbyte
1805 and inbyte functions.
1807 1997-12-29 Felix Lee <flee@cygnus.com>
1809 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1811 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1813 * Makefile.in (tmp-igen): Arrange for $zero to always be
1814 reset to zero after every instruction.
1816 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1818 * configure: Regenerated to track ../common/aclocal.m4 changes.
1821 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1823 * mips.igen (MSUB): Fix to work like MADD.
1824 * gencode.c (MSUB): Similarly.
1826 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1828 * configure: Regenerated to track ../common/aclocal.m4 changes.
1830 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1832 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1834 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1836 * sim-main.h (sim-fpu.h): Include.
1838 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1839 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1840 using host independant sim_fpu module.
1842 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1844 * interp.c (signal_exception): Report internal errors with SIGABRT
1847 * sim-main.h (C0_CONFIG): New register.
1848 (signal.h): No longer include.
1850 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1852 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1854 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1856 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1858 * mips.igen: Tag vr5000 instructions.
1859 (ANDI): Was missing mipsIV model, fix assembler syntax.
1860 (do_c_cond_fmt): New function.
1861 (C.cond.fmt): Handle mips I-III which do not support CC field
1863 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1864 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1866 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1867 vr5000 which saves LO in a GPR separatly.
1869 * configure.in (enable-sim-igen): For vr5000, select vr5000
1870 specific instructions.
1871 * configure: Re-generate.
1873 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1877 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1878 fmt_uninterpreted_64 bit cases to switch. Convert to
1881 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1883 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1884 as specified in IV3.2 spec.
1885 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1887 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1889 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1890 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1891 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1892 PENDING_FILL versions of instructions. Simplify.
1894 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1896 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1898 (MTHI, MFHI): Disable code checking HI-LO.
1900 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1902 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1904 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1906 * gencode.c (build_mips16_operands): Replace IPC with cia.
1908 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1909 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1911 (UndefinedResult): Replace function with macro/function
1913 (sim_engine_run): Don't save PC in IPC.
1915 * sim-main.h (IPC): Delete.
1918 * interp.c (signal_exception, store_word, load_word,
1919 address_translation, load_memory, store_memory, cache_op,
1920 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1921 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1922 current instruction address - cia - argument.
1923 (sim_read, sim_write): Call address_translation directly.
1924 (sim_engine_run): Rename variable vaddr to cia.
1925 (signal_exception): Pass cia to sim_monitor
1927 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1928 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1929 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1931 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1932 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1935 * interp.c (signal_exception): Pass restart address to
1938 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1939 idecode.o): Add dependency.
1941 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1943 (DELAY_SLOT): Update NIA not PC with branch address.
1944 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1946 * mips.igen: Use CIA not PC in branch calculations.
1947 (illegal): Call SignalException.
1948 (BEQ, ADDIU): Fix assembler.
1950 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1952 * m16.igen (JALX): Was missing.
1954 * configure.in (enable-sim-igen): New configuration option.
1955 * configure: Re-generate.
1957 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1959 * interp.c (load_memory, store_memory): Delete parameter RAW.
1960 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1961 bypassing {load,store}_memory.
1963 * sim-main.h (ByteSwapMem): Delete definition.
1965 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1967 * interp.c (sim_do_command, sim_commands): Delete mips specific
1968 commands. Handled by module sim-options.
1970 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1971 (WITH_MODULO_MEMORY): Define.
1973 * interp.c (sim_info): Delete code printing memory size.
1975 * interp.c (mips_size): Nee sim_size, delete function.
1977 (monitor, monitor_base, monitor_size): Delete global variables.
1978 (sim_open, sim_close): Delete code creating monitor and other
1979 memory regions. Use sim-memopts module, via sim_do_commandf, to
1980 manage memory regions.
1981 (load_memory, store_memory): Use sim-core for memory model.
1983 * interp.c (address_translation): Delete all memory map code
1984 except line forcing 32 bit addresses.
1986 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1988 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1991 * interp.c (logfh, logfile): Delete globals.
1992 (sim_open, sim_close): Delete code opening & closing log file.
1993 (mips_option_handler): Delete -l and -n options.
1994 (OPTION mips_options): Ditto.
1996 * interp.c (OPTION mips_options): Rename option trace to dinero.
1997 (mips_option_handler): Update.
1999 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2001 * interp.c (fetch_str): New function.
2002 (sim_monitor): Rewrite using sim_read & sim_write.
2003 (sim_open): Check magic number.
2004 (sim_open): Write monitor vectors into memory using sim_write.
2005 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2006 (sim_read, sim_write): Simplify - transfer data one byte at a
2008 (load_memory, store_memory): Clarify meaning of parameter RAW.
2010 * sim-main.h (isHOST): Defete definition.
2011 (isTARGET): Mark as depreciated.
2012 (address_translation): Delete parameter HOST.
2014 * interp.c (address_translation): Delete parameter HOST.
2016 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2020 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2021 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2023 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2025 * mips.igen: Add model filter field to records.
2027 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2029 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2031 interp.c (sim_engine_run): Do not compile function sim_engine_run
2032 when WITH_IGEN == 1.
2034 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2035 target architecture.
2037 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2038 igen. Replace with configuration variables sim_igen_flags /
2041 * m16.igen: New file. Copy mips16 insns here.
2042 * mips.igen: From here.
2044 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2046 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2048 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2050 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2052 * gencode.c (build_instruction): Follow sim_write's lead in using
2053 BigEndianMem instead of !ByteSwapMem.
2055 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2057 * configure.in (sim_gen): Dependent on target, select type of
2058 generator. Always select old style generator.
2060 configure: Re-generate.
2062 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2064 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2065 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2066 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2067 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2068 SIM_@sim_gen@_*, set by autoconf.
2070 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2072 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2074 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2075 CURRENT_FLOATING_POINT instead.
2077 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2078 (address_translation): Raise exception InstructionFetch when
2079 translation fails and isINSTRUCTION.
2081 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2082 sim_engine_run): Change type of of vaddr and paddr to
2084 (address_translation, prefetch, load_memory, store_memory,
2085 cache_op): Change type of vAddr and pAddr to address_word.
2087 * gencode.c (build_instruction): Change type of vaddr and paddr to
2090 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2092 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2093 macro to obtain result of ALU op.
2095 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2097 * interp.c (sim_info): Call profile_print.
2099 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2103 * sim-main.h (WITH_PROFILE): Do not define, defined in
2104 common/sim-config.h. Use sim-profile module.
2105 (simPROFILE): Delete defintion.
2107 * interp.c (PROFILE): Delete definition.
2108 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2109 (sim_close): Delete code writing profile histogram.
2110 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2112 (sim_engine_run): Delete code profiling the PC.
2114 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2116 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2118 * interp.c (sim_monitor): Make register pointers of type
2121 * sim-main.h: Make registers of type unsigned_word not
2124 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2126 * interp.c (sync_operation): Rename from SyncOperation, make
2127 global, add SD argument.
2128 (prefetch): Rename from Prefetch, make global, add SD argument.
2129 (decode_coproc): Make global.
2131 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2133 * gencode.c (build_instruction): Generate DecodeCoproc not
2134 decode_coproc calls.
2136 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2137 (SizeFGR): Move to sim-main.h
2138 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2139 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2140 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2142 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2143 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2144 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2145 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2146 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2147 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2149 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2151 (sim-alu.h): Include.
2152 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2153 (sim_cia): Typedef to instruction_address.
2155 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2157 * Makefile.in (interp.o): Rename generated file engine.c to
2162 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2164 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2166 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2168 * gencode.c (build_instruction): For "FPSQRT", output correct
2169 number of arguments to Recip.
2171 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2173 * Makefile.in (interp.o): Depends on sim-main.h
2175 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2177 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2178 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2179 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2180 STATE, DSSTATE): Define
2181 (GPR, FGRIDX, ..): Define.
2183 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2184 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2185 (GPR, FGRIDX, ...): Delete macros.
2187 * interp.c: Update names to match defines from sim-main.h
2189 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2191 * interp.c (sim_monitor): Add SD argument.
2192 (sim_warning): Delete. Replace calls with calls to
2194 (sim_error): Delete. Replace calls with sim_io_error.
2195 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2196 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2197 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2199 (mips_size): Rename from sim_size. Add SD argument.
2201 * interp.c (simulator): Delete global variable.
2202 (callback): Delete global variable.
2203 (mips_option_handler, sim_open, sim_write, sim_read,
2204 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2205 sim_size,sim_monitor): Use sim_io_* not callback->*.
2206 (sim_open): ZALLOC simulator struct.
2207 (PROFILE): Do not define.
2209 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2211 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2212 support.h with corresponding code.
2214 * sim-main.h (word64, uword64), support.h: Move definition to
2216 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2219 * Makefile.in: Update dependencies
2220 * interp.c: Do not include.
2222 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2224 * interp.c (address_translation, load_memory, store_memory,
2225 cache_op): Rename to from AddressTranslation et.al., make global,
2228 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2231 * interp.c (SignalException): Rename to signal_exception, make
2234 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2236 * sim-main.h (SignalException, SignalExceptionInterrupt,
2237 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2238 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2239 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2242 * interp.c, support.h: Use.
2244 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2246 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2247 to value_fpr / store_fpr. Add SD argument.
2248 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2249 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2251 * sim-main.h (ValueFPR, StoreFPR): Define.
2253 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2255 * interp.c (sim_engine_run): Check consistency between configure
2256 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2259 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2260 (mips_fpu): Configure WITH_FLOATING_POINT.
2261 (mips_endian): Configure WITH_TARGET_ENDIAN.
2262 * configure: Update.
2264 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2266 * configure: Regenerated to track ../common/aclocal.m4 changes.
2268 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2270 * configure: Regenerated.
2272 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2274 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2276 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2278 * gencode.c (print_igen_insn_models): Assume certain architectures
2279 include all mips* instructions.
2280 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2283 * Makefile.in (tmp.igen): Add target. Generate igen input from
2286 * gencode.c (FEATURE_IGEN): Define.
2287 (main): Add --igen option. Generate output in igen format.
2288 (process_instructions): Format output according to igen option.
2289 (print_igen_insn_format): New function.
2290 (print_igen_insn_models): New function.
2291 (process_instructions): Only issue warnings and ignore
2292 instructions when no FEATURE_IGEN.
2294 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2296 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2299 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301 * configure: Regenerated to track ../common/aclocal.m4 changes.
2303 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2305 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2306 SIM_RESERVED_BITS): Delete, moved to common.
2307 (SIM_EXTRA_CFLAGS): Update.
2309 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2311 * configure.in: Configure non-strict memory alignment.
2312 * configure: Regenerated to track ../common/aclocal.m4 changes.
2314 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2316 * configure: Regenerated to track ../common/aclocal.m4 changes.
2318 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2320 * gencode.c (SDBBP,DERET): Added (3900) insns.
2321 (RFE): Turn on for 3900.
2322 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2323 (dsstate): Made global.
2324 (SUBTARGET_R3900): Added.
2325 (CANCELDELAYSLOT): New.
2326 (SignalException): Ignore SystemCall rather than ignore and
2327 terminate. Add DebugBreakPoint handling.
2328 (decode_coproc): New insns RFE, DERET; and new registers Debug
2329 and DEPC protected by SUBTARGET_R3900.
2330 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2332 * Makefile.in,configure.in: Add mips subtarget option.
2333 * configure: Update.
2335 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2337 * gencode.c: Add r3900 (tx39).
2340 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2342 * gencode.c (build_instruction): Don't need to subtract 4 for
2345 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2347 * interp.c: Correct some HASFPU problems.
2349 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2351 * configure: Regenerated to track ../common/aclocal.m4 changes.
2353 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2355 * interp.c (mips_options): Fix samples option short form, should
2358 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2360 * interp.c (sim_info): Enable info code. Was just returning.
2362 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2364 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2367 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2369 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2371 (build_instruction): Ditto for LL.
2373 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2375 * configure: Regenerated to track ../common/aclocal.m4 changes.
2377 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2379 * configure: Regenerated to track ../common/aclocal.m4 changes.
2382 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2384 * interp.c (sim_open): Add call to sim_analyze_program, update
2387 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2389 * interp.c (sim_kill): Delete.
2390 (sim_create_inferior): Add ABFD argument. Set PC from same.
2391 (sim_load): Move code initializing trap handlers from here.
2392 (sim_open): To here.
2393 (sim_load): Delete, use sim-hload.c.
2395 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2397 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2399 * configure: Regenerated to track ../common/aclocal.m4 changes.
2402 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2404 * interp.c (sim_open): Add ABFD argument.
2405 (sim_load): Move call to sim_config from here.
2406 (sim_open): To here. Check return status.
2408 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2410 * gencode.c (build_instruction): Two arg MADD should
2411 not assign result to $0.
2413 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2415 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2416 * sim/mips/configure.in: Regenerate.
2418 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2420 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2421 signed8, unsigned8 et.al. types.
2423 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2424 hosts when selecting subreg.
2426 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2428 * interp.c (sim_engine_run): Reset the ZERO register to zero
2429 regardless of FEATURE_WARN_ZERO.
2430 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2432 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2434 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2435 (SignalException): For BreakPoints ignore any mode bits and just
2437 (SignalException): Always set the CAUSE register.
2439 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2441 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2442 exception has been taken.
2444 * interp.c: Implement the ERET and mt/f sr instructions.
2446 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2448 * interp.c (SignalException): Don't bother restarting an
2451 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2453 * interp.c (SignalException): Really take an interrupt.
2454 (interrupt_event): Only deliver interrupts when enabled.
2456 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2458 * interp.c (sim_info): Only print info when verbose.
2459 (sim_info) Use sim_io_printf for output.
2461 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2463 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2466 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2468 * interp.c (sim_do_command): Check for common commands if a
2469 simulator specific command fails.
2471 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2473 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2474 and simBE when DEBUG is defined.
2476 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2478 * interp.c (interrupt_event): New function. Pass exception event
2479 onto exception handler.
2481 * configure.in: Check for stdlib.h.
2482 * configure: Regenerate.
2484 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2485 variable declaration.
2486 (build_instruction): Initialize memval1.
2487 (build_instruction): Add UNUSED attribute to byte, bigend,
2489 (build_operands): Ditto.
2491 * interp.c: Fix GCC warnings.
2492 (sim_get_quit_code): Delete.
2494 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2495 * Makefile.in: Ditto.
2496 * configure: Re-generate.
2498 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2500 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2502 * interp.c (mips_option_handler): New function parse argumes using
2504 (myname): Replace with STATE_MY_NAME.
2505 (sim_open): Delete check for host endianness - performed by
2507 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2508 (sim_open): Move much of the initialization from here.
2509 (sim_load): To here. After the image has been loaded and
2511 (sim_open): Move ColdReset from here.
2512 (sim_create_inferior): To here.
2513 (sim_open): Make FP check less dependant on host endianness.
2515 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2517 * interp.c (sim_set_callbacks): Delete.
2519 * interp.c (membank, membank_base, membank_size): Replace with
2520 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2521 (sim_open): Remove call to callback->init. gdb/run do this.
2525 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2527 * interp.c (big_endian_p): Delete, replaced by
2528 current_target_byte_order.
2530 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2532 * interp.c (host_read_long, host_read_word, host_swap_word,
2533 host_swap_long): Delete. Using common sim-endian.
2534 (sim_fetch_register, sim_store_register): Use H2T.
2535 (pipeline_ticks): Delete. Handled by sim-events.
2537 (sim_engine_run): Update.
2539 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2541 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2543 (SignalException): To here. Signal using sim_engine_halt.
2544 (sim_stop_reason): Delete, moved to common.
2546 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2548 * interp.c (sim_open): Add callback argument.
2549 (sim_set_callbacks): Delete SIM_DESC argument.
2552 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2554 * Makefile.in (SIM_OBJS): Add common modules.
2556 * interp.c (sim_set_callbacks): Also set SD callback.
2557 (set_endianness, xfer_*, swap_*): Delete.
2558 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2559 Change to functions using sim-endian macros.
2560 (control_c, sim_stop): Delete, use common version.
2561 (simulate): Convert into.
2562 (sim_engine_run): This function.
2563 (sim_resume): Delete.
2565 * interp.c (simulation): New variable - the simulator object.
2566 (sim_kind): Delete global - merged into simulation.
2567 (sim_load): Cleanup. Move PC assignment from here.
2568 (sim_create_inferior): To here.
2570 * sim-main.h: New file.
2571 * interp.c (sim-main.h): Include.
2573 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2575 * configure: Regenerated to track ../common/aclocal.m4 changes.
2577 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2579 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2581 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2583 * gencode.c (build_instruction): DIV instructions: check
2584 for division by zero and integer overflow before using
2585 host's division operation.
2587 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2589 * Makefile.in (SIM_OBJS): Add sim-load.o.
2590 * interp.c: #include bfd.h.
2591 (target_byte_order): Delete.
2592 (sim_kind, myname, big_endian_p): New static locals.
2593 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2594 after argument parsing. Recognize -E arg, set endianness accordingly.
2595 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2596 load file into simulator. Set PC from bfd.
2597 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2598 (set_endianness): Use big_endian_p instead of target_byte_order.
2600 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2602 * interp.c (sim_size): Delete prototype - conflicts with
2603 definition in remote-sim.h. Correct definition.
2605 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2607 * configure: Regenerated to track ../common/aclocal.m4 changes.
2610 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2612 * interp.c (sim_open): New arg `kind'.
2614 * configure: Regenerated to track ../common/aclocal.m4 changes.
2616 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2618 * configure: Regenerated to track ../common/aclocal.m4 changes.
2620 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2622 * interp.c (sim_open): Set optind to 0 before calling getopt.
2624 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2626 * configure: Regenerated to track ../common/aclocal.m4 changes.
2628 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2630 * interp.c : Replace uses of pr_addr with pr_uword64
2631 where the bit length is always 64 independent of SIM_ADDR.
2632 (pr_uword64) : added.
2634 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2636 * configure: Re-generate.
2638 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2640 * configure: Regenerate to track ../common/aclocal.m4 changes.
2642 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2644 * interp.c (sim_open): New SIM_DESC result. Argument is now
2646 (other sim_*): New SIM_DESC argument.
2648 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2650 * interp.c: Fix printing of addresses for non-64-bit targets.
2651 (pr_addr): Add function to print address based on size.
2653 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2655 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2657 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2659 * gencode.c (build_mips16_operands): Correct computation of base
2660 address for extended PC relative instruction.
2662 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2664 * interp.c (mips16_entry): Add support for floating point cases.
2665 (SignalException): Pass floating point cases to mips16_entry.
2666 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2668 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2670 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2671 and then set the state to fmt_uninterpreted.
2672 (COP_SW): Temporarily set the state to fmt_word while calling
2675 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2677 * gencode.c (build_instruction): The high order may be set in the
2678 comparison flags at any ISA level, not just ISA 4.
2680 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2682 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2683 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2684 * configure.in: sinclude ../common/aclocal.m4.
2685 * configure: Regenerated.
2687 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2689 * configure: Rebuild after change to aclocal.m4.
2691 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2693 * configure configure.in Makefile.in: Update to new configure
2694 scheme which is more compatible with WinGDB builds.
2695 * configure.in: Improve comment on how to run autoconf.
2696 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2697 * Makefile.in: Use autoconf substitution to install common
2700 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2702 * gencode.c (build_instruction): Use BigEndianCPU instead of
2705 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2707 * interp.c (sim_monitor): Make output to stdout visible in
2708 wingdb's I/O log window.
2710 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2712 * support.h: Undo previous change to SIGTRAP
2715 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2717 * interp.c (store_word, load_word): New static functions.
2718 (mips16_entry): New static function.
2719 (SignalException): Look for mips16 entry and exit instructions.
2720 (simulate): Use the correct index when setting fpr_state after
2721 doing a pending move.
2723 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2725 * interp.c: Fix byte-swapping code throughout to work on
2726 both little- and big-endian hosts.
2728 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2730 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2731 with gdb/config/i386/xm-windows.h.
2733 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2735 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2736 that messes up arithmetic shifts.
2738 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2740 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2741 SIGTRAP and SIGQUIT for _WIN32.
2743 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2745 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2746 force a 64 bit multiplication.
2747 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2748 destination register is 0, since that is the default mips16 nop
2751 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2753 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2754 (build_endian_shift): Don't check proc64.
2755 (build_instruction): Always set memval to uword64. Cast op2 to
2756 uword64 when shifting it left in memory instructions. Always use
2757 the same code for stores--don't special case proc64.
2759 * gencode.c (build_mips16_operands): Fix base PC value for PC
2761 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2763 * interp.c (simJALDELAYSLOT): Define.
2764 (JALDELAYSLOT): Define.
2765 (INDELAYSLOT, INJALDELAYSLOT): Define.
2766 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2768 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2770 * interp.c (sim_open): add flush_cache as a PMON routine
2771 (sim_monitor): handle flush_cache by ignoring it
2773 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2775 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2777 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2778 (BigEndianMem): Rename to ByteSwapMem and change sense.
2779 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2780 BigEndianMem references to !ByteSwapMem.
2781 (set_endianness): New function, with prototype.
2782 (sim_open): Call set_endianness.
2783 (sim_info): Use simBE instead of BigEndianMem.
2784 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2785 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2786 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2787 ifdefs, keeping the prototype declaration.
2788 (swap_word): Rewrite correctly.
2789 (ColdReset): Delete references to CONFIG. Delete endianness related
2790 code; moved to set_endianness.
2792 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2794 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2795 * interp.c (CHECKHILO): Define away.
2796 (simSIGINT): New macro.
2797 (membank_size): Increase from 1MB to 2MB.
2798 (control_c): New function.
2799 (sim_resume): Rename parameter signal to signal_number. Add local
2800 variable prev. Call signal before and after simulate.
2801 (sim_stop_reason): Add simSIGINT support.
2802 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2804 (sim_warning): Delete call to SignalException. Do call printf_filtered
2806 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2807 a call to sim_warning.
2809 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2811 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2812 16 bit instructions.
2814 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2816 Add support for mips16 (16 bit MIPS implementation):
2817 * gencode.c (inst_type): Add mips16 instruction encoding types.
2818 (GETDATASIZEINSN): Define.
2819 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2820 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2822 (MIPS16_DECODE): New table, for mips16 instructions.
2823 (bitmap_val): New static function.
2824 (struct mips16_op): Define.
2825 (mips16_op_table): New table, for mips16 operands.
2826 (build_mips16_operands): New static function.
2827 (process_instructions): If PC is odd, decode a mips16
2828 instruction. Break out instruction handling into new
2829 build_instruction function.
2830 (build_instruction): New static function, broken out of
2831 process_instructions. Check modifiers rather than flags for SHIFT
2832 bit count and m[ft]{hi,lo} direction.
2833 (usage): Pass program name to fprintf.
2834 (main): Remove unused variable this_option_optind. Change
2835 ``*loptarg++'' to ``loptarg++''.
2836 (my_strtoul): Parenthesize && within ||.
2837 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2838 (simulate): If PC is odd, fetch a 16 bit instruction, and
2839 increment PC by 2 rather than 4.
2840 * configure.in: Add case for mips16*-*-*.
2841 * configure: Rebuild.
2843 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2845 * interp.c: Allow -t to enable tracing in standalone simulator.
2846 Fix garbage output in trace file and error messages.
2848 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2850 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2851 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2852 * configure.in: Simplify using macros in ../common/aclocal.m4.
2853 * configure: Regenerated.
2854 * tconfig.in: New file.
2856 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2858 * interp.c: Fix bugs in 64-bit port.
2859 Use ansi function declarations for msvc compiler.
2860 Initialize and test file pointer in trace code.
2861 Prevent duplicate definition of LAST_EMED_REGNUM.
2863 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2865 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2867 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2869 * interp.c (SignalException): Check for explicit terminating
2871 * gencode.c: Pass instruction value through SignalException()
2872 calls for Trap, Breakpoint and Syscall.
2874 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2876 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2877 only used on those hosts that provide it.
2878 * configure.in: Add sqrt() to list of functions to be checked for.
2879 * config.in: Re-generated.
2880 * configure: Re-generated.
2882 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2884 * gencode.c (process_instructions): Call build_endian_shift when
2885 expanding STORE RIGHT, to fix swr.
2886 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2887 clear the high bits.
2888 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2889 Fix float to int conversions to produce signed values.
2891 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2893 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2894 (process_instructions): Correct handling of nor instruction.
2895 Correct shift count for 32 bit shift instructions. Correct sign
2896 extension for arithmetic shifts to not shift the number of bits in
2897 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2898 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2900 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2901 It's OK to have a mult follow a mult. What's not OK is to have a
2902 mult follow an mfhi.
2903 (Convert): Comment out incorrect rounding code.
2905 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2907 * interp.c (sim_monitor): Improved monitor printf
2908 simulation. Tidied up simulator warnings, and added "--log" option
2909 for directing warning message output.
2910 * gencode.c: Use sim_warning() rather than WARNING macro.
2912 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2914 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2915 getopt1.o, rather than on gencode.c. Link objects together.
2916 Don't link against -liberty.
2917 (gencode.o, getopt.o, getopt1.o): New targets.
2918 * gencode.c: Include <ctype.h> and "ansidecl.h".
2919 (AND): Undefine after including "ansidecl.h".
2920 (ULONG_MAX): Define if not defined.
2921 (OP_*): Don't define macros; now defined in opcode/mips.h.
2922 (main): Call my_strtoul rather than strtoul.
2923 (my_strtoul): New static function.
2925 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2927 * gencode.c (process_instructions): Generate word64 and uword64
2928 instead of `long long' and `unsigned long long' data types.
2929 * interp.c: #include sysdep.h to get signals, and define default
2931 * (Convert): Work around for Visual-C++ compiler bug with type
2933 * support.h: Make things compile under Visual-C++ by using
2934 __int64 instead of `long long'. Change many refs to long long
2935 into word64/uword64 typedefs.
2937 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2939 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2940 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2942 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2943 (AC_PROG_INSTALL): Added.
2944 (AC_PROG_CC): Moved to before configure.host call.
2945 * configure: Rebuilt.
2947 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2949 * configure.in: Define @SIMCONF@ depending on mips target.
2950 * configure: Rebuild.
2951 * Makefile.in (run): Add @SIMCONF@ to control simulator
2953 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2954 * interp.c: Remove some debugging, provide more detailed error
2955 messages, update memory accesses to use LOADDRMASK.
2957 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2959 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2960 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2962 * configure: Rebuild.
2963 * config.in: New file, generated by autoheader.
2964 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2965 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2966 HAVE_ANINT and HAVE_AINT, as appropriate.
2967 * Makefile.in (run): Use @LIBS@ rather than -lm.
2968 (interp.o): Depend upon config.h.
2969 (Makefile): Just rebuild Makefile.
2970 (clean): Remove stamp-h.
2971 (mostlyclean): Make the same as clean, not as distclean.
2972 (config.h, stamp-h): New targets.
2974 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2976 * interp.c (ColdReset): Fix boolean test. Make all simulator
2979 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2981 * interp.c (xfer_direct_word, xfer_direct_long,
2982 swap_direct_word, swap_direct_long, xfer_big_word,
2983 xfer_big_long, xfer_little_word, xfer_little_long,
2984 swap_word,swap_long): Added.
2985 * interp.c (ColdReset): Provide function indirection to
2986 host<->simulated_target transfer routines.
2987 * interp.c (sim_store_register, sim_fetch_register): Updated to
2988 make use of indirected transfer routines.
2990 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2992 * gencode.c (process_instructions): Ensure FP ABS instruction
2994 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2995 system call support.
2997 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2999 * interp.c (sim_do_command): Complain if callback structure not
3002 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3004 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3005 support for Sun hosts.
3006 * Makefile.in (gencode): Ensure the host compiler and libraries
3007 used for cross-hosted build.
3009 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3011 * interp.c, gencode.c: Some more (TODO) tidying.
3013 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3015 * gencode.c, interp.c: Replaced explicit long long references with
3016 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3017 * support.h (SET64LO, SET64HI): Macros added.
3019 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3021 * configure: Regenerate with autoconf 2.7.
3023 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3025 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3026 * support.h: Remove superfluous "1" from #if.
3027 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3029 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3031 * interp.c (StoreFPR): Control UndefinedResult() call on
3032 WARN_RESULT manifest.
3034 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3036 * gencode.c: Tidied instruction decoding, and added FP instruction
3039 * interp.c: Added dineroIII, and BSD profiling support. Also
3040 run-time FP handling.
3042 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3044 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3045 gencode.c, interp.c, support.h: created.