sim/mips/ChangeLog

   1 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
   4         * configure: Regenerate.
   5
   6 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
   7
   8         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
   9         * mips.igen: Remove all invocations of check_branch_bug and
  10         mark_branch_bug.
  11
  12 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
  13
  14         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
  15
  16 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
  17
  18         * mips.igen (do_load_double, do_store_double): New functions.
  19         (LDC1, SDC1): Rename to...
  20         (LDC1b, SDC1b): respectively.
  21         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
  22
  23 2002-07-29  Michael Snyder  <msnyder@redhat.com>
  24
  25         * cp1.c (fp_recip2): Modify initialization expression so that
  26         GCC will recognize it as constant.
  27
  28 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
  29
  30         * mdmx.c (SD_): Delete.
  31         (Unpredictable): Re-define, for now, to directly invoke
  32         unpredictable_action().
  33         (mdmx_acc_op): Fix error in .ob immediate handling.
  34
  35 2002-06-18  Andrew Cagney  <cagney@redhat.com>
  36
  37         * interp.c (sim_firmware_command): Initialize `address'.
  38
  39 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
  40
  41         * configure: Regenerated to track ../common/aclocal.m4 changes.
  42
  43 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
  44             Ed Satterthwaite  <ehs@broadcom.com>
  45
  46         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
  47         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
  48         * mips.igen: Include mips3d.igen.
  49         (mips3d): New model name for MIPS-3D ASE instructions.
  50         (CVT.W.fmt): Don't use this instruction for word (source) format
  51         instructions.
  52         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
  53         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
  54         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
  55         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
  56         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
  57         (RSquareRoot1, RSquareRoot2): New macros.
  58         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
  59         (fp_rsqrt2): New functions.
  60         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
  61         * configure: Regenerate.
  62
  63 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
  64             Ed Satterthwaite  <ehs@broadcom.com>
  65
  66         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
  67         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
  68         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
  69         (convert): Note that this function is not used for paired-single
  70         format conversions.
  71         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
  72         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
  73         (check_fmt_p): Enable paired-single support.
  74         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
  75         (PUU.PS): New instructions.
  76         (CVT.S.fmt): Don't use this instruction for paired-single format
  77         destinations.
  78         * sim-main.h (FP_formats): New value 'fmt_ps.'
  79         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
  80         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
  81
  82 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  83
  84         * mips.igen: Fix formatting of function calls in
  85         many FP operations.
  86
  87 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  88
  89         * mips.igen (MOVN, MOVZ): Trace result.
  90         (TNEI): Print "tnei" as the opcode name in traces.
  91         (CEIL.W): Add disassembly string for traces.
  92         (RSQRT.fmt): Make location of disassembly string consistent
  93         with other instructions.
  94
  95 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
  96
  97         * mips.igen (X): Delete unused function.
  98
  99 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 100
 101         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 102
 103 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 104             Ed Satterthwaite  <ehs@broadcom.com>
 105
 106         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 107         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 108         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 109         (fp_nmsub): New prototypes.
 110         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 111         (NegMultiplySub): New defines.
 112         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 113         (MADD.D, MADD.S): Replace with...
 114         (MADD.fmt): New instruction.
 115         (MSUB.D, MSUB.S): Replace with...
 116         (MSUB.fmt): New instruction.
 117         (NMADD.D, NMADD.S): Replace with...
 118         (NMADD.fmt): New instruction.
 119         (NMSUB.D, MSUB.S): Replace with...
 120         (NMSUB.fmt): New instruction.
 121
 122 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 123             Ed Satterthwaite  <ehs@broadcom.com>
 124
 125         * cp1.c: Fix more comment spelling and formatting.
 126         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 127         (denorm_mode): New function.
 128         (fpu_unary, fpu_binary): Round results after operation, collect
 129         status from rounding operations, and update the FCSR.
 130         (convert): Collect status from integer conversions and rounding
 131         operations, and update the FCSR.  Adjust NaN values that result
 132         from conversions.  Convert to use sim_io_eprintf rather than
 133         fprintf, and remove some debugging code.
 134         * cp1.h (fenr_FS): New define.
 135
 136 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 137
 138         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 139         rounding mode to sim FP rounding mode flag conversion code into...
 140         (rounding_mode): New function.
 141
 142 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 143
 144         * cp1.c: Clean up formatting of a few comments.
 145         (value_fpr): Reformat switch statement.
 146
 147 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 148             Ed Satterthwaite  <ehs@broadcom.com>
 149
 150         * cp1.h: New file.
 151         * sim-main.h: Include cp1.h.
 152         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 153         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 154         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 155         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 156         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 157         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 158         * cp1.c: Don't include sim-fpu.h; already included by
 159         sim-main.h.  Clean up formatting of some comments.
 160         (NaN, Equal, Less): Remove.
 161         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 162         (fp_cmp): New functions.
 163         * mips.igen (do_c_cond_fmt): Remove.
 164         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 165         Compare.  Add result tracing.
 166         (CxC1): Remove, replace with...
 167         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 168         (DMxC1): Remove, replace with...
 169         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 170         (MxC1): Remove, replace with...
 171         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 172
 173 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 174
 175         * sim-main.h (FGRIDX): Remove, replace all uses with...
 176         (FGR_BASE): New macro.
 177         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 178         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 179         (NR_FGR, FGR): Likewise.
 180         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 181         * mips.igen: Likewise.
 182
 183 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 184
 185         * cp1.c: Add an FSF Copyright notice to this file.
 186
 187 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 188             Ed Satterthwaite  <ehs@broadcom.com>
 189
 190         * cp1.c (Infinity): Remove.
 191         * sim-main.h (Infinity): Likewise.
 192
 193         * cp1.c (fp_unary, fp_binary): New functions.
 194         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 195         (fp_sqrt): New functions, implemented in terms of the above.
 196         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 197         (Recip, SquareRoot): Remove (replaced by functions above).
 198         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 199         (fp_recip, fp_sqrt): New prototypes.
 200         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 201         (Recip, SquareRoot): Replace prototypes with #defines which
 202         invoke the functions above.
 203
 204 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 205
 206         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 207         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 208         file, remove PARAMS from prototypes.
 209         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 210         simulator state arguments.
 211         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 212         pass simulator state arguments.
 213         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 214         (store_fpr, convert): Remove 'sd' argument.
 215         (value_fpr): Likewise.  Convert to use 'SD' instead.
 216
 217 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 218
 219         * cp1.c (Min, Max): Remove #if 0'd functions.
 220         * sim-main.h (Min, Max): Remove.
 221
 222 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 223
 224         * cp1.c: fix formatting of switch case and default labels.
 225         * interp.c: Likewise.
 226         * sim-main.c: Likewise.
 227
 228 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 229
 230         * cp1.c: Clean up comments which describe FP formats.
 231          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 232
 233 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 234             Ed Satterthwaite  <ehs@broadcom.com>
 235
 236         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 237         Broadcom SiByte SB-1 processor configurations.
 238         * configure: Regenerate.
 239         * sb1.igen: New file.
 240         * mips.igen: Include sb1.igen.
 241         (sb1): New model.
 242         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 243         * mdmx.igen: Add "sb1" model to all appropriate functions and
 244         instructions.
 245         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 246         (ob_func, ob_acc): Reference the above.
 247         (qh_acc): Adjust to keep the same size as ob_acc.
 248         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 249         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 250
 251 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 252
 253         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 254
 255 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 256             Ed Satterthwaite  <ehs@broadcom.com>
 257
 258         * mips.igen (mdmx): New (pseudo-)model.
 259         * mdmx.c, mdmx.igen: New files.
 260         * Makefile.in (SIM_OBJS): Add mdmx.o.
 261         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 262         New typedefs.
 263         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 264         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 265         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 266         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 267         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 268         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 269         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 270         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 271         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 272         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 273         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 274         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 275         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 276         (qh_fmtsel): New macros.
 277         (_sim_cpu): New member "acc".
 278         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 279         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 280
 281 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 282
 283         * interp.c: Use 'deprecated' rather than 'depreciated.'
 284         * sim-main.h: Likewise.
 285
 286 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 287
 288         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 289         which wouldn't compile anyway.
 290         * sim-main.h (unpredictable_action): New function prototype.
 291         (Unpredictable): Define to call igen function unpredictable().
 292         (NotWordValue): New macro to call igen function not_word_value().
 293         (UndefinedResult): Remove.
 294         * interp.c (undefined_result): Remove.
 295         (unpredictable_action): New function.
 296         * mips.igen (not_word_value, unpredictable): New functions.
 297         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 298         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 299         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 300         NotWordValue() to check for unpredictable inputs, then
 301         Unpredictable() to handle them.
 302
 303 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 304
 305         * mips.igen: Fix formatting of calls to Unpredictable().
 306
 307 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 308
 309         * interp.c (sim_open): Revert previous change.
 310
 311 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 312
 313         * interp.c (sim_open): Disable chunk of code that wrote code in
 314         vector table entries.
 315
 316 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 317
 318         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 319         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 320         unused definitions.
 321
 322 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 323
 324         * cp1.c: Fix many formatting issues.
 325
 326 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 327
 328         * cp1.c (fpu_format_name): New function to replace...
 329         (DOFMT): This.  Delete, and update all callers.
 330         (fpu_rounding_mode_name): New function to replace...
 331         (RMMODE): This.  Delete, and update all callers.
 332
 333 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 334
 335         * interp.c: Move FPU support routines from here to...
 336         * cp1.c: Here.  New file.
 337         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 338         (cp1.o): New target.
 339
 340 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 341
 342         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 343         * mips.igen (mips32, mips64): New models, add to all instructions
 344         and functions as appropriate.
 345         (loadstore_ea, check_u64): New variant for model mips64.
 346         (check_fmt_p): New variant for models mipsV and mips64, remove
 347         mipsV model marking fro other variant.
 348         (SLL) Rename to...
 349         (SLLa) this.
 350         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 351         for mips32 and mips64.
 352         (DCLO, DCLZ): New instructions for mips64.
 353
 354 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 355
 356         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 357         immediate or code as a hex value with the "%#lx" format.
 358         (ANDI): Likewise, and fix printed instruction name.
 359
 360 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 361
 362         * sim-main.h (UndefinedResult, Unpredictable): New macros
 363         which currently do nothing.
 364
 365 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 366
 367         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 368         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 369         (status_CU3): New definitions.
 370
 371         * sim-main.h (ExceptionCause): Add new values for MIPS32
 372         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 373         for DebugBreakPoint and NMIReset to note their status in
 374         MIPS32 and MIPS64.
 375         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 376         (SignalExceptionCacheErr): New exception macros.
 377
 378 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 379
 380         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 381         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 382         is always enabled.
 383         (SignalExceptionCoProcessorUnusable): Take as argument the
 384         unusable coprocessor number.
 385
 386 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 387
 388         * mips.igen: Fix formatting of all SignalException calls.
 389
 390 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 391
 392         * sim-main.h (SIGNEXTEND): Remove.
 393
 394 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 395
 396         * mips.igen: Remove gencode comment from top of file, fix
 397         spelling in another comment.
 398
 399 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 400
 401         * mips.igen (check_fmt, check_fmt_p): New functions to check
 402         whether specific floating point formats are usable.
 403         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 404         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 405         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 406         Use the new functions.
 407         (do_c_cond_fmt): Remove format checks...
 408         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 409
 410 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 411
 412         * mips.igen: Fix formatting of check_fpu calls.
 413
 414 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 415
 416         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 417
 418 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 419
 420         * mips.igen: Remove whitespace at end of lines.
 421
 422 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 423
 424         * mips.igen (loadstore_ea): New function to do effective
 425         address calculations.
 426         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 427         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 428         CACHE): Use loadstore_ea to do effective address computations.
 429
 430 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 431
 432         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 433         * mips.igen (LL, CxC1, MxC1): Likewise.
 434
 435 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 436
 437         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 438         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 439         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 440         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 441         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 442         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 443         Don't split opcode fields by hand, use the opcode field values
 444         provided by igen.
 445
 446 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 447
 448         * mips.igen (do_divu): Fix spacing.
 449
 450         * mips.igen (do_dsllv): Move to be right before DSLLV,
 451         to match the rest of the do_<shift> functions.
 452
 453 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 454
 455         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 456         DSRL32, do_dsrlv): Trace inputs and results.
 457
 458 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 459
 460         * mips.igen (CACHE): Provide instruction-printing string.
 461
 462         * interp.c (signal_exception): Comment tokens after #endif.
 463
 464 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 465
 466         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 467         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 468         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 469         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 470         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 471         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 472         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 473         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 474
 475 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 476
 477         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 478         instruction-printing string.
 479         (LWU): Use '64' as the filter flag.
 480
 481 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 482
 483         * mips.igen (SDXC1): Fix instruction-printing string.
 484
 485 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 486
 487         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 488         filter flags "32,f".
 489
 490 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 491
 492         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 493         as the filter flag.
 494
 495 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 496
 497         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 498         add a comma) so that it more closely match the MIPS ISA
 499         documentation opcode partitioning.
 500         (PREF): Put useful names on opcode fields, and include
 501         instruction-printing string.
 502
 503 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 504
 505         * mips.igen (check_u64): New function which in the future will
 506         check whether 64-bit instructions are usable and signal an
 507         exception if not.  Currently a no-op.
 508         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 509         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 510         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 511         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 512
 513         * mips.igen (check_fpu): New function which in the future will
 514         check whether FPU instructions are usable and signal an exception
 515         if not.  Currently a no-op.
 516         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 517         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 518         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 519         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 520         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 521         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 522         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 523         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 524
 525 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 526
 527         * mips.igen (do_load_left, do_load_right): Move to be immediately
 528         following do_load.
 529         (do_store_left, do_store_right): Move to be immediately following
 530         do_store.
 531
 532 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 533
 534         * mips.igen (mipsV): New model name.  Also, add it to
 535         all instructions and functions where it is appropriate.
 536
 537 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 538
 539         * mips.igen: For all functions and instructions, list model
 540         names that support that instruction one per line.
 541
 542 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 543
 544         * mips.igen: Add some additional comments about supported
 545         models, and about which instructions go where.
 546         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 547         order as is used in the rest of the file.
 548
 549 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 550
 551         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 552         indicating that ALU32_END or ALU64_END are there to check
 553         for overflow.
 554         (DADD): Likewise, but also remove previous comment about
 555         overflow checking.
 556
 557 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 558
 559         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 560         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 561         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 562         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 563         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 564         fields (i.e., add and move commas) so that they more closely
 565         match the MIPS ISA documentation opcode partitioning.
 566
 567 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 568
 569         * mips.igen (ADDI): Print immediate value.
 570         (BREAK): Print code.
 571         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 572         (SLL): Print "nop" specially, and don't run the code
 573         that does the shift for the "nop" case.
 574
 575 2001-11-17  Fred Fish  <fnf@redhat.com>
 576
 577         * sim-main.h (float_operation): Move enum declaration outside
 578         of _sim_cpu struct declaration.
 579
 580 2001-04-12  Jim Blandy  <jimb@redhat.com>
 581
 582         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 583         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 584         set of the FCSR.
 585         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 586         PENDING_FILL, and you can get the intended effect gracefully by
 587         calling PENDING_SCHED directly.
 588
 589 2001-02-23  Ben Elliston  <bje@redhat.com>
 590
 591         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 592         already defined elsewhere.
 593
 594 2001-02-19  Ben Elliston  <bje@redhat.com>
 595
 596         * sim-main.h (sim_monitor): Return an int.
 597         * interp.c (sim_monitor): Add return values.
 598         (signal_exception): Handle error conditions from sim_monitor.
 599
 600 2001-02-08  Ben Elliston  <bje@redhat.com>
 601
 602         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 603         (store_memory): Likewise, pass cia to sim_core_write*.
 604
 605 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 606
 607         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 608         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 609
 610 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 611
 612         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 613         * Makefile.in: Don't delete *.igen when cleaning directory.
 614
 615 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 616
 617         * m16.igen (break): Call SignalException not sim_engine_halt.
 618
 619 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 620
 621         From Jason Eckhardt:
 622         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 623
 624 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 625
 626         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 627
 628 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 629
 630         * mips.igen (do_dmultx): Fix typo.
 631
 632 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 633
 634         * configure: Regenerated to track ../common/aclocal.m4 changes.
 635
 636 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 637
 638         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 639
 640 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 641
 642         * sim-main.h (GPR_CLEAR): Define macro.
 643
 644 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 645
 646         * interp.c (decode_coproc): Output long using %lx and not %s.
 647
 648 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 649
 650         * interp.c (sim_open): Sort & extend dummy memory regions for
 651         --board=jmr3904 for eCos.
 652
 653 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 654
 655         * configure: Regenerated.
 656
 657 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 658
 659         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 660         calls, conditional on the simulator being in verbose mode.
 661
 662 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 663
 664         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 665         cache don't get ReservedInstruction traps.
 666
 667 1999-11-29  Mark Salter  <msalter@cygnus.com>
 668
 669         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 670         to clear status bits in sdisr register. This is how the hardware works.
 671
 672         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 673         being used by cygmon.
 674
 675 1999-11-11  Andrew Haley  <aph@cygnus.com>
 676
 677         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 678         instructions.
 679
 680 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 681
 682         * mips.igen (MULT): Correct previous mis-applied patch.
 683
 684 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 685
 686         * mips.igen (delayslot32): Handle sequence like
 687         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 688         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 689         (MULT): Actually pass the third register...
 690
 691 1999-09-03  Mark Salter  <msalter@cygnus.com>
 692
 693         * interp.c (sim_open): Added more memory aliases for additional
 694         hardware being touched by cygmon on jmr3904 board.
 695
 696 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 697
 698         * configure: Regenerated to track ../common/aclocal.m4 changes.
 699
 700 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 701
 702         * interp.c (sim_store_register): Handle case where client - GDB -
 703         specifies that a 4 byte register is 8 bytes in size.
 704         (sim_fetch_register): Ditto.
 705
 706 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 707
 708         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 709         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 710         (idt_monitor_base): Base address for IDT monitor traps.
 711         (pmon_monitor_base): Ditto for PMON.
 712         (lsipmon_monitor_base): Ditto for LSI PMON.
 713         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 714         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 715         (sim_firmware_command): New function.
 716         (mips_option_handler): Call it for OPTION_FIRMWARE.
 717         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 718         option was given, add no monitor by default.  Add BREAK hooks only if
 719         monitors are also there.
 720
 721 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 722
 723         * interp.c (sim_monitor): Flush output before reading input.
 724
 725 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 726
 727         * tconfig.in (SIM_HANDLES_LMA): Always define.
 728
 729 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 730
 731         From Mark Salter <msalter@cygnus.com>:
 732         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 733         (sim_open): Add setup for BSP board.
 734
 735 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 736
 737         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 738         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 739         them as unimplemented.
 740
 741 1999-05-08  Felix Lee  <flee@cygnus.com>
 742
 743         * configure: Regenerated to track ../common/aclocal.m4 changes.
 744
 745 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 746
 747         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 748
 749 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 750
 751         * configure.in: Any mips64vr5*-*-* target should have
 752         -DTARGET_ENABLE_FR=1.
 753         (default_endian): Any mips64vr*el-*-* target should default to
 754         LITTLE_ENDIAN.
 755         * configure: Re-generate.
 756
 757 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 758
 759         * mips.igen (ldl): Extend from _16_, not 32.
 760
 761 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 762
 763         * interp.c (sim_store_register): Force registers written to by GDB
 764         into an un-interpreted state.
 765
 766 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 767
 768         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 769         CPU, start periodic background I/O polls.
 770         (tx3904sio_poll): New function: periodic I/O poller.
 771
 772 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 773
 774         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 775
 776 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 777
 778         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 779         case statement.
 780
 781 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 782
 783         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 784         (load_word): Call SIM_CORE_SIGNAL hook on error.
 785         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 786         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 787         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 788         * sim-main.h (COP0_BADVADDR): Define.
 789         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 790         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 791         (_sim_cpu): Add exc_* fields to store register value snapshots.
 792         * mips.igen (*): Replace memory-related SignalException* calls
 793         with references to SIM_CORE_SIGNAL hook.
 794
 795         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 796         fix.
 797         * sim-main.c (*): Minor warning cleanups.
 798
 799 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 800
 801         * m16.igen (DADDIU5): Correct type-o.
 802
 803 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 804
 805         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 806         variables.
 807
 808 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 809
 810         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 811         to include path.
 812         (interp.o): Add dependency on itable.h
 813         (oengine.c, gencode): Delete remaining references.
 814         (BUILT_SRC_FROM_GEN): Clean up.
 815
 816 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 817
 818         * vr4run.c: New.
 819         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 820         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 821         tmp-run-hack) : New.
 822         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 823         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 824         Drop the "64" qualifier to get the HACK generator working.
 825         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 826         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 827         qualifier to get the hack generator working.
 828         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 829         (DSLL): Use do_dsll.
 830         (DSLLV): Use do_dsllv.
 831         (DSRA): Use do_dsra.
 832         (DSRL): Use do_dsrl.
 833         (DSRLV): Use do_dsrlv.
 834         (BC1): Move *vr4100 to get the HACK generator working.
 835         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 836         get the HACK generator working.
 837         (MACC) Rename to get the HACK generator working.
 838         (DMACC,MACCS,DMACCS): Add the 64.
 839
 840 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 841
 842         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 843         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 844
 845 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 846
 847     * mips/interp.c (DEBUG): Cleanups.
 848
 849 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 850
 851         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 852         (tx3904sio_tickle): fflush after a stdout character output.
 853
 854 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 855
 856         * interp.c (sim_close): Uninstall modules.
 857
 858 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 859
 860         * sim-main.h, interp.c (sim_monitor): Change to global
 861         function.
 862
 863 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 864
 865         * configure.in (vr4100): Only include vr4100 instructions in
 866         simulator.
 867         * configure: Re-generate.
 868         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 869
 870 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 871
 872         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 873         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 874         true alternative.
 875
 876         * configure.in (sim_default_gen, sim_use_gen): Replace with
 877         sim_gen.
 878         (--enable-sim-igen): Delete config option. Always using IGEN.
 879         * configure: Re-generate.
 880
 881         * Makefile.in (gencode): Kill, kill, kill.
 882         * gencode.c: Ditto.
 883
 884 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 885
 886         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 887         bit mips16 igen simulator.
 888         * configure: Re-generate.
 889
 890         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 891         as part of vr4100 ISA.
 892         * vr.igen: Mark all instructions as 64 bit only.
 893
 894 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 895
 896         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 897         Pacify GCC.
 898
 899 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 900
 901         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 902         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 903         * configure: Re-generate.
 904
 905         * m16.igen (BREAK): Define breakpoint instruction.
 906         (JALX32): Mark instruction as mips16 and not r3900.
 907         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 908
 909         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 910
 911 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 912
 913         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 914         insn as a debug breakpoint.
 915
 916         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 917         pending.slot_size.
 918         (PENDING_SCHED): Clean up trace statement.
 919         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 920         (PENDING_FILL): Delay write by only one cycle.
 921         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 922
 923         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 924         of pending writes.
 925         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 926         32 & 64.
 927         (pending_tick): Move incrementing of index to FOR statement.
 928         (pending_tick): Only update PENDING_OUT after a write has occured.
 929
 930         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 931         build simulator.
 932         * configure: Re-generate.
 933
 934         * interp.c (sim_engine_run OLD): Delete explicit call to
 935         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 936
 937 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 938
 939         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 940         interrupt level number to match changed SignalExceptionInterrupt
 941         macro.
 942
 943 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 944
 945         * interp.c: #include "itable.h" if WITH_IGEN.
 946         (get_insn_name): New function.
 947         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 948         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 949
 950 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 951
 952         * configure: Rebuilt to inhale new common/aclocal.m4.
 953
 954 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 955
 956         * dv-tx3904sio.c: Include sim-assert.h.
 957
 958 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 959
 960         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 961         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 962         Reorganize target-specific sim-hardware checks.
 963         * configure: rebuilt.
 964         * interp.c (sim_open): For tx39 target boards, set
 965         OPERATING_ENVIRONMENT, add tx3904sio devices.
 966         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 967         ROM executables.  Install dv-sockser into sim-modules list.
 968
 969         * dv-tx3904irc.c: Compiler warning clean-up.
 970         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 971         frequent hw-trace messages.
 972
 973 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 974
 975         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 976
 977 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 978
 979         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 980
 981         * vr.igen: New file.
 982         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 983         * mips.igen: Define vr4100 model. Include vr.igen.
 984 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 985
 986         * mips.igen (check_mf_hilo): Correct check.
 987
 988 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 989
 990         * sim-main.h (interrupt_event): Add prototype.
 991
 992         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 993         register_ptr, register_value.
 994         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 995
 996         * sim-main.h (tracefh): Make extern.
 997
 998 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 999
1000         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1001         Reduce unnecessarily high timer event frequency.
1002         * dv-tx3904cpu.c: Ditto for interrupt event.
1003
1004 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1005
1006         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1007         to allay warnings.
1008         (interrupt_event): Made non-static.
1009
1010         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1011         interchange of configuration values for external vs. internal
1012         clock dividers.
1013
1014 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1015
1016         * mips.igen (BREAK): Moved code to here for
1017         simulator-reserved break instructions.
1018         * gencode.c (build_instruction): Ditto.
1019         * interp.c (signal_exception): Code moved from here.  Non-
1020         reserved instructions now use exception vector, rather
1021         than halting sim.
1022         * sim-main.h: Moved magic constants to here.
1023
1024 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1025
1026         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1027         register upon non-zero interrupt event level, clear upon zero
1028         event value.
1029         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1030         by passing zero event value.
1031         (*_io_{read,write}_buffer): Endianness fixes.
1032         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1033         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1034
1035         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1036         serial I/O and timer module at base address 0xFFFF0000.
1037
1038 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1039
1040         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1041         and BigEndianCPU.
1042
1043 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1044
1045         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1046         parts.
1047         * configure: Update.
1048
1049 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1050
1051         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1052         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1053         * configure.in: Include tx3904tmr in hw_device list.
1054         * configure: Rebuilt.
1055         * interp.c (sim_open): Instantiate three timer instances.
1056         Fix address typo of tx3904irc instance.
1057
1058 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1059
1060         * interp.c (signal_exception): SystemCall exception now uses
1061         the exception vector.
1062
1063 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1064
1065         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1066         to allay warnings.
1067
1068 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1069
1070         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1071
1072 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1073
1074         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1075
1076         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1077         sim-main.h. Declare a struct hw_descriptor instead of struct
1078         hw_device_descriptor.
1079
1080 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1081
1082         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1083         right bits and then re-align left hand bytes to correct byte
1084         lanes.  Fix incorrect computation in do_store_left when loading
1085         bytes from second word.
1086
1087 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1088
1089         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1090         * interp.c (sim_open): Only create a device tree when HW is
1091         enabled.
1092
1093         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1094         * interp.c (signal_exception): Ditto.
1095
1096 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1097
1098         * gencode.c: Mark BEGEZALL as LIKELY.
1099
1100 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1101
1102         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1103         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1104
1105 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1106
1107         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1108         modules.  Recognize TX39 target with "mips*tx39" pattern.
1109         * configure: Rebuilt.
1110         * sim-main.h (*): Added many macros defining bits in
1111         TX39 control registers.
1112         (SignalInterrupt): Send actual PC instead of NULL.
1113         (SignalNMIReset): New exception type.
1114         * interp.c (board): New variable for future use to identify
1115         a particular board being simulated.
1116         (mips_option_handler,mips_options): Added "--board" option.
1117         (interrupt_event): Send actual PC.
1118         (sim_open): Make memory layout conditional on board setting.
1119         (signal_exception): Initial implementation of hardware interrupt
1120         handling.  Accept another break instruction variant for simulator
1121         exit.
1122         (decode_coproc): Implement RFE instruction for TX39.
1123         (mips.igen): Decode RFE instruction as such.
1124         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1125         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1126         bbegin to implement memory map.
1127         * dv-tx3904cpu.c: New file.
1128         * dv-tx3904irc.c: New file.
1129
1130 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1131
1132         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1133
1134 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1135
1136         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1137         with calls to check_div_hilo.
1138
1139 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1140
1141         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1142         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1143         Add special r3900 version of do_mult_hilo.
1144         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1145         with calls to check_mult_hilo.
1146         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1147         with calls to check_div_hilo.
1148
1149 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1150
1151         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1152         Document a replacement.
1153
1154 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1155
1156         * interp.c (sim_monitor): Make mon_printf work.
1157
1158 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1159
1160         * sim-main.h (INSN_NAME): New arg `cpu'.
1161
1162 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1163
1164         * configure: Regenerated to track ../common/aclocal.m4 changes.
1165
1166 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1167
1168         * configure: Regenerated to track ../common/aclocal.m4 changes.
1169         * config.in: Ditto.
1170
1171 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1172
1173         * acconfig.h: New file.
1174         * configure.in: Reverted change of Apr 24; use sinclude again.
1175
1176 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1177
1178         * configure: Regenerated to track ../common/aclocal.m4 changes.
1179         * config.in: Ditto.
1180
1181 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1182
1183         * configure.in: Don't call sinclude.
1184
1185 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1186
1187         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1188
1189 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1190
1191         * mips.igen (ERET): Implement.
1192
1193         * interp.c (decode_coproc): Return sign-extended EPC.
1194
1195         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1196
1197         * interp.c (signal_exception): Do not ignore Trap.
1198         (signal_exception): On TRAP, restart at exception address.
1199         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1200         (signal_exception): Update.
1201         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1202         so that TRAP instructions are caught.
1203
1204 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1205
1206         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1207         contains HI/LO access history.
1208         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1209         (HIACCESS, LOACCESS): Delete, replace with
1210         (HIHISTORY, LOHISTORY): New macros.
1211         (CHECKHILO): Delete all, moved to mips.igen
1212
1213         * gencode.c (build_instruction): Do not generate checks for
1214         correct HI/LO register usage.
1215
1216         * interp.c (old_engine_run): Delete checks for correct HI/LO
1217         register usage.
1218
1219         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1220         check_mf_cycles): New functions.
1221         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1222         do_divu, domultx, do_mult, do_multu): Use.
1223
1224         * tx.igen ("madd", "maddu"): Use.
1225
1226 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1227
1228         * mips.igen (DSRAV): Use function do_dsrav.
1229         (SRAV): Use new function do_srav.
1230
1231         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1232         (B): Sign extend 11 bit immediate.
1233         (EXT-B*): Shift 16 bit immediate left by 1.
1234         (ADDIU*): Don't sign extend immediate value.
1235
1236 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1237
1238         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1239
1240         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1241         functions.
1242
1243         * mips.igen (delayslot32, nullify_next_insn): New functions.
1244         (m16.igen): Always include.
1245         (do_*): Add more tracing.
1246
1247         * m16.igen (delayslot16): Add NIA argument, could be called by a
1248         32 bit MIPS16 instruction.
1249
1250         * interp.c (ifetch16): Move function from here.
1251         * sim-main.c (ifetch16): To here.
1252
1253         * sim-main.c (ifetch16, ifetch32): Update to match current
1254         implementations of LH, LW.
1255         (signal_exception): Don't print out incorrect hex value of illegal
1256         instruction.
1257
1258 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1259
1260         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1261         instruction.
1262
1263         * m16.igen: Implement MIPS16 instructions.
1264
1265         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1266         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1267         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1268         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1269         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1270         bodies of corresponding code from 32 bit insn to these.  Also used
1271         by MIPS16 versions of functions.
1272
1273         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1274         (IMEM16): Drop NR argument from macro.
1275
1276 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1277
1278         * Makefile.in (SIM_OBJS): Add sim-main.o.
1279
1280         * sim-main.h (address_translation, load_memory, store_memory,
1281         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1282         as INLINE_SIM_MAIN.
1283         (pr_addr, pr_uword64): Declare.
1284         (sim-main.c): Include when H_REVEALS_MODULE_P.
1285
1286         * interp.c (address_translation, load_memory, store_memory,
1287         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1288         from here.
1289         * sim-main.c: To here. Fix compilation problems.
1290
1291         * configure.in: Enable inlining.
1292         * configure: Re-config.
1293
1294 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1295
1296         * configure: Regenerated to track ../common/aclocal.m4 changes.
1297
1298 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1299
1300         * mips.igen: Include tx.igen.
1301         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1302         * tx.igen: New file, contains MADD and MADDU.
1303
1304         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1305         the hardwired constant `7'.
1306         (store_memory): Ditto.
1307         (LOADDRMASK): Move definition to sim-main.h.
1308
1309         mips.igen (MTC0): Enable for r3900.
1310         (ADDU): Add trace.
1311
1312         mips.igen (do_load_byte): Delete.
1313         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1314         do_store_right): New functions.
1315         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1316
1317         configure.in: Let the tx39 use igen again.
1318         configure: Update.
1319
1320 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1321
1322         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1323         not an address sized quantity.  Return zero for cache sizes.
1324
1325 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1326
1327         * mips.igen (r3900): r3900 does not support 64 bit integer
1328         operations.
1329
1330 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1331
1332         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1333         than igen one.
1334         * configure : Rebuild.
1335
1336 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1337
1338         * configure: Regenerated to track ../common/aclocal.m4 changes.
1339
1340 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1341
1342         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1343
1344 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1345
1346         * configure: Regenerated to track ../common/aclocal.m4 changes.
1347         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1348
1349 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1350
1351         * configure: Regenerated to track ../common/aclocal.m4 changes.
1352
1353 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1354
1355         * interp.c (Max, Min): Comment out functions. Not yet used.
1356
1357 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1358
1359         * configure: Regenerated to track ../common/aclocal.m4 changes.
1360
1361 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1362
1363         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1364         configurable settings for stand-alone simulator.
1365
1366         * configure.in: Added X11 search, just in case.
1367
1368         * configure: Regenerated.
1369
1370 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1371
1372         * interp.c (sim_write, sim_read, load_memory, store_memory):
1373         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1374
1375 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1376
1377         * sim-main.h (GETFCC): Return an unsigned value.
1378
1379 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1380
1381         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1382         (DADD): Result destination is RD not RT.
1383
1384 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1385
1386         * sim-main.h (HIACCESS, LOACCESS): Always define.
1387
1388         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1389
1390         * interp.c (sim_info): Delete.
1391
1392 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1393
1394         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1395         (mips_option_handler): New argument `cpu'.
1396         (sim_open): Update call to sim_add_option_table.
1397
1398 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1399
1400         * mips.igen (CxC1): Add tracing.
1401
1402 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1403
1404         * sim-main.h (Max, Min): Declare.
1405
1406         * interp.c (Max, Min): New functions.
1407
1408         * mips.igen (BC1): Add tracing.
1409
1410 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1411
1412         * interp.c Added memory map for stack in vr4100
1413
1414 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1415
1416         * interp.c (load_memory): Add missing "break"'s.
1417
1418 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1419
1420         * interp.c (sim_store_register, sim_fetch_register): Pass in
1421         length parameter.  Return -1.
1422
1423 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1424
1425         * interp.c: Added hardware init hook, fixed warnings.
1426
1427 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1428
1429         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1430
1431 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1432
1433         * interp.c (ifetch16): New function.
1434
1435         * sim-main.h (IMEM32): Rename IMEM.
1436         (IMEM16_IMMED): Define.
1437         (IMEM16): Define.
1438         (DELAY_SLOT): Update.
1439
1440         * m16run.c (sim_engine_run): New file.
1441
1442         * m16.igen: All instructions except LB.
1443         (LB): Call do_load_byte.
1444         * mips.igen (do_load_byte): New function.
1445         (LB): Call do_load_byte.
1446
1447         * mips.igen: Move spec for insn bit size and high bit from here.
1448         * Makefile.in (tmp-igen, tmp-m16): To here.
1449
1450         * m16.dc: New file, decode mips16 instructions.
1451
1452         * Makefile.in (SIM_NO_ALL): Define.
1453         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1454
1455 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1456
1457         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1458         point unit to 32 bit registers.
1459         * configure: Re-generate.
1460
1461 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1462
1463         * configure.in (sim_use_gen): Make IGEN the default simulator
1464         generator for generic 32 and 64 bit mips targets.
1465         * configure: Re-generate.
1466
1467 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1468
1469         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1470         bitsize.
1471
1472         * interp.c (sim_fetch_register, sim_store_register): Read/write
1473         FGR from correct location.
1474         (sim_open): Set size of FGR's according to
1475         WITH_TARGET_FLOATING_POINT_BITSIZE.
1476
1477         * sim-main.h (FGR): Store floating point registers in a separate
1478         array.
1479
1480 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1481
1482         * configure: Regenerated to track ../common/aclocal.m4 changes.
1483
1484 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1485
1486         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1487
1488         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1489
1490         * interp.c (pending_tick): New function.  Deliver pending writes.
1491
1492         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1493         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1494         it can handle mixed sized quantites and single bits.
1495
1496 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1497
1498         * interp.c (oengine.h): Do not include when building with IGEN.
1499         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1500         (sim_info): Ditto for PROCESSOR_64BIT.
1501         (sim_monitor): Replace ut_reg with unsigned_word.
1502         (*): Ditto for t_reg.
1503         (LOADDRMASK): Define.
1504         (sim_open): Remove defunct check that host FP is IEEE compliant,
1505         using software to emulate floating point.
1506         (value_fpr, ...): Always compile, was conditional on HASFPU.
1507
1508 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1509
1510         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1511         size.
1512
1513         * interp.c (SD, CPU): Define.
1514         (mips_option_handler): Set flags in each CPU.
1515         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1516         (sim_close): Do not clear STATE, deleted anyway.
1517         (sim_write, sim_read): Assume CPU zero's vm should be used for
1518         data transfers.
1519         (sim_create_inferior): Set the PC for all processors.
1520         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1521         argument.
1522         (mips16_entry): Pass correct nr of args to store_word, load_word.
1523         (ColdReset): Cold reset all cpu's.
1524         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1525         (sim_monitor, load_memory, store_memory, signal_exception): Use
1526         `CPU' instead of STATE_CPU.
1527
1528
1529         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1530         SD or CPU_.
1531
1532         * sim-main.h (signal_exception): Add sim_cpu arg.
1533         (SignalException*): Pass both SD and CPU to signal_exception.
1534         * interp.c (signal_exception): Update.
1535
1536         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1537         Ditto
1538         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1539         address_translation): Ditto
1540         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1541
1542 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1543
1544         * configure: Regenerated to track ../common/aclocal.m4 changes.
1545
1546 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1547
1548         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1549
1550         * mips.igen (model): Map processor names onto BFD name.
1551
1552         * sim-main.h (CPU_CIA): Delete.
1553         (SET_CIA, GET_CIA): Define
1554
1555 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1556
1557         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1558         regiser.
1559
1560         * configure.in (default_endian): Configure a big-endian simulator
1561         by default.
1562         * configure: Re-generate.
1563
1564 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1565
1566         * configure: Regenerated to track ../common/aclocal.m4 changes.
1567
1568 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1569
1570         * interp.c (sim_monitor): Handle Densan monitor outbyte
1571         and inbyte functions.
1572
1573 1997-12-29  Felix Lee  <flee@cygnus.com>
1574
1575         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1576
1577 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1578
1579         * Makefile.in (tmp-igen): Arrange for $zero to always be
1580         reset to zero after every instruction.
1581
1582 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1583
1584         * configure: Regenerated to track ../common/aclocal.m4 changes.
1585         * config.in: Ditto.
1586
1587 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1588
1589         * mips.igen (MSUB): Fix to work like MADD.
1590         * gencode.c (MSUB): Similarly.
1591
1592 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1593
1594         * configure: Regenerated to track ../common/aclocal.m4 changes.
1595
1596 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1597
1598         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1599
1600 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1601
1602         * sim-main.h (sim-fpu.h): Include.
1603
1604         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1605         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1606         using host independant sim_fpu module.
1607
1608 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1609
1610         * interp.c (signal_exception): Report internal errors with SIGABRT
1611         not SIGQUIT.
1612
1613         * sim-main.h (C0_CONFIG): New register.
1614         (signal.h): No longer include.
1615
1616         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1617
1618 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1619
1620         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1621
1622 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1623
1624         * mips.igen: Tag vr5000 instructions.
1625         (ANDI): Was missing mipsIV model, fix assembler syntax.
1626         (do_c_cond_fmt): New function.
1627         (C.cond.fmt): Handle mips I-III which do not support CC field
1628         separatly.
1629         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1630         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1631         in IV3.2 spec.
1632         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1633         vr5000 which saves LO in a GPR separatly.
1634
1635         * configure.in (enable-sim-igen): For vr5000, select vr5000
1636         specific instructions.
1637         * configure: Re-generate.
1638
1639 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1640
1641         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1642
1643         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1644         fmt_uninterpreted_64 bit cases to switch.  Convert to
1645         fmt_formatted,
1646
1647         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1648
1649         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1650         as specified in IV3.2 spec.
1651         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1652
1653 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1654
1655         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1656         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1657         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1658         PENDING_FILL versions of instructions.  Simplify.
1659         (X): New function.
1660         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1661         instructions.
1662         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1663         a signed value.
1664         (MTHI, MFHI): Disable code checking HI-LO.
1665
1666         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1667         global.
1668         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1669
1670 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1671
1672         * gencode.c (build_mips16_operands): Replace IPC with cia.
1673
1674         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1675         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1676         IPC to `cia'.
1677         (UndefinedResult): Replace function with macro/function
1678         combination.
1679         (sim_engine_run): Don't save PC in IPC.
1680
1681         * sim-main.h (IPC): Delete.
1682
1683
1684         * interp.c (signal_exception, store_word, load_word,
1685         address_translation, load_memory, store_memory, cache_op,
1686         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1687         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1688         current instruction address - cia - argument.
1689         (sim_read, sim_write): Call address_translation directly.
1690         (sim_engine_run): Rename variable vaddr to cia.
1691         (signal_exception): Pass cia to sim_monitor
1692
1693         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1694         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1695         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1696
1697         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1698         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1699         SIM_ASSERT.
1700
1701         * interp.c (signal_exception): Pass restart address to
1702         sim_engine_restart.
1703
1704         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1705         idecode.o): Add dependency.
1706
1707         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1708         Delete definitions
1709         (DELAY_SLOT): Update NIA not PC with branch address.
1710         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1711
1712         * mips.igen: Use CIA not PC in branch calculations.
1713         (illegal): Call SignalException.
1714         (BEQ, ADDIU): Fix assembler.
1715
1716 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1717
1718         * m16.igen (JALX): Was missing.
1719
1720         * configure.in (enable-sim-igen): New configuration option.
1721         * configure: Re-generate.
1722
1723         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1724
1725         * interp.c (load_memory, store_memory): Delete parameter RAW.
1726         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1727         bypassing {load,store}_memory.
1728
1729         * sim-main.h (ByteSwapMem): Delete definition.
1730
1731         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1732
1733         * interp.c (sim_do_command, sim_commands): Delete mips specific
1734         commands.  Handled by module sim-options.
1735
1736         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1737         (WITH_MODULO_MEMORY): Define.
1738
1739         * interp.c (sim_info): Delete code printing memory size.
1740
1741         * interp.c (mips_size): Nee sim_size, delete function.
1742         (power2): Delete.
1743         (monitor, monitor_base, monitor_size): Delete global variables.
1744         (sim_open, sim_close): Delete code creating monitor and other
1745         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1746         manage memory regions.
1747         (load_memory, store_memory): Use sim-core for memory model.
1748
1749         * interp.c (address_translation): Delete all memory map code
1750         except line forcing 32 bit addresses.
1751
1752 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1753
1754         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1755         trace options.
1756
1757         * interp.c (logfh, logfile): Delete globals.
1758         (sim_open, sim_close): Delete code opening & closing log file.
1759         (mips_option_handler): Delete -l and -n options.
1760         (OPTION mips_options): Ditto.
1761
1762         * interp.c (OPTION mips_options): Rename option trace to dinero.
1763         (mips_option_handler): Update.
1764
1765 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1766
1767         * interp.c (fetch_str): New function.
1768         (sim_monitor): Rewrite using sim_read & sim_write.
1769         (sim_open): Check magic number.
1770         (sim_open): Write monitor vectors into memory using sim_write.
1771         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1772         (sim_read, sim_write): Simplify - transfer data one byte at a
1773         time.
1774         (load_memory, store_memory): Clarify meaning of parameter RAW.
1775
1776         * sim-main.h (isHOST): Defete definition.
1777         (isTARGET): Mark as depreciated.
1778         (address_translation): Delete parameter HOST.
1779
1780         * interp.c (address_translation): Delete parameter HOST.
1781
1782 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1783
1784         * mips.igen:
1785
1786         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1787         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1788
1789 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1790
1791         * mips.igen: Add model filter field to records.
1792
1793 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1794
1795         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1796
1797         interp.c (sim_engine_run): Do not compile function sim_engine_run
1798         when WITH_IGEN == 1.
1799
1800         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1801         target architecture.
1802
1803         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1804         igen. Replace with configuration variables sim_igen_flags /
1805         sim_m16_flags.
1806
1807         * m16.igen: New file.  Copy mips16 insns here.
1808         * mips.igen: From here.
1809
1810 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1811
1812         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1813         to top.
1814         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1815
1816 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1817
1818         * gencode.c (build_instruction): Follow sim_write's lead in using
1819         BigEndianMem instead of !ByteSwapMem.
1820
1821 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1822
1823         * configure.in (sim_gen): Dependent on target, select type of
1824         generator.  Always select old style generator.
1825
1826         configure: Re-generate.
1827
1828         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1829         targets.
1830         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1831         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1832         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1833         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1834         SIM_@sim_gen@_*, set by autoconf.
1835
1836 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1837
1838         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1839
1840         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1841         CURRENT_FLOATING_POINT instead.
1842
1843         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1844         (address_translation): Raise exception InstructionFetch when
1845         translation fails and isINSTRUCTION.
1846
1847         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1848         sim_engine_run): Change type of of vaddr and paddr to
1849         address_word.
1850         (address_translation, prefetch, load_memory, store_memory,
1851         cache_op): Change type of vAddr and pAddr to address_word.
1852
1853         * gencode.c (build_instruction): Change type of vaddr and paddr to
1854         address_word.
1855
1856 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1857
1858         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1859         macro to obtain result of ALU op.
1860
1861 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1862
1863         * interp.c (sim_info): Call profile_print.
1864
1865 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1866
1867         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1868
1869         * sim-main.h (WITH_PROFILE): Do not define, defined in
1870         common/sim-config.h.  Use sim-profile module.
1871         (simPROFILE): Delete defintion.
1872
1873         * interp.c (PROFILE): Delete definition.
1874         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1875         (sim_close): Delete code writing profile histogram.
1876         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1877         Delete.
1878         (sim_engine_run): Delete code profiling the PC.
1879
1880 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1881
1882         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1883
1884         * interp.c (sim_monitor): Make register pointers of type
1885         unsigned_word*.
1886
1887         * sim-main.h: Make registers of type unsigned_word not
1888         signed_word.
1889
1890 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1891
1892         * interp.c (sync_operation): Rename from SyncOperation, make
1893         global, add SD argument.
1894         (prefetch): Rename from Prefetch, make global, add SD argument.
1895         (decode_coproc): Make global.
1896
1897         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1898
1899         * gencode.c (build_instruction): Generate DecodeCoproc not
1900         decode_coproc calls.
1901
1902         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1903         (SizeFGR): Move to sim-main.h
1904         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1905         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1906         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1907         sim-main.h.
1908         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1909         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1910         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1911         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1912         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1913         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1914
1915         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1916         exception.
1917         (sim-alu.h): Include.
1918         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1919         (sim_cia): Typedef to instruction_address.
1920
1921 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1922
1923         * Makefile.in (interp.o): Rename generated file engine.c to
1924         oengine.c.
1925
1926         * interp.c: Update.
1927
1928 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1929
1930         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1931
1932 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * gencode.c (build_instruction): For "FPSQRT", output correct
1935         number of arguments to Recip.
1936
1937 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1938
1939         * Makefile.in (interp.o): Depends on sim-main.h
1940
1941         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1942
1943         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1944         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1945         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1946         STATE, DSSTATE): Define
1947         (GPR, FGRIDX, ..): Define.
1948
1949         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1950         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1951         (GPR, FGRIDX, ...): Delete macros.
1952
1953         * interp.c: Update names to match defines from sim-main.h
1954
1955 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1956
1957         * interp.c (sim_monitor): Add SD argument.
1958         (sim_warning): Delete.  Replace calls with calls to
1959         sim_io_eprintf.
1960         (sim_error): Delete. Replace calls with sim_io_error.
1961         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1962         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1963         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1964         argument.
1965         (mips_size): Rename from sim_size. Add SD argument.
1966
1967         * interp.c (simulator): Delete global variable.
1968         (callback): Delete global variable.
1969         (mips_option_handler, sim_open, sim_write, sim_read,
1970         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1971         sim_size,sim_monitor): Use sim_io_* not callback->*.
1972         (sim_open): ZALLOC simulator struct.
1973         (PROFILE): Do not define.
1974
1975 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1976
1977         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1978         support.h with corresponding code.
1979
1980         * sim-main.h (word64, uword64), support.h: Move definition to
1981         sim-main.h.
1982         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1983
1984         * support.h: Delete
1985         * Makefile.in: Update dependencies
1986         * interp.c: Do not include.
1987
1988 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1989
1990         * interp.c (address_translation, load_memory, store_memory,
1991         cache_op): Rename to from AddressTranslation et.al., make global,
1992         add SD argument
1993
1994         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1995         CacheOp): Define.
1996
1997         * interp.c (SignalException): Rename to signal_exception, make
1998         global.
1999
2000         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2001
2002         * sim-main.h (SignalException, SignalExceptionInterrupt,
2003         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2004         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2005         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2006         Define.
2007
2008         * interp.c, support.h: Use.
2009
2010 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2011
2012         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2013         to value_fpr / store_fpr. Add SD argument.
2014         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2015         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2016
2017         * sim-main.h (ValueFPR, StoreFPR): Define.
2018
2019 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2020
2021         * interp.c (sim_engine_run): Check consistency between configure
2022         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2023         and HASFPU.
2024
2025         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2026         (mips_fpu): Configure WITH_FLOATING_POINT.
2027         (mips_endian): Configure WITH_TARGET_ENDIAN.
2028         * configure: Update.
2029
2030 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2031
2032         * configure: Regenerated to track ../common/aclocal.m4 changes.
2033
2034 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2035
2036         * configure: Regenerated.
2037
2038 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2039
2040         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2041
2042 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2043
2044         * gencode.c (print_igen_insn_models): Assume certain architectures
2045         include all mips* instructions.
2046         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2047         instruction.
2048
2049         * Makefile.in (tmp.igen): Add target. Generate igen input from
2050         gencode file.
2051
2052         * gencode.c (FEATURE_IGEN): Define.
2053         (main): Add --igen option.  Generate output in igen format.
2054         (process_instructions): Format output according to igen option.
2055         (print_igen_insn_format): New function.
2056         (print_igen_insn_models): New function.
2057         (process_instructions): Only issue warnings and ignore
2058         instructions when no FEATURE_IGEN.
2059
2060 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2061
2062         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2063         MIPS targets.
2064
2065 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2066
2067         * configure: Regenerated to track ../common/aclocal.m4 changes.
2068
2069 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2070
2071         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2072         SIM_RESERVED_BITS): Delete, moved to common.
2073         (SIM_EXTRA_CFLAGS): Update.
2074
2075 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2076
2077         * configure.in: Configure non-strict memory alignment.
2078         * configure: Regenerated to track ../common/aclocal.m4 changes.
2079
2080 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2081
2082         * configure: Regenerated to track ../common/aclocal.m4 changes.
2083
2084 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2085
2086         * gencode.c (SDBBP,DERET): Added (3900) insns.
2087         (RFE): Turn on for 3900.
2088         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2089         (dsstate): Made global.
2090         (SUBTARGET_R3900): Added.
2091         (CANCELDELAYSLOT): New.
2092         (SignalException): Ignore SystemCall rather than ignore and
2093         terminate.  Add DebugBreakPoint handling.
2094         (decode_coproc): New insns RFE, DERET; and new registers Debug
2095         and DEPC protected by SUBTARGET_R3900.
2096         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2097         bits explicitly.
2098         * Makefile.in,configure.in: Add mips subtarget option.
2099         * configure: Update.
2100
2101 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2102
2103         * gencode.c: Add r3900 (tx39).
2104
2105
2106 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2107
2108         * gencode.c (build_instruction): Don't need to subtract 4 for
2109         JALR, just 2.
2110
2111 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2112
2113         * interp.c: Correct some HASFPU problems.
2114
2115 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2116
2117         * configure: Regenerated to track ../common/aclocal.m4 changes.
2118
2119 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2120
2121         * interp.c (mips_options): Fix samples option short form, should
2122         be `x'.
2123
2124 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2125
2126         * interp.c (sim_info): Enable info code.  Was just returning.
2127
2128 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2129
2130         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2131         MFC0.
2132
2133 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2134
2135         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2136         constants.
2137         (build_instruction): Ditto for LL.
2138
2139 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2140
2141         * configure: Regenerated to track ../common/aclocal.m4 changes.
2142
2143 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2144
2145         * configure: Regenerated to track ../common/aclocal.m4 changes.
2146         * config.in: Ditto.
2147
2148 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2149
2150         * interp.c (sim_open): Add call to sim_analyze_program, update
2151         call to sim_config.
2152
2153 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2154
2155         * interp.c (sim_kill): Delete.
2156         (sim_create_inferior): Add ABFD argument. Set PC from same.
2157         (sim_load): Move code initializing trap handlers from here.
2158         (sim_open): To here.
2159         (sim_load): Delete, use sim-hload.c.
2160
2161         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2162
2163 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2164
2165         * configure: Regenerated to track ../common/aclocal.m4 changes.
2166         * config.in: Ditto.
2167
2168 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2169
2170         * interp.c (sim_open): Add ABFD argument.
2171         (sim_load): Move call to sim_config from here.
2172         (sim_open): To here.  Check return status.
2173
2174 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2175
2176         * gencode.c (build_instruction): Two arg MADD should
2177         not assign result to $0.
2178
2179 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2180
2181         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2182         * sim/mips/configure.in: Regenerate.
2183
2184 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2185
2186         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2187         signed8, unsigned8 et.al. types.
2188
2189         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2190         hosts when selecting subreg.
2191
2192 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2193
2194         * interp.c (sim_engine_run): Reset the ZERO register to zero
2195         regardless of FEATURE_WARN_ZERO.
2196         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2197
2198 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2199
2200         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2201         (SignalException): For BreakPoints ignore any mode bits and just
2202         save the PC.
2203         (SignalException): Always set the CAUSE register.
2204
2205 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2206
2207         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2208         exception has been taken.
2209
2210         * interp.c: Implement the ERET and mt/f sr instructions.
2211
2212 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2213
2214         * interp.c (SignalException): Don't bother restarting an
2215         interrupt.
2216
2217 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2218
2219         * interp.c (SignalException): Really take an interrupt.
2220         (interrupt_event): Only deliver interrupts when enabled.
2221
2222 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2223
2224         * interp.c (sim_info): Only print info when verbose.
2225         (sim_info) Use sim_io_printf for output.
2226
2227 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2228
2229         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2230         mips architectures.
2231
2232 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2233
2234         * interp.c (sim_do_command): Check for common commands if a
2235         simulator specific command fails.
2236
2237 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2238
2239         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2240         and simBE when DEBUG is defined.
2241
2242 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2243
2244         * interp.c (interrupt_event): New function.  Pass exception event
2245         onto exception handler.
2246
2247         * configure.in: Check for stdlib.h.
2248         * configure: Regenerate.
2249
2250         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2251         variable declaration.
2252         (build_instruction): Initialize memval1.
2253         (build_instruction): Add UNUSED attribute to byte, bigend,
2254         reverse.
2255         (build_operands): Ditto.
2256
2257         * interp.c: Fix GCC warnings.
2258         (sim_get_quit_code): Delete.
2259
2260         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2261         * Makefile.in: Ditto.
2262         * configure: Re-generate.
2263
2264         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2265
2266 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2267
2268         * interp.c (mips_option_handler): New function parse argumes using
2269         sim-options.
2270         (myname): Replace with STATE_MY_NAME.
2271         (sim_open): Delete check for host endianness - performed by
2272         sim_config.
2273         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2274         (sim_open): Move much of the initialization from here.
2275         (sim_load): To here.  After the image has been loaded and
2276         endianness set.
2277         (sim_open): Move ColdReset from here.
2278         (sim_create_inferior): To here.
2279         (sim_open): Make FP check less dependant on host endianness.
2280
2281         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2282         run.
2283         * interp.c (sim_set_callbacks): Delete.
2284
2285         * interp.c (membank, membank_base, membank_size): Replace with
2286         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2287         (sim_open): Remove call to callback->init. gdb/run do this.
2288
2289         * interp.c: Update
2290
2291         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2292
2293         * interp.c (big_endian_p): Delete, replaced by
2294         current_target_byte_order.
2295
2296 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2297
2298         * interp.c (host_read_long, host_read_word, host_swap_word,
2299         host_swap_long): Delete. Using common sim-endian.
2300         (sim_fetch_register, sim_store_register): Use H2T.
2301         (pipeline_ticks): Delete.  Handled by sim-events.
2302         (sim_info): Update.
2303         (sim_engine_run): Update.
2304
2305 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2306
2307         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2308         reason from here.
2309         (SignalException): To here. Signal using sim_engine_halt.
2310         (sim_stop_reason): Delete, moved to common.
2311
2312 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2313
2314         * interp.c (sim_open): Add callback argument.
2315         (sim_set_callbacks): Delete SIM_DESC argument.
2316         (sim_size): Ditto.
2317
2318 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2319
2320         * Makefile.in (SIM_OBJS): Add common modules.
2321
2322         * interp.c (sim_set_callbacks): Also set SD callback.
2323         (set_endianness, xfer_*, swap_*): Delete.
2324         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2325         Change to functions using sim-endian macros.
2326         (control_c, sim_stop): Delete, use common version.
2327         (simulate): Convert into.
2328         (sim_engine_run): This function.
2329         (sim_resume): Delete.
2330
2331         * interp.c (simulation): New variable - the simulator object.
2332         (sim_kind): Delete global - merged into simulation.
2333         (sim_load): Cleanup.  Move PC assignment from here.
2334         (sim_create_inferior): To here.
2335
2336         * sim-main.h: New file.
2337         * interp.c (sim-main.h): Include.
2338
2339 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2340
2341         * configure: Regenerated to track ../common/aclocal.m4 changes.
2342
2343 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2344
2345         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2346
2347 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2348
2349         * gencode.c (build_instruction): DIV instructions: check
2350         for division by zero and integer overflow before using
2351         host's division operation.
2352
2353 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2354
2355         * Makefile.in (SIM_OBJS): Add sim-load.o.
2356         * interp.c: #include bfd.h.
2357         (target_byte_order): Delete.
2358         (sim_kind, myname, big_endian_p): New static locals.
2359         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2360         after argument parsing.  Recognize -E arg, set endianness accordingly.
2361         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2362         load file into simulator.  Set PC from bfd.
2363         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2364         (set_endianness): Use big_endian_p instead of target_byte_order.
2365
2366 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2367
2368         * interp.c (sim_size): Delete prototype - conflicts with
2369         definition in remote-sim.h.  Correct definition.
2370
2371 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2372
2373         * configure: Regenerated to track ../common/aclocal.m4 changes.
2374         * config.in: Ditto.
2375
2376 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2377
2378         * interp.c (sim_open): New arg `kind'.
2379
2380         * configure: Regenerated to track ../common/aclocal.m4 changes.
2381
2382 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2383
2384         * configure: Regenerated to track ../common/aclocal.m4 changes.
2385
2386 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2387
2388         * interp.c (sim_open): Set optind to 0 before calling getopt.
2389
2390 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2391
2392         * configure: Regenerated to track ../common/aclocal.m4 changes.
2393
2394 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2395
2396         * interp.c : Replace uses of pr_addr with pr_uword64
2397         where the bit length is always 64 independent of SIM_ADDR.
2398         (pr_uword64) : added.
2399
2400 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2401
2402         * configure: Re-generate.
2403
2404 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2405
2406         * configure: Regenerate to track ../common/aclocal.m4 changes.
2407
2408 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2409
2410         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2411         in argv form.
2412         (other sim_*): New SIM_DESC argument.
2413
2414 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2415
2416         * interp.c: Fix printing of addresses for non-64-bit targets.
2417         (pr_addr): Add function to print address based on size.
2418
2419 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2420
2421         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2422
2423 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2424
2425         * gencode.c (build_mips16_operands): Correct computation of base
2426         address for extended PC relative instruction.
2427
2428 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2429
2430         * interp.c (mips16_entry): Add support for floating point cases.
2431         (SignalException): Pass floating point cases to mips16_entry.
2432         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2433         registers.
2434         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2435         or fmt_word.
2436         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2437         and then set the state to fmt_uninterpreted.
2438         (COP_SW): Temporarily set the state to fmt_word while calling
2439         ValueFPR.
2440
2441 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2442
2443         * gencode.c (build_instruction): The high order may be set in the
2444         comparison flags at any ISA level, not just ISA 4.
2445
2446 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2447
2448         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2449         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2450         * configure.in: sinclude ../common/aclocal.m4.
2451         * configure: Regenerated.
2452
2453 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2454
2455         * configure: Rebuild after change to aclocal.m4.
2456
2457 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2458
2459         * configure configure.in Makefile.in:  Update to new configure
2460         scheme which is more compatible with WinGDB builds.
2461         * configure.in:  Improve comment on how to run autoconf.
2462         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2463         * Makefile.in:  Use autoconf substitution to install common
2464         makefile fragment.
2465
2466 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2467
2468         * gencode.c (build_instruction): Use BigEndianCPU instead of
2469         ByteSwapMem.
2470
2471 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2472
2473         * interp.c (sim_monitor): Make output to stdout visible in
2474         wingdb's I/O log window.
2475
2476 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2477
2478         * support.h: Undo previous change to SIGTRAP
2479         and SIGQUIT values.
2480
2481 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2482
2483         * interp.c (store_word, load_word): New static functions.
2484         (mips16_entry): New static function.
2485         (SignalException): Look for mips16 entry and exit instructions.
2486         (simulate): Use the correct index when setting fpr_state after
2487         doing a pending move.
2488
2489 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2490
2491         * interp.c: Fix byte-swapping code throughout to work on
2492         both little- and big-endian hosts.
2493
2494 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2495
2496         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2497         with gdb/config/i386/xm-windows.h.
2498
2499 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2500
2501         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2502         that messes up arithmetic shifts.
2503
2504 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2505
2506         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2507         SIGTRAP and SIGQUIT for _WIN32.
2508
2509 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2510
2511         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2512         force a 64 bit multiplication.
2513         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2514         destination register is 0, since that is the default mips16 nop
2515         instruction.
2516
2517 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2518
2519         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2520         (build_endian_shift): Don't check proc64.
2521         (build_instruction): Always set memval to uword64.  Cast op2 to
2522         uword64 when shifting it left in memory instructions.  Always use
2523         the same code for stores--don't special case proc64.
2524
2525         * gencode.c (build_mips16_operands): Fix base PC value for PC
2526         relative operands.
2527         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2528         jal instruction.
2529         * interp.c (simJALDELAYSLOT): Define.
2530         (JALDELAYSLOT): Define.
2531         (INDELAYSLOT, INJALDELAYSLOT): Define.
2532         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2533
2534 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2535
2536         * interp.c (sim_open): add flush_cache as a PMON routine
2537         (sim_monitor): handle flush_cache by ignoring it
2538
2539 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2540
2541         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2542         BigEndianMem.
2543         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2544         (BigEndianMem): Rename to ByteSwapMem and change sense.
2545         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2546         BigEndianMem references to !ByteSwapMem.
2547         (set_endianness): New function, with prototype.
2548         (sim_open): Call set_endianness.
2549         (sim_info): Use simBE instead of BigEndianMem.
2550         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2551         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2552         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2553         ifdefs, keeping the prototype declaration.
2554         (swap_word): Rewrite correctly.
2555         (ColdReset): Delete references to CONFIG.  Delete endianness related
2556         code; moved to set_endianness.
2557
2558 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2559
2560         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2561         * interp.c (CHECKHILO): Define away.
2562         (simSIGINT): New macro.
2563         (membank_size): Increase from 1MB to 2MB.
2564         (control_c): New function.
2565         (sim_resume): Rename parameter signal to signal_number.  Add local
2566         variable prev.  Call signal before and after simulate.
2567         (sim_stop_reason): Add simSIGINT support.
2568         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2569         functions always.
2570         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2571         if logfh is NULL.
2572         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2573         a call to sim_warning.
2574
2575 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2576
2577         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2578         16 bit instructions.
2579
2580 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2581
2582         Add support for mips16 (16 bit MIPS implementation):
2583         * gencode.c (inst_type): Add mips16 instruction encoding types.
2584         (GETDATASIZEINSN): Define.
2585         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2586         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2587         mtlo.
2588         (MIPS16_DECODE): New table, for mips16 instructions.
2589         (bitmap_val): New static function.
2590         (struct mips16_op): Define.
2591         (mips16_op_table): New table, for mips16 operands.
2592         (build_mips16_operands): New static function.
2593         (process_instructions): If PC is odd, decode a mips16
2594         instruction.  Break out instruction handling into new
2595         build_instruction function.
2596         (build_instruction): New static function, broken out of
2597         process_instructions.  Check modifiers rather than flags for SHIFT
2598         bit count and m[ft]{hi,lo} direction.
2599         (usage): Pass program name to fprintf.
2600         (main): Remove unused variable this_option_optind.  Change
2601         ``*loptarg++'' to ``loptarg++''.
2602         (my_strtoul): Parenthesize && within ||.
2603         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2604         (simulate): If PC is odd, fetch a 16 bit instruction, and
2605         increment PC by 2 rather than 4.
2606         * configure.in: Add case for mips16*-*-*.
2607         * configure: Rebuild.
2608
2609 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2610
2611         * interp.c: Allow -t to enable tracing in standalone simulator.
2612         Fix garbage output in trace file and error messages.
2613
2614 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2615
2616         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2617         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2618         * configure.in: Simplify using macros in ../common/aclocal.m4.
2619         * configure: Regenerated.
2620         * tconfig.in: New file.
2621
2622 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2623
2624         * interp.c: Fix bugs in 64-bit port.
2625         Use ansi function declarations for msvc compiler.
2626         Initialize and test file pointer in trace code.
2627         Prevent duplicate definition of LAST_EMED_REGNUM.
2628
2629 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2630
2631         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2632
2633 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2634
2635         * interp.c (SignalException): Check for explicit terminating
2636         breakpoint value.
2637         * gencode.c: Pass instruction value through SignalException()
2638         calls for Trap, Breakpoint and Syscall.
2639
2640 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2641
2642         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2643         only used on those hosts that provide it.
2644         * configure.in: Add sqrt() to list of functions to be checked for.
2645         * config.in: Re-generated.
2646         * configure: Re-generated.
2647
2648 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2649
2650         * gencode.c (process_instructions): Call build_endian_shift when
2651         expanding STORE RIGHT, to fix swr.
2652         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2653         clear the high bits.
2654         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2655         Fix float to int conversions to produce signed values.
2656
2657 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2658
2659         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2660         (process_instructions): Correct handling of nor instruction.
2661         Correct shift count for 32 bit shift instructions. Correct sign
2662         extension for arithmetic shifts to not shift the number of bits in
2663         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2664         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2665         Fix madd.
2666         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2667         It's OK to have a mult follow a mult.  What's not OK is to have a
2668         mult follow an mfhi.
2669         (Convert): Comment out incorrect rounding code.
2670
2671 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2672
2673         * interp.c (sim_monitor): Improved monitor printf
2674         simulation. Tidied up simulator warnings, and added "--log" option
2675         for directing warning message output.
2676         * gencode.c: Use sim_warning() rather than WARNING macro.
2677
2678 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2679
2680         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2681         getopt1.o, rather than on gencode.c.  Link objects together.
2682         Don't link against -liberty.
2683         (gencode.o, getopt.o, getopt1.o): New targets.
2684         * gencode.c: Include <ctype.h> and "ansidecl.h".
2685         (AND): Undefine after including "ansidecl.h".
2686         (ULONG_MAX): Define if not defined.
2687         (OP_*): Don't define macros; now defined in opcode/mips.h.
2688         (main): Call my_strtoul rather than strtoul.
2689         (my_strtoul): New static function.
2690
2691 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2692
2693         * gencode.c (process_instructions):  Generate word64 and uword64
2694         instead of `long long' and `unsigned long long' data types.
2695         * interp.c:  #include sysdep.h to get signals, and define default
2696         for SIGBUS.
2697         * (Convert):  Work around for Visual-C++ compiler bug with type
2698         conversion.
2699         * support.h:  Make things compile under Visual-C++ by using
2700         __int64 instead of `long long'.  Change many refs to long long
2701         into word64/uword64 typedefs.
2702
2703 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2704
2705         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2706         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2707         (docdir): Removed.
2708         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2709         (AC_PROG_INSTALL): Added.
2710         (AC_PROG_CC): Moved to before configure.host call.
2711         * configure: Rebuilt.
2712
2713 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2714
2715         * configure.in: Define @SIMCONF@ depending on mips target.
2716         * configure: Rebuild.
2717         * Makefile.in (run): Add @SIMCONF@ to control simulator
2718         construction.
2719         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2720         * interp.c: Remove some debugging, provide more detailed error
2721         messages, update memory accesses to use LOADDRMASK.
2722
2723 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2724
2725         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2726         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2727         stamp-h.
2728         * configure: Rebuild.
2729         * config.in: New file, generated by autoheader.
2730         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2731         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2732         HAVE_ANINT and HAVE_AINT, as appropriate.
2733         * Makefile.in (run): Use @LIBS@ rather than -lm.
2734         (interp.o): Depend upon config.h.
2735         (Makefile): Just rebuild Makefile.
2736         (clean): Remove stamp-h.
2737         (mostlyclean): Make the same as clean, not as distclean.
2738         (config.h, stamp-h): New targets.
2739
2740 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2741
2742         * interp.c (ColdReset): Fix boolean test. Make all simulator
2743         globals static.
2744
2745 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2746
2747         * interp.c (xfer_direct_word, xfer_direct_long,
2748         swap_direct_word, swap_direct_long, xfer_big_word,
2749         xfer_big_long, xfer_little_word, xfer_little_long,
2750         swap_word,swap_long): Added.
2751         * interp.c (ColdReset): Provide function indirection to
2752         host<->simulated_target transfer routines.
2753         * interp.c (sim_store_register, sim_fetch_register): Updated to
2754         make use of indirected transfer routines.
2755
2756 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2757
2758         * gencode.c (process_instructions): Ensure FP ABS instruction
2759         recognised.
2760         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2761         system call support.
2762
2763 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2764
2765         * interp.c (sim_do_command): Complain if callback structure not
2766         initialised.
2767
2768 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2769
2770         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2771         support for Sun hosts.
2772         * Makefile.in (gencode): Ensure the host compiler and libraries
2773         used for cross-hosted build.
2774
2775 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2776
2777         * interp.c, gencode.c: Some more (TODO) tidying.
2778
2779 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2780
2781         * gencode.c, interp.c: Replaced explicit long long references with
2782         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2783         * support.h (SET64LO, SET64HI): Macros added.
2784
2785 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2786
2787         * configure: Regenerate with autoconf 2.7.
2788
2789 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2790
2791         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2792         * support.h: Remove superfluous "1" from #if.
2793         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2794
2795 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2796
2797         * interp.c (StoreFPR): Control UndefinedResult() call on
2798         WARN_RESULT manifest.
2799
2800 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2801
2802         * gencode.c: Tidied instruction decoding, and added FP instruction
2803         support.
2804
2805         * interp.c: Added dineroIII, and BSD profiling support. Also
2806         run-time FP handling.
2807
2808 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2809
2810         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2811         gencode.c, interp.c, support.h: created.