sim/mips/ChangeLog

   1 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * mips.igen: Remove whitespace at end of lines.
   4
   5 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
   6
   7         * mips.igen (loadstore_ea): New function to do effective
   8         address calculations.
   9         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
  10         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
  11         CACHE): Use loadstore_ea to do effective address computations.
  12
  13 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  14
  15         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
  16         * mips.igen (LL, CxC1, MxC1): Likewise.
  17
  18 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
  19
  20         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
  21         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
  22         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
  23         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
  24         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
  25         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
  26         Don't split opcode fields by hand, use the opcode field values
  27         provided by igen.
  28
  29 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  30
  31         * mips.igen (do_divu): Fix spacing.
  32
  33         * mips.igen (do_dsllv): Move to be right before DSLLV,
  34         to match the rest of the do_<shift> functions.
  35
  36 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  37
  38         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
  39         DSRL32, do_dsrlv): Trace inputs and results.
  40
  41 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
  42
  43         * mips.igen (CACHE): Provide instruction-printing string.
  44
  45         * interp.c (signal_exception): Comment tokens after #endif.
  46
  47 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
  48
  49         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
  50         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
  51         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
  52         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
  53         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
  54         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
  55         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
  56         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
  57
  58 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
  59
  60         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
  61         instruction-printing string.
  62         (LWU): Use '64' as the filter flag.
  63
  64 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
  65
  66         * mips.igen (SDXC1): Fix instruction-printing string.
  67
  68 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
  69
  70         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
  71         filter flags "32,f".
  72
  73 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
  74
  75         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
  76         as the filter flag.
  77
  78 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
  79
  80         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
  81         add a comma) so that it more closely match the MIPS ISA
  82         documentation opcode partitioning.
  83         (PREF): Put useful names on opcode fields, and include
  84         instruction-printing string.
  85
  86 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
  87
  88         * mips.igen (check_u64): New function which in the future will
  89         check whether 64-bit instructions are usable and signal an
  90         exception if not.  Currently a no-op.
  91         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
  92         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
  93         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
  94         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
  95
  96         * mips.igen (check_fpu): New function which in the future will
  97         check whether FPU instructions are usable and signal an exception
  98         if not.  Currently a no-op.
  99         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 100         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 101         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 102         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 103         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 104         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 105         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 106         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 107
 108 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 109
 110         * mips.igen (do_load_left, do_load_right): Move to be immediately
 111         following do_load.
 112         (do_store_left, do_store_right): Move to be immediately following
 113         do_store.
 114
 115 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 116
 117         * mips.igen (mipsV): New model name.  Also, add it to
 118         all instructions and functions where it is appropriate.
 119
 120 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 121
 122         * mips.igen: For all functions and instructions, list model
 123         names that support that instruction one per line.
 124
 125 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 126
 127         * mips.igen: Add some additional comments about supported
 128         models, and about which instructions go where.
 129         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 130         order as is used in the rest of the file.
 131
 132 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 133
 134         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 135         indicating that ALU32_END or ALU64_END are there to check
 136         for overflow.
 137         (DADD): Likewise, but also remove previous comment about
 138         overflow checking.
 139
 140 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 141
 142         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 143         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 144         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 145         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 146         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 147         fields (i.e., add and move commas) so that they more closely
 148         match the MIPS ISA documentation opcode partitioning.
 149
 150 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 151
 152         * mips.igen (ADDI): Print immediate value.
 153         (BREAK): Print code.
 154         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 155         (SLL): Print "nop" specially, and don't run the code
 156         that does the shift for the "nop" case.
 157
 158 2001-11-17  Fred Fish  <fnf@redhat.com>
 159
 160         * sim-main.h (float_operation): Move enum declaration outside
 161         of _sim_cpu struct declaration.
 162
 163 2001-04-12  Jim Blandy  <jimb@redhat.com>
 164
 165         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 166         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 167         set of the FCSR.
 168         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 169         PENDING_FILL, and you can get the intended effect gracefully by
 170         calling PENDING_SCHED directly.
 171
 172 2001-02-23  Ben Elliston  <bje@redhat.com>
 173
 174         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 175         already defined elsewhere.
 176
 177 2001-02-19  Ben Elliston  <bje@redhat.com>
 178
 179         * sim-main.h (sim_monitor): Return an int.
 180         * interp.c (sim_monitor): Add return values.
 181         (signal_exception): Handle error conditions from sim_monitor.
 182
 183 2001-02-08  Ben Elliston  <bje@redhat.com>
 184
 185         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 186         (store_memory): Likewise, pass cia to sim_core_write*.
 187
 188 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 189
 190         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 191         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 192
 193 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 194
 195         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 196         * Makefile.in: Don't delete *.igen when cleaning directory.
 197
 198 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 199
 200         * m16.igen (break): Call SignalException not sim_engine_halt.
 201
 202 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 203
 204         From Jason Eckhardt:
 205         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 206
 207 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 208
 209         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 210
 211 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 212
 213         * mips.igen (do_dmultx): Fix typo.
 214
 215 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 216
 217         * configure: Regenerated to track ../common/aclocal.m4 changes.
 218
 219 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 220
 221         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 222
 223 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 224
 225         * sim-main.h (GPR_CLEAR): Define macro.
 226
 227 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 228
 229         * interp.c (decode_coproc): Output long using %lx and not %s.
 230
 231 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 232
 233         * interp.c (sim_open): Sort & extend dummy memory regions for
 234         --board=jmr3904 for eCos.
 235
 236 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 237
 238         * configure: Regenerated.
 239
 240 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 241
 242         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 243         calls, conditional on the simulator being in verbose mode.
 244
 245 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 246
 247         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 248         cache don't get ReservedInstruction traps.
 249
 250 1999-11-29  Mark Salter  <msalter@cygnus.com>
 251
 252         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 253         to clear status bits in sdisr register. This is how the hardware works.
 254
 255         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 256         being used by cygmon.
 257
 258 1999-11-11  Andrew Haley  <aph@cygnus.com>
 259
 260         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 261         instructions.
 262
 263 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 264
 265         * mips.igen (MULT): Correct previous mis-applied patch.
 266
 267 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 268
 269         * mips.igen (delayslot32): Handle sequence like
 270         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 271         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 272         (MULT): Actually pass the third register...
 273
 274 1999-09-03  Mark Salter  <msalter@cygnus.com>
 275
 276         * interp.c (sim_open): Added more memory aliases for additional
 277         hardware being touched by cygmon on jmr3904 board.
 278
 279 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 280
 281         * configure: Regenerated to track ../common/aclocal.m4 changes.
 282
 283 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 284
 285         * interp.c (sim_store_register): Handle case where client - GDB -
 286         specifies that a 4 byte register is 8 bytes in size.
 287         (sim_fetch_register): Ditto.
 288
 289 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 290
 291         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 292         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 293         (idt_monitor_base): Base address for IDT monitor traps.
 294         (pmon_monitor_base): Ditto for PMON.
 295         (lsipmon_monitor_base): Ditto for LSI PMON.
 296         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 297         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 298         (sim_firmware_command): New function.
 299         (mips_option_handler): Call it for OPTION_FIRMWARE.
 300         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 301         option was given, add no monitor by default.  Add BREAK hooks only if
 302         monitors are also there.
 303
 304 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 305
 306         * interp.c (sim_monitor): Flush output before reading input.
 307
 308 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 309
 310         * tconfig.in (SIM_HANDLES_LMA): Always define.
 311
 312 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 313
 314         From Mark Salter <msalter@cygnus.com>:
 315         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 316         (sim_open): Add setup for BSP board.
 317
 318 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 319
 320         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 321         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 322         them as unimplemented.
 323
 324 1999-05-08  Felix Lee  <flee@cygnus.com>
 325
 326         * configure: Regenerated to track ../common/aclocal.m4 changes.
 327
 328 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 329
 330         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 331
 332 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 333
 334         * configure.in: Any mips64vr5*-*-* target should have
 335         -DTARGET_ENABLE_FR=1.
 336         (default_endian): Any mips64vr*el-*-* target should default to
 337         LITTLE_ENDIAN.
 338         * configure: Re-generate.
 339
 340 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 341
 342         * mips.igen (ldl): Extend from _16_, not 32.
 343
 344 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 345
 346         * interp.c (sim_store_register): Force registers written to by GDB
 347         into an un-interpreted state.
 348
 349 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 350
 351         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 352         CPU, start periodic background I/O polls.
 353         (tx3904sio_poll): New function: periodic I/O poller.
 354
 355 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 356
 357         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 358
 359 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 360
 361         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 362         case statement.
 363
 364 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 365
 366         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 367         (load_word): Call SIM_CORE_SIGNAL hook on error.
 368         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 369         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 370         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 371         * sim-main.h (COP0_BADVADDR): Define.
 372         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 373         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 374         (_sim_cpu): Add exc_* fields to store register value snapshots.
 375         * mips.igen (*): Replace memory-related SignalException* calls
 376         with references to SIM_CORE_SIGNAL hook.
 377
 378         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 379         fix.
 380         * sim-main.c (*): Minor warning cleanups.
 381
 382 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 383
 384         * m16.igen (DADDIU5): Correct type-o.
 385
 386 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 387
 388         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 389         variables.
 390
 391 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 392
 393         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 394         to include path.
 395         (interp.o): Add dependency on itable.h
 396         (oengine.c, gencode): Delete remaining references.
 397         (BUILT_SRC_FROM_GEN): Clean up.
 398
 399 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 400
 401         * vr4run.c: New.
 402         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 403         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 404         tmp-run-hack) : New.
 405         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 406         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 407         Drop the "64" qualifier to get the HACK generator working.
 408         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 409         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 410         qualifier to get the hack generator working.
 411         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 412         (DSLL): Use do_dsll.
 413         (DSLLV): Use do_dsllv.
 414         (DSRA): Use do_dsra.
 415         (DSRL): Use do_dsrl.
 416         (DSRLV): Use do_dsrlv.
 417         (BC1): Move *vr4100 to get the HACK generator working.
 418         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 419         get the HACK generator working.
 420         (MACC) Rename to get the HACK generator working.
 421         (DMACC,MACCS,DMACCS): Add the 64.
 422
 423 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 424
 425         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 426         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 427
 428 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 429
 430     * mips/interp.c (DEBUG): Cleanups.
 431
 432 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 433
 434         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 435         (tx3904sio_tickle): fflush after a stdout character output.
 436
 437 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 438
 439         * interp.c (sim_close): Uninstall modules.
 440
 441 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 442
 443         * sim-main.h, interp.c (sim_monitor): Change to global
 444         function.
 445
 446 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 447
 448         * configure.in (vr4100): Only include vr4100 instructions in
 449         simulator.
 450         * configure: Re-generate.
 451         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 452
 453 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 454
 455         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 456         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 457         true alternative.
 458
 459         * configure.in (sim_default_gen, sim_use_gen): Replace with
 460         sim_gen.
 461         (--enable-sim-igen): Delete config option. Always using IGEN.
 462         * configure: Re-generate.
 463
 464         * Makefile.in (gencode): Kill, kill, kill.
 465         * gencode.c: Ditto.
 466
 467 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 468
 469         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 470         bit mips16 igen simulator.
 471         * configure: Re-generate.
 472
 473         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 474         as part of vr4100 ISA.
 475         * vr.igen: Mark all instructions as 64 bit only.
 476
 477 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 478
 479         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 480         Pacify GCC.
 481
 482 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 483
 484         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 485         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 486         * configure: Re-generate.
 487
 488         * m16.igen (BREAK): Define breakpoint instruction.
 489         (JALX32): Mark instruction as mips16 and not r3900.
 490         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 491
 492         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 493
 494 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 495
 496         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 497         insn as a debug breakpoint.
 498
 499         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 500         pending.slot_size.
 501         (PENDING_SCHED): Clean up trace statement.
 502         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 503         (PENDING_FILL): Delay write by only one cycle.
 504         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 505
 506         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 507         of pending writes.
 508         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 509         32 & 64.
 510         (pending_tick): Move incrementing of index to FOR statement.
 511         (pending_tick): Only update PENDING_OUT after a write has occured.
 512
 513         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 514         build simulator.
 515         * configure: Re-generate.
 516
 517         * interp.c (sim_engine_run OLD): Delete explicit call to
 518         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 519
 520 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 521
 522         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 523         interrupt level number to match changed SignalExceptionInterrupt
 524         macro.
 525
 526 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 527
 528         * interp.c: #include "itable.h" if WITH_IGEN.
 529         (get_insn_name): New function.
 530         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 531         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 532
 533 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 534
 535         * configure: Rebuilt to inhale new common/aclocal.m4.
 536
 537 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 538
 539         * dv-tx3904sio.c: Include sim-assert.h.
 540
 541 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 542
 543         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 544         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 545         Reorganize target-specific sim-hardware checks.
 546         * configure: rebuilt.
 547         * interp.c (sim_open): For tx39 target boards, set
 548         OPERATING_ENVIRONMENT, add tx3904sio devices.
 549         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 550         ROM executables.  Install dv-sockser into sim-modules list.
 551
 552         * dv-tx3904irc.c: Compiler warning clean-up.
 553         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 554         frequent hw-trace messages.
 555
 556 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 557
 558         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 559
 560 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 561
 562         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 563
 564         * vr.igen: New file.
 565         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 566         * mips.igen: Define vr4100 model. Include vr.igen.
 567 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 568
 569         * mips.igen (check_mf_hilo): Correct check.
 570
 571 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 572
 573         * sim-main.h (interrupt_event): Add prototype.
 574
 575         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 576         register_ptr, register_value.
 577         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 578
 579         * sim-main.h (tracefh): Make extern.
 580
 581 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 582
 583         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 584         Reduce unnecessarily high timer event frequency.
 585         * dv-tx3904cpu.c: Ditto for interrupt event.
 586
 587 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 588
 589         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 590         to allay warnings.
 591         (interrupt_event): Made non-static.
 592
 593         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 594         interchange of configuration values for external vs. internal
 595         clock dividers.
 596
 597 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 598
 599         * mips.igen (BREAK): Moved code to here for
 600         simulator-reserved break instructions.
 601         * gencode.c (build_instruction): Ditto.
 602         * interp.c (signal_exception): Code moved from here.  Non-
 603         reserved instructions now use exception vector, rather
 604         than halting sim.
 605         * sim-main.h: Moved magic constants to here.
 606
 607 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 608
 609         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 610         register upon non-zero interrupt event level, clear upon zero
 611         event value.
 612         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 613         by passing zero event value.
 614         (*_io_{read,write}_buffer): Endianness fixes.
 615         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 616         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 617
 618         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 619         serial I/O and timer module at base address 0xFFFF0000.
 620
 621 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 622
 623         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 624         and BigEndianCPU.
 625
 626 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 627
 628         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 629         parts.
 630         * configure: Update.
 631
 632 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 633
 634         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 635         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 636         * configure.in: Include tx3904tmr in hw_device list.
 637         * configure: Rebuilt.
 638         * interp.c (sim_open): Instantiate three timer instances.
 639         Fix address typo of tx3904irc instance.
 640
 641 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 642
 643         * interp.c (signal_exception): SystemCall exception now uses
 644         the exception vector.
 645
 646 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 647
 648         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 649         to allay warnings.
 650
 651 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 652
 653         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 654
 655 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 656
 657         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 658
 659         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 660         sim-main.h. Declare a struct hw_descriptor instead of struct
 661         hw_device_descriptor.
 662
 663 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 664
 665         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 666         right bits and then re-align left hand bytes to correct byte
 667         lanes.  Fix incorrect computation in do_store_left when loading
 668         bytes from second word.
 669
 670 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 671
 672         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 673         * interp.c (sim_open): Only create a device tree when HW is
 674         enabled.
 675
 676         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 677         * interp.c (signal_exception): Ditto.
 678
 679 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 680
 681         * gencode.c: Mark BEGEZALL as LIKELY.
 682
 683 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 684
 685         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 686         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 687
 688 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 689
 690         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 691         modules.  Recognize TX39 target with "mips*tx39" pattern.
 692         * configure: Rebuilt.
 693         * sim-main.h (*): Added many macros defining bits in
 694         TX39 control registers.
 695         (SignalInterrupt): Send actual PC instead of NULL.
 696         (SignalNMIReset): New exception type.
 697         * interp.c (board): New variable for future use to identify
 698         a particular board being simulated.
 699         (mips_option_handler,mips_options): Added "--board" option.
 700         (interrupt_event): Send actual PC.
 701         (sim_open): Make memory layout conditional on board setting.
 702         (signal_exception): Initial implementation of hardware interrupt
 703         handling.  Accept another break instruction variant for simulator
 704         exit.
 705         (decode_coproc): Implement RFE instruction for TX39.
 706         (mips.igen): Decode RFE instruction as such.
 707         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 708         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 709         bbegin to implement memory map.
 710         * dv-tx3904cpu.c: New file.
 711         * dv-tx3904irc.c: New file.
 712
 713 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 714
 715         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 716
 717 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 718
 719         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 720         with calls to check_div_hilo.
 721
 722 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 723
 724         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 725         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 726         Add special r3900 version of do_mult_hilo.
 727         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 728         with calls to check_mult_hilo.
 729         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 730         with calls to check_div_hilo.
 731
 732 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 733
 734         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 735         Document a replacement.
 736
 737 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 738
 739         * interp.c (sim_monitor): Make mon_printf work.
 740
 741 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 742
 743         * sim-main.h (INSN_NAME): New arg `cpu'.
 744
 745 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 746
 747         * configure: Regenerated to track ../common/aclocal.m4 changes.
 748
 749 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 750
 751         * configure: Regenerated to track ../common/aclocal.m4 changes.
 752         * config.in: Ditto.
 753
 754 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 755
 756         * acconfig.h: New file.
 757         * configure.in: Reverted change of Apr 24; use sinclude again.
 758
 759 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 760
 761         * configure: Regenerated to track ../common/aclocal.m4 changes.
 762         * config.in: Ditto.
 763
 764 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 765
 766         * configure.in: Don't call sinclude.
 767
 768 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 769
 770         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 771
 772 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 773
 774         * mips.igen (ERET): Implement.
 775
 776         * interp.c (decode_coproc): Return sign-extended EPC.
 777
 778         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 779
 780         * interp.c (signal_exception): Do not ignore Trap.
 781         (signal_exception): On TRAP, restart at exception address.
 782         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 783         (signal_exception): Update.
 784         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 785         so that TRAP instructions are caught.
 786
 787 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 788
 789         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 790         contains HI/LO access history.
 791         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 792         (HIACCESS, LOACCESS): Delete, replace with
 793         (HIHISTORY, LOHISTORY): New macros.
 794         (CHECKHILO): Delete all, moved to mips.igen
 795
 796         * gencode.c (build_instruction): Do not generate checks for
 797         correct HI/LO register usage.
 798
 799         * interp.c (old_engine_run): Delete checks for correct HI/LO
 800         register usage.
 801
 802         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 803         check_mf_cycles): New functions.
 804         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 805         do_divu, domultx, do_mult, do_multu): Use.
 806
 807         * tx.igen ("madd", "maddu"): Use.
 808
 809 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 810
 811         * mips.igen (DSRAV): Use function do_dsrav.
 812         (SRAV): Use new function do_srav.
 813
 814         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 815         (B): Sign extend 11 bit immediate.
 816         (EXT-B*): Shift 16 bit immediate left by 1.
 817         (ADDIU*): Don't sign extend immediate value.
 818
 819 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 820
 821         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 822
 823         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 824         functions.
 825
 826         * mips.igen (delayslot32, nullify_next_insn): New functions.
 827         (m16.igen): Always include.
 828         (do_*): Add more tracing.
 829
 830         * m16.igen (delayslot16): Add NIA argument, could be called by a
 831         32 bit MIPS16 instruction.
 832
 833         * interp.c (ifetch16): Move function from here.
 834         * sim-main.c (ifetch16): To here.
 835
 836         * sim-main.c (ifetch16, ifetch32): Update to match current
 837         implementations of LH, LW.
 838         (signal_exception): Don't print out incorrect hex value of illegal
 839         instruction.
 840
 841 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 842
 843         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 844         instruction.
 845
 846         * m16.igen: Implement MIPS16 instructions.
 847
 848         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 849         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 850         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 851         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 852         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 853         bodies of corresponding code from 32 bit insn to these.  Also used
 854         by MIPS16 versions of functions.
 855
 856         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 857         (IMEM16): Drop NR argument from macro.
 858
 859 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 860
 861         * Makefile.in (SIM_OBJS): Add sim-main.o.
 862
 863         * sim-main.h (address_translation, load_memory, store_memory,
 864         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 865         as INLINE_SIM_MAIN.
 866         (pr_addr, pr_uword64): Declare.
 867         (sim-main.c): Include when H_REVEALS_MODULE_P.
 868
 869         * interp.c (address_translation, load_memory, store_memory,
 870         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 871         from here.
 872         * sim-main.c: To here. Fix compilation problems.
 873
 874         * configure.in: Enable inlining.
 875         * configure: Re-config.
 876
 877 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 878
 879         * configure: Regenerated to track ../common/aclocal.m4 changes.
 880
 881 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 882
 883         * mips.igen: Include tx.igen.
 884         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 885         * tx.igen: New file, contains MADD and MADDU.
 886
 887         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 888         the hardwired constant `7'.
 889         (store_memory): Ditto.
 890         (LOADDRMASK): Move definition to sim-main.h.
 891
 892         mips.igen (MTC0): Enable for r3900.
 893         (ADDU): Add trace.
 894
 895         mips.igen (do_load_byte): Delete.
 896         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 897         do_store_right): New functions.
 898         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 899
 900         configure.in: Let the tx39 use igen again.
 901         configure: Update.
 902
 903 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 904
 905         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 906         not an address sized quantity.  Return zero for cache sizes.
 907
 908 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 909
 910         * mips.igen (r3900): r3900 does not support 64 bit integer
 911         operations.
 912
 913 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 914
 915         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 916         than igen one.
 917         * configure : Rebuild.
 918
 919 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 920
 921         * configure: Regenerated to track ../common/aclocal.m4 changes.
 922
 923 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 924
 925         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
 926
 927 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
 928
 929         * configure: Regenerated to track ../common/aclocal.m4 changes.
 930         * config.in: Regenerated to track ../common/aclocal.m4 changes.
 931
 932 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 933
 934         * configure: Regenerated to track ../common/aclocal.m4 changes.
 935
 936 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 937
 938         * interp.c (Max, Min): Comment out functions. Not yet used.
 939
 940 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 941
 942         * configure: Regenerated to track ../common/aclocal.m4 changes.
 943
 944 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
 945
 946         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 947         configurable settings for stand-alone simulator.
 948
 949         * configure.in: Added X11 search, just in case.
 950
 951         * configure: Regenerated.
 952
 953 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 954
 955         * interp.c (sim_write, sim_read, load_memory, store_memory):
 956         Replace sim_core_*_map with read_map, write_map, exec_map resp.
 957
 958 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 959
 960         * sim-main.h (GETFCC): Return an unsigned value.
 961
 962 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 963
 964         * mips.igen (DIV): Fix check for -1 / MIN_INT.
 965         (DADD): Result destination is RD not RT.
 966
 967 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 968
 969         * sim-main.h (HIACCESS, LOACCESS): Always define.
 970
 971         * mdmx.igen (Maxi, Mini): Rename Max, Min.
 972
 973         * interp.c (sim_info): Delete.
 974
 975 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
 976
 977         * interp.c (DECLARE_OPTION_HANDLER): Use it.
 978         (mips_option_handler): New argument `cpu'.
 979         (sim_open): Update call to sim_add_option_table.
 980
 981 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 982
 983         * mips.igen (CxC1): Add tracing.
 984
 985 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 986
 987         * sim-main.h (Max, Min): Declare.
 988
 989         * interp.c (Max, Min): New functions.
 990
 991         * mips.igen (BC1): Add tracing.
 992
 993 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
 994
 995         * interp.c Added memory map for stack in vr4100
 996
 997 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
 998
 999         * interp.c (load_memory): Add missing "break"'s.
1000
1001 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1002
1003         * interp.c (sim_store_register, sim_fetch_register): Pass in
1004         length parameter.  Return -1.
1005
1006 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1007
1008         * interp.c: Added hardware init hook, fixed warnings.
1009
1010 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1011
1012         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1013
1014 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1015
1016         * interp.c (ifetch16): New function.
1017
1018         * sim-main.h (IMEM32): Rename IMEM.
1019         (IMEM16_IMMED): Define.
1020         (IMEM16): Define.
1021         (DELAY_SLOT): Update.
1022
1023         * m16run.c (sim_engine_run): New file.
1024
1025         * m16.igen: All instructions except LB.
1026         (LB): Call do_load_byte.
1027         * mips.igen (do_load_byte): New function.
1028         (LB): Call do_load_byte.
1029
1030         * mips.igen: Move spec for insn bit size and high bit from here.
1031         * Makefile.in (tmp-igen, tmp-m16): To here.
1032
1033         * m16.dc: New file, decode mips16 instructions.
1034
1035         * Makefile.in (SIM_NO_ALL): Define.
1036         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1037
1038 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1039
1040         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1041         point unit to 32 bit registers.
1042         * configure: Re-generate.
1043
1044 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1045
1046         * configure.in (sim_use_gen): Make IGEN the default simulator
1047         generator for generic 32 and 64 bit mips targets.
1048         * configure: Re-generate.
1049
1050 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1051
1052         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1053         bitsize.
1054
1055         * interp.c (sim_fetch_register, sim_store_register): Read/write
1056         FGR from correct location.
1057         (sim_open): Set size of FGR's according to
1058         WITH_TARGET_FLOATING_POINT_BITSIZE.
1059
1060         * sim-main.h (FGR): Store floating point registers in a separate
1061         array.
1062
1063 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1064
1065         * configure: Regenerated to track ../common/aclocal.m4 changes.
1066
1067 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1068
1069         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1070
1071         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1072
1073         * interp.c (pending_tick): New function.  Deliver pending writes.
1074
1075         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1076         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1077         it can handle mixed sized quantites and single bits.
1078
1079 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1080
1081         * interp.c (oengine.h): Do not include when building with IGEN.
1082         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1083         (sim_info): Ditto for PROCESSOR_64BIT.
1084         (sim_monitor): Replace ut_reg with unsigned_word.
1085         (*): Ditto for t_reg.
1086         (LOADDRMASK): Define.
1087         (sim_open): Remove defunct check that host FP is IEEE compliant,
1088         using software to emulate floating point.
1089         (value_fpr, ...): Always compile, was conditional on HASFPU.
1090
1091 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1092
1093         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1094         size.
1095
1096         * interp.c (SD, CPU): Define.
1097         (mips_option_handler): Set flags in each CPU.
1098         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1099         (sim_close): Do not clear STATE, deleted anyway.
1100         (sim_write, sim_read): Assume CPU zero's vm should be used for
1101         data transfers.
1102         (sim_create_inferior): Set the PC for all processors.
1103         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1104         argument.
1105         (mips16_entry): Pass correct nr of args to store_word, load_word.
1106         (ColdReset): Cold reset all cpu's.
1107         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1108         (sim_monitor, load_memory, store_memory, signal_exception): Use
1109         `CPU' instead of STATE_CPU.
1110
1111
1112         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1113         SD or CPU_.
1114
1115         * sim-main.h (signal_exception): Add sim_cpu arg.
1116         (SignalException*): Pass both SD and CPU to signal_exception.
1117         * interp.c (signal_exception): Update.
1118
1119         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1120         Ditto
1121         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1122         address_translation): Ditto
1123         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1124
1125 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1126
1127         * configure: Regenerated to track ../common/aclocal.m4 changes.
1128
1129 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1130
1131         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1132
1133         * mips.igen (model): Map processor names onto BFD name.
1134
1135         * sim-main.h (CPU_CIA): Delete.
1136         (SET_CIA, GET_CIA): Define
1137
1138 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1139
1140         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1141         regiser.
1142
1143         * configure.in (default_endian): Configure a big-endian simulator
1144         by default.
1145         * configure: Re-generate.
1146
1147 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1148
1149         * configure: Regenerated to track ../common/aclocal.m4 changes.
1150
1151 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1152
1153         * interp.c (sim_monitor): Handle Densan monitor outbyte
1154         and inbyte functions.
1155
1156 1997-12-29  Felix Lee  <flee@cygnus.com>
1157
1158         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1159
1160 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1161
1162         * Makefile.in (tmp-igen): Arrange for $zero to always be
1163         reset to zero after every instruction.
1164
1165 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1166
1167         * configure: Regenerated to track ../common/aclocal.m4 changes.
1168         * config.in: Ditto.
1169
1170 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1171
1172         * mips.igen (MSUB): Fix to work like MADD.
1173         * gencode.c (MSUB): Similarly.
1174
1175 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1176
1177         * configure: Regenerated to track ../common/aclocal.m4 changes.
1178
1179 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1180
1181         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1182
1183 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1184
1185         * sim-main.h (sim-fpu.h): Include.
1186
1187         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1188         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1189         using host independant sim_fpu module.
1190
1191 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1192
1193         * interp.c (signal_exception): Report internal errors with SIGABRT
1194         not SIGQUIT.
1195
1196         * sim-main.h (C0_CONFIG): New register.
1197         (signal.h): No longer include.
1198
1199         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1200
1201 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1202
1203         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1204
1205 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1206
1207         * mips.igen: Tag vr5000 instructions.
1208         (ANDI): Was missing mipsIV model, fix assembler syntax.
1209         (do_c_cond_fmt): New function.
1210         (C.cond.fmt): Handle mips I-III which do not support CC field
1211         separatly.
1212         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1213         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1214         in IV3.2 spec.
1215         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1216         vr5000 which saves LO in a GPR separatly.
1217
1218         * configure.in (enable-sim-igen): For vr5000, select vr5000
1219         specific instructions.
1220         * configure: Re-generate.
1221
1222 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1223
1224         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1225
1226         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1227         fmt_uninterpreted_64 bit cases to switch.  Convert to
1228         fmt_formatted,
1229
1230         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1231
1232         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1233         as specified in IV3.2 spec.
1234         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1235
1236 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1237
1238         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1239         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1240         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1241         PENDING_FILL versions of instructions.  Simplify.
1242         (X): New function.
1243         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1244         instructions.
1245         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1246         a signed value.
1247         (MTHI, MFHI): Disable code checking HI-LO.
1248
1249         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1250         global.
1251         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1252
1253 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1254
1255         * gencode.c (build_mips16_operands): Replace IPC with cia.
1256
1257         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1258         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1259         IPC to `cia'.
1260         (UndefinedResult): Replace function with macro/function
1261         combination.
1262         (sim_engine_run): Don't save PC in IPC.
1263
1264         * sim-main.h (IPC): Delete.
1265
1266
1267         * interp.c (signal_exception, store_word, load_word,
1268         address_translation, load_memory, store_memory, cache_op,
1269         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1270         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1271         current instruction address - cia - argument.
1272         (sim_read, sim_write): Call address_translation directly.
1273         (sim_engine_run): Rename variable vaddr to cia.
1274         (signal_exception): Pass cia to sim_monitor
1275
1276         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1277         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1278         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1279
1280         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1281         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1282         SIM_ASSERT.
1283
1284         * interp.c (signal_exception): Pass restart address to
1285         sim_engine_restart.
1286
1287         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1288         idecode.o): Add dependency.
1289
1290         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1291         Delete definitions
1292         (DELAY_SLOT): Update NIA not PC with branch address.
1293         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1294
1295         * mips.igen: Use CIA not PC in branch calculations.
1296         (illegal): Call SignalException.
1297         (BEQ, ADDIU): Fix assembler.
1298
1299 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1300
1301         * m16.igen (JALX): Was missing.
1302
1303         * configure.in (enable-sim-igen): New configuration option.
1304         * configure: Re-generate.
1305
1306         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1307
1308         * interp.c (load_memory, store_memory): Delete parameter RAW.
1309         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1310         bypassing {load,store}_memory.
1311
1312         * sim-main.h (ByteSwapMem): Delete definition.
1313
1314         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1315
1316         * interp.c (sim_do_command, sim_commands): Delete mips specific
1317         commands.  Handled by module sim-options.
1318
1319         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1320         (WITH_MODULO_MEMORY): Define.
1321
1322         * interp.c (sim_info): Delete code printing memory size.
1323
1324         * interp.c (mips_size): Nee sim_size, delete function.
1325         (power2): Delete.
1326         (monitor, monitor_base, monitor_size): Delete global variables.
1327         (sim_open, sim_close): Delete code creating monitor and other
1328         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1329         manage memory regions.
1330         (load_memory, store_memory): Use sim-core for memory model.
1331
1332         * interp.c (address_translation): Delete all memory map code
1333         except line forcing 32 bit addresses.
1334
1335 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1336
1337         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1338         trace options.
1339
1340         * interp.c (logfh, logfile): Delete globals.
1341         (sim_open, sim_close): Delete code opening & closing log file.
1342         (mips_option_handler): Delete -l and -n options.
1343         (OPTION mips_options): Ditto.
1344
1345         * interp.c (OPTION mips_options): Rename option trace to dinero.
1346         (mips_option_handler): Update.
1347
1348 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1349
1350         * interp.c (fetch_str): New function.
1351         (sim_monitor): Rewrite using sim_read & sim_write.
1352         (sim_open): Check magic number.
1353         (sim_open): Write monitor vectors into memory using sim_write.
1354         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1355         (sim_read, sim_write): Simplify - transfer data one byte at a
1356         time.
1357         (load_memory, store_memory): Clarify meaning of parameter RAW.
1358
1359         * sim-main.h (isHOST): Defete definition.
1360         (isTARGET): Mark as depreciated.
1361         (address_translation): Delete parameter HOST.
1362
1363         * interp.c (address_translation): Delete parameter HOST.
1364
1365 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1366
1367         * mips.igen:
1368
1369         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1370         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1371
1372 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1373
1374         * mips.igen: Add model filter field to records.
1375
1376 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1377
1378         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1379
1380         interp.c (sim_engine_run): Do not compile function sim_engine_run
1381         when WITH_IGEN == 1.
1382
1383         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1384         target architecture.
1385
1386         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1387         igen. Replace with configuration variables sim_igen_flags /
1388         sim_m16_flags.
1389
1390         * m16.igen: New file.  Copy mips16 insns here.
1391         * mips.igen: From here.
1392
1393 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1394
1395         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1396         to top.
1397         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1398
1399 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1400
1401         * gencode.c (build_instruction): Follow sim_write's lead in using
1402         BigEndianMem instead of !ByteSwapMem.
1403
1404 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1405
1406         * configure.in (sim_gen): Dependent on target, select type of
1407         generator.  Always select old style generator.
1408
1409         configure: Re-generate.
1410
1411         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1412         targets.
1413         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1414         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1415         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1416         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1417         SIM_@sim_gen@_*, set by autoconf.
1418
1419 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1420
1421         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1422
1423         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1424         CURRENT_FLOATING_POINT instead.
1425
1426         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1427         (address_translation): Raise exception InstructionFetch when
1428         translation fails and isINSTRUCTION.
1429
1430         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1431         sim_engine_run): Change type of of vaddr and paddr to
1432         address_word.
1433         (address_translation, prefetch, load_memory, store_memory,
1434         cache_op): Change type of vAddr and pAddr to address_word.
1435
1436         * gencode.c (build_instruction): Change type of vaddr and paddr to
1437         address_word.
1438
1439 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1440
1441         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1442         macro to obtain result of ALU op.
1443
1444 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1445
1446         * interp.c (sim_info): Call profile_print.
1447
1448 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1449
1450         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1451
1452         * sim-main.h (WITH_PROFILE): Do not define, defined in
1453         common/sim-config.h.  Use sim-profile module.
1454         (simPROFILE): Delete defintion.
1455
1456         * interp.c (PROFILE): Delete definition.
1457         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1458         (sim_close): Delete code writing profile histogram.
1459         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1460         Delete.
1461         (sim_engine_run): Delete code profiling the PC.
1462
1463 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1464
1465         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1466
1467         * interp.c (sim_monitor): Make register pointers of type
1468         unsigned_word*.
1469
1470         * sim-main.h: Make registers of type unsigned_word not
1471         signed_word.
1472
1473 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1474
1475         * interp.c (sync_operation): Rename from SyncOperation, make
1476         global, add SD argument.
1477         (prefetch): Rename from Prefetch, make global, add SD argument.
1478         (decode_coproc): Make global.
1479
1480         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1481
1482         * gencode.c (build_instruction): Generate DecodeCoproc not
1483         decode_coproc calls.
1484
1485         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1486         (SizeFGR): Move to sim-main.h
1487         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1488         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1489         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1490         sim-main.h.
1491         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1492         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1493         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1494         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1495         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1496         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1497
1498         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1499         exception.
1500         (sim-alu.h): Include.
1501         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1502         (sim_cia): Typedef to instruction_address.
1503
1504 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1505
1506         * Makefile.in (interp.o): Rename generated file engine.c to
1507         oengine.c.
1508
1509         * interp.c: Update.
1510
1511 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1512
1513         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1514
1515 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1516
1517         * gencode.c (build_instruction): For "FPSQRT", output correct
1518         number of arguments to Recip.
1519
1520 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1521
1522         * Makefile.in (interp.o): Depends on sim-main.h
1523
1524         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1525
1526         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1527         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1528         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1529         STATE, DSSTATE): Define
1530         (GPR, FGRIDX, ..): Define.
1531
1532         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1533         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1534         (GPR, FGRIDX, ...): Delete macros.
1535
1536         * interp.c: Update names to match defines from sim-main.h
1537
1538 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1539
1540         * interp.c (sim_monitor): Add SD argument.
1541         (sim_warning): Delete.  Replace calls with calls to
1542         sim_io_eprintf.
1543         (sim_error): Delete. Replace calls with sim_io_error.
1544         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1545         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1546         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1547         argument.
1548         (mips_size): Rename from sim_size. Add SD argument.
1549
1550         * interp.c (simulator): Delete global variable.
1551         (callback): Delete global variable.
1552         (mips_option_handler, sim_open, sim_write, sim_read,
1553         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1554         sim_size,sim_monitor): Use sim_io_* not callback->*.
1555         (sim_open): ZALLOC simulator struct.
1556         (PROFILE): Do not define.
1557
1558 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1559
1560         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1561         support.h with corresponding code.
1562
1563         * sim-main.h (word64, uword64), support.h: Move definition to
1564         sim-main.h.
1565         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1566
1567         * support.h: Delete
1568         * Makefile.in: Update dependencies
1569         * interp.c: Do not include.
1570
1571 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1572
1573         * interp.c (address_translation, load_memory, store_memory,
1574         cache_op): Rename to from AddressTranslation et.al., make global,
1575         add SD argument
1576
1577         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1578         CacheOp): Define.
1579
1580         * interp.c (SignalException): Rename to signal_exception, make
1581         global.
1582
1583         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1584
1585         * sim-main.h (SignalException, SignalExceptionInterrupt,
1586         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1587         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1588         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1589         Define.
1590
1591         * interp.c, support.h: Use.
1592
1593 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1594
1595         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1596         to value_fpr / store_fpr. Add SD argument.
1597         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1598         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1599
1600         * sim-main.h (ValueFPR, StoreFPR): Define.
1601
1602 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1603
1604         * interp.c (sim_engine_run): Check consistency between configure
1605         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1606         and HASFPU.
1607
1608         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1609         (mips_fpu): Configure WITH_FLOATING_POINT.
1610         (mips_endian): Configure WITH_TARGET_ENDIAN.
1611         * configure: Update.
1612
1613 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1614
1615         * configure: Regenerated to track ../common/aclocal.m4 changes.
1616
1617 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1618
1619         * configure: Regenerated.
1620
1621 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1622
1623         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1624
1625 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1626
1627         * gencode.c (print_igen_insn_models): Assume certain architectures
1628         include all mips* instructions.
1629         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1630         instruction.
1631
1632         * Makefile.in (tmp.igen): Add target. Generate igen input from
1633         gencode file.
1634
1635         * gencode.c (FEATURE_IGEN): Define.
1636         (main): Add --igen option.  Generate output in igen format.
1637         (process_instructions): Format output according to igen option.
1638         (print_igen_insn_format): New function.
1639         (print_igen_insn_models): New function.
1640         (process_instructions): Only issue warnings and ignore
1641         instructions when no FEATURE_IGEN.
1642
1643 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1644
1645         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1646         MIPS targets.
1647
1648 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1649
1650         * configure: Regenerated to track ../common/aclocal.m4 changes.
1651
1652 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1653
1654         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1655         SIM_RESERVED_BITS): Delete, moved to common.
1656         (SIM_EXTRA_CFLAGS): Update.
1657
1658 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1659
1660         * configure.in: Configure non-strict memory alignment.
1661         * configure: Regenerated to track ../common/aclocal.m4 changes.
1662
1663 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1664
1665         * configure: Regenerated to track ../common/aclocal.m4 changes.
1666
1667 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1668
1669         * gencode.c (SDBBP,DERET): Added (3900) insns.
1670         (RFE): Turn on for 3900.
1671         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1672         (dsstate): Made global.
1673         (SUBTARGET_R3900): Added.
1674         (CANCELDELAYSLOT): New.
1675         (SignalException): Ignore SystemCall rather than ignore and
1676         terminate.  Add DebugBreakPoint handling.
1677         (decode_coproc): New insns RFE, DERET; and new registers Debug
1678         and DEPC protected by SUBTARGET_R3900.
1679         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1680         bits explicitly.
1681         * Makefile.in,configure.in: Add mips subtarget option.
1682         * configure: Update.
1683
1684 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1685
1686         * gencode.c: Add r3900 (tx39).
1687
1688
1689 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1690
1691         * gencode.c (build_instruction): Don't need to subtract 4 for
1692         JALR, just 2.
1693
1694 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1695
1696         * interp.c: Correct some HASFPU problems.
1697
1698 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1699
1700         * configure: Regenerated to track ../common/aclocal.m4 changes.
1701
1702 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1703
1704         * interp.c (mips_options): Fix samples option short form, should
1705         be `x'.
1706
1707 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1708
1709         * interp.c (sim_info): Enable info code.  Was just returning.
1710
1711 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1712
1713         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1714         MFC0.
1715
1716 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1717
1718         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1719         constants.
1720         (build_instruction): Ditto for LL.
1721
1722 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1723
1724         * configure: Regenerated to track ../common/aclocal.m4 changes.
1725
1726 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1727
1728         * configure: Regenerated to track ../common/aclocal.m4 changes.
1729         * config.in: Ditto.
1730
1731 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1732
1733         * interp.c (sim_open): Add call to sim_analyze_program, update
1734         call to sim_config.
1735
1736 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1737
1738         * interp.c (sim_kill): Delete.
1739         (sim_create_inferior): Add ABFD argument. Set PC from same.
1740         (sim_load): Move code initializing trap handlers from here.
1741         (sim_open): To here.
1742         (sim_load): Delete, use sim-hload.c.
1743
1744         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1745
1746 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1747
1748         * configure: Regenerated to track ../common/aclocal.m4 changes.
1749         * config.in: Ditto.
1750
1751 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1752
1753         * interp.c (sim_open): Add ABFD argument.
1754         (sim_load): Move call to sim_config from here.
1755         (sim_open): To here.  Check return status.
1756
1757 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1758
1759         * gencode.c (build_instruction): Two arg MADD should
1760         not assign result to $0.
1761
1762 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1763
1764         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1765         * sim/mips/configure.in: Regenerate.
1766
1767 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1768
1769         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1770         signed8, unsigned8 et.al. types.
1771
1772         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1773         hosts when selecting subreg.
1774
1775 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1776
1777         * interp.c (sim_engine_run): Reset the ZERO register to zero
1778         regardless of FEATURE_WARN_ZERO.
1779         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1780
1781 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1782
1783         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1784         (SignalException): For BreakPoints ignore any mode bits and just
1785         save the PC.
1786         (SignalException): Always set the CAUSE register.
1787
1788 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1789
1790         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1791         exception has been taken.
1792
1793         * interp.c: Implement the ERET and mt/f sr instructions.
1794
1795 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1796
1797         * interp.c (SignalException): Don't bother restarting an
1798         interrupt.
1799
1800 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1801
1802         * interp.c (SignalException): Really take an interrupt.
1803         (interrupt_event): Only deliver interrupts when enabled.
1804
1805 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1806
1807         * interp.c (sim_info): Only print info when verbose.
1808         (sim_info) Use sim_io_printf for output.
1809
1810 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1811
1812         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1813         mips architectures.
1814
1815 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1816
1817         * interp.c (sim_do_command): Check for common commands if a
1818         simulator specific command fails.
1819
1820 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1821
1822         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1823         and simBE when DEBUG is defined.
1824
1825 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1826
1827         * interp.c (interrupt_event): New function.  Pass exception event
1828         onto exception handler.
1829
1830         * configure.in: Check for stdlib.h.
1831         * configure: Regenerate.
1832
1833         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1834         variable declaration.
1835         (build_instruction): Initialize memval1.
1836         (build_instruction): Add UNUSED attribute to byte, bigend,
1837         reverse.
1838         (build_operands): Ditto.
1839
1840         * interp.c: Fix GCC warnings.
1841         (sim_get_quit_code): Delete.
1842
1843         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1844         * Makefile.in: Ditto.
1845         * configure: Re-generate.
1846
1847         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1848
1849 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1850
1851         * interp.c (mips_option_handler): New function parse argumes using
1852         sim-options.
1853         (myname): Replace with STATE_MY_NAME.
1854         (sim_open): Delete check for host endianness - performed by
1855         sim_config.
1856         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1857         (sim_open): Move much of the initialization from here.
1858         (sim_load): To here.  After the image has been loaded and
1859         endianness set.
1860         (sim_open): Move ColdReset from here.
1861         (sim_create_inferior): To here.
1862         (sim_open): Make FP check less dependant on host endianness.
1863
1864         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1865         run.
1866         * interp.c (sim_set_callbacks): Delete.
1867
1868         * interp.c (membank, membank_base, membank_size): Replace with
1869         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1870         (sim_open): Remove call to callback->init. gdb/run do this.
1871
1872         * interp.c: Update
1873
1874         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1875
1876         * interp.c (big_endian_p): Delete, replaced by
1877         current_target_byte_order.
1878
1879 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1880
1881         * interp.c (host_read_long, host_read_word, host_swap_word,
1882         host_swap_long): Delete. Using common sim-endian.
1883         (sim_fetch_register, sim_store_register): Use H2T.
1884         (pipeline_ticks): Delete.  Handled by sim-events.
1885         (sim_info): Update.
1886         (sim_engine_run): Update.
1887
1888 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1889
1890         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1891         reason from here.
1892         (SignalException): To here. Signal using sim_engine_halt.
1893         (sim_stop_reason): Delete, moved to common.
1894
1895 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
1896
1897         * interp.c (sim_open): Add callback argument.
1898         (sim_set_callbacks): Delete SIM_DESC argument.
1899         (sim_size): Ditto.
1900
1901 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1902
1903         * Makefile.in (SIM_OBJS): Add common modules.
1904
1905         * interp.c (sim_set_callbacks): Also set SD callback.
1906         (set_endianness, xfer_*, swap_*): Delete.
1907         (host_read_word, host_read_long, host_swap_word, host_swap_long):
1908         Change to functions using sim-endian macros.
1909         (control_c, sim_stop): Delete, use common version.
1910         (simulate): Convert into.
1911         (sim_engine_run): This function.
1912         (sim_resume): Delete.
1913
1914         * interp.c (simulation): New variable - the simulator object.
1915         (sim_kind): Delete global - merged into simulation.
1916         (sim_load): Cleanup.  Move PC assignment from here.
1917         (sim_create_inferior): To here.
1918
1919         * sim-main.h: New file.
1920         * interp.c (sim-main.h): Include.
1921
1922 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
1923
1924         * configure: Regenerated to track ../common/aclocal.m4 changes.
1925
1926 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
1927
1928         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1929
1930 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
1931
1932         * gencode.c (build_instruction): DIV instructions: check
1933         for division by zero and integer overflow before using
1934         host's division operation.
1935
1936 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
1937
1938         * Makefile.in (SIM_OBJS): Add sim-load.o.
1939         * interp.c: #include bfd.h.
1940         (target_byte_order): Delete.
1941         (sim_kind, myname, big_endian_p): New static locals.
1942         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
1943         after argument parsing.  Recognize -E arg, set endianness accordingly.
1944         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
1945         load file into simulator.  Set PC from bfd.
1946         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
1947         (set_endianness): Use big_endian_p instead of target_byte_order.
1948
1949 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1950
1951         * interp.c (sim_size): Delete prototype - conflicts with
1952         definition in remote-sim.h.  Correct definition.
1953
1954 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1955
1956         * configure: Regenerated to track ../common/aclocal.m4 changes.
1957         * config.in: Ditto.
1958
1959 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
1960
1961         * interp.c (sim_open): New arg `kind'.
1962
1963         * configure: Regenerated to track ../common/aclocal.m4 changes.
1964
1965 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1966
1967         * configure: Regenerated to track ../common/aclocal.m4 changes.
1968
1969 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
1970
1971         * interp.c (sim_open): Set optind to 0 before calling getopt.
1972
1973 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1974
1975         * configure: Regenerated to track ../common/aclocal.m4 changes.
1976
1977 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
1978
1979         * interp.c : Replace uses of pr_addr with pr_uword64
1980         where the bit length is always 64 independent of SIM_ADDR.
1981         (pr_uword64) : added.
1982
1983 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1984
1985         * configure: Re-generate.
1986
1987 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
1988
1989         * configure: Regenerate to track ../common/aclocal.m4 changes.
1990
1991 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
1992
1993         * interp.c (sim_open): New SIM_DESC result.  Argument is now
1994         in argv form.
1995         (other sim_*): New SIM_DESC argument.
1996
1997 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
1998
1999         * interp.c: Fix printing of addresses for non-64-bit targets.
2000         (pr_addr): Add function to print address based on size.
2001
2002 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2003
2004         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2005
2006 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2007
2008         * gencode.c (build_mips16_operands): Correct computation of base
2009         address for extended PC relative instruction.
2010
2011 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2012
2013         * interp.c (mips16_entry): Add support for floating point cases.
2014         (SignalException): Pass floating point cases to mips16_entry.
2015         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2016         registers.
2017         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2018         or fmt_word.
2019         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2020         and then set the state to fmt_uninterpreted.
2021         (COP_SW): Temporarily set the state to fmt_word while calling
2022         ValueFPR.
2023
2024 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2025
2026         * gencode.c (build_instruction): The high order may be set in the
2027         comparison flags at any ISA level, not just ISA 4.
2028
2029 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2030
2031         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2032         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2033         * configure.in: sinclude ../common/aclocal.m4.
2034         * configure: Regenerated.
2035
2036 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2037
2038         * configure: Rebuild after change to aclocal.m4.
2039
2040 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2041
2042         * configure configure.in Makefile.in:  Update to new configure
2043         scheme which is more compatible with WinGDB builds.
2044         * configure.in:  Improve comment on how to run autoconf.
2045         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2046         * Makefile.in:  Use autoconf substitution to install common
2047         makefile fragment.
2048
2049 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2050
2051         * gencode.c (build_instruction): Use BigEndianCPU instead of
2052         ByteSwapMem.
2053
2054 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2055
2056         * interp.c (sim_monitor): Make output to stdout visible in
2057         wingdb's I/O log window.
2058
2059 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2060
2061         * support.h: Undo previous change to SIGTRAP
2062         and SIGQUIT values.
2063
2064 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2065
2066         * interp.c (store_word, load_word): New static functions.
2067         (mips16_entry): New static function.
2068         (SignalException): Look for mips16 entry and exit instructions.
2069         (simulate): Use the correct index when setting fpr_state after
2070         doing a pending move.
2071
2072 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2073
2074         * interp.c: Fix byte-swapping code throughout to work on
2075         both little- and big-endian hosts.
2076
2077 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2078
2079         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2080         with gdb/config/i386/xm-windows.h.
2081
2082 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2083
2084         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2085         that messes up arithmetic shifts.
2086
2087 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2088
2089         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2090         SIGTRAP and SIGQUIT for _WIN32.
2091
2092 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2093
2094         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2095         force a 64 bit multiplication.
2096         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2097         destination register is 0, since that is the default mips16 nop
2098         instruction.
2099
2100 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2101
2102         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2103         (build_endian_shift): Don't check proc64.
2104         (build_instruction): Always set memval to uword64.  Cast op2 to
2105         uword64 when shifting it left in memory instructions.  Always use
2106         the same code for stores--don't special case proc64.
2107
2108         * gencode.c (build_mips16_operands): Fix base PC value for PC
2109         relative operands.
2110         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2111         jal instruction.
2112         * interp.c (simJALDELAYSLOT): Define.
2113         (JALDELAYSLOT): Define.
2114         (INDELAYSLOT, INJALDELAYSLOT): Define.
2115         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2116
2117 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2118
2119         * interp.c (sim_open): add flush_cache as a PMON routine
2120         (sim_monitor): handle flush_cache by ignoring it
2121
2122 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2123
2124         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2125         BigEndianMem.
2126         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2127         (BigEndianMem): Rename to ByteSwapMem and change sense.
2128         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2129         BigEndianMem references to !ByteSwapMem.
2130         (set_endianness): New function, with prototype.
2131         (sim_open): Call set_endianness.
2132         (sim_info): Use simBE instead of BigEndianMem.
2133         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2134         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2135         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2136         ifdefs, keeping the prototype declaration.
2137         (swap_word): Rewrite correctly.
2138         (ColdReset): Delete references to CONFIG.  Delete endianness related
2139         code; moved to set_endianness.
2140
2141 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2142
2143         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2144         * interp.c (CHECKHILO): Define away.
2145         (simSIGINT): New macro.
2146         (membank_size): Increase from 1MB to 2MB.
2147         (control_c): New function.
2148         (sim_resume): Rename parameter signal to signal_number.  Add local
2149         variable prev.  Call signal before and after simulate.
2150         (sim_stop_reason): Add simSIGINT support.
2151         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2152         functions always.
2153         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2154         if logfh is NULL.
2155         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2156         a call to sim_warning.
2157
2158 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2159
2160         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2161         16 bit instructions.
2162
2163 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2164
2165         Add support for mips16 (16 bit MIPS implementation):
2166         * gencode.c (inst_type): Add mips16 instruction encoding types.
2167         (GETDATASIZEINSN): Define.
2168         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2169         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2170         mtlo.
2171         (MIPS16_DECODE): New table, for mips16 instructions.
2172         (bitmap_val): New static function.
2173         (struct mips16_op): Define.
2174         (mips16_op_table): New table, for mips16 operands.
2175         (build_mips16_operands): New static function.
2176         (process_instructions): If PC is odd, decode a mips16
2177         instruction.  Break out instruction handling into new
2178         build_instruction function.
2179         (build_instruction): New static function, broken out of
2180         process_instructions.  Check modifiers rather than flags for SHIFT
2181         bit count and m[ft]{hi,lo} direction.
2182         (usage): Pass program name to fprintf.
2183         (main): Remove unused variable this_option_optind.  Change
2184         ``*loptarg++'' to ``loptarg++''.
2185         (my_strtoul): Parenthesize && within ||.
2186         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2187         (simulate): If PC is odd, fetch a 16 bit instruction, and
2188         increment PC by 2 rather than 4.
2189         * configure.in: Add case for mips16*-*-*.
2190         * configure: Rebuild.
2191
2192 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2193
2194         * interp.c: Allow -t to enable tracing in standalone simulator.
2195         Fix garbage output in trace file and error messages.
2196
2197 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2198
2199         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2200         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2201         * configure.in: Simplify using macros in ../common/aclocal.m4.
2202         * configure: Regenerated.
2203         * tconfig.in: New file.
2204
2205 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2206
2207         * interp.c: Fix bugs in 64-bit port.
2208         Use ansi function declarations for msvc compiler.
2209         Initialize and test file pointer in trace code.
2210         Prevent duplicate definition of LAST_EMED_REGNUM.
2211
2212 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2213
2214         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2215
2216 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2217
2218         * interp.c (SignalException): Check for explicit terminating
2219         breakpoint value.
2220         * gencode.c: Pass instruction value through SignalException()
2221         calls for Trap, Breakpoint and Syscall.
2222
2223 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2224
2225         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2226         only used on those hosts that provide it.
2227         * configure.in: Add sqrt() to list of functions to be checked for.
2228         * config.in: Re-generated.
2229         * configure: Re-generated.
2230
2231 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2232
2233         * gencode.c (process_instructions): Call build_endian_shift when
2234         expanding STORE RIGHT, to fix swr.
2235         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2236         clear the high bits.
2237         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2238         Fix float to int conversions to produce signed values.
2239
2240 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2241
2242         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2243         (process_instructions): Correct handling of nor instruction.
2244         Correct shift count for 32 bit shift instructions. Correct sign
2245         extension for arithmetic shifts to not shift the number of bits in
2246         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2247         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2248         Fix madd.
2249         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2250         It's OK to have a mult follow a mult.  What's not OK is to have a
2251         mult follow an mfhi.
2252         (Convert): Comment out incorrect rounding code.
2253
2254 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2255
2256         * interp.c (sim_monitor): Improved monitor printf
2257         simulation. Tidied up simulator warnings, and added "--log" option
2258         for directing warning message output.
2259         * gencode.c: Use sim_warning() rather than WARNING macro.
2260
2261 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2262
2263         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2264         getopt1.o, rather than on gencode.c.  Link objects together.
2265         Don't link against -liberty.
2266         (gencode.o, getopt.o, getopt1.o): New targets.
2267         * gencode.c: Include <ctype.h> and "ansidecl.h".
2268         (AND): Undefine after including "ansidecl.h".
2269         (ULONG_MAX): Define if not defined.
2270         (OP_*): Don't define macros; now defined in opcode/mips.h.
2271         (main): Call my_strtoul rather than strtoul.
2272         (my_strtoul): New static function.
2273
2274 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2275
2276         * gencode.c (process_instructions):  Generate word64 and uword64
2277         instead of `long long' and `unsigned long long' data types.
2278         * interp.c:  #include sysdep.h to get signals, and define default
2279         for SIGBUS.
2280         * (Convert):  Work around for Visual-C++ compiler bug with type
2281         conversion.
2282         * support.h:  Make things compile under Visual-C++ by using
2283         __int64 instead of `long long'.  Change many refs to long long
2284         into word64/uword64 typedefs.
2285
2286 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2287
2288         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2289         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2290         (docdir): Removed.
2291         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2292         (AC_PROG_INSTALL): Added.
2293         (AC_PROG_CC): Moved to before configure.host call.
2294         * configure: Rebuilt.
2295
2296 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2297
2298         * configure.in: Define @SIMCONF@ depending on mips target.
2299         * configure: Rebuild.
2300         * Makefile.in (run): Add @SIMCONF@ to control simulator
2301         construction.
2302         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2303         * interp.c: Remove some debugging, provide more detailed error
2304         messages, update memory accesses to use LOADDRMASK.
2305
2306 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2307
2308         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2309         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2310         stamp-h.
2311         * configure: Rebuild.
2312         * config.in: New file, generated by autoheader.
2313         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2314         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2315         HAVE_ANINT and HAVE_AINT, as appropriate.
2316         * Makefile.in (run): Use @LIBS@ rather than -lm.
2317         (interp.o): Depend upon config.h.
2318         (Makefile): Just rebuild Makefile.
2319         (clean): Remove stamp-h.
2320         (mostlyclean): Make the same as clean, not as distclean.
2321         (config.h, stamp-h): New targets.
2322
2323 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2324
2325         * interp.c (ColdReset): Fix boolean test. Make all simulator
2326         globals static.
2327
2328 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2329
2330         * interp.c (xfer_direct_word, xfer_direct_long,
2331         swap_direct_word, swap_direct_long, xfer_big_word,
2332         xfer_big_long, xfer_little_word, xfer_little_long,
2333         swap_word,swap_long): Added.
2334         * interp.c (ColdReset): Provide function indirection to
2335         host<->simulated_target transfer routines.
2336         * interp.c (sim_store_register, sim_fetch_register): Updated to
2337         make use of indirected transfer routines.
2338
2339 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2340
2341         * gencode.c (process_instructions): Ensure FP ABS instruction
2342         recognised.
2343         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2344         system call support.
2345
2346 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2347
2348         * interp.c (sim_do_command): Complain if callback structure not
2349         initialised.
2350
2351 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2352
2353         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2354         support for Sun hosts.
2355         * Makefile.in (gencode): Ensure the host compiler and libraries
2356         used for cross-hosted build.
2357
2358 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2359
2360         * interp.c, gencode.c: Some more (TODO) tidying.
2361
2362 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2363
2364         * gencode.c, interp.c: Replaced explicit long long references with
2365         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2366         * support.h (SET64LO, SET64HI): Macros added.
2367
2368 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2369
2370         * configure: Regenerate with autoconf 2.7.
2371
2372 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2373
2374         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2375         * support.h: Remove superfluous "1" from #if.
2376         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2377
2378 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2379
2380         * interp.c (StoreFPR): Control UndefinedResult() call on
2381         WARN_RESULT manifest.
2382
2383 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2384
2385         * gencode.c: Tidied instruction decoding, and added FP instruction
2386         support.
2387
2388         * interp.c: Added dineroIII, and BSD profiling support. Also
2389         run-time FP handling.
2390
2391 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2392
2393         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2394         gencode.c, interp.c, support.h: created.