sim/mips/ChangeLog

   1 start-sanitize-sky
   2 Fri Apr 17 14:50:39 1998  Frank Ch. Eigler  <fche@cygnus.com>
   3
   4         * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
   5         * interp.c (cop_[ls]q): Fixes corresponding to above.
   6
   7 end-sanitize-sky
   8 start-sanitize-sky
   9 Thu Apr 16 15:24:14 1998  Frank Ch. Eigler  <fche@cygnus.com>
  10
  11         * interp.c (decode_coproc): Adapt COP2 micro interlock to
  12         clarified specs.  Reset "M" bit; exit also on "E" bit.
  13
  14 end-sanitize-sky
  15 start-sanitize-r5900
  16 Thu Apr 16 10:40:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  17
  18         * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
  19         * mips.igen (CFC1, CTC1): R5900 des not use generic version.
  20
  21         * r5900.igen (r59fp_unpack): New function.
  22         (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
  23         RSQRT.S, SQRT.S): Use.
  24         (r59fp_zero): New function.
  25         (r59fp_overflow): Generate r5900 specific overflow value.
  26         (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
  27         to zero.
  28         (CVT.S.W, CVT.W.S): Exchange implementations.
  29
  30         * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
  31
  32 end-sanitize-r5900
  33 start-sanitize-tx19
  34 Thu Apr 16 09:14:44 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  35
  36         * configure.in (tx19, sim_use_gen): Switch to igen.
  37         * configure: Re-build.
  38
  39 end-sanitize-tx19
  40 start-sanitize-sky
  41 Wed Apr 15 12:41:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
  42
  43         * interp.c (decode_coproc): Make COP2 branch code compile after
  44         igen signature changes.
  45
  46 end-sanitize-sky
  47 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  48
  49         * mips.igen (DSRAV): Use function do_dsrav.
  50         (SRAV): Use new function do_srav.
  51
  52         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
  53         (B): Sign extend 11 bit immediate.
  54         (EXT-B*): Shift 16 bit immediate left by 1.
  55         (ADDIU*): Don't sign extend immediate value.
  56
  57 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  58
  59         * m16run.c (sim_engine_run): Restore CIA after handling an event.
  60
  61 start-sanitize-tx19
  62         * mips.igen (mtc0): Valid tx19 instruction.
  63
  64 end-sanitize-tx19
  65         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
  66         functions.
  67
  68         * mips.igen (delayslot32, nullify_next_insn): New functions.
  69         (m16.igen): Always include.
  70         (do_*): Add more tracing.
  71
  72         * m16.igen (delayslot16): Add NIA argument, could be called by a
  73         32 bit MIPS16 instruction.
  74
  75         * interp.c (ifetch16): Move function from here.
  76         * sim-main.c (ifetch16): To here.
  77
  78         * sim-main.c (ifetch16, ifetch32): Update to match current
  79         implementations of LH, LW.
  80         (signal_exception): Don't print out incorrect hex value of illegal
  81         instruction.
  82
  83 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
  84
  85         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
  86         instruction.
  87
  88         * m16.igen: Implement MIPS16 instructions.
  89
  90         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
  91         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
  92         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
  93         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
  94         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
  95         bodies of corresponding code from 32 bit insn to these.  Also used
  96         by MIPS16 versions of functions.
  97
  98         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
  99         (IMEM16): Drop NR argument from macro.
 100
 101 start-sanitize-sky
 102 Mon Apr 13 16:28:52 1998  Frank Ch. Eigler  <fche@cygnus.com>
 103
 104         * interp.c (decode_coproc): Add proper 1000000 bit-string at top
 105         of VU lower instruction.
 106
 107 end-sanitize-sky
 108 start-sanitize-sky
 109 Thu Apr  9 16:38:23 1998  Frank Ch. Eigler  <fche@cygnus.com>
 110
 111         * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
 112         instead of QUADWORD.
 113
 114         * sim-main.h: Removed attempt at allowing 128-bit access.
 115
 116 end-sanitize-sky
 117 start-sanitize-sky
 118 Wed Apr  8 18:12:13 1998  Frank Ch. Eigler  <fche@cygnus.com>
 119
 120         * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
 121
 122         * interp.c (decode_coproc): Refer to VU CIA as a "special"
 123         register, not as a "misc" register.  Aha.  Add activity
 124         assertions after VCALLMS* instructions.
 125
 126 end-sanitize-sky
 127 start-sanitize-sky
 128 Tue Apr  7 18:32:49 1998  Frank Ch. Eigler  <fche@cygnus.com>
 129
 130         * interp.c (decode_coproc): Do not apply superfluous E (end) flag
 131         to upper code of generated VU instruction.
 132
 133 end-sanitize-sky
 134 start-sanitize-sky
 135 Mon Apr  6 19:55:56 1998  Frank Ch. Eigler  <fche@cygnus.com>
 136
 137         * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
 138
 139         * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
 140         for TARGET_SKY.
 141
 142         * r5900.igen (SQC2): Thinko.
 143
 144 end-sanitize-sky
 145 start-sanitize-sky
 146 Sun Apr  5 12:05:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 147
 148         * interp.c (*): Adapt code to merged VU device & state structs.
 149         (decode_coproc): Execute COP2 each macroinstruction without
 150         pipelining, by stepping VU to completion state.  Adapted to
 151         read_vu_*_reg style of register access.
 152
 153         * mips.igen ([SL]QC2): Removed these COP2 instructions.
 154
 155         * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
 156
 157         * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
 158
 159 end-sanitize-sky
 160 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 161
 162         * Makefile.in (SIM_OBJS): Add sim-main.o.
 163
 164         * sim-main.h (address_translation, load_memory, store_memory,
 165         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 166         as INLINE_SIM_MAIN.
 167         (pr_addr, pr_uword64): Declare.
 168         (sim-main.c): Include when H_REVEALS_MODULE_P.
 169
 170         * interp.c (address_translation, load_memory, store_memory,
 171         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
 172         from here.
 173         * sim-main.c: To here. Fix compilation problems.
 174
 175         * configure.in: Enable inlining.
 176         * configure: Re-config.
 177
 178 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 179
 180         * configure: Regenerated to track ../common/aclocal.m4 changes.
 181
 182 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 183
 184         * mips.igen: Include tx.igen.
 185         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
 186         * tx.igen: New file, contains MADD and MADDU.
 187
 188         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
 189         the hardwired constant `7'.
 190         (store_memory): Ditto.
 191         (LOADDRMASK): Move definition to sim-main.h.
 192
 193         mips.igen (MTC0): Enable for r3900.
 194         (ADDU): Add trace.
 195
 196         mips.igen (do_load_byte): Delete.
 197         (do_load, do_store, do_load_left, do_load_write, do_store_left,
 198         do_store_right): New functions.
 199         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
 200
 201         configure.in: Let the tx39 use igen again.
 202         configure: Update.
 203
 204 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 205
 206         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
 207         not an address sized quantity.  Return zero for cache sizes.
 208
 209 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 210
 211         * mips.igen (r3900): r3900 does not support 64 bit integer
 212         operations.
 213
 214 start-sanitize-sky
 215 Wed Apr 1 08:20:31 1998  Frank Ch. Eigler  <fche@cygnus.com>
 216
 217         * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
 218
 219 end-sanitize-sky
 220 start-sanitize-sky
 221 Mon Mar 30 18:41:43 1998  Frank Ch. Eigler  <fche@cygnus.com>
 222
 223         * interp.c (decode_coproc): Continuing COP2 work.
 224         (cop_[ls]q): Make sky-target-only.
 225
 226         * sim-main.h (COP_[LS]Q): Make sky-target-only.
 227 end-sanitize-sky
 228 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
 229
 230         * configure.in (mipstx39*-*-*): Use gencode simulator rather
 231         than igen one.
 232         * configure : Rebuild.
 233
 234 start-sanitize-sky
 235 Sun Mar 29 17:50:11       Frank Ch. Eigler  <fche@cygnus.com>
 236
 237         * interp.c (decode_coproc): Added a missing TARGET_SKY check
 238         around COP2 implementation skeleton.
 239
 240 end-sanitize-sky
 241 start-sanitize-sky
 242 Fri Mar 27 16:19:29 1998  Frank Ch. Eigler  <fche@cygnus.com>
 243
 244         * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
 245
 246         * interp.c (sim_{load,store}_register): Use new vu[01]_device
 247         static to access VU registers.
 248         (decode_coproc): Added skeleton of sky COP2 (VU) instruction
 249         decoding.  Work in progress.
 250
 251         * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
 252         overlapping/redundant bit pattern.
 253         (LQC2, SQC2): Added *5900 COP2 instruction skeleta.  Work in
 254         progress.
 255
 256         * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
 257         status register.
 258
 259         * interp.c (cop_lq, cop_sq): New functions for future 128-bit
 260         access to coprocessor registers.
 261
 262         * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
 263 end-sanitize-sky
 264 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 265
 266         * configure: Regenerated to track ../common/aclocal.m4 changes.
 267
 268 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 269
 270         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
 271
 272 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
 273
 274         * configure: Regenerated to track ../common/aclocal.m4 changes.
 275         * config.in: Regenerated to track ../common/aclocal.m4 changes.
 276
 277 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 278
 279         * configure: Regenerated to track ../common/aclocal.m4 changes.
 280
 281 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 282
 283         * interp.c (Max, Min): Comment out functions. Not yet used.
 284
 285 start-sanitize-vr4320
 286 Wed Mar 25 10:04:13 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 287
 288         * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
 289
 290 end-sanitize-vr4320
 291 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 292
 293         * configure: Regenerated to track ../common/aclocal.m4 changes.
 294
 295 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
 296
 297         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
 298         configurable settings for stand-alone simulator.
 299
 300 start-sanitize-sky
 301         * configure.in: Added --with-sim-gpu2 option to specify path of
 302         sky GPU2 library.  Triggers -DSKY_GPU2 for sky-gpuif.c, and
 303         links/compiles stand-alone simulator with this library.
 304
 305         * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
 306 end-sanitize-sky
 307         * configure.in: Added X11 search, just in case.
 308
 309         * configure: Regenerated.
 310
 311 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 312
 313         * interp.c (sim_write, sim_read, load_memory, store_memory):
 314         Replace sim_core_*_map with read_map, write_map, exec_map resp.
 315
 316 start-sanitize-vr4320
 317 Tue Mar 10 10:32:22 1998  Gavin Koch  <gavin@cygnus.com>
 318
 319         * vr4320.igen (clz,dclz) : Added.
 320         (dmac): Replaced 99, with LO.
 321
 322 end-sanitize-vr4320
 323 start-sanitize-vr5400
 324 Fri Mar  6 08:30:58 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 325
 326         * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
 327
 328 end-sanitize-vr5400
 329 start-sanitize-vr4320
 330 Tue Mar  3 11:56:29 1998  Gavin Koch  <gavin@cygnus.com>
 331
 332         * vr4320.igen: New file.
 333         * Makefile.in (vr4320.igen) : Added.
 334         * configure.in (mips64vr4320-*-*): Added.
 335         * configure : Rebuilt.
 336         * mips.igen : Correct the bfd-names in the mips-ISA model entries.
 337         Add the vr4320 model entry and mark the vr4320 insn as necessary.
 338
 339 end-sanitize-vr4320
 340 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 341
 342         * sim-main.h (GETFCC): Return an unsigned value.
 343
 344 start-sanitize-r5900
 345         * r5900.igen: Use an unsigned array index variable `i'.
 346         (QFSRV): Ditto for variable bytes.
 347
 348 end-sanitize-r5900
 349 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 350
 351         * mips.igen (DIV): Fix check for -1 / MIN_INT.
 352         (DADD): Result destination is RD not RT.
 353
 354 start-sanitize-r5900
 355         * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
 356         (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
 357         divide.
 358
 359 end-sanitize-r5900
 360 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 361
 362         * sim-main.h (HIACCESS, LOACCESS): Always define.
 363
 364         * mdmx.igen (Maxi, Mini): Rename Max, Min.
 365
 366         * interp.c (sim_info): Delete.
 367
 368 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
 369
 370         * interp.c (DECLARE_OPTION_HANDLER): Use it.
 371         (mips_option_handler): New argument `cpu'.
 372         (sim_open): Update call to sim_add_option_table.
 373
 374 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 375
 376         * mips.igen (CxC1): Add tracing.
 377
 378 start-sanitize-r5900
 379 Wed Feb 25 13:59:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 380
 381         * r5900.igen (StoreFP): Delete.
 382         (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
 383         New functions.
 384         (rsqrt.s, sqrt.s): Implement.
 385         (r59cond): New function.
 386         (C.COND.S): Call r59cond in assembler line.
 387         (cvt.w.s, cvt.s.w): Implement.
 388
 389         * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
 390         instruction set.
 391
 392         * sim-main.h: Define an enum of r5900 FCSR bit fields.
 393
 394 end-sanitize-r5900
 395 start-sanitize-r5900
 396 Tue Feb 24 14:44:18 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 397
 398         * r5900.igen: Add tracing to all p* instructions.
 399
 400 Tue Feb 24 02:47:33 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 401
 402         * interp.c (sim_store_register, sim_fetch_register): Pull swifty
 403         to get gdb talking to re-aranged sim_cpu register structure.
 404
 405 end-sanitize-r5900
 406 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 407
 408         * sim-main.h (Max, Min): Declare.
 409
 410         * interp.c (Max, Min): New functions.
 411
 412         * mips.igen (BC1): Add tracing.
 413
 414 start-sanitize-vr5400
 415 Fri Feb 20 16:27:17 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 416
 417         * mdmx.igen: Tag all functions as requiring either with mdmx or
 418         vr5400 processor.
 419
 420 end-sanitize-vr5400
 421 start-sanitize-r5900
 422 Fri Feb 20 15:55:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 423
 424         * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
 425         to 32.
 426         (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
 427
 428         * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
 429
 430         * r5900.igen: Rewrite.
 431
 432         * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
 433         struct.
 434         (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
 435         Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
 436
 437 end-sanitize-r5900
 438 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
 439
 440         * interp.c Added memory map for stack in vr4100
 441
 442 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
 443
 444         * interp.c (load_memory): Add missing "break"'s.
 445
 446 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 447
 448         * interp.c (sim_store_register, sim_fetch_register): Pass in
 449         length parameter.  Return -1.
 450
 451 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
 452
 453         * interp.c: Added hardware init hook, fixed warnings.
 454
 455 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 456
 457         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
 458
 459 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 460
 461         * interp.c (ifetch16): New function.
 462
 463         * sim-main.h (IMEM32): Rename IMEM.
 464         (IMEM16_IMMED): Define.
 465         (IMEM16): Define.
 466         (DELAY_SLOT): Update.
 467
 468         * m16run.c (sim_engine_run): New file.
 469
 470         * m16.igen: All instructions except LB.
 471         (LB): Call do_load_byte.
 472         * mips.igen (do_load_byte): New function.
 473         (LB): Call do_load_byte.
 474
 475         * mips.igen: Move spec for insn bit size and high bit from here.
 476         * Makefile.in (tmp-igen, tmp-m16): To here.
 477
 478         * m16.dc: New file, decode mips16 instructions.
 479
 480         * Makefile.in (SIM_NO_ALL): Define.
 481         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
 482
 483 start-sanitize-tx19
 484         * m16.igen: Mark all mips16 insns as being part of the tx19 insn
 485         set.
 486
 487 end-sanitize-tx19
 488 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 489
 490         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
 491         point unit to 32 bit registers.
 492         * configure: Re-generate.
 493
 494 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 495
 496         * configure.in (sim_use_gen): Make IGEN the default simulator
 497         generator for generic 32 and 64 bit mips targets.
 498         * configure: Re-generate.
 499
 500 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 501
 502         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
 503         bitsize.
 504
 505         * interp.c (sim_fetch_register, sim_store_register): Read/write
 506         FGR from correct location.
 507         (sim_open): Set size of FGR's according to
 508         WITH_TARGET_FLOATING_POINT_BITSIZE.
 509
 510         * sim-main.h (FGR): Store floating point registers in a separate
 511         array.
 512
 513 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 514
 515         * configure: Regenerated to track ../common/aclocal.m4 changes.
 516
 517 start-sanitize-vr5400
 518         * mdmx.igen: Mark all instructions as 64bit/fp specific.
 519
 520 end-sanitize-vr5400
 521 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 522
 523         * interp.c (ColdReset): Call PENDING_INVALIDATE.
 524
 525         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
 526
 527         * interp.c (pending_tick): New function.  Deliver pending writes.
 528
 529         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
 530         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
 531         it can handle mixed sized quantites and single bits.
 532
 533 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 534
 535         * interp.c (oengine.h): Do not include when building with IGEN.
 536         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
 537         (sim_info): Ditto for PROCESSOR_64BIT.
 538         (sim_monitor): Replace ut_reg with unsigned_word.
 539         (*): Ditto for t_reg.
 540         (LOADDRMASK): Define.
 541         (sim_open): Remove defunct check that host FP is IEEE compliant,
 542         using software to emulate floating point.
 543         (value_fpr, ...): Always compile, was conditional on HASFPU.
 544
 545 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 546
 547         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
 548         size.
 549
 550         * interp.c (SD, CPU): Define.
 551         (mips_option_handler): Set flags in each CPU.
 552         (interrupt_event): Assume CPU 0 is the one being iterrupted.
 553         (sim_close): Do not clear STATE, deleted anyway.
 554         (sim_write, sim_read): Assume CPU zero's vm should be used for
 555         data transfers.
 556         (sim_create_inferior): Set the PC for all processors.
 557         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
 558         argument.
 559         (mips16_entry): Pass correct nr of args to store_word, load_word.
 560         (ColdReset): Cold reset all cpu's.
 561         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
 562         (sim_monitor, load_memory, store_memory, signal_exception): Use
 563         `CPU' instead of STATE_CPU.
 564
 565
 566         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
 567         SD or CPU_.
 568
 569         * sim-main.h (signal_exception): Add sim_cpu arg.
 570         (SignalException*): Pass both SD and CPU to signal_exception.
 571         * interp.c (signal_exception): Update.
 572
 573         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
 574         Ditto
 575         (sync_operation, prefetch, cache_op, store_memory, load_memory,
 576         address_translation): Ditto
 577         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
 578
 579 start-sanitize-vr5400
 580         * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
 581         `sd'.
 582         (ByteAlign): Use StoreFPR, pass args in correct order.
 583
 584 end-sanitize-vr5400
 585 start-sanitize-r5900
 586 Sun Feb  1 10:59:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 587
 588         * configure.in (sim_igen_filter): For r5900, configure as SMP.
 589
 590 end-sanitize-r5900
 591 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 592
 593         * configure: Regenerated to track ../common/aclocal.m4 changes.
 594
 595 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 596
 597 start-sanitize-r5900
 598         * configure.in (sim_igen_filter): For r5900, use igen.
 599         * configure: Re-generate.
 600
 601 end-sanitize-r5900
 602         * interp.c (sim_engine_run): Add `nr_cpus' argument.
 603
 604         * mips.igen (model): Map processor names onto BFD name.
 605
 606         * sim-main.h (CPU_CIA): Delete.
 607         (SET_CIA, GET_CIA): Define
 608
 609 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 610
 611         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
 612         regiser.
 613
 614         * configure.in (default_endian): Configure a big-endian simulator
 615         by default.
 616         * configure: Re-generate.
 617
 618 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
 619
 620         * configure: Regenerated to track ../common/aclocal.m4 changes.
 621
 622 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
 623
 624         * interp.c (sim_monitor): Handle Densan monitor outbyte
 625         and inbyte functions.
 626
 627 1997-12-29  Felix Lee  <flee@cygnus.com>
 628
 629         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
 630
 631 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
 632
 633         * Makefile.in (tmp-igen): Arrange for $zero to always be
 634         reset to zero after every instruction.
 635
 636 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 637
 638         * configure: Regenerated to track ../common/aclocal.m4 changes.
 639         * config.in: Ditto.
 640
 641 start-sanitize-vr5400
 642 Sat Dec 13 15:18:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 643
 644         * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
 645         bit values.
 646
 647 end-sanitize-vr5400
 648 start-sanitize-vr5400
 649 Fri Dec 12 12:26:07 1997  Jeffrey A Law  (law@cygnus.com)
 650
 651         * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
 652         vr5400 with the vr5000 as the default.
 653
 654 end-sanitize-vr5400
 655 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
 656
 657         * mips.igen (MSUB): Fix to work like MADD.
 658         * gencode.c (MSUB): Similarly.
 659
 660 start-sanitize-vr5400
 661 Tue Dec  9 12:02:12 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 662
 663         * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
 664         vr5400.
 665
 666 end-sanitize-vr5400
 667 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
 668
 669         * configure: Regenerated to track ../common/aclocal.m4 changes.
 670
 671 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 672
 673         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
 674
 675 start-sanitize-vr5400
 676         * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
 677         (value_cc, store_cc): Implement.
 678
 679         * sim-main.h: Add 8*3*8 bit accumulator.
 680
 681         * vr5400.igen: Move mdmx instructins from here
 682         * mdmx.igen: To here - new file. Add/fix missing instructions.
 683         * mips.igen: Include mdmx.igen.
 684         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 685
 686 end-sanitize-vr5400
 687 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 688
 689         * sim-main.h (sim-fpu.h): Include.
 690
 691         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
 692         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
 693         using host independant sim_fpu module.
 694
 695 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 696
 697         * interp.c (signal_exception): Report internal errors with SIGABRT
 698         not SIGQUIT.
 699
 700         * sim-main.h (C0_CONFIG): New register.
 701         (signal.h): No longer include.
 702
 703         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
 704
 705 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
 706
 707         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
 708
 709 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 710
 711         * mips.igen: Tag vr5000 instructions.
 712         (ANDI): Was missing mipsIV model, fix assembler syntax.
 713         (do_c_cond_fmt): New function.
 714         (C.cond.fmt): Handle mips I-III which do not support CC field
 715         separatly.
 716         (bc1): Handle mips IV which do not have a delaed FCC separatly.
 717         (SDR): Mask paddr when BigEndianMem, not the converse as specified
 718         in IV3.2 spec.
 719         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
 720         vr5000 which saves LO in a GPR separatly.
 721
 722         * configure.in (enable-sim-igen): For vr5000, select vr5000
 723         specific instructions.
 724         * configure: Re-generate.
 725
 726 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 727
 728         * Makefile.in (SIM_OBJS): Add sim-fpu module.
 729
 730         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
 731         fmt_uninterpreted_64 bit cases to switch.  Convert to
 732         fmt_formatted,
 733
 734         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
 735
 736         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
 737         as specified in IV3.2 spec.
 738         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
 739
 740 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 741
 742         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
 743         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
 744         (start-sanitize-r5900):
 745         (LWXC1, SWXC1): Delete from r5900 instruction set.
 746         (end-sanitize-r5900):
 747         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
 748         PENDING_FILL versions of instructions.  Simplify.
 749         (X): New function.
 750         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
 751         instructions.
 752         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
 753         a signed value.
 754         (MTHI, MFHI): Disable code checking HI-LO.
 755
 756         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
 757         global.
 758         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
 759
 760 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 761
 762         * gencode.c (build_mips16_operands): Replace IPC with cia.
 763
 764         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
 765         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
 766         IPC to `cia'.
 767         (UndefinedResult): Replace function with macro/function
 768         combination.
 769         (sim_engine_run): Don't save PC in IPC.
 770
 771         * sim-main.h (IPC): Delete.
 772
 773         start-sanitize-vr5400
 774         * vr5400.igen (vr): Add missing cia argument to value_fpr.
 775         (do_select): Rename function select.
 776         end-sanitize-vr5400
 777
 778         * interp.c (signal_exception, store_word, load_word,
 779         address_translation, load_memory, store_memory, cache_op,
 780         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
 781         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
 782         current instruction address - cia - argument.
 783         (sim_read, sim_write): Call address_translation directly.
 784         (sim_engine_run): Rename variable vaddr to cia.
 785         (signal_exception): Pass cia to sim_monitor
 786
 787         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
 788         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
 789         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
 790
 791         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
 792         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
 793         SIM_ASSERT.
 794
 795         * interp.c (signal_exception): Pass restart address to
 796         sim_engine_restart.
 797
 798         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
 799         idecode.o): Add dependency.
 800
 801         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
 802         Delete definitions
 803         (DELAY_SLOT): Update NIA not PC with branch address.
 804         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
 805
 806         * mips.igen: Use CIA not PC in branch calculations.
 807         (illegal): Call SignalException.
 808         (BEQ, ADDIU): Fix assembler.
 809
 810 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 811
 812         * m16.igen (JALX): Was missing.
 813
 814         * configure.in (enable-sim-igen): New configuration option.
 815         * configure: Re-generate.
 816
 817         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
 818
 819         * interp.c (load_memory, store_memory): Delete parameter RAW.
 820         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
 821         bypassing {load,store}_memory.
 822
 823         * sim-main.h (ByteSwapMem): Delete definition.
 824
 825         * Makefile.in (SIM_OBJS): Add sim-memopt module.
 826
 827         * interp.c (sim_do_command, sim_commands): Delete mips specific
 828         commands.  Handled by module sim-options.
 829
 830         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
 831         (WITH_MODULO_MEMORY): Define.
 832
 833         * interp.c (sim_info): Delete code printing memory size.
 834
 835         * interp.c (mips_size): Nee sim_size, delete function.
 836         (power2): Delete.
 837         (monitor, monitor_base, monitor_size): Delete global variables.
 838         (sim_open, sim_close): Delete code creating monitor and other
 839         memory regions.  Use sim-memopts module, via sim_do_commandf, to
 840         manage memory regions.
 841         (load_memory, store_memory): Use sim-core for memory model.
 842
 843         * interp.c (address_translation): Delete all memory map code
 844         except line forcing 32 bit addresses.
 845
 846 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 847
 848         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
 849         trace options.
 850
 851         * interp.c (logfh, logfile): Delete globals.
 852         (sim_open, sim_close): Delete code opening & closing log file.
 853         (mips_option_handler): Delete -l and -n options.
 854         (OPTION mips_options): Ditto.
 855
 856         * interp.c (OPTION mips_options): Rename option trace to dinero.
 857         (mips_option_handler): Update.
 858
 859 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 860
 861         * interp.c (fetch_str): New function.
 862         (sim_monitor): Rewrite using sim_read & sim_write.
 863         (sim_open): Check magic number.
 864         (sim_open): Write monitor vectors into memory using sim_write.
 865         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
 866         (sim_read, sim_write): Simplify - transfer data one byte at a
 867         time.
 868         (load_memory, store_memory): Clarify meaning of parameter RAW.
 869
 870         * sim-main.h (isHOST): Defete definition.
 871         (isTARGET): Mark as depreciated.
 872         (address_translation): Delete parameter HOST.
 873
 874         * interp.c (address_translation): Delete parameter HOST.
 875
 876 start-sanitize-tx49
 877 Wed Oct 29 14:21:32 1997  Gavin Koch  <gavin@cygnus.com>
 878
 879         * gencode.c: Add tx49 configury and insns.
 880         * configure.in: Add tx49 configury.
 881         * configure: Update.
 882
 883 end-sanitize-tx49
 884 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 885
 886         * mips.igen:
 887
 888         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
 889         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
 890
 891 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 892
 893         * mips.igen: Add model filter field to records.
 894
 895 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 896
 897         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
 898
 899         interp.c (sim_engine_run): Do not compile function sim_engine_run
 900         when WITH_IGEN == 1.
 901
 902         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
 903         target architecture.
 904
 905         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
 906         igen. Replace with configuration variables sim_igen_flags /
 907         sim_m16_flags.
 908
 909         start-sanitize-r5900
 910         * r5900.igen: New file. Copy r5900 insns here.
 911         end-sanitize-r5900
 912         start-sanitize-vr5400
 913         * vr5400.igen: New file.
 914         end-sanitize-vr5400
 915         * m16.igen: New file.  Copy mips16 insns here.
 916         * mips.igen: From here.
 917
 918 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 919
 920         start-sanitize-vr5400
 921         * mips.igen: Tag all mipsIV instructions with vr5400 model.
 922
 923         * configure.in: Add mips64vr5400 target.
 924         * configure: Re-generate.
 925
 926         end-sanitize-vr5400
 927         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
 928         to top.
 929         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
 930
 931 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
 932
 933         * gencode.c (build_instruction): Follow sim_write's lead in using
 934         BigEndianMem instead of !ByteSwapMem.
 935
 936 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 937
 938         * configure.in (sim_gen): Dependent on target, select type of
 939         generator.  Always select old style generator.
 940
 941         configure: Re-generate.
 942
 943         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
 944         targets.
 945         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
 946         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
 947         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
 948         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
 949         SIM_@sim_gen@_*, set by autoconf.
 950
 951 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 952
 953         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
 954
 955         * interp.c (ColdReset): Remove #ifdef HASFPU, check
 956         CURRENT_FLOATING_POINT instead.
 957
 958         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
 959         (address_translation): Raise exception InstructionFetch when
 960         translation fails and isINSTRUCTION.
 961
 962         * interp.c (sim_open, sim_write, sim_monitor, store_word,
 963         sim_engine_run): Change type of of vaddr and paddr to
 964         address_word.
 965         (address_translation, prefetch, load_memory, store_memory,
 966         cache_op): Change type of vAddr and pAddr to address_word.
 967
 968         * gencode.c (build_instruction): Change type of vaddr and paddr to
 969         address_word.
 970
 971 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 972
 973         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
 974         macro to obtain result of ALU op.
 975
 976 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 977
 978         * interp.c (sim_info): Call profile_print.
 979
 980 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 981
 982         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
 983
 984         * sim-main.h (WITH_PROFILE): Do not define, defined in
 985         common/sim-config.h.  Use sim-profile module.
 986         (simPROFILE): Delete defintion.
 987
 988         * interp.c (PROFILE): Delete definition.
 989         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
 990         (sim_close): Delete code writing profile histogram.
 991         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
 992         Delete.
 993         (sim_engine_run): Delete code profiling the PC.
 994
 995 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 996
 997         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
 998
 999         * interp.c (sim_monitor): Make register pointers of type
1000         unsigned_word*.
1001
1002         * sim-main.h: Make registers of type unsigned_word not
1003         signed_word.
1004
1005 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1006
1007 start-sanitize-r5900
1008         * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1009         ...): Move to sim-main.h
1010
1011 end-sanitize-r5900
1012         * interp.c (sync_operation): Rename from SyncOperation, make
1013         global, add SD argument.
1014         (prefetch): Rename from Prefetch, make global, add SD argument.
1015         (decode_coproc): Make global.
1016
1017         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1018
1019         * gencode.c (build_instruction): Generate DecodeCoproc not
1020         decode_coproc calls.
1021
1022         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1023         (SizeFGR): Move to sim-main.h
1024         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1025         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1026         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1027         sim-main.h.
1028         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1029         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1030         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1031         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1032         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1033         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1034
1035         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1036         exception.
1037         (sim-alu.h): Include.
1038         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1039         (sim_cia): Typedef to instruction_address.
1040
1041 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1042
1043         * Makefile.in (interp.o): Rename generated file engine.c to
1044         oengine.c.
1045
1046         * interp.c: Update.
1047
1048 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1049
1050         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1051
1052 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1053
1054         * gencode.c (build_instruction): For "FPSQRT", output correct
1055         number of arguments to Recip.
1056
1057 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1058
1059         * Makefile.in (interp.o): Depends on sim-main.h
1060
1061         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1062
1063         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1064         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1065         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1066         STATE, DSSTATE): Define
1067         (GPR, FGRIDX, ..): Define.
1068
1069         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1070         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1071         (GPR, FGRIDX, ...): Delete macros.
1072
1073         * interp.c: Update names to match defines from sim-main.h
1074
1075 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1076
1077         * interp.c (sim_monitor): Add SD argument.
1078         (sim_warning): Delete.  Replace calls with calls to
1079         sim_io_eprintf.
1080         (sim_error): Delete. Replace calls with sim_io_error.
1081         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1082         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1083         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1084         argument.
1085         (mips_size): Rename from sim_size. Add SD argument.
1086
1087         * interp.c (simulator): Delete global variable.
1088         (callback): Delete global variable.
1089         (mips_option_handler, sim_open, sim_write, sim_read,
1090         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1091         sim_size,sim_monitor): Use sim_io_* not callback->*.
1092         (sim_open): ZALLOC simulator struct.
1093         (PROFILE): Do not define.
1094
1095 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1096
1097         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1098         support.h with corresponding code.
1099
1100         * sim-main.h (word64, uword64), support.h: Move definition to
1101         sim-main.h.
1102         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1103
1104         * support.h: Delete
1105         * Makefile.in: Update dependencies
1106         * interp.c: Do not include.
1107
1108 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1109
1110         * interp.c (address_translation, load_memory, store_memory,
1111         cache_op): Rename to from AddressTranslation et.al., make global,
1112         add SD argument
1113
1114         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1115         CacheOp): Define.
1116
1117         * interp.c (SignalException): Rename to signal_exception, make
1118         global.
1119
1120         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1121
1122         * sim-main.h (SignalException, SignalExceptionInterrupt,
1123         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1124         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1125         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1126         Define.
1127
1128         * interp.c, support.h: Use.
1129
1130 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1131
1132         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1133         to value_fpr / store_fpr. Add SD argument.
1134         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1135         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1136
1137         * sim-main.h (ValueFPR, StoreFPR): Define.
1138
1139 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1140
1141         * interp.c (sim_engine_run): Check consistency between configure
1142         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1143         and HASFPU.
1144
1145         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1146         (mips_fpu): Configure WITH_FLOATING_POINT.
1147         (mips_endian): Configure WITH_TARGET_ENDIAN.
1148         * configure: Update.
1149
1150 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1151
1152         * configure: Regenerated to track ../common/aclocal.m4 changes.
1153
1154 start-sanitize-r5900
1155 Mon Aug 25 19:11:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1156
1157         * interp.c (MAX_REG): Allow up-to 128 registers.
1158         (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1159         (REGISTER_SA): Ditto.
1160         (sim_open): Initialize register_widths for r5900 specific
1161         registers.
1162         (sim_fetch_register, sim_store_register): Check for request of
1163         r5900 specific SA register.  Check for request for hi 64 bits of
1164         r5900 specific registers.
1165
1166 end-sanitize-r5900
1167 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1168
1169         * configure: Regenerated.
1170
1171 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1172
1173         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1174
1175 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1176
1177         * gencode.c (print_igen_insn_models): Assume certain architectures
1178         include all mips* instructions.
1179         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1180         instruction.
1181
1182         * Makefile.in (tmp.igen): Add target. Generate igen input from
1183         gencode file.
1184
1185         * gencode.c (FEATURE_IGEN): Define.
1186         (main): Add --igen option.  Generate output in igen format.
1187         (process_instructions): Format output according to igen option.
1188         (print_igen_insn_format): New function.
1189         (print_igen_insn_models): New function.
1190         (process_instructions): Only issue warnings and ignore
1191         instructions when no FEATURE_IGEN.
1192
1193 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1194
1195         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1196         MIPS targets.
1197
1198 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1199
1200         * configure: Regenerated to track ../common/aclocal.m4 changes.
1201
1202 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1203
1204         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1205         SIM_RESERVED_BITS): Delete, moved to common.
1206         (SIM_EXTRA_CFLAGS): Update.
1207
1208 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1209
1210         * configure.in: Configure non-strict memory alignment.
1211         * configure: Regenerated to track ../common/aclocal.m4 changes.
1212
1213 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1214
1215         * configure: Regenerated to track ../common/aclocal.m4 changes.
1216
1217 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1218
1219         * gencode.c (SDBBP,DERET): Added (3900) insns.
1220         (RFE): Turn on for 3900.
1221         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1222         (dsstate): Made global.
1223         (SUBTARGET_R3900): Added.
1224         (CANCELDELAYSLOT): New.
1225         (SignalException): Ignore SystemCall rather than ignore and
1226         terminate.  Add DebugBreakPoint handling.
1227         (decode_coproc): New insns RFE, DERET; and new registers Debug
1228         and DEPC protected by SUBTARGET_R3900.
1229         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1230         bits explicitly.
1231         * Makefile.in,configure.in: Add mips subtarget option.
1232         * configure: Update.
1233
1234 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1235
1236         * gencode.c: Add r3900 (tx39).
1237
1238 start-sanitize-tx19
1239         * gencode.c: Fix some configuration problems by improving
1240         the relationship between tx19 and tx39.
1241 end-sanitize-tx19
1242
1243 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1244
1245         * gencode.c (build_instruction): Don't need to subtract 4 for
1246         JALR, just 2.
1247
1248 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1249
1250         * interp.c: Correct some HASFPU problems.
1251
1252 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1253
1254         * configure: Regenerated to track ../common/aclocal.m4 changes.
1255
1256 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1257
1258         * interp.c (mips_options): Fix samples option short form, should
1259         be `x'.
1260
1261 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1262
1263         * interp.c (sim_info): Enable info code.  Was just returning.
1264
1265 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1266
1267         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1268         MFC0.
1269
1270 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1271
1272         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1273         constants.
1274         (build_instruction): Ditto for LL.
1275
1276 start-sanitize-tx19
1277 Sun Sep  7 16:05:46 1997  Gavin Koch  <gavin@cygnus.com>
1278
1279         * mips/configure.in, mips/gencode: Add tx19/r1900.
1280
1281 end-sanitize-tx19
1282 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1283
1284         * configure: Regenerated to track ../common/aclocal.m4 changes.
1285
1286 start-sanitize-r5900
1287 Mon Sep  1 18:43:30 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1288
1289         * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1290         for overflow due to ABS of MININT, set result to MAXINT.
1291         (build_instruction): For "psrlvw", signextend bit 31.
1292
1293 end-sanitize-r5900
1294 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1295
1296         * configure: Regenerated to track ../common/aclocal.m4 changes.
1297         * config.in: Ditto.
1298
1299 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1300
1301         * interp.c (sim_open): Add call to sim_analyze_program, update
1302         call to sim_config.
1303
1304 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1305
1306         * interp.c (sim_kill): Delete.
1307         (sim_create_inferior): Add ABFD argument. Set PC from same.
1308         (sim_load): Move code initializing trap handlers from here.
1309         (sim_open): To here.
1310         (sim_load): Delete, use sim-hload.c.
1311
1312         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1313
1314 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1315
1316         * configure: Regenerated to track ../common/aclocal.m4 changes.
1317         * config.in: Ditto.
1318
1319 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1320
1321         * interp.c (sim_open): Add ABFD argument.
1322         (sim_load): Move call to sim_config from here.
1323         (sim_open): To here.  Check return status.
1324
1325 start-sanitize-r5900
1326         * gencode.c (build_instruction): Do not define x8000000000000000,
1327         x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1328
1329 end-sanitize-r5900
1330 start-sanitize-r5900
1331 Mon Jul 28 19:49:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1332
1333         * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1334         "pdivuw" check for overflow due to signed divide by -1.
1335
1336 end-sanitize-r5900
1337 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1338
1339         * gencode.c (build_instruction): Two arg MADD should
1340         not assign result to $0.
1341
1342 start-sanitize-r5900
1343 Thu Jul 10 11:58:48 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1344
1345         * gencode.c (build_instruction): For "ppac5" use unsigned
1346         arrithmetic so that the sign bit doesn't smear when right shifted.
1347         (build_instruction): For "pdiv" perform sign extension when
1348         storing results in HI and LO.
1349         (build_instructions): For "pdiv" and "pdivbw" check for
1350         divide-by-zero.
1351         (build_instruction): For "pmfhl.slw" update hi part of dest
1352         register as well as low part.
1353         (build_instruction): For "pmfhl" portably handle long long values.
1354         (build_instruction): For "pmfhl.sh" correctly negative values.
1355         Store half words 2 and three in the correct place.
1356         (build_instruction): For "psllvw", sign extend value after shift.
1357
1358 end-sanitize-r5900
1359 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1360
1361         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1362         * sim/mips/configure.in: Regenerate.
1363
1364 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1365
1366         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1367         signed8, unsigned8 et.al. types.
1368
1369 start-sanitize-r5900
1370         * gencode.c (build_instruction): For PMULTU* do not sign extend
1371         registers.  Make generated code easier to debug.
1372
1373 end-sanitize-r5900
1374         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1375         hosts when selecting subreg.
1376
1377 start-sanitize-r5900
1378 Tue Jul  8 18:07:20 1997  Andrew Cagney  <cagney@andros.cygnus.com>
1379
1380         * gencode.c (type_for_data_len): For 32bit operations concerned
1381         with overflow, perform op using 64bits.
1382         (build_instruction): For PADD, always compute operation using type
1383         returned by type_for_data_len.
1384         (build_instruction): For PSUBU, when overflow, saturate to zero as
1385         actually underflow.
1386
1387 end-sanitize-r5900
1388 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1389
1390 start-sanitize-r5900
1391         * gencode.c (build_instruction): Handle "pext5" according to
1392         version 1.95 of the r5900 ISA.
1393
1394         * gencode.c (build_instruction): Handle "ppac5" according to
1395         version 1.95 of the r5900 ISA.
1396
1397 end-sanitize-r5900
1398         * interp.c (sim_engine_run): Reset the ZERO register to zero
1399         regardless of FEATURE_WARN_ZERO.
1400         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1401
1402 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1403
1404         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1405         (SignalException): For BreakPoints ignore any mode bits and just
1406         save the PC.
1407         (SignalException): Always set the CAUSE register.
1408
1409 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1410
1411         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1412         exception has been taken.
1413
1414         * interp.c: Implement the ERET and mt/f sr instructions.
1415
1416 start-sanitize-r5900
1417 Mon Jun  2 23:28:19 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1418
1419         * gencode.c (build_instruction): For paddu, extract unsigned
1420         sub-fields.
1421
1422         * gencode.c (build_instruction): Saturate padds instead of padd
1423         instructions.
1424
1425 end-sanitize-r5900
1426 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1427
1428         * interp.c (SignalException): Don't bother restarting an
1429         interrupt.
1430
1431 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1432
1433         * interp.c (SignalException): Really take an interrupt.
1434         (interrupt_event): Only deliver interrupts when enabled.
1435
1436 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1437
1438         * interp.c (sim_info): Only print info when verbose.
1439         (sim_info) Use sim_io_printf for output.
1440
1441 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1442
1443         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1444         mips architectures.
1445
1446 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1447
1448         * interp.c (sim_do_command): Check for common commands if a
1449         simulator specific command fails.
1450
1451 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1452
1453         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1454         and simBE when DEBUG is defined.
1455
1456 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1457
1458         * interp.c (interrupt_event): New function.  Pass exception event
1459         onto exception handler.
1460
1461         * configure.in: Check for stdlib.h.
1462         * configure: Regenerate.
1463
1464         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1465         variable declaration.
1466         (build_instruction): Initialize memval1.
1467         (build_instruction): Add UNUSED attribute to byte, bigend,
1468         reverse.
1469         (build_operands): Ditto.
1470
1471         * interp.c: Fix GCC warnings.
1472         (sim_get_quit_code): Delete.
1473
1474         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1475         * Makefile.in: Ditto.
1476         * configure: Re-generate.
1477
1478         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1479
1480 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1481
1482         * interp.c (mips_option_handler): New function parse argumes using
1483         sim-options.
1484         (myname): Replace with STATE_MY_NAME.
1485         (sim_open): Delete check for host endianness - performed by
1486         sim_config.
1487         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1488         (sim_open): Move much of the initialization from here.
1489         (sim_load): To here.  After the image has been loaded and
1490         endianness set.
1491         (sim_open): Move ColdReset from here.
1492         (sim_create_inferior): To here.
1493         (sim_open): Make FP check less dependant on host endianness.
1494
1495         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1496         run.
1497         * interp.c (sim_set_callbacks): Delete.
1498
1499         * interp.c (membank, membank_base, membank_size): Replace with
1500         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1501         (sim_open): Remove call to callback->init. gdb/run do this.
1502
1503         * interp.c: Update
1504
1505         * sim-main.h (SIM_HAVE_FLATMEM): Define.
1506
1507         * interp.c (big_endian_p): Delete, replaced by
1508         current_target_byte_order.
1509
1510 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1511
1512         * interp.c (host_read_long, host_read_word, host_swap_word,
1513         host_swap_long): Delete. Using common sim-endian.
1514         (sim_fetch_register, sim_store_register): Use H2T.
1515         (pipeline_ticks): Delete.  Handled by sim-events.
1516         (sim_info): Update.
1517         (sim_engine_run): Update.
1518
1519 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1520
1521         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1522         reason from here.
1523         (SignalException): To here. Signal using sim_engine_halt.
1524         (sim_stop_reason): Delete, moved to common.
1525
1526 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
1527
1528         * interp.c (sim_open): Add callback argument.
1529         (sim_set_callbacks): Delete SIM_DESC argument.
1530         (sim_size): Ditto.
1531
1532 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1533
1534         * Makefile.in (SIM_OBJS): Add common modules.
1535
1536         * interp.c (sim_set_callbacks): Also set SD callback.
1537         (set_endianness, xfer_*, swap_*): Delete.
1538         (host_read_word, host_read_long, host_swap_word, host_swap_long):
1539         Change to functions using sim-endian macros.
1540         (control_c, sim_stop): Delete, use common version.
1541         (simulate): Convert into.
1542         (sim_engine_run): This function.
1543         (sim_resume): Delete.
1544
1545         * interp.c (simulation): New variable - the simulator object.
1546         (sim_kind): Delete global - merged into simulation.
1547         (sim_load): Cleanup.  Move PC assignment from here.
1548         (sim_create_inferior): To here.
1549
1550         * sim-main.h: New file.
1551         * interp.c (sim-main.h): Include.
1552
1553 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
1554
1555         * configure: Regenerated to track ../common/aclocal.m4 changes.
1556
1557 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
1558
1559         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1560
1561 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
1562
1563         * gencode.c (build_instruction): DIV instructions: check
1564         for division by zero and integer overflow before using
1565         host's division operation.
1566
1567 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
1568
1569         * Makefile.in (SIM_OBJS): Add sim-load.o.
1570         * interp.c: #include bfd.h.
1571         (target_byte_order): Delete.
1572         (sim_kind, myname, big_endian_p): New static locals.
1573         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
1574         after argument parsing.  Recognize -E arg, set endianness accordingly.
1575         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
1576         load file into simulator.  Set PC from bfd.
1577         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
1578         (set_endianness): Use big_endian_p instead of target_byte_order.
1579
1580 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1581
1582         * interp.c (sim_size): Delete prototype - conflicts with
1583         definition in remote-sim.h.  Correct definition.
1584
1585 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1586
1587         * configure: Regenerated to track ../common/aclocal.m4 changes.
1588         * config.in: Ditto.
1589
1590 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
1591
1592         * interp.c (sim_open): New arg `kind'.
1593
1594         * configure: Regenerated to track ../common/aclocal.m4 changes.
1595
1596 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1597
1598         * configure: Regenerated to track ../common/aclocal.m4 changes.
1599
1600 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
1601
1602         * interp.c (sim_open): Set optind to 0 before calling getopt.
1603
1604 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1605
1606         * configure: Regenerated to track ../common/aclocal.m4 changes.
1607
1608 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
1609
1610         * interp.c : Replace uses of pr_addr with pr_uword64
1611         where the bit length is always 64 independent of SIM_ADDR.
1612         (pr_uword64) : added.
1613
1614 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
1615
1616         * configure: Re-generate.
1617
1618 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
1619
1620         * configure: Regenerate to track ../common/aclocal.m4 changes.
1621
1622 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
1623
1624         * interp.c (sim_open): New SIM_DESC result.  Argument is now
1625         in argv form.
1626         (other sim_*): New SIM_DESC argument.
1627
1628 start-sanitize-r5900
1629 Wed Feb 26 18:32:21 1997  Gavin Koch  <gavin@cygnus.com>
1630
1631         * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1632         Change values to avoid overloading DOUBLEWORD which is tested
1633         for all insns.
1634         * gencode.c: reinstate "offending code".
1635
1636 end-sanitize-r5900
1637 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
1638
1639         * interp.c: Fix printing of addresses for non-64-bit targets.
1640         (pr_addr): Add function to print address based on size.
1641 start-sanitize-r5900
1642         * gencode.c: #ifdef out offending code until a permanent fix
1643         can be added.  Code is causing build errors for non-5900 mips targets.
1644 end-sanitize-r5900
1645
1646 start-sanitize-r5900
1647 Thu Feb 20 10:40:24 1997  Gavin Koch  <gavin@cetus.cygnus.com>
1648
1649         * gencode.c (process_instructions): Correct test for ISA dependent
1650         architecture bits in isa field of MIPS_DECODE.
1651
1652 end-sanitize-r5900
1653 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
1654
1655         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1656
1657 start-sanitize-r5900
1658 Tue Feb 18 17:03:47 1997  Gavin Koch  <gavin@cygnus.com>
1659
1660         * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1661         PMADDUW.
1662
1663 end-sanitize-r5900
1664 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
1665
1666         * gencode.c (build_mips16_operands): Correct computation of base
1667         address for extended PC relative instruction.
1668
1669 start-sanitize-r5900
1670 Fri Feb  7 11:12:44 1997  Gavin Koch  <gavin@cygnus.com>
1671
1672         * Makefile.in, configure, configure.in, gencode.c,
1673         interp.c, support.h: add r5900.
1674
1675 end-sanitize-r5900
1676 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
1677
1678         * interp.c (mips16_entry): Add support for floating point cases.
1679         (SignalException): Pass floating point cases to mips16_entry.
1680         (ValueFPR): Don't restrict fmt_single and fmt_word to even
1681         registers.
1682         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
1683         or fmt_word.
1684         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1685         and then set the state to fmt_uninterpreted.
1686         (COP_SW): Temporarily set the state to fmt_word while calling
1687         ValueFPR.
1688
1689 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
1690
1691         * gencode.c (build_instruction): The high order may be set in the
1692         comparison flags at any ISA level, not just ISA 4.
1693
1694 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
1695
1696         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1697         COMMON_{PRE,POST}_CONFIG_FRAG instead.
1698         * configure.in: sinclude ../common/aclocal.m4.
1699         * configure: Regenerated.
1700
1701 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
1702
1703         * configure: Rebuild after change to aclocal.m4.
1704
1705 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
1706
1707         * configure configure.in Makefile.in:  Update to new configure
1708         scheme which is more compatible with WinGDB builds.
1709         * configure.in:  Improve comment on how to run autoconf.
1710         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
1711         * Makefile.in:  Use autoconf substitution to install common
1712         makefile fragment.
1713
1714 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
1715
1716         * gencode.c (build_instruction): Use BigEndianCPU instead of
1717         ByteSwapMem.
1718
1719 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
1720
1721         * interp.c (sim_monitor): Make output to stdout visible in
1722         wingdb's I/O log window.
1723
1724 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
1725
1726         * support.h: Undo previous change to SIGTRAP
1727         and SIGQUIT values.
1728
1729 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
1730
1731         * interp.c (store_word, load_word): New static functions.
1732         (mips16_entry): New static function.
1733         (SignalException): Look for mips16 entry and exit instructions.
1734         (simulate): Use the correct index when setting fpr_state after
1735         doing a pending move.
1736
1737 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
1738
1739         * interp.c: Fix byte-swapping code throughout to work on
1740         both little- and big-endian hosts.
1741
1742 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
1743
1744         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1745         with gdb/config/i386/xm-windows.h.
1746
1747 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
1748
1749         * gencode.c (build_instruction): Work around MSVC++ code gen bug
1750         that messes up arithmetic shifts.
1751
1752 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
1753
1754         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
1755         SIGTRAP and SIGQUIT for _WIN32.
1756
1757 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
1758
1759         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
1760         force a 64 bit multiplication.
1761         (build_instruction) [OR]: In mips16 mode, don't do anything if the
1762         destination register is 0, since that is the default mips16 nop
1763         instruction.
1764
1765 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
1766
1767         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
1768         (build_endian_shift): Don't check proc64.
1769         (build_instruction): Always set memval to uword64.  Cast op2 to
1770         uword64 when shifting it left in memory instructions.  Always use
1771         the same code for stores--don't special case proc64.
1772
1773         * gencode.c (build_mips16_operands): Fix base PC value for PC
1774         relative operands.
1775         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
1776         jal instruction.
1777         * interp.c (simJALDELAYSLOT): Define.
1778         (JALDELAYSLOT): Define.
1779         (INDELAYSLOT, INJALDELAYSLOT): Define.
1780         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
1781
1782 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
1783
1784         * interp.c (sim_open): add flush_cache as a PMON routine
1785         (sim_monitor): handle flush_cache by ignoring it
1786
1787 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
1788
1789         * gencode.c (build_instruction): Use !ByteSwapMem instead of
1790         BigEndianMem.
1791         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
1792         (BigEndianMem): Rename to ByteSwapMem and change sense.
1793         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
1794         BigEndianMem references to !ByteSwapMem.
1795         (set_endianness): New function, with prototype.
1796         (sim_open): Call set_endianness.
1797         (sim_info): Use simBE instead of BigEndianMem.
1798         (xfer_direct_word, xfer_direct_long, swap_direct_word,
1799         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
1800         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
1801         ifdefs, keeping the prototype declaration.
1802         (swap_word): Rewrite correctly.
1803         (ColdReset): Delete references to CONFIG.  Delete endianness related
1804         code; moved to set_endianness.
1805
1806 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
1807
1808         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
1809         * interp.c (CHECKHILO): Define away.
1810         (simSIGINT): New macro.
1811         (membank_size): Increase from 1MB to 2MB.
1812         (control_c): New function.
1813         (sim_resume): Rename parameter signal to signal_number.  Add local
1814         variable prev.  Call signal before and after simulate.
1815         (sim_stop_reason): Add simSIGINT support.
1816         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
1817         functions always.
1818         (sim_warning): Delete call to SignalException.  Do call printf_filtered
1819         if logfh is NULL.
1820         (AddressTranslation): Add #ifdef DEBUG around debugging message and
1821         a call to sim_warning.
1822
1823 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
1824
1825         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
1826         16 bit instructions.
1827
1828 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
1829
1830         Add support for mips16 (16 bit MIPS implementation):
1831         * gencode.c (inst_type): Add mips16 instruction encoding types.
1832         (GETDATASIZEINSN): Define.
1833         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
1834         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
1835         mtlo.
1836         (MIPS16_DECODE): New table, for mips16 instructions.
1837         (bitmap_val): New static function.
1838         (struct mips16_op): Define.
1839         (mips16_op_table): New table, for mips16 operands.
1840         (build_mips16_operands): New static function.
1841         (process_instructions): If PC is odd, decode a mips16
1842         instruction.  Break out instruction handling into new
1843         build_instruction function.
1844         (build_instruction): New static function, broken out of
1845         process_instructions.  Check modifiers rather than flags for SHIFT
1846         bit count and m[ft]{hi,lo} direction.
1847         (usage): Pass program name to fprintf.
1848         (main): Remove unused variable this_option_optind.  Change
1849         ``*loptarg++'' to ``loptarg++''.
1850         (my_strtoul): Parenthesize && within ||.
1851         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
1852         (simulate): If PC is odd, fetch a 16 bit instruction, and
1853         increment PC by 2 rather than 4.
1854         * configure.in: Add case for mips16*-*-*.
1855         * configure: Rebuild.
1856
1857 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
1858
1859         * interp.c: Allow -t to enable tracing in standalone simulator.
1860         Fix garbage output in trace file and error messages.
1861
1862 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
1863
1864         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
1865         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
1866         * configure.in: Simplify using macros in ../common/aclocal.m4.
1867         * configure: Regenerated.
1868         * tconfig.in: New file.
1869
1870 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
1871
1872         * interp.c: Fix bugs in 64-bit port.
1873         Use ansi function declarations for msvc compiler.
1874         Initialize and test file pointer in trace code.
1875         Prevent duplicate definition of LAST_EMED_REGNUM.
1876
1877 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
1878
1879         * interp.c (xfer_big_long): Prevent unwanted sign extension.
1880
1881 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
1882
1883         * interp.c (SignalException): Check for explicit terminating
1884         breakpoint value.
1885         * gencode.c: Pass instruction value through SignalException()
1886         calls for Trap, Breakpoint and Syscall.
1887
1888 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
1889
1890         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
1891         only used on those hosts that provide it.
1892         * configure.in: Add sqrt() to list of functions to be checked for.
1893         * config.in: Re-generated.
1894         * configure: Re-generated.
1895
1896 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
1897
1898         * gencode.c (process_instructions): Call build_endian_shift when
1899         expanding STORE RIGHT, to fix swr.
1900         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
1901         clear the high bits.
1902         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
1903         Fix float to int conversions to produce signed values.
1904
1905 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
1906
1907         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
1908         (process_instructions): Correct handling of nor instruction.
1909         Correct shift count for 32 bit shift instructions. Correct sign
1910         extension for arithmetic shifts to not shift the number of bits in
1911         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
1912         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
1913         Fix madd.
1914         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
1915         It's OK to have a mult follow a mult.  What's not OK is to have a
1916         mult follow an mfhi.
1917         (Convert): Comment out incorrect rounding code.
1918
1919 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
1920
1921         * interp.c (sim_monitor): Improved monitor printf
1922         simulation. Tidied up simulator warnings, and added "--log" option
1923         for directing warning message output.
1924         * gencode.c: Use sim_warning() rather than WARNING macro.
1925
1926 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
1927
1928         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
1929         getopt1.o, rather than on gencode.c.  Link objects together.
1930         Don't link against -liberty.
1931         (gencode.o, getopt.o, getopt1.o): New targets.
1932         * gencode.c: Include <ctype.h> and "ansidecl.h".
1933         (AND): Undefine after including "ansidecl.h".
1934         (ULONG_MAX): Define if not defined.
1935         (OP_*): Don't define macros; now defined in opcode/mips.h.
1936         (main): Call my_strtoul rather than strtoul.
1937         (my_strtoul): New static function.
1938
1939 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
1940
1941         * gencode.c (process_instructions):  Generate word64 and uword64
1942         instead of `long long' and `unsigned long long' data types.
1943         * interp.c:  #include sysdep.h to get signals, and define default
1944         for SIGBUS.
1945         * (Convert):  Work around for Visual-C++ compiler bug with type
1946         conversion.
1947         * support.h:  Make things compile under Visual-C++ by using
1948         __int64 instead of `long long'.  Change many refs to long long
1949         into word64/uword64 typedefs.
1950
1951 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
1952
1953         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
1954         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
1955         (docdir): Removed.
1956         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
1957         (AC_PROG_INSTALL): Added.
1958         (AC_PROG_CC): Moved to before configure.host call.
1959         * configure: Rebuilt.
1960
1961 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
1962
1963         * configure.in: Define @SIMCONF@ depending on mips target.
1964         * configure: Rebuild.
1965         * Makefile.in (run): Add @SIMCONF@ to control simulator
1966         construction.
1967         * gencode.c: Change LOADDRMASK to 64bit memory model only.
1968         * interp.c: Remove some debugging, provide more detailed error
1969         messages, update memory accesses to use LOADDRMASK.
1970
1971 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
1972
1973         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
1974         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
1975         stamp-h.
1976         * configure: Rebuild.
1977         * config.in: New file, generated by autoheader.
1978         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
1979         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
1980         HAVE_ANINT and HAVE_AINT, as appropriate.
1981         * Makefile.in (run): Use @LIBS@ rather than -lm.
1982         (interp.o): Depend upon config.h.
1983         (Makefile): Just rebuild Makefile.
1984         (clean): Remove stamp-h.
1985         (mostlyclean): Make the same as clean, not as distclean.
1986         (config.h, stamp-h): New targets.
1987
1988 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
1989
1990         * interp.c (ColdReset): Fix boolean test. Make all simulator
1991         globals static.
1992
1993 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
1994
1995         * interp.c (xfer_direct_word, xfer_direct_long,
1996         swap_direct_word, swap_direct_long, xfer_big_word,
1997         xfer_big_long, xfer_little_word, xfer_little_long,
1998         swap_word,swap_long): Added.
1999         * interp.c (ColdReset): Provide function indirection to
2000         host<->simulated_target transfer routines.
2001         * interp.c (sim_store_register, sim_fetch_register): Updated to
2002         make use of indirected transfer routines.
2003
2004 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2005
2006         * gencode.c (process_instructions): Ensure FP ABS instruction
2007         recognised.
2008         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2009         system call support.
2010
2011 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2012
2013         * interp.c (sim_do_command): Complain if callback structure not
2014         initialised.
2015
2016 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2017
2018         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2019         support for Sun hosts.
2020         * Makefile.in (gencode): Ensure the host compiler and libraries
2021         used for cross-hosted build.
2022
2023 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2024
2025         * interp.c, gencode.c: Some more (TODO) tidying.
2026
2027 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2028
2029         * gencode.c, interp.c: Replaced explicit long long references with
2030         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2031         * support.h (SET64LO, SET64HI): Macros added.
2032
2033 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2034
2035         * configure: Regenerate with autoconf 2.7.
2036
2037 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2038
2039         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2040         * support.h: Remove superfluous "1" from #if.
2041         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2042
2043 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2044
2045         * interp.c (StoreFPR): Control UndefinedResult() call on
2046         WARN_RESULT manifest.
2047
2048 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2049
2050         * gencode.c: Tidied instruction decoding, and added FP instruction
2051         support.
2052
2053         * interp.c: Added dineroIII, and BSD profiling support. Also
2054         run-time FP handling.
2055
2056 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2057
2058         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2059         gencode.c, interp.c, support.h: created.