sim/mips/ChangeLog

   1 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
   2
   3         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
   4         which wouldn't compile anyway.
   5         * sim-main.h (unpredictable_action): New function prototype.
   6         (Unpredictable): Define to call igen function unpredictable().
   7         (NotWordValue): New macro to call igen function not_word_value().
   8         (UndefinedResult): Remove.
   9         * interp.c (undefined_result): Remove.
  10         (unpredictable_action): New function.
  11         * mips.igen (not_word_value, unpredictable): New functions.
  12         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
  13         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
  14         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
  15         NotWordValue() to check for unpredictable inputs, then
  16         Unpredictable() to handle them.
  17
  18 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
  19
  20         * mips.igen: Fix formatting of calls to Unpredictable().
  21
  22 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
  23
  24         * interp.c (sim_open): Revert previous change.
  25
  26 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
  27
  28         * interp.c (sim_open): Disable chunk of code that wrote code in
  29         vector table entries.
  30
  31 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
  32
  33         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
  34         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
  35         unused definitions.
  36
  37 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
  38
  39         * cp1.c: Fix many formatting issues.
  40
  41 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
  42
  43         * cp1.c (fpu_format_name): New function to replace...
  44         (DOFMT): This.  Delete, and update all callers.
  45         (fpu_rounding_mode_name): New function to replace...
  46         (RMMODE): This.  Delete, and update all callers.
  47
  48 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
  49
  50         * interp.c: Move FPU support routines from here to...
  51         * cp1.c: Here.  New file.
  52         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
  53         (cp1.o): New target.
  54
  55 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
  56
  57         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
  58         * mips.igen (mips32, mips64): New models, add to all instructions
  59         and functions as appropriate.
  60         (loadstore_ea, check_u64): New variant for model mips64.
  61         (check_fmt_p): New variant for models mipsV and mips64, remove
  62         mipsV model marking fro other variant.
  63         (SLL) Rename to...
  64         (SLLa) this.
  65         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
  66         for mips32 and mips64.
  67         (DCLO, DCLZ): New instructions for mips64.
  68
  69 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
  70
  71         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
  72         immediate or code as a hex value with the "%#lx" format.
  73         (ANDI): Likewise, and fix printed instruction name.
  74
  75 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  76
  77         * sim-main.h (UndefinedResult, Unpredictable): New macros
  78         which currently do nothing.
  79
  80 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  81
  82         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
  83         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
  84         (status_CU3): New definitions.
  85
  86         * sim-main.h (ExceptionCause): Add new values for MIPS32
  87         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
  88         for DebugBreakPoint and NMIReset to note their status in
  89         MIPS32 and MIPS64.
  90         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
  91         (SignalExceptionCacheErr): New exception macros.
  92
  93 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
  94
  95         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
  96         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
  97         is always enabled.
  98         (SignalExceptionCoProcessorUnusable): Take as argument the
  99         unusable coprocessor number.
 100
 101 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 102
 103         * mips.igen: Fix formatting of all SignalException calls.
 104
 105 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 106
 107         * sim-main.h (SIGNEXTEND): Remove.
 108
 109 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 110
 111         * mips.igen: Remove gencode comment from top of file, fix
 112         spelling in another comment.
 113
 114 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 115
 116         * mips.igen (check_fmt, check_fmt_p): New functions to check
 117         whether specific floating point formats are usable.
 118         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 119         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 120         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 121         Use the new functions.
 122         (do_c_cond_fmt): Remove format checks...
 123         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 124
 125 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 126
 127         * mips.igen: Fix formatting of check_fpu calls.
 128
 129 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 130
 131         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 132
 133 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 134
 135         * mips.igen: Remove whitespace at end of lines.
 136
 137 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 138
 139         * mips.igen (loadstore_ea): New function to do effective
 140         address calculations.
 141         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 142         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 143         CACHE): Use loadstore_ea to do effective address computations.
 144
 145 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 146
 147         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 148         * mips.igen (LL, CxC1, MxC1): Likewise.
 149
 150 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 151
 152         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 153         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 154         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 155         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 156         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 157         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 158         Don't split opcode fields by hand, use the opcode field values
 159         provided by igen.
 160
 161 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 162
 163         * mips.igen (do_divu): Fix spacing.
 164
 165         * mips.igen (do_dsllv): Move to be right before DSLLV,
 166         to match the rest of the do_<shift> functions.
 167
 168 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 169
 170         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 171         DSRL32, do_dsrlv): Trace inputs and results.
 172
 173 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 174
 175         * mips.igen (CACHE): Provide instruction-printing string.
 176
 177         * interp.c (signal_exception): Comment tokens after #endif.
 178
 179 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 180
 181         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 182         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 183         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 184         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 185         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 186         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 187         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 188         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 189
 190 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 191
 192         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 193         instruction-printing string.
 194         (LWU): Use '64' as the filter flag.
 195
 196 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 197
 198         * mips.igen (SDXC1): Fix instruction-printing string.
 199
 200 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 201
 202         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 203         filter flags "32,f".
 204
 205 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 206
 207         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 208         as the filter flag.
 209
 210 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 211
 212         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 213         add a comma) so that it more closely match the MIPS ISA
 214         documentation opcode partitioning.
 215         (PREF): Put useful names on opcode fields, and include
 216         instruction-printing string.
 217
 218 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 219
 220         * mips.igen (check_u64): New function which in the future will
 221         check whether 64-bit instructions are usable and signal an
 222         exception if not.  Currently a no-op.
 223         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 224         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 225         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 226         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 227
 228         * mips.igen (check_fpu): New function which in the future will
 229         check whether FPU instructions are usable and signal an exception
 230         if not.  Currently a no-op.
 231         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 232         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 233         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 234         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 235         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 236         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 237         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 238         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 239
 240 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 241
 242         * mips.igen (do_load_left, do_load_right): Move to be immediately
 243         following do_load.
 244         (do_store_left, do_store_right): Move to be immediately following
 245         do_store.
 246
 247 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 248
 249         * mips.igen (mipsV): New model name.  Also, add it to
 250         all instructions and functions where it is appropriate.
 251
 252 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 253
 254         * mips.igen: For all functions and instructions, list model
 255         names that support that instruction one per line.
 256
 257 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 258
 259         * mips.igen: Add some additional comments about supported
 260         models, and about which instructions go where.
 261         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 262         order as is used in the rest of the file.
 263
 264 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 265
 266         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 267         indicating that ALU32_END or ALU64_END are there to check
 268         for overflow.
 269         (DADD): Likewise, but also remove previous comment about
 270         overflow checking.
 271
 272 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 273
 274         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 275         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 276         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 277         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 278         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 279         fields (i.e., add and move commas) so that they more closely
 280         match the MIPS ISA documentation opcode partitioning.
 281
 282 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 283
 284         * mips.igen (ADDI): Print immediate value.
 285         (BREAK): Print code.
 286         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 287         (SLL): Print "nop" specially, and don't run the code
 288         that does the shift for the "nop" case.
 289
 290 2001-11-17  Fred Fish  <fnf@redhat.com>
 291
 292         * sim-main.h (float_operation): Move enum declaration outside
 293         of _sim_cpu struct declaration.
 294
 295 2001-04-12  Jim Blandy  <jimb@redhat.com>
 296
 297         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 298         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 299         set of the FCSR.
 300         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 301         PENDING_FILL, and you can get the intended effect gracefully by
 302         calling PENDING_SCHED directly.
 303
 304 2001-02-23  Ben Elliston  <bje@redhat.com>
 305
 306         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 307         already defined elsewhere.
 308
 309 2001-02-19  Ben Elliston  <bje@redhat.com>
 310
 311         * sim-main.h (sim_monitor): Return an int.
 312         * interp.c (sim_monitor): Add return values.
 313         (signal_exception): Handle error conditions from sim_monitor.
 314
 315 2001-02-08  Ben Elliston  <bje@redhat.com>
 316
 317         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 318         (store_memory): Likewise, pass cia to sim_core_write*.
 319
 320 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 321
 322         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 323         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 324
 325 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 326
 327         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 328         * Makefile.in: Don't delete *.igen when cleaning directory.
 329
 330 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 331
 332         * m16.igen (break): Call SignalException not sim_engine_halt.
 333
 334 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 335
 336         From Jason Eckhardt:
 337         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 338
 339 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 340
 341         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 342
 343 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 344
 345         * mips.igen (do_dmultx): Fix typo.
 346
 347 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 348
 349         * configure: Regenerated to track ../common/aclocal.m4 changes.
 350
 351 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 352
 353         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 354
 355 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 356
 357         * sim-main.h (GPR_CLEAR): Define macro.
 358
 359 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 360
 361         * interp.c (decode_coproc): Output long using %lx and not %s.
 362
 363 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
 364
 365         * interp.c (sim_open): Sort & extend dummy memory regions for
 366         --board=jmr3904 for eCos.
 367
 368 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
 369
 370         * configure: Regenerated.
 371
 372 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
 373
 374         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
 375         calls, conditional on the simulator being in verbose mode.
 376
 377 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
 378
 379         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
 380         cache don't get ReservedInstruction traps.
 381
 382 1999-11-29  Mark Salter  <msalter@cygnus.com>
 383
 384         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
 385         to clear status bits in sdisr register. This is how the hardware works.
 386
 387         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
 388         being used by cygmon.
 389
 390 1999-11-11  Andrew Haley  <aph@cygnus.com>
 391
 392         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
 393         instructions.
 394
 395 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
 396
 397         * mips.igen (MULT): Correct previous mis-applied patch.
 398
 399 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
 400
 401         * mips.igen (delayslot32): Handle sequence like
 402         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
 403         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
 404         (MULT): Actually pass the third register...
 405
 406 1999-09-03  Mark Salter  <msalter@cygnus.com>
 407
 408         * interp.c (sim_open): Added more memory aliases for additional
 409         hardware being touched by cygmon on jmr3904 board.
 410
 411 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 412
 413         * configure: Regenerated to track ../common/aclocal.m4 changes.
 414
 415 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 416
 417         * interp.c (sim_store_register): Handle case where client - GDB -
 418         specifies that a 4 byte register is 8 bytes in size.
 419         (sim_fetch_register): Ditto.
 420
 421 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
 422
 423         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
 424         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
 425         (idt_monitor_base): Base address for IDT monitor traps.
 426         (pmon_monitor_base): Ditto for PMON.
 427         (lsipmon_monitor_base): Ditto for LSI PMON.
 428         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
 429         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
 430         (sim_firmware_command): New function.
 431         (mips_option_handler): Call it for OPTION_FIRMWARE.
 432         (sim_open): Allocate memory for idt_monitor region.  If "--board"
 433         option was given, add no monitor by default.  Add BREAK hooks only if
 434         monitors are also there.
 435
 436 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 437
 438         * interp.c (sim_monitor): Flush output before reading input.
 439
 440 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 441
 442         * tconfig.in (SIM_HANDLES_LMA): Always define.
 443
 444 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 445
 446         From Mark Salter <msalter@cygnus.com>:
 447         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
 448         (sim_open): Add setup for BSP board.
 449
 450 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
 451
 452         * mips.igen (MULT, MULTU): Add syntax for two operand version.
 453         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
 454         them as unimplemented.
 455
 456 1999-05-08  Felix Lee  <flee@cygnus.com>
 457
 458         * configure: Regenerated to track ../common/aclocal.m4 changes.
 459
 460 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
 461
 462         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
 463
 464 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
 465
 466         * configure.in: Any mips64vr5*-*-* target should have
 467         -DTARGET_ENABLE_FR=1.
 468         (default_endian): Any mips64vr*el-*-* target should default to
 469         LITTLE_ENDIAN.
 470         * configure: Re-generate.
 471
 472 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
 473
 474         * mips.igen (ldl): Extend from _16_, not 32.
 475
 476 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
 477
 478         * interp.c (sim_store_register): Force registers written to by GDB
 479         into an un-interpreted state.
 480
 481 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
 482
 483         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
 484         CPU, start periodic background I/O polls.
 485         (tx3904sio_poll): New function: periodic I/O poller.
 486
 487 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
 488
 489         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
 490
 491 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
 492
 493         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
 494         case statement.
 495
 496 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
 497
 498         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
 499         (load_word): Call SIM_CORE_SIGNAL hook on error.
 500         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
 501         starting.  For exception dispatching, pass PC instead of NULL_CIA.
 502         (decode_coproc): Use COP0_BADVADDR to store faulting address.
 503         * sim-main.h (COP0_BADVADDR): Define.
 504         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
 505         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
 506         (_sim_cpu): Add exc_* fields to store register value snapshots.
 507         * mips.igen (*): Replace memory-related SignalException* calls
 508         with references to SIM_CORE_SIGNAL hook.
 509
 510         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
 511         fix.
 512         * sim-main.c (*): Minor warning cleanups.
 513
 514 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
 515
 516         * m16.igen (DADDIU5): Correct type-o.
 517
 518 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
 519
 520         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
 521         variables.
 522
 523 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
 524
 525         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
 526         to include path.
 527         (interp.o): Add dependency on itable.h
 528         (oengine.c, gencode): Delete remaining references.
 529         (BUILT_SRC_FROM_GEN): Clean up.
 530
 531 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
 532
 533         * vr4run.c: New.
 534         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
 535         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
 536         tmp-run-hack) : New.
 537         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
 538         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
 539         Drop the "64" qualifier to get the HACK generator working.
 540         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
 541         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
 542         qualifier to get the hack generator working.
 543         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
 544         (DSLL): Use do_dsll.
 545         (DSLLV): Use do_dsllv.
 546         (DSRA): Use do_dsra.
 547         (DSRL): Use do_dsrl.
 548         (DSRLV): Use do_dsrlv.
 549         (BC1): Move *vr4100 to get the HACK generator working.
 550         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
 551         get the HACK generator working.
 552         (MACC) Rename to get the HACK generator working.
 553         (DMACC,MACCS,DMACCS): Add the 64.
 554
 555 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
 556
 557         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
 558         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
 559
 560 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
 561
 562     * mips/interp.c (DEBUG): Cleanups.
 563
 564 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
 565
 566         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
 567         (tx3904sio_tickle): fflush after a stdout character output.
 568
 569 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
 570
 571         * interp.c (sim_close): Uninstall modules.
 572
 573 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 574
 575         * sim-main.h, interp.c (sim_monitor): Change to global
 576         function.
 577
 578 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 579
 580         * configure.in (vr4100): Only include vr4100 instructions in
 581         simulator.
 582         * configure: Re-generate.
 583         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
 584
 585 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 586
 587         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
 588         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
 589         true alternative.
 590
 591         * configure.in (sim_default_gen, sim_use_gen): Replace with
 592         sim_gen.
 593         (--enable-sim-igen): Delete config option. Always using IGEN.
 594         * configure: Re-generate.
 595
 596         * Makefile.in (gencode): Kill, kill, kill.
 597         * gencode.c: Ditto.
 598
 599 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 600
 601         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
 602         bit mips16 igen simulator.
 603         * configure: Re-generate.
 604
 605         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
 606         as part of vr4100 ISA.
 607         * vr.igen: Mark all instructions as 64 bit only.
 608
 609 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 610
 611         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
 612         Pacify GCC.
 613
 614 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 615
 616         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
 617         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
 618         * configure: Re-generate.
 619
 620         * m16.igen (BREAK): Define breakpoint instruction.
 621         (JALX32): Mark instruction as mips16 and not r3900.
 622         * mips.igen (C.cond.fmt): Fix typo in instruction format.
 623
 624         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
 625
 626 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 627
 628         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
 629         insn as a debug breakpoint.
 630
 631         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
 632         pending.slot_size.
 633         (PENDING_SCHED): Clean up trace statement.
 634         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
 635         (PENDING_FILL): Delay write by only one cycle.
 636         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
 637
 638         * sim-main.c (pending_tick): Clean up trace statements. Add trace
 639         of pending writes.
 640         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
 641         32 & 64.
 642         (pending_tick): Move incrementing of index to FOR statement.
 643         (pending_tick): Only update PENDING_OUT after a write has occured.
 644
 645         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
 646         build simulator.
 647         * configure: Re-generate.
 648
 649         * interp.c (sim_engine_run OLD): Delete explicit call to
 650         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
 651
 652 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
 653
 654         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
 655         interrupt level number to match changed SignalExceptionInterrupt
 656         macro.
 657
 658 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
 659
 660         * interp.c: #include "itable.h" if WITH_IGEN.
 661         (get_insn_name): New function.
 662         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
 663         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
 664
 665 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
 666
 667         * configure: Rebuilt to inhale new common/aclocal.m4.
 668
 669 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
 670
 671         * dv-tx3904sio.c: Include sim-assert.h.
 672
 673 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
 674
 675         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
 676         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
 677         Reorganize target-specific sim-hardware checks.
 678         * configure: rebuilt.
 679         * interp.c (sim_open): For tx39 target boards, set
 680         OPERATING_ENVIRONMENT, add tx3904sio devices.
 681         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
 682         ROM executables.  Install dv-sockser into sim-modules list.
 683
 684         * dv-tx3904irc.c: Compiler warning clean-up.
 685         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
 686         frequent hw-trace messages.
 687
 688 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 689
 690         * vr.igen (MulAcc): Identify as a vr4100 specific function.
 691
 692 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 693
 694         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
 695
 696         * vr.igen: New file.
 697         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
 698         * mips.igen: Define vr4100 model. Include vr.igen.
 699 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
 700
 701         * mips.igen (check_mf_hilo): Correct check.
 702
 703 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 704
 705         * sim-main.h (interrupt_event): Add prototype.
 706
 707         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
 708         register_ptr, register_value.
 709         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
 710
 711         * sim-main.h (tracefh): Make extern.
 712
 713 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
 714
 715         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
 716         Reduce unnecessarily high timer event frequency.
 717         * dv-tx3904cpu.c: Ditto for interrupt event.
 718
 719 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
 720
 721         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
 722         to allay warnings.
 723         (interrupt_event): Made non-static.
 724
 725         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
 726         interchange of configuration values for external vs. internal
 727         clock dividers.
 728
 729 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
 730
 731         * mips.igen (BREAK): Moved code to here for
 732         simulator-reserved break instructions.
 733         * gencode.c (build_instruction): Ditto.
 734         * interp.c (signal_exception): Code moved from here.  Non-
 735         reserved instructions now use exception vector, rather
 736         than halting sim.
 737         * sim-main.h: Moved magic constants to here.
 738
 739 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
 740
 741         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
 742         register upon non-zero interrupt event level, clear upon zero
 743         event value.
 744         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
 745         by passing zero event value.
 746         (*_io_{read,write}_buffer): Endianness fixes.
 747         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
 748         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
 749
 750         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
 751         serial I/O and timer module at base address 0xFFFF0000.
 752
 753 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
 754
 755         * mips.igen (SWC1) : Correct the handling of ReverseEndian
 756         and BigEndianCPU.
 757
 758 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
 759
 760         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
 761         parts.
 762         * configure: Update.
 763
 764 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
 765
 766         * dv-tx3904tmr.c: New file - implements tx3904 timer.
 767         * dv-tx3904{irc,cpu}.c: Mild reformatting.
 768         * configure.in: Include tx3904tmr in hw_device list.
 769         * configure: Rebuilt.
 770         * interp.c (sim_open): Instantiate three timer instances.
 771         Fix address typo of tx3904irc instance.
 772
 773 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
 774
 775         * interp.c (signal_exception): SystemCall exception now uses
 776         the exception vector.
 777
 778 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
 779
 780         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
 781         to allay warnings.
 782
 783 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 784
 785         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
 786
 787 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 788
 789         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
 790
 791         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
 792         sim-main.h. Declare a struct hw_descriptor instead of struct
 793         hw_device_descriptor.
 794
 795 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 796
 797         * mips.igen (do_store_left, do_load_left): Compute nr of left and
 798         right bits and then re-align left hand bytes to correct byte
 799         lanes.  Fix incorrect computation in do_store_left when loading
 800         bytes from second word.
 801
 802 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 803
 804         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
 805         * interp.c (sim_open): Only create a device tree when HW is
 806         enabled.
 807
 808         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
 809         * interp.c (signal_exception): Ditto.
 810
 811 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
 812
 813         * gencode.c: Mark BEGEZALL as LIKELY.
 814
 815 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 816
 817         * sim-main.h (ALU32_END): Sign extend 32 bit results.
 818         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
 819
 820 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
 821
 822         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
 823         modules.  Recognize TX39 target with "mips*tx39" pattern.
 824         * configure: Rebuilt.
 825         * sim-main.h (*): Added many macros defining bits in
 826         TX39 control registers.
 827         (SignalInterrupt): Send actual PC instead of NULL.
 828         (SignalNMIReset): New exception type.
 829         * interp.c (board): New variable for future use to identify
 830         a particular board being simulated.
 831         (mips_option_handler,mips_options): Added "--board" option.
 832         (interrupt_event): Send actual PC.
 833         (sim_open): Make memory layout conditional on board setting.
 834         (signal_exception): Initial implementation of hardware interrupt
 835         handling.  Accept another break instruction variant for simulator
 836         exit.
 837         (decode_coproc): Implement RFE instruction for TX39.
 838         (mips.igen): Decode RFE instruction as such.
 839         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
 840         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
 841         bbegin to implement memory map.
 842         * dv-tx3904cpu.c: New file.
 843         * dv-tx3904irc.c: New file.
 844
 845 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
 846
 847         * mips.igen (check_mt_hilo): Create a separate r3900 version.
 848
 849 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
 850
 851         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
 852         with calls to check_div_hilo.
 853
 854 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
 855
 856         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
 857         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
 858         Add special r3900 version of do_mult_hilo.
 859         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
 860         with calls to check_mult_hilo.
 861         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
 862         with calls to check_div_hilo.
 863
 864 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 865
 866         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
 867         Document a replacement.
 868
 869 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
 870
 871         * interp.c (sim_monitor): Make mon_printf work.
 872
 873 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
 874
 875         * sim-main.h (INSN_NAME): New arg `cpu'.
 876
 877 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
 878
 879         * configure: Regenerated to track ../common/aclocal.m4 changes.
 880
 881 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
 882
 883         * configure: Regenerated to track ../common/aclocal.m4 changes.
 884         * config.in: Ditto.
 885
 886 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
 887
 888         * acconfig.h: New file.
 889         * configure.in: Reverted change of Apr 24; use sinclude again.
 890
 891 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
 892
 893         * configure: Regenerated to track ../common/aclocal.m4 changes.
 894         * config.in: Ditto.
 895
 896 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
 897
 898         * configure.in: Don't call sinclude.
 899
 900 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
 901
 902         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
 903
 904 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 905
 906         * mips.igen (ERET): Implement.
 907
 908         * interp.c (decode_coproc): Return sign-extended EPC.
 909
 910         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
 911
 912         * interp.c (signal_exception): Do not ignore Trap.
 913         (signal_exception): On TRAP, restart at exception address.
 914         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
 915         (signal_exception): Update.
 916         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
 917         so that TRAP instructions are caught.
 918
 919 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 920
 921         * sim-main.h (struct hilo_access, struct hilo_history): Define,
 922         contains HI/LO access history.
 923         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
 924         (HIACCESS, LOACCESS): Delete, replace with
 925         (HIHISTORY, LOHISTORY): New macros.
 926         (CHECKHILO): Delete all, moved to mips.igen
 927
 928         * gencode.c (build_instruction): Do not generate checks for
 929         correct HI/LO register usage.
 930
 931         * interp.c (old_engine_run): Delete checks for correct HI/LO
 932         register usage.
 933
 934         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
 935         check_mf_cycles): New functions.
 936         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
 937         do_divu, domultx, do_mult, do_multu): Use.
 938
 939         * tx.igen ("madd", "maddu"): Use.
 940
 941 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 942
 943         * mips.igen (DSRAV): Use function do_dsrav.
 944         (SRAV): Use new function do_srav.
 945
 946         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
 947         (B): Sign extend 11 bit immediate.
 948         (EXT-B*): Shift 16 bit immediate left by 1.
 949         (ADDIU*): Don't sign extend immediate value.
 950
 951 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 952
 953         * m16run.c (sim_engine_run): Restore CIA after handling an event.
 954
 955         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
 956         functions.
 957
 958         * mips.igen (delayslot32, nullify_next_insn): New functions.
 959         (m16.igen): Always include.
 960         (do_*): Add more tracing.
 961
 962         * m16.igen (delayslot16): Add NIA argument, could be called by a
 963         32 bit MIPS16 instruction.
 964
 965         * interp.c (ifetch16): Move function from here.
 966         * sim-main.c (ifetch16): To here.
 967
 968         * sim-main.c (ifetch16, ifetch32): Update to match current
 969         implementations of LH, LW.
 970         (signal_exception): Don't print out incorrect hex value of illegal
 971         instruction.
 972
 973 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 974
 975         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
 976         instruction.
 977
 978         * m16.igen: Implement MIPS16 instructions.
 979
 980         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
 981         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
 982         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
 983         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
 984         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
 985         bodies of corresponding code from 32 bit insn to these.  Also used
 986         by MIPS16 versions of functions.
 987
 988         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
 989         (IMEM16): Drop NR argument from macro.
 990
 991 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
 992
 993         * Makefile.in (SIM_OBJS): Add sim-main.o.
 994
 995         * sim-main.h (address_translation, load_memory, store_memory,
 996         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
 997         as INLINE_SIM_MAIN.
 998         (pr_addr, pr_uword64): Declare.
 999         (sim-main.c): Include when H_REVEALS_MODULE_P.
1000
1001         * interp.c (address_translation, load_memory, store_memory,
1002         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1003         from here.
1004         * sim-main.c: To here. Fix compilation problems.
1005
1006         * configure.in: Enable inlining.
1007         * configure: Re-config.
1008
1009 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1010
1011         * configure: Regenerated to track ../common/aclocal.m4 changes.
1012
1013 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1014
1015         * mips.igen: Include tx.igen.
1016         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1017         * tx.igen: New file, contains MADD and MADDU.
1018
1019         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1020         the hardwired constant `7'.
1021         (store_memory): Ditto.
1022         (LOADDRMASK): Move definition to sim-main.h.
1023
1024         mips.igen (MTC0): Enable for r3900.
1025         (ADDU): Add trace.
1026
1027         mips.igen (do_load_byte): Delete.
1028         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1029         do_store_right): New functions.
1030         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1031
1032         configure.in: Let the tx39 use igen again.
1033         configure: Update.
1034
1035 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1036
1037         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1038         not an address sized quantity.  Return zero for cache sizes.
1039
1040 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1041
1042         * mips.igen (r3900): r3900 does not support 64 bit integer
1043         operations.
1044
1045 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1046
1047         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1048         than igen one.
1049         * configure : Rebuild.
1050
1051 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1052
1053         * configure: Regenerated to track ../common/aclocal.m4 changes.
1054
1055 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1056
1057         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1058
1059 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1060
1061         * configure: Regenerated to track ../common/aclocal.m4 changes.
1062         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1063
1064 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1065
1066         * configure: Regenerated to track ../common/aclocal.m4 changes.
1067
1068 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1069
1070         * interp.c (Max, Min): Comment out functions. Not yet used.
1071
1072 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1073
1074         * configure: Regenerated to track ../common/aclocal.m4 changes.
1075
1076 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1077
1078         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1079         configurable settings for stand-alone simulator.
1080
1081         * configure.in: Added X11 search, just in case.
1082
1083         * configure: Regenerated.
1084
1085 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1086
1087         * interp.c (sim_write, sim_read, load_memory, store_memory):
1088         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1089
1090 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1091
1092         * sim-main.h (GETFCC): Return an unsigned value.
1093
1094 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1095
1096         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1097         (DADD): Result destination is RD not RT.
1098
1099 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1100
1101         * sim-main.h (HIACCESS, LOACCESS): Always define.
1102
1103         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1104
1105         * interp.c (sim_info): Delete.
1106
1107 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1108
1109         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1110         (mips_option_handler): New argument `cpu'.
1111         (sim_open): Update call to sim_add_option_table.
1112
1113 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1114
1115         * mips.igen (CxC1): Add tracing.
1116
1117 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1118
1119         * sim-main.h (Max, Min): Declare.
1120
1121         * interp.c (Max, Min): New functions.
1122
1123         * mips.igen (BC1): Add tracing.
1124
1125 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1126
1127         * interp.c Added memory map for stack in vr4100
1128
1129 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1130
1131         * interp.c (load_memory): Add missing "break"'s.
1132
1133 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1134
1135         * interp.c (sim_store_register, sim_fetch_register): Pass in
1136         length parameter.  Return -1.
1137
1138 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1139
1140         * interp.c: Added hardware init hook, fixed warnings.
1141
1142 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1143
1144         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1145
1146 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1147
1148         * interp.c (ifetch16): New function.
1149
1150         * sim-main.h (IMEM32): Rename IMEM.
1151         (IMEM16_IMMED): Define.
1152         (IMEM16): Define.
1153         (DELAY_SLOT): Update.
1154
1155         * m16run.c (sim_engine_run): New file.
1156
1157         * m16.igen: All instructions except LB.
1158         (LB): Call do_load_byte.
1159         * mips.igen (do_load_byte): New function.
1160         (LB): Call do_load_byte.
1161
1162         * mips.igen: Move spec for insn bit size and high bit from here.
1163         * Makefile.in (tmp-igen, tmp-m16): To here.
1164
1165         * m16.dc: New file, decode mips16 instructions.
1166
1167         * Makefile.in (SIM_NO_ALL): Define.
1168         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1169
1170 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1171
1172         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1173         point unit to 32 bit registers.
1174         * configure: Re-generate.
1175
1176 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1177
1178         * configure.in (sim_use_gen): Make IGEN the default simulator
1179         generator for generic 32 and 64 bit mips targets.
1180         * configure: Re-generate.
1181
1182 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1183
1184         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1185         bitsize.
1186
1187         * interp.c (sim_fetch_register, sim_store_register): Read/write
1188         FGR from correct location.
1189         (sim_open): Set size of FGR's according to
1190         WITH_TARGET_FLOATING_POINT_BITSIZE.
1191
1192         * sim-main.h (FGR): Store floating point registers in a separate
1193         array.
1194
1195 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1196
1197         * configure: Regenerated to track ../common/aclocal.m4 changes.
1198
1199 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1200
1201         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1202
1203         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1204
1205         * interp.c (pending_tick): New function.  Deliver pending writes.
1206
1207         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1208         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1209         it can handle mixed sized quantites and single bits.
1210
1211 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1212
1213         * interp.c (oengine.h): Do not include when building with IGEN.
1214         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1215         (sim_info): Ditto for PROCESSOR_64BIT.
1216         (sim_monitor): Replace ut_reg with unsigned_word.
1217         (*): Ditto for t_reg.
1218         (LOADDRMASK): Define.
1219         (sim_open): Remove defunct check that host FP is IEEE compliant,
1220         using software to emulate floating point.
1221         (value_fpr, ...): Always compile, was conditional on HASFPU.
1222
1223 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1224
1225         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1226         size.
1227
1228         * interp.c (SD, CPU): Define.
1229         (mips_option_handler): Set flags in each CPU.
1230         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1231         (sim_close): Do not clear STATE, deleted anyway.
1232         (sim_write, sim_read): Assume CPU zero's vm should be used for
1233         data transfers.
1234         (sim_create_inferior): Set the PC for all processors.
1235         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1236         argument.
1237         (mips16_entry): Pass correct nr of args to store_word, load_word.
1238         (ColdReset): Cold reset all cpu's.
1239         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1240         (sim_monitor, load_memory, store_memory, signal_exception): Use
1241         `CPU' instead of STATE_CPU.
1242
1243
1244         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1245         SD or CPU_.
1246
1247         * sim-main.h (signal_exception): Add sim_cpu arg.
1248         (SignalException*): Pass both SD and CPU to signal_exception.
1249         * interp.c (signal_exception): Update.
1250
1251         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1252         Ditto
1253         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1254         address_translation): Ditto
1255         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1256
1257 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1258
1259         * configure: Regenerated to track ../common/aclocal.m4 changes.
1260
1261 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1262
1263         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1264
1265         * mips.igen (model): Map processor names onto BFD name.
1266
1267         * sim-main.h (CPU_CIA): Delete.
1268         (SET_CIA, GET_CIA): Define
1269
1270 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1271
1272         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1273         regiser.
1274
1275         * configure.in (default_endian): Configure a big-endian simulator
1276         by default.
1277         * configure: Re-generate.
1278
1279 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1280
1281         * configure: Regenerated to track ../common/aclocal.m4 changes.
1282
1283 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1284
1285         * interp.c (sim_monitor): Handle Densan monitor outbyte
1286         and inbyte functions.
1287
1288 1997-12-29  Felix Lee  <flee@cygnus.com>
1289
1290         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1291
1292 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1293
1294         * Makefile.in (tmp-igen): Arrange for $zero to always be
1295         reset to zero after every instruction.
1296
1297 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1298
1299         * configure: Regenerated to track ../common/aclocal.m4 changes.
1300         * config.in: Ditto.
1301
1302 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1303
1304         * mips.igen (MSUB): Fix to work like MADD.
1305         * gencode.c (MSUB): Similarly.
1306
1307 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1308
1309         * configure: Regenerated to track ../common/aclocal.m4 changes.
1310
1311 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1312
1313         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1314
1315 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1316
1317         * sim-main.h (sim-fpu.h): Include.
1318
1319         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1320         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1321         using host independant sim_fpu module.
1322
1323 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1324
1325         * interp.c (signal_exception): Report internal errors with SIGABRT
1326         not SIGQUIT.
1327
1328         * sim-main.h (C0_CONFIG): New register.
1329         (signal.h): No longer include.
1330
1331         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1332
1333 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1334
1335         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1336
1337 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1338
1339         * mips.igen: Tag vr5000 instructions.
1340         (ANDI): Was missing mipsIV model, fix assembler syntax.
1341         (do_c_cond_fmt): New function.
1342         (C.cond.fmt): Handle mips I-III which do not support CC field
1343         separatly.
1344         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1345         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1346         in IV3.2 spec.
1347         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1348         vr5000 which saves LO in a GPR separatly.
1349
1350         * configure.in (enable-sim-igen): For vr5000, select vr5000
1351         specific instructions.
1352         * configure: Re-generate.
1353
1354 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1355
1356         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1357
1358         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1359         fmt_uninterpreted_64 bit cases to switch.  Convert to
1360         fmt_formatted,
1361
1362         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1363
1364         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1365         as specified in IV3.2 spec.
1366         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1367
1368 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1369
1370         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1371         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1372         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1373         PENDING_FILL versions of instructions.  Simplify.
1374         (X): New function.
1375         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1376         instructions.
1377         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1378         a signed value.
1379         (MTHI, MFHI): Disable code checking HI-LO.
1380
1381         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1382         global.
1383         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1384
1385 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1386
1387         * gencode.c (build_mips16_operands): Replace IPC with cia.
1388
1389         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1390         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1391         IPC to `cia'.
1392         (UndefinedResult): Replace function with macro/function
1393         combination.
1394         (sim_engine_run): Don't save PC in IPC.
1395
1396         * sim-main.h (IPC): Delete.
1397
1398
1399         * interp.c (signal_exception, store_word, load_word,
1400         address_translation, load_memory, store_memory, cache_op,
1401         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1402         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1403         current instruction address - cia - argument.
1404         (sim_read, sim_write): Call address_translation directly.
1405         (sim_engine_run): Rename variable vaddr to cia.
1406         (signal_exception): Pass cia to sim_monitor
1407
1408         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1409         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1410         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1411
1412         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1413         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1414         SIM_ASSERT.
1415
1416         * interp.c (signal_exception): Pass restart address to
1417         sim_engine_restart.
1418
1419         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1420         idecode.o): Add dependency.
1421
1422         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1423         Delete definitions
1424         (DELAY_SLOT): Update NIA not PC with branch address.
1425         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1426
1427         * mips.igen: Use CIA not PC in branch calculations.
1428         (illegal): Call SignalException.
1429         (BEQ, ADDIU): Fix assembler.
1430
1431 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1432
1433         * m16.igen (JALX): Was missing.
1434
1435         * configure.in (enable-sim-igen): New configuration option.
1436         * configure: Re-generate.
1437
1438         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1439
1440         * interp.c (load_memory, store_memory): Delete parameter RAW.
1441         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1442         bypassing {load,store}_memory.
1443
1444         * sim-main.h (ByteSwapMem): Delete definition.
1445
1446         * Makefile.in (SIM_OBJS): Add sim-memopt module.
1447
1448         * interp.c (sim_do_command, sim_commands): Delete mips specific
1449         commands.  Handled by module sim-options.
1450
1451         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1452         (WITH_MODULO_MEMORY): Define.
1453
1454         * interp.c (sim_info): Delete code printing memory size.
1455
1456         * interp.c (mips_size): Nee sim_size, delete function.
1457         (power2): Delete.
1458         (monitor, monitor_base, monitor_size): Delete global variables.
1459         (sim_open, sim_close): Delete code creating monitor and other
1460         memory regions.  Use sim-memopts module, via sim_do_commandf, to
1461         manage memory regions.
1462         (load_memory, store_memory): Use sim-core for memory model.
1463
1464         * interp.c (address_translation): Delete all memory map code
1465         except line forcing 32 bit addresses.
1466
1467 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1468
1469         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
1470         trace options.
1471
1472         * interp.c (logfh, logfile): Delete globals.
1473         (sim_open, sim_close): Delete code opening & closing log file.
1474         (mips_option_handler): Delete -l and -n options.
1475         (OPTION mips_options): Ditto.
1476
1477         * interp.c (OPTION mips_options): Rename option trace to dinero.
1478         (mips_option_handler): Update.
1479
1480 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1481
1482         * interp.c (fetch_str): New function.
1483         (sim_monitor): Rewrite using sim_read & sim_write.
1484         (sim_open): Check magic number.
1485         (sim_open): Write monitor vectors into memory using sim_write.
1486         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1487         (sim_read, sim_write): Simplify - transfer data one byte at a
1488         time.
1489         (load_memory, store_memory): Clarify meaning of parameter RAW.
1490
1491         * sim-main.h (isHOST): Defete definition.
1492         (isTARGET): Mark as depreciated.
1493         (address_translation): Delete parameter HOST.
1494
1495         * interp.c (address_translation): Delete parameter HOST.
1496
1497 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1498
1499         * mips.igen:
1500
1501         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1502         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1503
1504 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1505
1506         * mips.igen: Add model filter field to records.
1507
1508 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1509
1510         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
1511
1512         interp.c (sim_engine_run): Do not compile function sim_engine_run
1513         when WITH_IGEN == 1.
1514
1515         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1516         target architecture.
1517
1518         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1519         igen. Replace with configuration variables sim_igen_flags /
1520         sim_m16_flags.
1521
1522         * m16.igen: New file.  Copy mips16 insns here.
1523         * mips.igen: From here.
1524
1525 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1526
1527         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1528         to top.
1529         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1530
1531 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
1532
1533         * gencode.c (build_instruction): Follow sim_write's lead in using
1534         BigEndianMem instead of !ByteSwapMem.
1535
1536 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1537
1538         * configure.in (sim_gen): Dependent on target, select type of
1539         generator.  Always select old style generator.
1540
1541         configure: Re-generate.
1542
1543         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1544         targets.
1545         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1546         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1547         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1548         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1549         SIM_@sim_gen@_*, set by autoconf.
1550
1551 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1552
1553         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1554
1555         * interp.c (ColdReset): Remove #ifdef HASFPU, check
1556         CURRENT_FLOATING_POINT instead.
1557
1558         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1559         (address_translation): Raise exception InstructionFetch when
1560         translation fails and isINSTRUCTION.
1561
1562         * interp.c (sim_open, sim_write, sim_monitor, store_word,
1563         sim_engine_run): Change type of of vaddr and paddr to
1564         address_word.
1565         (address_translation, prefetch, load_memory, store_memory,
1566         cache_op): Change type of vAddr and pAddr to address_word.
1567
1568         * gencode.c (build_instruction): Change type of vaddr and paddr to
1569         address_word.
1570
1571 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1572
1573         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1574         macro to obtain result of ALU op.
1575
1576 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1577
1578         * interp.c (sim_info): Call profile_print.
1579
1580 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1581
1582         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1583
1584         * sim-main.h (WITH_PROFILE): Do not define, defined in
1585         common/sim-config.h.  Use sim-profile module.
1586         (simPROFILE): Delete defintion.
1587
1588         * interp.c (PROFILE): Delete definition.
1589         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1590         (sim_close): Delete code writing profile histogram.
1591         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1592         Delete.
1593         (sim_engine_run): Delete code profiling the PC.
1594
1595 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1596
1597         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1598
1599         * interp.c (sim_monitor): Make register pointers of type
1600         unsigned_word*.
1601
1602         * sim-main.h: Make registers of type unsigned_word not
1603         signed_word.
1604
1605 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1606
1607         * interp.c (sync_operation): Rename from SyncOperation, make
1608         global, add SD argument.
1609         (prefetch): Rename from Prefetch, make global, add SD argument.
1610         (decode_coproc): Make global.
1611
1612         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1613
1614         * gencode.c (build_instruction): Generate DecodeCoproc not
1615         decode_coproc calls.
1616
1617         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1618         (SizeFGR): Move to sim-main.h
1619         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1620         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1621         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1622         sim-main.h.
1623         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1624         FP_RM_TOMINF, GETRM): Move to sim-main.h.
1625         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1626         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1627         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1628         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1629
1630         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1631         exception.
1632         (sim-alu.h): Include.
1633         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1634         (sim_cia): Typedef to instruction_address.
1635
1636 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1637
1638         * Makefile.in (interp.o): Rename generated file engine.c to
1639         oengine.c.
1640
1641         * interp.c: Update.
1642
1643 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1644
1645         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1646
1647 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1648
1649         * gencode.c (build_instruction): For "FPSQRT", output correct
1650         number of arguments to Recip.
1651
1652 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1653
1654         * Makefile.in (interp.o): Depends on sim-main.h
1655
1656         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1657
1658         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1659         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1660         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1661         STATE, DSSTATE): Define
1662         (GPR, FGRIDX, ..): Define.
1663
1664         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1665         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1666         (GPR, FGRIDX, ...): Delete macros.
1667
1668         * interp.c: Update names to match defines from sim-main.h
1669
1670 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1671
1672         * interp.c (sim_monitor): Add SD argument.
1673         (sim_warning): Delete.  Replace calls with calls to
1674         sim_io_eprintf.
1675         (sim_error): Delete. Replace calls with sim_io_error.
1676         (open_trace, writeout32, writeout16, getnum): Add SD argument.
1677         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1678         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1679         argument.
1680         (mips_size): Rename from sim_size. Add SD argument.
1681
1682         * interp.c (simulator): Delete global variable.
1683         (callback): Delete global variable.
1684         (mips_option_handler, sim_open, sim_write, sim_read,
1685         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1686         sim_size,sim_monitor): Use sim_io_* not callback->*.
1687         (sim_open): ZALLOC simulator struct.
1688         (PROFILE): Do not define.
1689
1690 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1691
1692         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1693         support.h with corresponding code.
1694
1695         * sim-main.h (word64, uword64), support.h: Move definition to
1696         sim-main.h.
1697         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1698
1699         * support.h: Delete
1700         * Makefile.in: Update dependencies
1701         * interp.c: Do not include.
1702
1703 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1704
1705         * interp.c (address_translation, load_memory, store_memory,
1706         cache_op): Rename to from AddressTranslation et.al., make global,
1707         add SD argument
1708
1709         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1710         CacheOp): Define.
1711
1712         * interp.c (SignalException): Rename to signal_exception, make
1713         global.
1714
1715         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1716
1717         * sim-main.h (SignalException, SignalExceptionInterrupt,
1718         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1719         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1720         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1721         Define.
1722
1723         * interp.c, support.h: Use.
1724
1725 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1726
1727         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1728         to value_fpr / store_fpr. Add SD argument.
1729         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1730         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1731
1732         * sim-main.h (ValueFPR, StoreFPR): Define.
1733
1734 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1735
1736         * interp.c (sim_engine_run): Check consistency between configure
1737         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1738         and HASFPU.
1739
1740         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1741         (mips_fpu): Configure WITH_FLOATING_POINT.
1742         (mips_endian): Configure WITH_TARGET_ENDIAN.
1743         * configure: Update.
1744
1745 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1746
1747         * configure: Regenerated to track ../common/aclocal.m4 changes.
1748
1749 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
1750
1751         * configure: Regenerated.
1752
1753 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
1754
1755         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1756
1757 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1758
1759         * gencode.c (print_igen_insn_models): Assume certain architectures
1760         include all mips* instructions.
1761         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1762         instruction.
1763
1764         * Makefile.in (tmp.igen): Add target. Generate igen input from
1765         gencode file.
1766
1767         * gencode.c (FEATURE_IGEN): Define.
1768         (main): Add --igen option.  Generate output in igen format.
1769         (process_instructions): Format output according to igen option.
1770         (print_igen_insn_format): New function.
1771         (print_igen_insn_models): New function.
1772         (process_instructions): Only issue warnings and ignore
1773         instructions when no FEATURE_IGEN.
1774
1775 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1776
1777         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1778         MIPS targets.
1779
1780 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1781
1782         * configure: Regenerated to track ../common/aclocal.m4 changes.
1783
1784 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1785
1786         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1787         SIM_RESERVED_BITS): Delete, moved to common.
1788         (SIM_EXTRA_CFLAGS): Update.
1789
1790 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1791
1792         * configure.in: Configure non-strict memory alignment.
1793         * configure: Regenerated to track ../common/aclocal.m4 changes.
1794
1795 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1796
1797         * configure: Regenerated to track ../common/aclocal.m4 changes.
1798
1799 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
1800
1801         * gencode.c (SDBBP,DERET): Added (3900) insns.
1802         (RFE): Turn on for 3900.
1803         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1804         (dsstate): Made global.
1805         (SUBTARGET_R3900): Added.
1806         (CANCELDELAYSLOT): New.
1807         (SignalException): Ignore SystemCall rather than ignore and
1808         terminate.  Add DebugBreakPoint handling.
1809         (decode_coproc): New insns RFE, DERET; and new registers Debug
1810         and DEPC protected by SUBTARGET_R3900.
1811         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1812         bits explicitly.
1813         * Makefile.in,configure.in: Add mips subtarget option.
1814         * configure: Update.
1815
1816 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
1817
1818         * gencode.c: Add r3900 (tx39).
1819
1820
1821 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
1822
1823         * gencode.c (build_instruction): Don't need to subtract 4 for
1824         JALR, just 2.
1825
1826 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
1827
1828         * interp.c: Correct some HASFPU problems.
1829
1830 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1831
1832         * configure: Regenerated to track ../common/aclocal.m4 changes.
1833
1834 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1835
1836         * interp.c (mips_options): Fix samples option short form, should
1837         be `x'.
1838
1839 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1840
1841         * interp.c (sim_info): Enable info code.  Was just returning.
1842
1843 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1844
1845         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1846         MFC0.
1847
1848 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1849
1850         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1851         constants.
1852         (build_instruction): Ditto for LL.
1853
1854 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
1855
1856         * configure: Regenerated to track ../common/aclocal.m4 changes.
1857
1858 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1859
1860         * configure: Regenerated to track ../common/aclocal.m4 changes.
1861         * config.in: Ditto.
1862
1863 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1864
1865         * interp.c (sim_open): Add call to sim_analyze_program, update
1866         call to sim_config.
1867
1868 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1869
1870         * interp.c (sim_kill): Delete.
1871         (sim_create_inferior): Add ABFD argument. Set PC from same.
1872         (sim_load): Move code initializing trap handlers from here.
1873         (sim_open): To here.
1874         (sim_load): Delete, use sim-hload.c.
1875
1876         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1877
1878 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1879
1880         * configure: Regenerated to track ../common/aclocal.m4 changes.
1881         * config.in: Ditto.
1882
1883 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1884
1885         * interp.c (sim_open): Add ABFD argument.
1886         (sim_load): Move call to sim_config from here.
1887         (sim_open): To here.  Check return status.
1888
1889 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
1890
1891         * gencode.c (build_instruction): Two arg MADD should
1892         not assign result to $0.
1893
1894 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
1895
1896         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1897         * sim/mips/configure.in: Regenerate.
1898
1899 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
1900
1901         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1902         signed8, unsigned8 et.al. types.
1903
1904         * interp.c (SUB_REG_FETCH): Handle both little and big endian
1905         hosts when selecting subreg.
1906
1907 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
1908
1909         * interp.c (sim_engine_run): Reset the ZERO register to zero
1910         regardless of FEATURE_WARN_ZERO.
1911         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1912
1913 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1914
1915         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1916         (SignalException): For BreakPoints ignore any mode bits and just
1917         save the PC.
1918         (SignalException): Always set the CAUSE register.
1919
1920 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1921
1922         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1923         exception has been taken.
1924
1925         * interp.c: Implement the ERET and mt/f sr instructions.
1926
1927 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1928
1929         * interp.c (SignalException): Don't bother restarting an
1930         interrupt.
1931
1932 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1933
1934         * interp.c (SignalException): Really take an interrupt.
1935         (interrupt_event): Only deliver interrupts when enabled.
1936
1937 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1938
1939         * interp.c (sim_info): Only print info when verbose.
1940         (sim_info) Use sim_io_printf for output.
1941
1942 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1943
1944         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1945         mips architectures.
1946
1947 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1948
1949         * interp.c (sim_do_command): Check for common commands if a
1950         simulator specific command fails.
1951
1952 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
1953
1954         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1955         and simBE when DEBUG is defined.
1956
1957 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1958
1959         * interp.c (interrupt_event): New function.  Pass exception event
1960         onto exception handler.
1961
1962         * configure.in: Check for stdlib.h.
1963         * configure: Regenerate.
1964
1965         * gencode.c (build_instruction): Add UNUSED attribute to tempS
1966         variable declaration.
1967         (build_instruction): Initialize memval1.
1968         (build_instruction): Add UNUSED attribute to byte, bigend,
1969         reverse.
1970         (build_operands): Ditto.
1971
1972         * interp.c: Fix GCC warnings.
1973         (sim_get_quit_code): Delete.
1974
1975         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1976         * Makefile.in: Ditto.
1977         * configure: Re-generate.
1978
1979         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1980
1981 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1982
1983         * interp.c (mips_option_handler): New function parse argumes using
1984         sim-options.
1985         (myname): Replace with STATE_MY_NAME.
1986         (sim_open): Delete check for host endianness - performed by
1987         sim_config.
1988         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1989         (sim_open): Move much of the initialization from here.
1990         (sim_load): To here.  After the image has been loaded and
1991         endianness set.
1992         (sim_open): Move ColdReset from here.
1993         (sim_create_inferior): To here.
1994         (sim_open): Make FP check less dependant on host endianness.
1995
1996         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1997         run.
1998         * interp.c (sim_set_callbacks): Delete.
1999
2000         * interp.c (membank, membank_base, membank_size): Replace with
2001         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2002         (sim_open): Remove call to callback->init. gdb/run do this.
2003
2004         * interp.c: Update
2005
2006         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2007
2008         * interp.c (big_endian_p): Delete, replaced by
2009         current_target_byte_order.
2010
2011 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2012
2013         * interp.c (host_read_long, host_read_word, host_swap_word,
2014         host_swap_long): Delete. Using common sim-endian.
2015         (sim_fetch_register, sim_store_register): Use H2T.
2016         (pipeline_ticks): Delete.  Handled by sim-events.
2017         (sim_info): Update.
2018         (sim_engine_run): Update.
2019
2020 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2021
2022         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2023         reason from here.
2024         (SignalException): To here. Signal using sim_engine_halt.
2025         (sim_stop_reason): Delete, moved to common.
2026
2027 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2028
2029         * interp.c (sim_open): Add callback argument.
2030         (sim_set_callbacks): Delete SIM_DESC argument.
2031         (sim_size): Ditto.
2032
2033 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2034
2035         * Makefile.in (SIM_OBJS): Add common modules.
2036
2037         * interp.c (sim_set_callbacks): Also set SD callback.
2038         (set_endianness, xfer_*, swap_*): Delete.
2039         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2040         Change to functions using sim-endian macros.
2041         (control_c, sim_stop): Delete, use common version.
2042         (simulate): Convert into.
2043         (sim_engine_run): This function.
2044         (sim_resume): Delete.
2045
2046         * interp.c (simulation): New variable - the simulator object.
2047         (sim_kind): Delete global - merged into simulation.
2048         (sim_load): Cleanup.  Move PC assignment from here.
2049         (sim_create_inferior): To here.
2050
2051         * sim-main.h: New file.
2052         * interp.c (sim-main.h): Include.
2053
2054 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2055
2056         * configure: Regenerated to track ../common/aclocal.m4 changes.
2057
2058 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2059
2060         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2061
2062 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2063
2064         * gencode.c (build_instruction): DIV instructions: check
2065         for division by zero and integer overflow before using
2066         host's division operation.
2067
2068 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2069
2070         * Makefile.in (SIM_OBJS): Add sim-load.o.
2071         * interp.c: #include bfd.h.
2072         (target_byte_order): Delete.
2073         (sim_kind, myname, big_endian_p): New static locals.
2074         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2075         after argument parsing.  Recognize -E arg, set endianness accordingly.
2076         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2077         load file into simulator.  Set PC from bfd.
2078         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2079         (set_endianness): Use big_endian_p instead of target_byte_order.
2080
2081 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2082
2083         * interp.c (sim_size): Delete prototype - conflicts with
2084         definition in remote-sim.h.  Correct definition.
2085
2086 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2087
2088         * configure: Regenerated to track ../common/aclocal.m4 changes.
2089         * config.in: Ditto.
2090
2091 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2092
2093         * interp.c (sim_open): New arg `kind'.
2094
2095         * configure: Regenerated to track ../common/aclocal.m4 changes.
2096
2097 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2098
2099         * configure: Regenerated to track ../common/aclocal.m4 changes.
2100
2101 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2102
2103         * interp.c (sim_open): Set optind to 0 before calling getopt.
2104
2105 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2106
2107         * configure: Regenerated to track ../common/aclocal.m4 changes.
2108
2109 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2110
2111         * interp.c : Replace uses of pr_addr with pr_uword64
2112         where the bit length is always 64 independent of SIM_ADDR.
2113         (pr_uword64) : added.
2114
2115 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2116
2117         * configure: Re-generate.
2118
2119 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2120
2121         * configure: Regenerate to track ../common/aclocal.m4 changes.
2122
2123 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2124
2125         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2126         in argv form.
2127         (other sim_*): New SIM_DESC argument.
2128
2129 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2130
2131         * interp.c: Fix printing of addresses for non-64-bit targets.
2132         (pr_addr): Add function to print address based on size.
2133
2134 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2135
2136         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2137
2138 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2139
2140         * gencode.c (build_mips16_operands): Correct computation of base
2141         address for extended PC relative instruction.
2142
2143 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2144
2145         * interp.c (mips16_entry): Add support for floating point cases.
2146         (SignalException): Pass floating point cases to mips16_entry.
2147         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2148         registers.
2149         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2150         or fmt_word.
2151         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2152         and then set the state to fmt_uninterpreted.
2153         (COP_SW): Temporarily set the state to fmt_word while calling
2154         ValueFPR.
2155
2156 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2157
2158         * gencode.c (build_instruction): The high order may be set in the
2159         comparison flags at any ISA level, not just ISA 4.
2160
2161 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2162
2163         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2164         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2165         * configure.in: sinclude ../common/aclocal.m4.
2166         * configure: Regenerated.
2167
2168 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2169
2170         * configure: Rebuild after change to aclocal.m4.
2171
2172 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2173
2174         * configure configure.in Makefile.in:  Update to new configure
2175         scheme which is more compatible with WinGDB builds.
2176         * configure.in:  Improve comment on how to run autoconf.
2177         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2178         * Makefile.in:  Use autoconf substitution to install common
2179         makefile fragment.
2180
2181 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2182
2183         * gencode.c (build_instruction): Use BigEndianCPU instead of
2184         ByteSwapMem.
2185
2186 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2187
2188         * interp.c (sim_monitor): Make output to stdout visible in
2189         wingdb's I/O log window.
2190
2191 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2192
2193         * support.h: Undo previous change to SIGTRAP
2194         and SIGQUIT values.
2195
2196 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2197
2198         * interp.c (store_word, load_word): New static functions.
2199         (mips16_entry): New static function.
2200         (SignalException): Look for mips16 entry and exit instructions.
2201         (simulate): Use the correct index when setting fpr_state after
2202         doing a pending move.
2203
2204 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2205
2206         * interp.c: Fix byte-swapping code throughout to work on
2207         both little- and big-endian hosts.
2208
2209 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2210
2211         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2212         with gdb/config/i386/xm-windows.h.
2213
2214 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2215
2216         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2217         that messes up arithmetic shifts.
2218
2219 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2220
2221         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2222         SIGTRAP and SIGQUIT for _WIN32.
2223
2224 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2225
2226         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2227         force a 64 bit multiplication.
2228         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2229         destination register is 0, since that is the default mips16 nop
2230         instruction.
2231
2232 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2233
2234         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2235         (build_endian_shift): Don't check proc64.
2236         (build_instruction): Always set memval to uword64.  Cast op2 to
2237         uword64 when shifting it left in memory instructions.  Always use
2238         the same code for stores--don't special case proc64.
2239
2240         * gencode.c (build_mips16_operands): Fix base PC value for PC
2241         relative operands.
2242         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2243         jal instruction.
2244         * interp.c (simJALDELAYSLOT): Define.
2245         (JALDELAYSLOT): Define.
2246         (INDELAYSLOT, INJALDELAYSLOT): Define.
2247         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2248
2249 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2250
2251         * interp.c (sim_open): add flush_cache as a PMON routine
2252         (sim_monitor): handle flush_cache by ignoring it
2253
2254 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2255
2256         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2257         BigEndianMem.
2258         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2259         (BigEndianMem): Rename to ByteSwapMem and change sense.
2260         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2261         BigEndianMem references to !ByteSwapMem.
2262         (set_endianness): New function, with prototype.
2263         (sim_open): Call set_endianness.
2264         (sim_info): Use simBE instead of BigEndianMem.
2265         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2266         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2267         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2268         ifdefs, keeping the prototype declaration.
2269         (swap_word): Rewrite correctly.
2270         (ColdReset): Delete references to CONFIG.  Delete endianness related
2271         code; moved to set_endianness.
2272
2273 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2274
2275         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2276         * interp.c (CHECKHILO): Define away.
2277         (simSIGINT): New macro.
2278         (membank_size): Increase from 1MB to 2MB.
2279         (control_c): New function.
2280         (sim_resume): Rename parameter signal to signal_number.  Add local
2281         variable prev.  Call signal before and after simulate.
2282         (sim_stop_reason): Add simSIGINT support.
2283         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2284         functions always.
2285         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2286         if logfh is NULL.
2287         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2288         a call to sim_warning.
2289
2290 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2291
2292         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2293         16 bit instructions.
2294
2295 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2296
2297         Add support for mips16 (16 bit MIPS implementation):
2298         * gencode.c (inst_type): Add mips16 instruction encoding types.
2299         (GETDATASIZEINSN): Define.
2300         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2301         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2302         mtlo.
2303         (MIPS16_DECODE): New table, for mips16 instructions.
2304         (bitmap_val): New static function.
2305         (struct mips16_op): Define.
2306         (mips16_op_table): New table, for mips16 operands.
2307         (build_mips16_operands): New static function.
2308         (process_instructions): If PC is odd, decode a mips16
2309         instruction.  Break out instruction handling into new
2310         build_instruction function.
2311         (build_instruction): New static function, broken out of
2312         process_instructions.  Check modifiers rather than flags for SHIFT
2313         bit count and m[ft]{hi,lo} direction.
2314         (usage): Pass program name to fprintf.
2315         (main): Remove unused variable this_option_optind.  Change
2316         ``*loptarg++'' to ``loptarg++''.
2317         (my_strtoul): Parenthesize && within ||.
2318         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2319         (simulate): If PC is odd, fetch a 16 bit instruction, and
2320         increment PC by 2 rather than 4.
2321         * configure.in: Add case for mips16*-*-*.
2322         * configure: Rebuild.
2323
2324 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2325
2326         * interp.c: Allow -t to enable tracing in standalone simulator.
2327         Fix garbage output in trace file and error messages.
2328
2329 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2330
2331         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2332         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2333         * configure.in: Simplify using macros in ../common/aclocal.m4.
2334         * configure: Regenerated.
2335         * tconfig.in: New file.
2336
2337 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2338
2339         * interp.c: Fix bugs in 64-bit port.
2340         Use ansi function declarations for msvc compiler.
2341         Initialize and test file pointer in trace code.
2342         Prevent duplicate definition of LAST_EMED_REGNUM.
2343
2344 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2345
2346         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2347
2348 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2349
2350         * interp.c (SignalException): Check for explicit terminating
2351         breakpoint value.
2352         * gencode.c: Pass instruction value through SignalException()
2353         calls for Trap, Breakpoint and Syscall.
2354
2355 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2356
2357         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2358         only used on those hosts that provide it.
2359         * configure.in: Add sqrt() to list of functions to be checked for.
2360         * config.in: Re-generated.
2361         * configure: Re-generated.
2362
2363 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2364
2365         * gencode.c (process_instructions): Call build_endian_shift when
2366         expanding STORE RIGHT, to fix swr.
2367         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2368         clear the high bits.
2369         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2370         Fix float to int conversions to produce signed values.
2371
2372 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
2373
2374         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2375         (process_instructions): Correct handling of nor instruction.
2376         Correct shift count for 32 bit shift instructions. Correct sign
2377         extension for arithmetic shifts to not shift the number of bits in
2378         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
2379         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
2380         Fix madd.
2381         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2382         It's OK to have a mult follow a mult.  What's not OK is to have a
2383         mult follow an mfhi.
2384         (Convert): Comment out incorrect rounding code.
2385
2386 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
2387
2388         * interp.c (sim_monitor): Improved monitor printf
2389         simulation. Tidied up simulator warnings, and added "--log" option
2390         for directing warning message output.
2391         * gencode.c: Use sim_warning() rather than WARNING macro.
2392
2393 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2394
2395         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2396         getopt1.o, rather than on gencode.c.  Link objects together.
2397         Don't link against -liberty.
2398         (gencode.o, getopt.o, getopt1.o): New targets.
2399         * gencode.c: Include <ctype.h> and "ansidecl.h".
2400         (AND): Undefine after including "ansidecl.h".
2401         (ULONG_MAX): Define if not defined.
2402         (OP_*): Don't define macros; now defined in opcode/mips.h.
2403         (main): Call my_strtoul rather than strtoul.
2404         (my_strtoul): New static function.
2405
2406 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
2407
2408         * gencode.c (process_instructions):  Generate word64 and uword64
2409         instead of `long long' and `unsigned long long' data types.
2410         * interp.c:  #include sysdep.h to get signals, and define default
2411         for SIGBUS.
2412         * (Convert):  Work around for Visual-C++ compiler bug with type
2413         conversion.
2414         * support.h:  Make things compile under Visual-C++ by using
2415         __int64 instead of `long long'.  Change many refs to long long
2416         into word64/uword64 typedefs.
2417
2418 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
2419
2420         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2421         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2422         (docdir): Removed.
2423         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2424         (AC_PROG_INSTALL): Added.
2425         (AC_PROG_CC): Moved to before configure.host call.
2426         * configure: Rebuilt.
2427
2428 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
2429
2430         * configure.in: Define @SIMCONF@ depending on mips target.
2431         * configure: Rebuild.
2432         * Makefile.in (run): Add @SIMCONF@ to control simulator
2433         construction.
2434         * gencode.c: Change LOADDRMASK to 64bit memory model only.
2435         * interp.c: Remove some debugging, provide more detailed error
2436         messages, update memory accesses to use LOADDRMASK.
2437
2438 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
2439
2440         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2441         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
2442         stamp-h.
2443         * configure: Rebuild.
2444         * config.in: New file, generated by autoheader.
2445         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
2446         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
2447         HAVE_ANINT and HAVE_AINT, as appropriate.
2448         * Makefile.in (run): Use @LIBS@ rather than -lm.
2449         (interp.o): Depend upon config.h.
2450         (Makefile): Just rebuild Makefile.
2451         (clean): Remove stamp-h.
2452         (mostlyclean): Make the same as clean, not as distclean.
2453         (config.h, stamp-h): New targets.
2454
2455 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2456
2457         * interp.c (ColdReset): Fix boolean test. Make all simulator
2458         globals static.
2459
2460 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
2461
2462         * interp.c (xfer_direct_word, xfer_direct_long,
2463         swap_direct_word, swap_direct_long, xfer_big_word,
2464         xfer_big_long, xfer_little_word, xfer_little_long,
2465         swap_word,swap_long): Added.
2466         * interp.c (ColdReset): Provide function indirection to
2467         host<->simulated_target transfer routines.
2468         * interp.c (sim_store_register, sim_fetch_register): Updated to
2469         make use of indirected transfer routines.
2470
2471 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
2472
2473         * gencode.c (process_instructions): Ensure FP ABS instruction
2474         recognised.
2475         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2476         system call support.
2477
2478 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
2479
2480         * interp.c (sim_do_command): Complain if callback structure not
2481         initialised.
2482
2483 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
2484
2485         * interp.c (Convert): Provide round-to-nearest and round-to-zero
2486         support for Sun hosts.
2487         * Makefile.in (gencode): Ensure the host compiler and libraries
2488         used for cross-hosted build.
2489
2490 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
2491
2492         * interp.c, gencode.c: Some more (TODO) tidying.
2493
2494 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
2495
2496         * gencode.c, interp.c: Replaced explicit long long references with
2497         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2498         * support.h (SET64LO, SET64HI): Macros added.
2499
2500 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
2501
2502         * configure: Regenerate with autoconf 2.7.
2503
2504 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
2505
2506         * interp.c (LoadMemory): Enclose text following #endif in /* */.
2507         * support.h: Remove superfluous "1" from #if.
2508         * support.h (CHECKSIM): Remove stray 'a' at end of line.
2509
2510 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
2511
2512         * interp.c (StoreFPR): Control UndefinedResult() call on
2513         WARN_RESULT manifest.
2514
2515 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
2516
2517         * gencode.c: Tidied instruction decoding, and added FP instruction
2518         support.
2519
2520         * interp.c: Added dineroIII, and BSD profiling support. Also
2521         run-time FP handling.
2522
2523 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
2524
2525         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2526         gencode.c, interp.c, support.h: created.