1 2002-02-27 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (check_u64): New function which in the future will
4 check whether 64-bit instructions are usable and signal an
5 exception if not. Currently a no-op.
6 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
7 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
8 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
9 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
11 * mips.igen (check_fpu): New function which in the future will
12 check whether FPU instructions are usable and signal an exception
13 if not. Currently a no-op.
14 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
15 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
16 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
17 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
18 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
19 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
20 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
21 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
23 2002-02-27 Chris Demetriou <cgd@broadcom.com>
25 * mips.igen (do_load_left, do_load_right): Move to be immediately
27 (do_store_left, do_store_right): Move to be immediately following
30 2002-02-27 Chris Demetriou <cgd@broadcom.com>
32 * mips.igen (mipsV): New model name. Also, add it to
33 all instructions and functions where it is appropriate.
35 2002-02-18 Chris Demetriou <cgd@broadcom.com>
37 * mips.igen: For all functions and instructions, list model
38 names that support that instruction one per line.
40 2002-02-11 Chris Demetriou <cgd@broadcom.com>
42 * mips.igen: Add some additional comments about supported
43 models, and about which instructions go where.
44 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
45 order as is used in the rest of the file.
47 2002-02-11 Chris Demetriou <cgd@broadcom.com>
49 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
50 indicating that ALU32_END or ALU64_END are there to check
52 (DADD): Likewise, but also remove previous comment about
55 2002-02-10 Chris Demetriou <cgd@broadcom.com>
57 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
58 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
59 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
60 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
61 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
62 fields (i.e., add and move commas) so that they more closely
63 match the MIPS ISA documentation opcode partitioning.
65 2002-02-10 Chris Demetriou <cgd@broadcom.com>
67 * mips.igen (ADDI): Print immediate value.
69 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
70 (SLL): Print "nop" specially, and don't run the code
71 that does the shift for the "nop" case.
73 2001-11-17 Fred Fish <fnf@redhat.com>
75 * sim-main.h (float_operation): Move enum declaration outside
76 of _sim_cpu struct declaration.
78 2001-04-12 Jim Blandy <jimb@redhat.com>
80 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
81 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
83 * sim-main.h (COCIDX): Remove definition; this isn't supported by
84 PENDING_FILL, and you can get the intended effect gracefully by
85 calling PENDING_SCHED directly.
87 2001-02-23 Ben Elliston <bje@redhat.com>
89 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
90 already defined elsewhere.
92 2001-02-19 Ben Elliston <bje@redhat.com>
94 * sim-main.h (sim_monitor): Return an int.
95 * interp.c (sim_monitor): Add return values.
96 (signal_exception): Handle error conditions from sim_monitor.
98 2001-02-08 Ben Elliston <bje@redhat.com>
100 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
101 (store_memory): Likewise, pass cia to sim_core_write*.
103 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
105 On advice from Chris G. Demetriou <cgd@sibyte.com>:
106 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
108 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
110 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
111 * Makefile.in: Don't delete *.igen when cleaning directory.
113 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
115 * m16.igen (break): Call SignalException not sim_engine_halt.
117 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
120 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
122 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
124 * mips.igen (MxC1, DMxC1): Fix printf formatting.
126 2000-05-24 Michael Hayes <mhayes@cygnus.com>
128 * mips.igen (do_dmultx): Fix typo.
130 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
132 * configure: Regenerated to track ../common/aclocal.m4 changes.
134 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
136 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
138 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
140 * sim-main.h (GPR_CLEAR): Define macro.
142 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
144 * interp.c (decode_coproc): Output long using %lx and not %s.
146 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
148 * interp.c (sim_open): Sort & extend dummy memory regions for
149 --board=jmr3904 for eCos.
151 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
153 * configure: Regenerated.
155 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
157 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
158 calls, conditional on the simulator being in verbose mode.
160 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
162 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
163 cache don't get ReservedInstruction traps.
165 1999-11-29 Mark Salter <msalter@cygnus.com>
167 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
168 to clear status bits in sdisr register. This is how the hardware works.
170 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
171 being used by cygmon.
173 1999-11-11 Andrew Haley <aph@cygnus.com>
175 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
178 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
180 * mips.igen (MULT): Correct previous mis-applied patch.
182 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
184 * mips.igen (delayslot32): Handle sequence like
185 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
186 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
187 (MULT): Actually pass the third register...
189 1999-09-03 Mark Salter <msalter@cygnus.com>
191 * interp.c (sim_open): Added more memory aliases for additional
192 hardware being touched by cygmon on jmr3904 board.
194 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
196 * configure: Regenerated to track ../common/aclocal.m4 changes.
198 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
200 * interp.c (sim_store_register): Handle case where client - GDB -
201 specifies that a 4 byte register is 8 bytes in size.
202 (sim_fetch_register): Ditto.
204 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
206 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
207 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
208 (idt_monitor_base): Base address for IDT monitor traps.
209 (pmon_monitor_base): Ditto for PMON.
210 (lsipmon_monitor_base): Ditto for LSI PMON.
211 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
212 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
213 (sim_firmware_command): New function.
214 (mips_option_handler): Call it for OPTION_FIRMWARE.
215 (sim_open): Allocate memory for idt_monitor region. If "--board"
216 option was given, add no monitor by default. Add BREAK hooks only if
217 monitors are also there.
219 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
221 * interp.c (sim_monitor): Flush output before reading input.
223 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
225 * tconfig.in (SIM_HANDLES_LMA): Always define.
227 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
229 From Mark Salter <msalter@cygnus.com>:
230 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
231 (sim_open): Add setup for BSP board.
233 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
235 * mips.igen (MULT, MULTU): Add syntax for two operand version.
236 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
237 them as unimplemented.
239 1999-05-08 Felix Lee <flee@cygnus.com>
241 * configure: Regenerated to track ../common/aclocal.m4 changes.
243 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
245 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
247 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
249 * configure.in: Any mips64vr5*-*-* target should have
250 -DTARGET_ENABLE_FR=1.
251 (default_endian): Any mips64vr*el-*-* target should default to
253 * configure: Re-generate.
255 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
257 * mips.igen (ldl): Extend from _16_, not 32.
259 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
261 * interp.c (sim_store_register): Force registers written to by GDB
262 into an un-interpreted state.
264 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
266 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
267 CPU, start periodic background I/O polls.
268 (tx3904sio_poll): New function: periodic I/O poller.
270 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
272 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
274 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
276 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
279 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
281 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
282 (load_word): Call SIM_CORE_SIGNAL hook on error.
283 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
284 starting. For exception dispatching, pass PC instead of NULL_CIA.
285 (decode_coproc): Use COP0_BADVADDR to store faulting address.
286 * sim-main.h (COP0_BADVADDR): Define.
287 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
288 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
289 (_sim_cpu): Add exc_* fields to store register value snapshots.
290 * mips.igen (*): Replace memory-related SignalException* calls
291 with references to SIM_CORE_SIGNAL hook.
293 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
295 * sim-main.c (*): Minor warning cleanups.
297 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
299 * m16.igen (DADDIU5): Correct type-o.
301 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
303 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
306 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
308 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
310 (interp.o): Add dependency on itable.h
311 (oengine.c, gencode): Delete remaining references.
312 (BUILT_SRC_FROM_GEN): Clean up.
314 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
317 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
318 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
320 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
321 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
322 Drop the "64" qualifier to get the HACK generator working.
323 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
324 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
325 qualifier to get the hack generator working.
326 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
328 (DSLLV): Use do_dsllv.
331 (DSRLV): Use do_dsrlv.
332 (BC1): Move *vr4100 to get the HACK generator working.
333 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
334 get the HACK generator working.
335 (MACC) Rename to get the HACK generator working.
336 (DMACC,MACCS,DMACCS): Add the 64.
338 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
340 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
341 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
343 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
345 * mips/interp.c (DEBUG): Cleanups.
347 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
349 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
350 (tx3904sio_tickle): fflush after a stdout character output.
352 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
354 * interp.c (sim_close): Uninstall modules.
356 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
358 * sim-main.h, interp.c (sim_monitor): Change to global
361 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
363 * configure.in (vr4100): Only include vr4100 instructions in
365 * configure: Re-generate.
366 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
368 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
370 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
371 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
374 * configure.in (sim_default_gen, sim_use_gen): Replace with
376 (--enable-sim-igen): Delete config option. Always using IGEN.
377 * configure: Re-generate.
379 * Makefile.in (gencode): Kill, kill, kill.
382 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
384 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
385 bit mips16 igen simulator.
386 * configure: Re-generate.
388 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
389 as part of vr4100 ISA.
390 * vr.igen: Mark all instructions as 64 bit only.
392 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
394 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
397 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
399 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
400 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
401 * configure: Re-generate.
403 * m16.igen (BREAK): Define breakpoint instruction.
404 (JALX32): Mark instruction as mips16 and not r3900.
405 * mips.igen (C.cond.fmt): Fix typo in instruction format.
407 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
409 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
411 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
412 insn as a debug breakpoint.
414 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
416 (PENDING_SCHED): Clean up trace statement.
417 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
418 (PENDING_FILL): Delay write by only one cycle.
419 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
421 * sim-main.c (pending_tick): Clean up trace statements. Add trace
423 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
425 (pending_tick): Move incrementing of index to FOR statement.
426 (pending_tick): Only update PENDING_OUT after a write has occured.
428 * configure.in: Add explicit mips-lsi-* target. Use gencode to
430 * configure: Re-generate.
432 * interp.c (sim_engine_run OLD): Delete explicit call to
433 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
435 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
437 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
438 interrupt level number to match changed SignalExceptionInterrupt
441 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
443 * interp.c: #include "itable.h" if WITH_IGEN.
444 (get_insn_name): New function.
445 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
446 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
448 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
450 * configure: Rebuilt to inhale new common/aclocal.m4.
452 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
454 * dv-tx3904sio.c: Include sim-assert.h.
456 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
458 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
459 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
460 Reorganize target-specific sim-hardware checks.
461 * configure: rebuilt.
462 * interp.c (sim_open): For tx39 target boards, set
463 OPERATING_ENVIRONMENT, add tx3904sio devices.
464 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
465 ROM executables. Install dv-sockser into sim-modules list.
467 * dv-tx3904irc.c: Compiler warning clean-up.
468 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
469 frequent hw-trace messages.
471 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
473 * vr.igen (MulAcc): Identify as a vr4100 specific function.
475 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
477 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
480 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
481 * mips.igen: Define vr4100 model. Include vr.igen.
482 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
484 * mips.igen (check_mf_hilo): Correct check.
486 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
488 * sim-main.h (interrupt_event): Add prototype.
490 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
491 register_ptr, register_value.
492 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
494 * sim-main.h (tracefh): Make extern.
496 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
498 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
499 Reduce unnecessarily high timer event frequency.
500 * dv-tx3904cpu.c: Ditto for interrupt event.
502 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
504 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
506 (interrupt_event): Made non-static.
508 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
509 interchange of configuration values for external vs. internal
512 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
514 * mips.igen (BREAK): Moved code to here for
515 simulator-reserved break instructions.
516 * gencode.c (build_instruction): Ditto.
517 * interp.c (signal_exception): Code moved from here. Non-
518 reserved instructions now use exception vector, rather
520 * sim-main.h: Moved magic constants to here.
522 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
524 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
525 register upon non-zero interrupt event level, clear upon zero
527 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
528 by passing zero event value.
529 (*_io_{read,write}_buffer): Endianness fixes.
530 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
531 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
533 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
534 serial I/O and timer module at base address 0xFFFF0000.
536 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
538 * mips.igen (SWC1) : Correct the handling of ReverseEndian
541 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
543 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
547 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
549 * dv-tx3904tmr.c: New file - implements tx3904 timer.
550 * dv-tx3904{irc,cpu}.c: Mild reformatting.
551 * configure.in: Include tx3904tmr in hw_device list.
552 * configure: Rebuilt.
553 * interp.c (sim_open): Instantiate three timer instances.
554 Fix address typo of tx3904irc instance.
556 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
558 * interp.c (signal_exception): SystemCall exception now uses
559 the exception vector.
561 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
563 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
566 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
568 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
570 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
572 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
574 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
575 sim-main.h. Declare a struct hw_descriptor instead of struct
576 hw_device_descriptor.
578 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
580 * mips.igen (do_store_left, do_load_left): Compute nr of left and
581 right bits and then re-align left hand bytes to correct byte
582 lanes. Fix incorrect computation in do_store_left when loading
583 bytes from second word.
585 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
587 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
588 * interp.c (sim_open): Only create a device tree when HW is
591 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
592 * interp.c (signal_exception): Ditto.
594 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
596 * gencode.c: Mark BEGEZALL as LIKELY.
598 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
600 * sim-main.h (ALU32_END): Sign extend 32 bit results.
601 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
603 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
605 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
606 modules. Recognize TX39 target with "mips*tx39" pattern.
607 * configure: Rebuilt.
608 * sim-main.h (*): Added many macros defining bits in
609 TX39 control registers.
610 (SignalInterrupt): Send actual PC instead of NULL.
611 (SignalNMIReset): New exception type.
612 * interp.c (board): New variable for future use to identify
613 a particular board being simulated.
614 (mips_option_handler,mips_options): Added "--board" option.
615 (interrupt_event): Send actual PC.
616 (sim_open): Make memory layout conditional on board setting.
617 (signal_exception): Initial implementation of hardware interrupt
618 handling. Accept another break instruction variant for simulator
620 (decode_coproc): Implement RFE instruction for TX39.
621 (mips.igen): Decode RFE instruction as such.
622 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
623 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
624 bbegin to implement memory map.
625 * dv-tx3904cpu.c: New file.
626 * dv-tx3904irc.c: New file.
628 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
630 * mips.igen (check_mt_hilo): Create a separate r3900 version.
632 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
634 * tx.igen (madd,maddu): Replace calls to check_op_hilo
635 with calls to check_div_hilo.
637 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
639 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
640 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
641 Add special r3900 version of do_mult_hilo.
642 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
643 with calls to check_mult_hilo.
644 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
645 with calls to check_div_hilo.
647 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
649 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
650 Document a replacement.
652 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
654 * interp.c (sim_monitor): Make mon_printf work.
656 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
658 * sim-main.h (INSN_NAME): New arg `cpu'.
660 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
662 * configure: Regenerated to track ../common/aclocal.m4 changes.
664 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
666 * configure: Regenerated to track ../common/aclocal.m4 changes.
669 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
671 * acconfig.h: New file.
672 * configure.in: Reverted change of Apr 24; use sinclude again.
674 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
676 * configure: Regenerated to track ../common/aclocal.m4 changes.
679 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
681 * configure.in: Don't call sinclude.
683 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
685 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
687 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
689 * mips.igen (ERET): Implement.
691 * interp.c (decode_coproc): Return sign-extended EPC.
693 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
695 * interp.c (signal_exception): Do not ignore Trap.
696 (signal_exception): On TRAP, restart at exception address.
697 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
698 (signal_exception): Update.
699 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
700 so that TRAP instructions are caught.
702 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
704 * sim-main.h (struct hilo_access, struct hilo_history): Define,
705 contains HI/LO access history.
706 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
707 (HIACCESS, LOACCESS): Delete, replace with
708 (HIHISTORY, LOHISTORY): New macros.
709 (CHECKHILO): Delete all, moved to mips.igen
711 * gencode.c (build_instruction): Do not generate checks for
712 correct HI/LO register usage.
714 * interp.c (old_engine_run): Delete checks for correct HI/LO
717 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
718 check_mf_cycles): New functions.
719 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
720 do_divu, domultx, do_mult, do_multu): Use.
722 * tx.igen ("madd", "maddu"): Use.
724 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
726 * mips.igen (DSRAV): Use function do_dsrav.
727 (SRAV): Use new function do_srav.
729 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
730 (B): Sign extend 11 bit immediate.
731 (EXT-B*): Shift 16 bit immediate left by 1.
732 (ADDIU*): Don't sign extend immediate value.
734 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
736 * m16run.c (sim_engine_run): Restore CIA after handling an event.
738 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
741 * mips.igen (delayslot32, nullify_next_insn): New functions.
742 (m16.igen): Always include.
743 (do_*): Add more tracing.
745 * m16.igen (delayslot16): Add NIA argument, could be called by a
746 32 bit MIPS16 instruction.
748 * interp.c (ifetch16): Move function from here.
749 * sim-main.c (ifetch16): To here.
751 * sim-main.c (ifetch16, ifetch32): Update to match current
752 implementations of LH, LW.
753 (signal_exception): Don't print out incorrect hex value of illegal
756 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
758 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
761 * m16.igen: Implement MIPS16 instructions.
763 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
764 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
765 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
766 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
767 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
768 bodies of corresponding code from 32 bit insn to these. Also used
769 by MIPS16 versions of functions.
771 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
772 (IMEM16): Drop NR argument from macro.
774 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
776 * Makefile.in (SIM_OBJS): Add sim-main.o.
778 * sim-main.h (address_translation, load_memory, store_memory,
779 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
781 (pr_addr, pr_uword64): Declare.
782 (sim-main.c): Include when H_REVEALS_MODULE_P.
784 * interp.c (address_translation, load_memory, store_memory,
785 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
787 * sim-main.c: To here. Fix compilation problems.
789 * configure.in: Enable inlining.
790 * configure: Re-config.
792 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
794 * configure: Regenerated to track ../common/aclocal.m4 changes.
796 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
798 * mips.igen: Include tx.igen.
799 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
800 * tx.igen: New file, contains MADD and MADDU.
802 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
803 the hardwired constant `7'.
804 (store_memory): Ditto.
805 (LOADDRMASK): Move definition to sim-main.h.
807 mips.igen (MTC0): Enable for r3900.
810 mips.igen (do_load_byte): Delete.
811 (do_load, do_store, do_load_left, do_load_write, do_store_left,
812 do_store_right): New functions.
813 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
815 configure.in: Let the tx39 use igen again.
818 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
820 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
821 not an address sized quantity. Return zero for cache sizes.
823 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
825 * mips.igen (r3900): r3900 does not support 64 bit integer
828 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
830 * configure.in (mipstx39*-*-*): Use gencode simulator rather
832 * configure : Rebuild.
834 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
836 * configure: Regenerated to track ../common/aclocal.m4 changes.
838 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
840 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
842 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
844 * configure: Regenerated to track ../common/aclocal.m4 changes.
845 * config.in: Regenerated to track ../common/aclocal.m4 changes.
847 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
849 * configure: Regenerated to track ../common/aclocal.m4 changes.
851 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
853 * interp.c (Max, Min): Comment out functions. Not yet used.
855 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
857 * configure: Regenerated to track ../common/aclocal.m4 changes.
859 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
861 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
862 configurable settings for stand-alone simulator.
864 * configure.in: Added X11 search, just in case.
866 * configure: Regenerated.
868 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
870 * interp.c (sim_write, sim_read, load_memory, store_memory):
871 Replace sim_core_*_map with read_map, write_map, exec_map resp.
873 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
875 * sim-main.h (GETFCC): Return an unsigned value.
877 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
879 * mips.igen (DIV): Fix check for -1 / MIN_INT.
880 (DADD): Result destination is RD not RT.
882 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
884 * sim-main.h (HIACCESS, LOACCESS): Always define.
886 * mdmx.igen (Maxi, Mini): Rename Max, Min.
888 * interp.c (sim_info): Delete.
890 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
892 * interp.c (DECLARE_OPTION_HANDLER): Use it.
893 (mips_option_handler): New argument `cpu'.
894 (sim_open): Update call to sim_add_option_table.
896 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
898 * mips.igen (CxC1): Add tracing.
900 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
902 * sim-main.h (Max, Min): Declare.
904 * interp.c (Max, Min): New functions.
906 * mips.igen (BC1): Add tracing.
908 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
910 * interp.c Added memory map for stack in vr4100
912 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
914 * interp.c (load_memory): Add missing "break"'s.
916 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
918 * interp.c (sim_store_register, sim_fetch_register): Pass in
919 length parameter. Return -1.
921 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
923 * interp.c: Added hardware init hook, fixed warnings.
925 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
927 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
929 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
931 * interp.c (ifetch16): New function.
933 * sim-main.h (IMEM32): Rename IMEM.
934 (IMEM16_IMMED): Define.
936 (DELAY_SLOT): Update.
938 * m16run.c (sim_engine_run): New file.
940 * m16.igen: All instructions except LB.
941 (LB): Call do_load_byte.
942 * mips.igen (do_load_byte): New function.
943 (LB): Call do_load_byte.
945 * mips.igen: Move spec for insn bit size and high bit from here.
946 * Makefile.in (tmp-igen, tmp-m16): To here.
948 * m16.dc: New file, decode mips16 instructions.
950 * Makefile.in (SIM_NO_ALL): Define.
951 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
953 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
955 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
956 point unit to 32 bit registers.
957 * configure: Re-generate.
959 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
961 * configure.in (sim_use_gen): Make IGEN the default simulator
962 generator for generic 32 and 64 bit mips targets.
963 * configure: Re-generate.
965 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
967 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
970 * interp.c (sim_fetch_register, sim_store_register): Read/write
971 FGR from correct location.
972 (sim_open): Set size of FGR's according to
973 WITH_TARGET_FLOATING_POINT_BITSIZE.
975 * sim-main.h (FGR): Store floating point registers in a separate
978 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
980 * configure: Regenerated to track ../common/aclocal.m4 changes.
982 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
984 * interp.c (ColdReset): Call PENDING_INVALIDATE.
986 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
988 * interp.c (pending_tick): New function. Deliver pending writes.
990 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
991 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
992 it can handle mixed sized quantites and single bits.
994 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
996 * interp.c (oengine.h): Do not include when building with IGEN.
997 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
998 (sim_info): Ditto for PROCESSOR_64BIT.
999 (sim_monitor): Replace ut_reg with unsigned_word.
1000 (*): Ditto for t_reg.
1001 (LOADDRMASK): Define.
1002 (sim_open): Remove defunct check that host FP is IEEE compliant,
1003 using software to emulate floating point.
1004 (value_fpr, ...): Always compile, was conditional on HASFPU.
1006 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1008 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1011 * interp.c (SD, CPU): Define.
1012 (mips_option_handler): Set flags in each CPU.
1013 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1014 (sim_close): Do not clear STATE, deleted anyway.
1015 (sim_write, sim_read): Assume CPU zero's vm should be used for
1017 (sim_create_inferior): Set the PC for all processors.
1018 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1020 (mips16_entry): Pass correct nr of args to store_word, load_word.
1021 (ColdReset): Cold reset all cpu's.
1022 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1023 (sim_monitor, load_memory, store_memory, signal_exception): Use
1024 `CPU' instead of STATE_CPU.
1027 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1030 * sim-main.h (signal_exception): Add sim_cpu arg.
1031 (SignalException*): Pass both SD and CPU to signal_exception.
1032 * interp.c (signal_exception): Update.
1034 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1036 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1037 address_translation): Ditto
1038 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1040 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1042 * configure: Regenerated to track ../common/aclocal.m4 changes.
1044 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1046 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1048 * mips.igen (model): Map processor names onto BFD name.
1050 * sim-main.h (CPU_CIA): Delete.
1051 (SET_CIA, GET_CIA): Define
1053 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1055 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1058 * configure.in (default_endian): Configure a big-endian simulator
1060 * configure: Re-generate.
1062 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1064 * configure: Regenerated to track ../common/aclocal.m4 changes.
1066 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1068 * interp.c (sim_monitor): Handle Densan monitor outbyte
1069 and inbyte functions.
1071 1997-12-29 Felix Lee <flee@cygnus.com>
1073 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1075 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1077 * Makefile.in (tmp-igen): Arrange for $zero to always be
1078 reset to zero after every instruction.
1080 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1082 * configure: Regenerated to track ../common/aclocal.m4 changes.
1085 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1087 * mips.igen (MSUB): Fix to work like MADD.
1088 * gencode.c (MSUB): Similarly.
1090 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1092 * configure: Regenerated to track ../common/aclocal.m4 changes.
1094 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1096 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1098 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1100 * sim-main.h (sim-fpu.h): Include.
1102 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1103 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1104 using host independant sim_fpu module.
1106 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1108 * interp.c (signal_exception): Report internal errors with SIGABRT
1111 * sim-main.h (C0_CONFIG): New register.
1112 (signal.h): No longer include.
1114 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1116 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1118 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1120 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1122 * mips.igen: Tag vr5000 instructions.
1123 (ANDI): Was missing mipsIV model, fix assembler syntax.
1124 (do_c_cond_fmt): New function.
1125 (C.cond.fmt): Handle mips I-III which do not support CC field
1127 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1128 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1130 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1131 vr5000 which saves LO in a GPR separatly.
1133 * configure.in (enable-sim-igen): For vr5000, select vr5000
1134 specific instructions.
1135 * configure: Re-generate.
1137 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1139 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1141 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1142 fmt_uninterpreted_64 bit cases to switch. Convert to
1145 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1147 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1148 as specified in IV3.2 spec.
1149 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1151 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1153 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1154 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1155 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1156 PENDING_FILL versions of instructions. Simplify.
1158 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1160 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1162 (MTHI, MFHI): Disable code checking HI-LO.
1164 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1166 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1168 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1170 * gencode.c (build_mips16_operands): Replace IPC with cia.
1172 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1173 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1175 (UndefinedResult): Replace function with macro/function
1177 (sim_engine_run): Don't save PC in IPC.
1179 * sim-main.h (IPC): Delete.
1182 * interp.c (signal_exception, store_word, load_word,
1183 address_translation, load_memory, store_memory, cache_op,
1184 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1185 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1186 current instruction address - cia - argument.
1187 (sim_read, sim_write): Call address_translation directly.
1188 (sim_engine_run): Rename variable vaddr to cia.
1189 (signal_exception): Pass cia to sim_monitor
1191 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1192 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1193 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1195 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1196 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1199 * interp.c (signal_exception): Pass restart address to
1202 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1203 idecode.o): Add dependency.
1205 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1207 (DELAY_SLOT): Update NIA not PC with branch address.
1208 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1210 * mips.igen: Use CIA not PC in branch calculations.
1211 (illegal): Call SignalException.
1212 (BEQ, ADDIU): Fix assembler.
1214 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1216 * m16.igen (JALX): Was missing.
1218 * configure.in (enable-sim-igen): New configuration option.
1219 * configure: Re-generate.
1221 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1223 * interp.c (load_memory, store_memory): Delete parameter RAW.
1224 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1225 bypassing {load,store}_memory.
1227 * sim-main.h (ByteSwapMem): Delete definition.
1229 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1231 * interp.c (sim_do_command, sim_commands): Delete mips specific
1232 commands. Handled by module sim-options.
1234 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1235 (WITH_MODULO_MEMORY): Define.
1237 * interp.c (sim_info): Delete code printing memory size.
1239 * interp.c (mips_size): Nee sim_size, delete function.
1241 (monitor, monitor_base, monitor_size): Delete global variables.
1242 (sim_open, sim_close): Delete code creating monitor and other
1243 memory regions. Use sim-memopts module, via sim_do_commandf, to
1244 manage memory regions.
1245 (load_memory, store_memory): Use sim-core for memory model.
1247 * interp.c (address_translation): Delete all memory map code
1248 except line forcing 32 bit addresses.
1250 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1252 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1255 * interp.c (logfh, logfile): Delete globals.
1256 (sim_open, sim_close): Delete code opening & closing log file.
1257 (mips_option_handler): Delete -l and -n options.
1258 (OPTION mips_options): Ditto.
1260 * interp.c (OPTION mips_options): Rename option trace to dinero.
1261 (mips_option_handler): Update.
1263 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1265 * interp.c (fetch_str): New function.
1266 (sim_monitor): Rewrite using sim_read & sim_write.
1267 (sim_open): Check magic number.
1268 (sim_open): Write monitor vectors into memory using sim_write.
1269 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1270 (sim_read, sim_write): Simplify - transfer data one byte at a
1272 (load_memory, store_memory): Clarify meaning of parameter RAW.
1274 * sim-main.h (isHOST): Defete definition.
1275 (isTARGET): Mark as depreciated.
1276 (address_translation): Delete parameter HOST.
1278 * interp.c (address_translation): Delete parameter HOST.
1280 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1284 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1285 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1287 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1289 * mips.igen: Add model filter field to records.
1291 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1293 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1295 interp.c (sim_engine_run): Do not compile function sim_engine_run
1296 when WITH_IGEN == 1.
1298 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1299 target architecture.
1301 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1302 igen. Replace with configuration variables sim_igen_flags /
1305 * m16.igen: New file. Copy mips16 insns here.
1306 * mips.igen: From here.
1308 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1310 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1312 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1314 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1316 * gencode.c (build_instruction): Follow sim_write's lead in using
1317 BigEndianMem instead of !ByteSwapMem.
1319 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1321 * configure.in (sim_gen): Dependent on target, select type of
1322 generator. Always select old style generator.
1324 configure: Re-generate.
1326 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1328 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1329 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1330 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1331 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1332 SIM_@sim_gen@_*, set by autoconf.
1334 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1336 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1338 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1339 CURRENT_FLOATING_POINT instead.
1341 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1342 (address_translation): Raise exception InstructionFetch when
1343 translation fails and isINSTRUCTION.
1345 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1346 sim_engine_run): Change type of of vaddr and paddr to
1348 (address_translation, prefetch, load_memory, store_memory,
1349 cache_op): Change type of vAddr and pAddr to address_word.
1351 * gencode.c (build_instruction): Change type of vaddr and paddr to
1354 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1357 macro to obtain result of ALU op.
1359 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1361 * interp.c (sim_info): Call profile_print.
1363 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1365 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1367 * sim-main.h (WITH_PROFILE): Do not define, defined in
1368 common/sim-config.h. Use sim-profile module.
1369 (simPROFILE): Delete defintion.
1371 * interp.c (PROFILE): Delete definition.
1372 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1373 (sim_close): Delete code writing profile histogram.
1374 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1376 (sim_engine_run): Delete code profiling the PC.
1378 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1380 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1382 * interp.c (sim_monitor): Make register pointers of type
1385 * sim-main.h: Make registers of type unsigned_word not
1388 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1390 * interp.c (sync_operation): Rename from SyncOperation, make
1391 global, add SD argument.
1392 (prefetch): Rename from Prefetch, make global, add SD argument.
1393 (decode_coproc): Make global.
1395 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1397 * gencode.c (build_instruction): Generate DecodeCoproc not
1398 decode_coproc calls.
1400 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1401 (SizeFGR): Move to sim-main.h
1402 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1403 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1404 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1406 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1407 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1408 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1409 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1410 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1411 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1413 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1415 (sim-alu.h): Include.
1416 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1417 (sim_cia): Typedef to instruction_address.
1419 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1421 * Makefile.in (interp.o): Rename generated file engine.c to
1426 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1428 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1430 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1432 * gencode.c (build_instruction): For "FPSQRT", output correct
1433 number of arguments to Recip.
1435 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1437 * Makefile.in (interp.o): Depends on sim-main.h
1439 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1441 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1442 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1443 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1444 STATE, DSSTATE): Define
1445 (GPR, FGRIDX, ..): Define.
1447 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1448 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1449 (GPR, FGRIDX, ...): Delete macros.
1451 * interp.c: Update names to match defines from sim-main.h
1453 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1455 * interp.c (sim_monitor): Add SD argument.
1456 (sim_warning): Delete. Replace calls with calls to
1458 (sim_error): Delete. Replace calls with sim_io_error.
1459 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1460 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1461 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1463 (mips_size): Rename from sim_size. Add SD argument.
1465 * interp.c (simulator): Delete global variable.
1466 (callback): Delete global variable.
1467 (mips_option_handler, sim_open, sim_write, sim_read,
1468 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1469 sim_size,sim_monitor): Use sim_io_* not callback->*.
1470 (sim_open): ZALLOC simulator struct.
1471 (PROFILE): Do not define.
1473 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1475 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1476 support.h with corresponding code.
1478 * sim-main.h (word64, uword64), support.h: Move definition to
1480 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1483 * Makefile.in: Update dependencies
1484 * interp.c: Do not include.
1486 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1488 * interp.c (address_translation, load_memory, store_memory,
1489 cache_op): Rename to from AddressTranslation et.al., make global,
1492 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1495 * interp.c (SignalException): Rename to signal_exception, make
1498 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1500 * sim-main.h (SignalException, SignalExceptionInterrupt,
1501 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1502 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1503 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1506 * interp.c, support.h: Use.
1508 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1511 to value_fpr / store_fpr. Add SD argument.
1512 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1513 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1515 * sim-main.h (ValueFPR, StoreFPR): Define.
1517 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1519 * interp.c (sim_engine_run): Check consistency between configure
1520 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1523 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1524 (mips_fpu): Configure WITH_FLOATING_POINT.
1525 (mips_endian): Configure WITH_TARGET_ENDIAN.
1526 * configure: Update.
1528 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530 * configure: Regenerated to track ../common/aclocal.m4 changes.
1532 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1534 * configure: Regenerated.
1536 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1538 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1540 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1542 * gencode.c (print_igen_insn_models): Assume certain architectures
1543 include all mips* instructions.
1544 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1547 * Makefile.in (tmp.igen): Add target. Generate igen input from
1550 * gencode.c (FEATURE_IGEN): Define.
1551 (main): Add --igen option. Generate output in igen format.
1552 (process_instructions): Format output according to igen option.
1553 (print_igen_insn_format): New function.
1554 (print_igen_insn_models): New function.
1555 (process_instructions): Only issue warnings and ignore
1556 instructions when no FEATURE_IGEN.
1558 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1560 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1563 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1565 * configure: Regenerated to track ../common/aclocal.m4 changes.
1567 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1569 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1570 SIM_RESERVED_BITS): Delete, moved to common.
1571 (SIM_EXTRA_CFLAGS): Update.
1573 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1575 * configure.in: Configure non-strict memory alignment.
1576 * configure: Regenerated to track ../common/aclocal.m4 changes.
1578 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1580 * configure: Regenerated to track ../common/aclocal.m4 changes.
1582 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1584 * gencode.c (SDBBP,DERET): Added (3900) insns.
1585 (RFE): Turn on for 3900.
1586 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1587 (dsstate): Made global.
1588 (SUBTARGET_R3900): Added.
1589 (CANCELDELAYSLOT): New.
1590 (SignalException): Ignore SystemCall rather than ignore and
1591 terminate. Add DebugBreakPoint handling.
1592 (decode_coproc): New insns RFE, DERET; and new registers Debug
1593 and DEPC protected by SUBTARGET_R3900.
1594 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1596 * Makefile.in,configure.in: Add mips subtarget option.
1597 * configure: Update.
1599 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1601 * gencode.c: Add r3900 (tx39).
1604 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1606 * gencode.c (build_instruction): Don't need to subtract 4 for
1609 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1611 * interp.c: Correct some HASFPU problems.
1613 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1615 * configure: Regenerated to track ../common/aclocal.m4 changes.
1617 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1619 * interp.c (mips_options): Fix samples option short form, should
1622 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1624 * interp.c (sim_info): Enable info code. Was just returning.
1626 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1628 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1631 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1633 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1635 (build_instruction): Ditto for LL.
1637 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1639 * configure: Regenerated to track ../common/aclocal.m4 changes.
1641 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1643 * configure: Regenerated to track ../common/aclocal.m4 changes.
1646 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1648 * interp.c (sim_open): Add call to sim_analyze_program, update
1651 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1653 * interp.c (sim_kill): Delete.
1654 (sim_create_inferior): Add ABFD argument. Set PC from same.
1655 (sim_load): Move code initializing trap handlers from here.
1656 (sim_open): To here.
1657 (sim_load): Delete, use sim-hload.c.
1659 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1661 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1663 * configure: Regenerated to track ../common/aclocal.m4 changes.
1666 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1668 * interp.c (sim_open): Add ABFD argument.
1669 (sim_load): Move call to sim_config from here.
1670 (sim_open): To here. Check return status.
1672 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1674 * gencode.c (build_instruction): Two arg MADD should
1675 not assign result to $0.
1677 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1679 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1680 * sim/mips/configure.in: Regenerate.
1682 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1684 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1685 signed8, unsigned8 et.al. types.
1687 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1688 hosts when selecting subreg.
1690 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1692 * interp.c (sim_engine_run): Reset the ZERO register to zero
1693 regardless of FEATURE_WARN_ZERO.
1694 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1696 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1698 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1699 (SignalException): For BreakPoints ignore any mode bits and just
1701 (SignalException): Always set the CAUSE register.
1703 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1705 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1706 exception has been taken.
1708 * interp.c: Implement the ERET and mt/f sr instructions.
1710 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1712 * interp.c (SignalException): Don't bother restarting an
1715 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1717 * interp.c (SignalException): Really take an interrupt.
1718 (interrupt_event): Only deliver interrupts when enabled.
1720 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1722 * interp.c (sim_info): Only print info when verbose.
1723 (sim_info) Use sim_io_printf for output.
1725 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1730 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1732 * interp.c (sim_do_command): Check for common commands if a
1733 simulator specific command fails.
1735 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1737 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1738 and simBE when DEBUG is defined.
1740 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1742 * interp.c (interrupt_event): New function. Pass exception event
1743 onto exception handler.
1745 * configure.in: Check for stdlib.h.
1746 * configure: Regenerate.
1748 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1749 variable declaration.
1750 (build_instruction): Initialize memval1.
1751 (build_instruction): Add UNUSED attribute to byte, bigend,
1753 (build_operands): Ditto.
1755 * interp.c: Fix GCC warnings.
1756 (sim_get_quit_code): Delete.
1758 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1759 * Makefile.in: Ditto.
1760 * configure: Re-generate.
1762 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1764 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1766 * interp.c (mips_option_handler): New function parse argumes using
1768 (myname): Replace with STATE_MY_NAME.
1769 (sim_open): Delete check for host endianness - performed by
1771 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1772 (sim_open): Move much of the initialization from here.
1773 (sim_load): To here. After the image has been loaded and
1775 (sim_open): Move ColdReset from here.
1776 (sim_create_inferior): To here.
1777 (sim_open): Make FP check less dependant on host endianness.
1779 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1781 * interp.c (sim_set_callbacks): Delete.
1783 * interp.c (membank, membank_base, membank_size): Replace with
1784 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1785 (sim_open): Remove call to callback->init. gdb/run do this.
1789 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1791 * interp.c (big_endian_p): Delete, replaced by
1792 current_target_byte_order.
1794 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1796 * interp.c (host_read_long, host_read_word, host_swap_word,
1797 host_swap_long): Delete. Using common sim-endian.
1798 (sim_fetch_register, sim_store_register): Use H2T.
1799 (pipeline_ticks): Delete. Handled by sim-events.
1801 (sim_engine_run): Update.
1803 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1805 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1807 (SignalException): To here. Signal using sim_engine_halt.
1808 (sim_stop_reason): Delete, moved to common.
1810 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1812 * interp.c (sim_open): Add callback argument.
1813 (sim_set_callbacks): Delete SIM_DESC argument.
1816 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1818 * Makefile.in (SIM_OBJS): Add common modules.
1820 * interp.c (sim_set_callbacks): Also set SD callback.
1821 (set_endianness, xfer_*, swap_*): Delete.
1822 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1823 Change to functions using sim-endian macros.
1824 (control_c, sim_stop): Delete, use common version.
1825 (simulate): Convert into.
1826 (sim_engine_run): This function.
1827 (sim_resume): Delete.
1829 * interp.c (simulation): New variable - the simulator object.
1830 (sim_kind): Delete global - merged into simulation.
1831 (sim_load): Cleanup. Move PC assignment from here.
1832 (sim_create_inferior): To here.
1834 * sim-main.h: New file.
1835 * interp.c (sim-main.h): Include.
1837 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1839 * configure: Regenerated to track ../common/aclocal.m4 changes.
1841 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1843 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1845 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1847 * gencode.c (build_instruction): DIV instructions: check
1848 for division by zero and integer overflow before using
1849 host's division operation.
1851 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1853 * Makefile.in (SIM_OBJS): Add sim-load.o.
1854 * interp.c: #include bfd.h.
1855 (target_byte_order): Delete.
1856 (sim_kind, myname, big_endian_p): New static locals.
1857 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1858 after argument parsing. Recognize -E arg, set endianness accordingly.
1859 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1860 load file into simulator. Set PC from bfd.
1861 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1862 (set_endianness): Use big_endian_p instead of target_byte_order.
1864 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1866 * interp.c (sim_size): Delete prototype - conflicts with
1867 definition in remote-sim.h. Correct definition.
1869 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1871 * configure: Regenerated to track ../common/aclocal.m4 changes.
1874 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1876 * interp.c (sim_open): New arg `kind'.
1878 * configure: Regenerated to track ../common/aclocal.m4 changes.
1880 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1882 * configure: Regenerated to track ../common/aclocal.m4 changes.
1884 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1886 * interp.c (sim_open): Set optind to 0 before calling getopt.
1888 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1890 * configure: Regenerated to track ../common/aclocal.m4 changes.
1892 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1894 * interp.c : Replace uses of pr_addr with pr_uword64
1895 where the bit length is always 64 independent of SIM_ADDR.
1896 (pr_uword64) : added.
1898 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1900 * configure: Re-generate.
1902 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1904 * configure: Regenerate to track ../common/aclocal.m4 changes.
1906 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1908 * interp.c (sim_open): New SIM_DESC result. Argument is now
1910 (other sim_*): New SIM_DESC argument.
1912 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1914 * interp.c: Fix printing of addresses for non-64-bit targets.
1915 (pr_addr): Add function to print address based on size.
1917 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1919 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1921 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1923 * gencode.c (build_mips16_operands): Correct computation of base
1924 address for extended PC relative instruction.
1926 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1928 * interp.c (mips16_entry): Add support for floating point cases.
1929 (SignalException): Pass floating point cases to mips16_entry.
1930 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1932 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1934 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1935 and then set the state to fmt_uninterpreted.
1936 (COP_SW): Temporarily set the state to fmt_word while calling
1939 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1941 * gencode.c (build_instruction): The high order may be set in the
1942 comparison flags at any ISA level, not just ISA 4.
1944 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1946 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1947 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1948 * configure.in: sinclude ../common/aclocal.m4.
1949 * configure: Regenerated.
1951 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1953 * configure: Rebuild after change to aclocal.m4.
1955 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
1957 * configure configure.in Makefile.in: Update to new configure
1958 scheme which is more compatible with WinGDB builds.
1959 * configure.in: Improve comment on how to run autoconf.
1960 * configure: Re-run autoconf to get new ../common/aclocal.m4.
1961 * Makefile.in: Use autoconf substitution to install common
1964 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
1966 * gencode.c (build_instruction): Use BigEndianCPU instead of
1969 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
1971 * interp.c (sim_monitor): Make output to stdout visible in
1972 wingdb's I/O log window.
1974 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
1976 * support.h: Undo previous change to SIGTRAP
1979 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
1981 * interp.c (store_word, load_word): New static functions.
1982 (mips16_entry): New static function.
1983 (SignalException): Look for mips16 entry and exit instructions.
1984 (simulate): Use the correct index when setting fpr_state after
1985 doing a pending move.
1987 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
1989 * interp.c: Fix byte-swapping code throughout to work on
1990 both little- and big-endian hosts.
1992 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
1994 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
1995 with gdb/config/i386/xm-windows.h.
1997 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
1999 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2000 that messes up arithmetic shifts.
2002 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2004 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2005 SIGTRAP and SIGQUIT for _WIN32.
2007 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2009 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2010 force a 64 bit multiplication.
2011 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2012 destination register is 0, since that is the default mips16 nop
2015 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2017 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2018 (build_endian_shift): Don't check proc64.
2019 (build_instruction): Always set memval to uword64. Cast op2 to
2020 uword64 when shifting it left in memory instructions. Always use
2021 the same code for stores--don't special case proc64.
2023 * gencode.c (build_mips16_operands): Fix base PC value for PC
2025 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2027 * interp.c (simJALDELAYSLOT): Define.
2028 (JALDELAYSLOT): Define.
2029 (INDELAYSLOT, INJALDELAYSLOT): Define.
2030 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2032 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2034 * interp.c (sim_open): add flush_cache as a PMON routine
2035 (sim_monitor): handle flush_cache by ignoring it
2037 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2039 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2041 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2042 (BigEndianMem): Rename to ByteSwapMem and change sense.
2043 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2044 BigEndianMem references to !ByteSwapMem.
2045 (set_endianness): New function, with prototype.
2046 (sim_open): Call set_endianness.
2047 (sim_info): Use simBE instead of BigEndianMem.
2048 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2049 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2050 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2051 ifdefs, keeping the prototype declaration.
2052 (swap_word): Rewrite correctly.
2053 (ColdReset): Delete references to CONFIG. Delete endianness related
2054 code; moved to set_endianness.
2056 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2058 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2059 * interp.c (CHECKHILO): Define away.
2060 (simSIGINT): New macro.
2061 (membank_size): Increase from 1MB to 2MB.
2062 (control_c): New function.
2063 (sim_resume): Rename parameter signal to signal_number. Add local
2064 variable prev. Call signal before and after simulate.
2065 (sim_stop_reason): Add simSIGINT support.
2066 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2068 (sim_warning): Delete call to SignalException. Do call printf_filtered
2070 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2071 a call to sim_warning.
2073 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2075 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2076 16 bit instructions.
2078 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2080 Add support for mips16 (16 bit MIPS implementation):
2081 * gencode.c (inst_type): Add mips16 instruction encoding types.
2082 (GETDATASIZEINSN): Define.
2083 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2084 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2086 (MIPS16_DECODE): New table, for mips16 instructions.
2087 (bitmap_val): New static function.
2088 (struct mips16_op): Define.
2089 (mips16_op_table): New table, for mips16 operands.
2090 (build_mips16_operands): New static function.
2091 (process_instructions): If PC is odd, decode a mips16
2092 instruction. Break out instruction handling into new
2093 build_instruction function.
2094 (build_instruction): New static function, broken out of
2095 process_instructions. Check modifiers rather than flags for SHIFT
2096 bit count and m[ft]{hi,lo} direction.
2097 (usage): Pass program name to fprintf.
2098 (main): Remove unused variable this_option_optind. Change
2099 ``*loptarg++'' to ``loptarg++''.
2100 (my_strtoul): Parenthesize && within ||.
2101 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2102 (simulate): If PC is odd, fetch a 16 bit instruction, and
2103 increment PC by 2 rather than 4.
2104 * configure.in: Add case for mips16*-*-*.
2105 * configure: Rebuild.
2107 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2109 * interp.c: Allow -t to enable tracing in standalone simulator.
2110 Fix garbage output in trace file and error messages.
2112 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2114 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2115 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2116 * configure.in: Simplify using macros in ../common/aclocal.m4.
2117 * configure: Regenerated.
2118 * tconfig.in: New file.
2120 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2122 * interp.c: Fix bugs in 64-bit port.
2123 Use ansi function declarations for msvc compiler.
2124 Initialize and test file pointer in trace code.
2125 Prevent duplicate definition of LAST_EMED_REGNUM.
2127 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2129 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2131 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2133 * interp.c (SignalException): Check for explicit terminating
2135 * gencode.c: Pass instruction value through SignalException()
2136 calls for Trap, Breakpoint and Syscall.
2138 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2140 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2141 only used on those hosts that provide it.
2142 * configure.in: Add sqrt() to list of functions to be checked for.
2143 * config.in: Re-generated.
2144 * configure: Re-generated.
2146 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2148 * gencode.c (process_instructions): Call build_endian_shift when
2149 expanding STORE RIGHT, to fix swr.
2150 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2151 clear the high bits.
2152 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2153 Fix float to int conversions to produce signed values.
2155 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2157 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2158 (process_instructions): Correct handling of nor instruction.
2159 Correct shift count for 32 bit shift instructions. Correct sign
2160 extension for arithmetic shifts to not shift the number of bits in
2161 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2162 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2164 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2165 It's OK to have a mult follow a mult. What's not OK is to have a
2166 mult follow an mfhi.
2167 (Convert): Comment out incorrect rounding code.
2169 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2171 * interp.c (sim_monitor): Improved monitor printf
2172 simulation. Tidied up simulator warnings, and added "--log" option
2173 for directing warning message output.
2174 * gencode.c: Use sim_warning() rather than WARNING macro.
2176 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2178 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2179 getopt1.o, rather than on gencode.c. Link objects together.
2180 Don't link against -liberty.
2181 (gencode.o, getopt.o, getopt1.o): New targets.
2182 * gencode.c: Include <ctype.h> and "ansidecl.h".
2183 (AND): Undefine after including "ansidecl.h".
2184 (ULONG_MAX): Define if not defined.
2185 (OP_*): Don't define macros; now defined in opcode/mips.h.
2186 (main): Call my_strtoul rather than strtoul.
2187 (my_strtoul): New static function.
2189 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2191 * gencode.c (process_instructions): Generate word64 and uword64
2192 instead of `long long' and `unsigned long long' data types.
2193 * interp.c: #include sysdep.h to get signals, and define default
2195 * (Convert): Work around for Visual-C++ compiler bug with type
2197 * support.h: Make things compile under Visual-C++ by using
2198 __int64 instead of `long long'. Change many refs to long long
2199 into word64/uword64 typedefs.
2201 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2203 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2204 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2206 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2207 (AC_PROG_INSTALL): Added.
2208 (AC_PROG_CC): Moved to before configure.host call.
2209 * configure: Rebuilt.
2211 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2213 * configure.in: Define @SIMCONF@ depending on mips target.
2214 * configure: Rebuild.
2215 * Makefile.in (run): Add @SIMCONF@ to control simulator
2217 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2218 * interp.c: Remove some debugging, provide more detailed error
2219 messages, update memory accesses to use LOADDRMASK.
2221 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2223 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2224 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2226 * configure: Rebuild.
2227 * config.in: New file, generated by autoheader.
2228 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2229 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2230 HAVE_ANINT and HAVE_AINT, as appropriate.
2231 * Makefile.in (run): Use @LIBS@ rather than -lm.
2232 (interp.o): Depend upon config.h.
2233 (Makefile): Just rebuild Makefile.
2234 (clean): Remove stamp-h.
2235 (mostlyclean): Make the same as clean, not as distclean.
2236 (config.h, stamp-h): New targets.
2238 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2240 * interp.c (ColdReset): Fix boolean test. Make all simulator
2243 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2245 * interp.c (xfer_direct_word, xfer_direct_long,
2246 swap_direct_word, swap_direct_long, xfer_big_word,
2247 xfer_big_long, xfer_little_word, xfer_little_long,
2248 swap_word,swap_long): Added.
2249 * interp.c (ColdReset): Provide function indirection to
2250 host<->simulated_target transfer routines.
2251 * interp.c (sim_store_register, sim_fetch_register): Updated to
2252 make use of indirected transfer routines.
2254 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2256 * gencode.c (process_instructions): Ensure FP ABS instruction
2258 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2259 system call support.
2261 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2263 * interp.c (sim_do_command): Complain if callback structure not
2266 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2268 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2269 support for Sun hosts.
2270 * Makefile.in (gencode): Ensure the host compiler and libraries
2271 used for cross-hosted build.
2273 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2275 * interp.c, gencode.c: Some more (TODO) tidying.
2277 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2279 * gencode.c, interp.c: Replaced explicit long long references with
2280 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2281 * support.h (SET64LO, SET64HI): Macros added.
2283 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2285 * configure: Regenerate with autoconf 2.7.
2287 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2289 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2290 * support.h: Remove superfluous "1" from #if.
2291 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2293 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2295 * interp.c (StoreFPR): Control UndefinedResult() call on
2296 WARN_RESULT manifest.
2298 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2300 * gencode.c: Tidied instruction decoding, and added FP instruction
2303 * interp.c: Added dineroIII, and BSD profiling support. Also
2304 run-time FP handling.
2306 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2308 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2309 gencode.c, interp.c, support.h: created.