2 Wed Sep 9 11:28:20 1998 Ron Unrau <runrau@cygnus.com>
4 * sim-main.h: track COP0 registers
5 * interp.c (sim_{fetch,store}_register): read/write COP0 registers
7 Fri Sep 4 10:37:57 1998 Frank Ch. Eigler <fche@cygnus.com>
9 * r5900.igen (mtsab): Correct typo in input register.
11 * sim-main.h (TMP_*): New macros for accessing local 128-bit
12 temporary for multimedia instructions.
13 * r5900.igen (*): Convert most instructions to use new TMP
14 macros to store output result during computation.
18 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
20 * dv-tx3904sio.c: Include sim-assert.h.
22 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
24 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
25 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
26 Reorganize target-specific sim-hardware checks.
28 * interp.c (sim_open): For tx39 target boards, set
29 OPERATING_ENVIRONMENT, add tx3904sio devices.
30 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
31 ROM executables. Install dv-sockser into sim-modules list.
33 * dv-tx3904irc.c: Compiler warning clean-up.
34 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
35 frequent hw-trace messages.
38 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
40 * vr.igen (MulAcc): Identify as a vr4100 specific function.
42 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
44 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
47 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
48 * mips.igen: Define vr4100 model. Include vr.igen.
50 * vr5400.igen: Move instructions to vr.igen
51 * Makefile.in (IGEN_INCLUDE): Remove vr5400.igen.
54 * vr4320.igen: Move instructions to vr.igen.
55 * Makefile.in (IGEN_INCLUDE): Remove vr5320.igen.
59 Tue Jul 14 16:10:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
61 * r5900.igen (r59fp_overflow): Replace argument ANS with argument
64 (r59fp_store): Update calls.
65 (DIV.S): Compute 0/0 sign from inputs. Ditto for X/0.
68 start-sanitize-branchbug4011
69 Mon Jun 29 09:31:27 1998 Gavin Koch <gavin@cygnus.com>
71 * interp.c (OPTION_BRANCH_BUG_4011): Add.
72 (mips_option_handler): Handle OPTION_BRANCH_BUG_4011.
73 (mips_options): Define the option.
74 * mips.igen (check_4011_branch_bug): New.
75 (mark_4011_branch_bug): New.
76 (all branch insn): Call mark_branch_bug, and check_branch_bug.
77 * sim-main.h (branchbug4011_option, branchbug4011_last_target,
78 branchbug4011_last_cia, BRANCHBUG4011_OPTION,
79 BRANCHBUG4011_LAST_TARGET, BRANCHBUG4011_LAST_CIA,
80 check_branch_bug, mark_branch_bug): Define.
82 end-sanitize-branchbug4011
83 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
85 * mips.igen (check_mf_hilo): Correct check.
88 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
90 * sim-main.h (NR_COP0_GPR, COP0_GPR, cop0_gpr, NR_COP0_BP,
91 COP0_BP, cop0_bp, NR_COP0_P, COP0_P, cop0_p): Add 32 COP0 general
92 purpose registers, add 8 COP0 break-point registers, add 64 COP0
93 performance registers.
95 * interp.c (decode_coproc): Accept any MTC0/MFC0, MTBP/MFBP, MTP*
96 MFP* instructions. Just transfer value to/from corresponding
99 * r5900.igen (BC0F, BC0FL, BC0T, BC0TL): Implement, assume COP0
100 status is always true.
101 (CACHE, TLBP, TPGWI, TLBWR): Treat as NOP.
102 (EI, DI): Set/clear Status-EIE bit.
106 Fri Jun 19 14:44:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
108 * mips.igen (BC0F, BC0FL, BC0T, BC0TL): Move to sky code to
112 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
115 * sky-vu.c (vu0_read_cop2_register, vu0_write_cop2_register): Call
117 * sky-gdb.c: Include "sim-assert.h".
120 * sim-main.h (interrupt_event): Add prototype.
122 start-sanitize-tx3904
123 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
124 register_ptr, register_value.
125 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
128 * sim-main.h (tracefh): Make extern.
130 start-sanitize-tx3904
131 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
133 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
134 Reduce unnecessarily high timer event frequency.
135 * dv-tx3904cpu.c: Ditto for interrupt event.
139 Tue Jun 16 14:12:09 1998 Frank Ch. Eigler <fche@cygnus.com>
141 * interp.c (decode_coproc): Removed COP2 branches.
142 * r5900.igen: Moved COP2 branch instructions here.
143 * mips.igen: Restricted COPz == COP2 bit pattern to
144 exclude COP2 branches.
147 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
149 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
151 (interrupt_event): Made non-static.
152 start-sanitize-tx3904
154 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
155 interchange of configuration values for external vs. internal
159 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
161 * mips.igen (BREAK): Moved code to here for
162 simulator-reserved break instructions.
163 * gencode.c (build_instruction): Ditto.
164 * interp.c (signal_exception): Code moved from here. Non-
165 reserved instructions now use exception vector, rather
167 * sim-main.h: Moved magic constants to here.
169 start-sanitize-tx3904
170 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
172 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
173 register upon non-zero interrupt event level, clear upon zero
175 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
176 by passing zero event value.
177 (*_io_{read,write}_buffer): Endianness fixes.
178 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
179 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
181 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
182 serial I/O and timer module at base address 0xFFFF0000.
185 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
187 * mips.igen (SWC1) : Correct the handling of ReverseEndian
190 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
192 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
196 start-sanitize-tx3904
197 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
199 * dv-tx3904tmr.c: New file - implements tx3904 timer.
200 * dv-tx3904{irc,cpu}.c: Mild reformatting.
201 * configure.in: Include tx3904tmr in hw_device list.
202 * configure: Rebuilt.
203 * interp.c (sim_open): Instantiate three timer instances.
204 Fix address typo of tx3904irc instance.
208 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
210 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
211 Select corresponding check_mt_hilo function.
212 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
215 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
219 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
221 * interp.c (signal_exception): SystemCall exception now uses
222 the exception vector.
224 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
226 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
230 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
232 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
236 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
238 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
240 start-sanitize-tx3904
241 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
243 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
245 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
246 sim-main.h. Declare a struct hw_descriptor instead of struct
247 hw_device_descriptor.
250 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
252 * mips.igen (do_store_left, do_load_left): Compute nr of left and
253 right bits and then re-align left hand bytes to correct byte
254 lanes. Fix incorrect computation in do_store_left when loading
255 bytes from second word.
257 start-sanitize-tx3904
258 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
260 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
261 * interp.c (sim_open): Only create a device tree when HW is
264 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
265 * interp.c (signal_exception): Ditto.
268 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
270 * gencode.c: Mark BEGEZALL as LIKELY.
272 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
274 * sim-main.h (ALU32_END): Sign extend 32 bit results.
275 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
278 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
280 * interp.c (sim_fetch_register): Convert internal r5900 regs to
284 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
286 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
287 modules. Recognize TX39 target with "mips*tx39" pattern.
288 * configure: Rebuilt.
289 * sim-main.h (*): Added many macros defining bits in
290 TX39 control registers.
291 (SignalInterrupt): Send actual PC instead of NULL.
292 (SignalNMIReset): New exception type.
293 * interp.c (board): New variable for future use to identify
294 a particular board being simulated.
295 (mips_option_handler,mips_options): Added "--board" option.
296 (interrupt_event): Send actual PC.
297 (sim_open): Make memory layout conditional on board setting.
298 (signal_exception): Initial implementation of hardware interrupt
299 handling. Accept another break instruction variant for simulator
301 (decode_coproc): Implement RFE instruction for TX39.
302 (mips.igen): Decode RFE instruction as such.
303 start-sanitize-tx3904
304 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
305 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
306 bbegin to implement memory map.
307 * dv-tx3904cpu.c: New file.
308 * dv-tx3904irc.c: New file.
311 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
313 * mips.igen (check_mt_hilo): Create a separate r3900 version.
316 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
318 * r5900.igen: Replace the calls and the definition of the
319 function check_op_hilo_hi1lo1 with the pair
320 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
323 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
325 * tx.igen (madd,maddu): Replace calls to check_op_hilo
326 with calls to check_div_hilo.
328 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
330 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
331 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
332 Add special r3900 version of do_mult_hilo.
333 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
334 with calls to check_mult_hilo.
335 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
336 with calls to check_div_hilo.
338 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
340 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
341 Document a replacement.
343 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
345 * interp.c (sim_monitor): Make mon_printf work.
347 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
349 * sim-main.h (INSN_NAME): New arg `cpu'.
352 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
354 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
359 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
361 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
362 * r5900.igen (r59fp_overflow): Use.
364 * r5900.igen (r59fp_op3): Rename to
365 (r59fp_mula): This, delete opm argument.
366 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
367 (r59fp_mula): Overflowing product propogates through to result.
368 (r59fp_mula): ACC to the MAX propogates to result.
369 (r59fp_mula): Underflow during multiply only sets SU.
372 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
374 * configure: Regenerated to track ../common/aclocal.m4 changes.
376 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
378 * configure: Regenerated to track ../common/aclocal.m4 changes.
381 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
383 * acconfig.h: New file.
384 * configure.in: Reverted change of Apr 24; use sinclude again.
386 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
388 * configure: Regenerated to track ../common/aclocal.m4 changes.
391 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
393 * configure.in: Don't call sinclude.
395 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
397 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
399 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
401 * mips.igen (ERET): Implement.
403 * interp.c (decode_coproc): Return sign-extended EPC.
405 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
407 * interp.c (signal_exception): Do not ignore Trap.
408 (signal_exception): On TRAP, restart at exception address.
409 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
410 (signal_exception): Update.
411 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
412 so that TRAP instructions are caught.
414 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
416 * sim-main.h (struct hilo_access, struct hilo_history): Define,
417 contains HI/LO access history.
418 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
419 (HIACCESS, LOACCESS): Delete, replace with
420 (HIHISTORY, LOHISTORY): New macros.
421 (start-sanitize-r5900):
422 (struct sim_5900_cpu): Make hi1access, lo1access of type
424 (HI1ACCESS, LO1ACCESS): Delete, replace with
425 (HI1HISTORY, LO1HISTORY): New macros.
426 (end-sanitize-r5900):
427 (CHECKHILO): Delete all, moved to mips.igen
429 * gencode.c (build_instruction): Do not generate checks for
430 correct HI/LO register usage.
432 * interp.c (old_engine_run): Delete checks for correct HI/LO
435 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
436 check_mf_cycles): New functions.
437 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
438 do_divu, domultx, do_mult, do_multu): Use.
440 * tx.igen ("madd", "maddu"): Use.
441 (start-sanitize-r5900):
443 r5900.igen: Update all HI/LO checks.
444 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
445 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
446 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
447 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
448 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
450 (end-sanitize-r5900):
453 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
455 * interp.c (decode_coproc): Correct CMFC2/QMTC2
458 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
459 instead of a single 128-bit access.
463 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
465 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
466 * interp.c (cop_[ls]q): Fixes corresponding to above.
470 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
472 * interp.c (decode_coproc): Adapt COP2 micro interlock to
473 clarified specs. Reset "M" bit; exit also on "E" bit.
477 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
479 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
480 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
482 * r5900.igen (r59fp_unpack): New function.
483 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
484 RSQRT.S, SQRT.S): Use.
485 (r59fp_zero): New function.
486 (r59fp_overflow): Generate r5900 specific overflow value.
487 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
489 (CVT.S.W, CVT.W.S): Exchange implementations.
491 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
495 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
497 * configure.in (tx19, sim_use_gen): Switch to igen.
498 * configure: Re-build.
502 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
504 * interp.c (decode_coproc): Make COP2 branch code compile after
505 igen signature changes.
508 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
510 * mips.igen (DSRAV): Use function do_dsrav.
511 (SRAV): Use new function do_srav.
513 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
514 (B): Sign extend 11 bit immediate.
515 (EXT-B*): Shift 16 bit immediate left by 1.
516 (ADDIU*): Don't sign extend immediate value.
518 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
520 * m16run.c (sim_engine_run): Restore CIA after handling an event.
523 * mips.igen (mtc0): Valid tx19 instruction.
526 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
529 * mips.igen (delayslot32, nullify_next_insn): New functions.
530 (m16.igen): Always include.
531 (do_*): Add more tracing.
533 * m16.igen (delayslot16): Add NIA argument, could be called by a
534 32 bit MIPS16 instruction.
536 * interp.c (ifetch16): Move function from here.
537 * sim-main.c (ifetch16): To here.
539 * sim-main.c (ifetch16, ifetch32): Update to match current
540 implementations of LH, LW.
541 (signal_exception): Don't print out incorrect hex value of illegal
544 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
546 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
549 * m16.igen: Implement MIPS16 instructions.
551 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
552 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
553 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
554 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
555 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
556 bodies of corresponding code from 32 bit insn to these. Also used
557 by MIPS16 versions of functions.
559 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
560 (IMEM16): Drop NR argument from macro.
563 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
565 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
566 of VU lower instruction.
570 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
572 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
575 * sim-main.h: Removed attempt at allowing 128-bit access.
579 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
581 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
583 * interp.c (decode_coproc): Refer to VU CIA as a "special"
584 register, not as a "misc" register. Aha. Add activity
585 assertions after VCALLMS* instructions.
589 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
591 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
592 to upper code of generated VU instruction.
596 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
598 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
600 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
603 * r5900.igen (SQC2): Thinko.
607 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
609 * interp.c (*): Adapt code to merged VU device & state structs.
610 (decode_coproc): Execute COP2 each macroinstruction without
611 pipelining, by stepping VU to completion state. Adapted to
612 read_vu_*_reg style of register access.
614 * mips.igen ([SL]QC2): Removed these COP2 instructions.
616 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
618 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
621 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
623 * Makefile.in (SIM_OBJS): Add sim-main.o.
625 * sim-main.h (address_translation, load_memory, store_memory,
626 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
628 (pr_addr, pr_uword64): Declare.
629 (sim-main.c): Include when H_REVEALS_MODULE_P.
631 * interp.c (address_translation, load_memory, store_memory,
632 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
634 * sim-main.c: To here. Fix compilation problems.
636 * configure.in: Enable inlining.
637 * configure: Re-config.
639 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
641 * configure: Regenerated to track ../common/aclocal.m4 changes.
643 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
645 * mips.igen: Include tx.igen.
646 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
647 * tx.igen: New file, contains MADD and MADDU.
649 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
650 the hardwired constant `7'.
651 (store_memory): Ditto.
652 (LOADDRMASK): Move definition to sim-main.h.
654 mips.igen (MTC0): Enable for r3900.
657 mips.igen (do_load_byte): Delete.
658 (do_load, do_store, do_load_left, do_load_write, do_store_left,
659 do_store_right): New functions.
660 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
662 configure.in: Let the tx39 use igen again.
665 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
667 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
668 not an address sized quantity. Return zero for cache sizes.
670 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
672 * mips.igen (r3900): r3900 does not support 64 bit integer
676 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
678 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
682 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
684 * interp.c (decode_coproc): Continuing COP2 work.
685 (cop_[ls]q): Make sky-target-only.
687 * sim-main.h (COP_[LS]Q): Make sky-target-only.
689 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
691 * configure.in (mipstx39*-*-*): Use gencode simulator rather
693 * configure : Rebuild.
696 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
698 * interp.c (decode_coproc): Added a missing TARGET_SKY check
699 around COP2 implementation skeleton.
703 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
705 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
707 * interp.c (sim_{load,store}_register): Use new vu[01]_device
708 static to access VU registers.
709 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
710 decoding. Work in progress.
712 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
713 overlapping/redundant bit pattern.
714 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
717 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
720 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
721 access to coprocessor registers.
723 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
725 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
727 * configure: Regenerated to track ../common/aclocal.m4 changes.
729 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
731 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
733 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
735 * configure: Regenerated to track ../common/aclocal.m4 changes.
736 * config.in: Regenerated to track ../common/aclocal.m4 changes.
738 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
740 * configure: Regenerated to track ../common/aclocal.m4 changes.
742 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
744 * interp.c (Max, Min): Comment out functions. Not yet used.
746 start-sanitize-vr4320
747 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
749 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
752 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
754 * configure: Regenerated to track ../common/aclocal.m4 changes.
756 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
758 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
759 configurable settings for stand-alone simulator.
762 * configure.in: Added --with-sim-gpu2 option to specify path of
763 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
764 links/compiles stand-alone simulator with this library.
766 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
768 * configure.in: Added X11 search, just in case.
770 * configure: Regenerated.
772 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
774 * interp.c (sim_write, sim_read, load_memory, store_memory):
775 Replace sim_core_*_map with read_map, write_map, exec_map resp.
777 start-sanitize-vr4320
778 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
780 * vr4320.igen (clz,dclz) : Added.
781 (dmac): Replaced 99, with LO.
784 start-sanitize-cygnus
785 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
787 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
790 start-sanitize-vr4320
791 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
793 * vr4320.igen: New file.
794 * Makefile.in (vr4320.igen) : Added.
795 * configure.in (mips64vr4320-*-*): Added.
796 * configure : Rebuilt.
797 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
798 Add the vr4320 model entry and mark the vr4320 insn as necessary.
801 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
803 * sim-main.h (GETFCC): Return an unsigned value.
806 * r5900.igen: Use an unsigned array index variable `i'.
807 (QFSRV): Ditto for variable bytes.
810 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
812 * mips.igen (DIV): Fix check for -1 / MIN_INT.
813 (DADD): Result destination is RD not RT.
816 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
817 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
821 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
823 * sim-main.h (HIACCESS, LOACCESS): Always define.
825 * mdmx.igen (Maxi, Mini): Rename Max, Min.
827 * interp.c (sim_info): Delete.
829 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
831 * interp.c (DECLARE_OPTION_HANDLER): Use it.
832 (mips_option_handler): New argument `cpu'.
833 (sim_open): Update call to sim_add_option_table.
835 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
837 * mips.igen (CxC1): Add tracing.
840 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
842 * r5900.igen (StoreFP): Delete.
843 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
845 (rsqrt.s, sqrt.s): Implement.
846 (r59cond): New function.
847 (C.COND.S): Call r59cond in assembler line.
848 (cvt.w.s, cvt.s.w): Implement.
850 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
853 * sim-main.h: Define an enum of r5900 FCSR bit fields.
857 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
859 * r5900.igen: Add tracing to all p* instructions.
861 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
863 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
864 to get gdb talking to re-aranged sim_cpu register structure.
867 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
869 * sim-main.h (Max, Min): Declare.
871 * interp.c (Max, Min): New functions.
873 * mips.igen (BC1): Add tracing.
875 start-sanitize-cygnus
876 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
878 * mdmx.igen: Tag all functions as requiring either with mdmx or
883 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
885 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
887 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
889 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
891 * r5900.igen: Rewrite.
893 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
895 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
896 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
899 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
901 * interp.c Added memory map for stack in vr4100
903 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
905 * interp.c (load_memory): Add missing "break"'s.
907 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
909 * interp.c (sim_store_register, sim_fetch_register): Pass in
910 length parameter. Return -1.
912 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
914 * interp.c: Added hardware init hook, fixed warnings.
916 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
918 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
920 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
922 * interp.c (ifetch16): New function.
924 * sim-main.h (IMEM32): Rename IMEM.
925 (IMEM16_IMMED): Define.
927 (DELAY_SLOT): Update.
929 * m16run.c (sim_engine_run): New file.
931 * m16.igen: All instructions except LB.
932 (LB): Call do_load_byte.
933 * mips.igen (do_load_byte): New function.
934 (LB): Call do_load_byte.
936 * mips.igen: Move spec for insn bit size and high bit from here.
937 * Makefile.in (tmp-igen, tmp-m16): To here.
939 * m16.dc: New file, decode mips16 instructions.
941 * Makefile.in (SIM_NO_ALL): Define.
942 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
945 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
949 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
951 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
952 point unit to 32 bit registers.
953 * configure: Re-generate.
955 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
957 * configure.in (sim_use_gen): Make IGEN the default simulator
958 generator for generic 32 and 64 bit mips targets.
959 * configure: Re-generate.
961 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
963 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
966 * interp.c (sim_fetch_register, sim_store_register): Read/write
967 FGR from correct location.
968 (sim_open): Set size of FGR's according to
969 WITH_TARGET_FLOATING_POINT_BITSIZE.
971 * sim-main.h (FGR): Store floating point registers in a separate
974 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
976 * configure: Regenerated to track ../common/aclocal.m4 changes.
978 start-sanitize-cygnus
979 * mdmx.igen: Mark all instructions as 64bit/fp specific.
982 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
984 * interp.c (ColdReset): Call PENDING_INVALIDATE.
986 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
988 * interp.c (pending_tick): New function. Deliver pending writes.
990 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
991 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
992 it can handle mixed sized quantites and single bits.
994 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
996 * interp.c (oengine.h): Do not include when building with IGEN.
997 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
998 (sim_info): Ditto for PROCESSOR_64BIT.
999 (sim_monitor): Replace ut_reg with unsigned_word.
1000 (*): Ditto for t_reg.
1001 (LOADDRMASK): Define.
1002 (sim_open): Remove defunct check that host FP is IEEE compliant,
1003 using software to emulate floating point.
1004 (value_fpr, ...): Always compile, was conditional on HASFPU.
1006 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1008 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1011 * interp.c (SD, CPU): Define.
1012 (mips_option_handler): Set flags in each CPU.
1013 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1014 (sim_close): Do not clear STATE, deleted anyway.
1015 (sim_write, sim_read): Assume CPU zero's vm should be used for
1017 (sim_create_inferior): Set the PC for all processors.
1018 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1020 (mips16_entry): Pass correct nr of args to store_word, load_word.
1021 (ColdReset): Cold reset all cpu's.
1022 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1023 (sim_monitor, load_memory, store_memory, signal_exception): Use
1024 `CPU' instead of STATE_CPU.
1027 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1030 * sim-main.h (signal_exception): Add sim_cpu arg.
1031 (SignalException*): Pass both SD and CPU to signal_exception.
1032 * interp.c (signal_exception): Update.
1034 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1036 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1037 address_translation): Ditto
1038 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1040 start-sanitize-cygnus
1041 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
1043 (ByteAlign): Use StoreFPR, pass args in correct order.
1046 start-sanitize-r5900
1047 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1049 * configure.in (sim_igen_filter): For r5900, configure as SMP.
1052 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1054 * configure: Regenerated to track ../common/aclocal.m4 changes.
1056 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1058 start-sanitize-r5900
1059 * configure.in (sim_igen_filter): For r5900, use igen.
1060 * configure: Re-generate.
1063 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1065 * mips.igen (model): Map processor names onto BFD name.
1067 * sim-main.h (CPU_CIA): Delete.
1068 (SET_CIA, GET_CIA): Define
1070 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1072 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1075 * configure.in (default_endian): Configure a big-endian simulator
1077 * configure: Re-generate.
1079 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1081 * configure: Regenerated to track ../common/aclocal.m4 changes.
1083 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1085 * interp.c (sim_monitor): Handle Densan monitor outbyte
1086 and inbyte functions.
1088 1997-12-29 Felix Lee <flee@cygnus.com>
1090 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1092 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1094 * Makefile.in (tmp-igen): Arrange for $zero to always be
1095 reset to zero after every instruction.
1097 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1099 * configure: Regenerated to track ../common/aclocal.m4 changes.
1102 start-sanitize-cygnus
1103 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1105 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
1108 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
1110 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
1111 vr5400 with the vr5000 as the default.
1114 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1116 * mips.igen (MSUB): Fix to work like MADD.
1117 * gencode.c (MSUB): Similarly.
1119 start-sanitize-cygnus
1120 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
1122 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
1126 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1128 * configure: Regenerated to track ../common/aclocal.m4 changes.
1130 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1132 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1134 start-sanitize-cygnus
1135 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
1136 (value_cc, store_cc): Implement.
1138 * sim-main.h: Add 8*3*8 bit accumulator.
1140 * vr5400.igen: Move mdmx instructins from here
1141 * mdmx.igen: To here - new file. Add/fix missing instructions.
1142 * mips.igen: Include mdmx.igen.
1143 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1146 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1148 * sim-main.h (sim-fpu.h): Include.
1150 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1151 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1152 using host independant sim_fpu module.
1154 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1156 * interp.c (signal_exception): Report internal errors with SIGABRT
1159 * sim-main.h (C0_CONFIG): New register.
1160 (signal.h): No longer include.
1162 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1164 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1166 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1168 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1170 * mips.igen: Tag vr5000 instructions.
1171 (ANDI): Was missing mipsIV model, fix assembler syntax.
1172 (do_c_cond_fmt): New function.
1173 (C.cond.fmt): Handle mips I-III which do not support CC field
1175 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1176 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1178 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1179 vr5000 which saves LO in a GPR separatly.
1181 * configure.in (enable-sim-igen): For vr5000, select vr5000
1182 specific instructions.
1183 * configure: Re-generate.
1185 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1187 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1189 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1190 fmt_uninterpreted_64 bit cases to switch. Convert to
1193 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1195 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1196 as specified in IV3.2 spec.
1197 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1199 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1201 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1202 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1203 (start-sanitize-r5900):
1204 (LWXC1, SWXC1): Delete from r5900 instruction set.
1205 (end-sanitize-r5900):
1206 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1207 PENDING_FILL versions of instructions. Simplify.
1209 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1211 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1213 (MTHI, MFHI): Disable code checking HI-LO.
1215 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1217 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1219 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1221 * gencode.c (build_mips16_operands): Replace IPC with cia.
1223 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1224 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1226 (UndefinedResult): Replace function with macro/function
1228 (sim_engine_run): Don't save PC in IPC.
1230 * sim-main.h (IPC): Delete.
1232 start-sanitize-cygnus
1233 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1234 (do_select): Rename function select.
1237 * interp.c (signal_exception, store_word, load_word,
1238 address_translation, load_memory, store_memory, cache_op,
1239 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1240 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1241 current instruction address - cia - argument.
1242 (sim_read, sim_write): Call address_translation directly.
1243 (sim_engine_run): Rename variable vaddr to cia.
1244 (signal_exception): Pass cia to sim_monitor
1246 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1247 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1248 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1250 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1251 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1254 * interp.c (signal_exception): Pass restart address to
1257 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1258 idecode.o): Add dependency.
1260 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1262 (DELAY_SLOT): Update NIA not PC with branch address.
1263 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1265 * mips.igen: Use CIA not PC in branch calculations.
1266 (illegal): Call SignalException.
1267 (BEQ, ADDIU): Fix assembler.
1269 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1271 * m16.igen (JALX): Was missing.
1273 * configure.in (enable-sim-igen): New configuration option.
1274 * configure: Re-generate.
1276 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1278 * interp.c (load_memory, store_memory): Delete parameter RAW.
1279 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1280 bypassing {load,store}_memory.
1282 * sim-main.h (ByteSwapMem): Delete definition.
1284 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1286 * interp.c (sim_do_command, sim_commands): Delete mips specific
1287 commands. Handled by module sim-options.
1289 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1290 (WITH_MODULO_MEMORY): Define.
1292 * interp.c (sim_info): Delete code printing memory size.
1294 * interp.c (mips_size): Nee sim_size, delete function.
1296 (monitor, monitor_base, monitor_size): Delete global variables.
1297 (sim_open, sim_close): Delete code creating monitor and other
1298 memory regions. Use sim-memopts module, via sim_do_commandf, to
1299 manage memory regions.
1300 (load_memory, store_memory): Use sim-core for memory model.
1302 * interp.c (address_translation): Delete all memory map code
1303 except line forcing 32 bit addresses.
1305 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1307 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1310 * interp.c (logfh, logfile): Delete globals.
1311 (sim_open, sim_close): Delete code opening & closing log file.
1312 (mips_option_handler): Delete -l and -n options.
1313 (OPTION mips_options): Ditto.
1315 * interp.c (OPTION mips_options): Rename option trace to dinero.
1316 (mips_option_handler): Update.
1318 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1320 * interp.c (fetch_str): New function.
1321 (sim_monitor): Rewrite using sim_read & sim_write.
1322 (sim_open): Check magic number.
1323 (sim_open): Write monitor vectors into memory using sim_write.
1324 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1325 (sim_read, sim_write): Simplify - transfer data one byte at a
1327 (load_memory, store_memory): Clarify meaning of parameter RAW.
1329 * sim-main.h (isHOST): Defete definition.
1330 (isTARGET): Mark as depreciated.
1331 (address_translation): Delete parameter HOST.
1333 * interp.c (address_translation): Delete parameter HOST.
1336 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1338 * gencode.c: Add tx49 configury and insns.
1339 * configure.in: Add tx49 configury.
1340 * configure: Update.
1343 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1347 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1348 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1350 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1352 * mips.igen: Add model filter field to records.
1354 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1356 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1358 interp.c (sim_engine_run): Do not compile function sim_engine_run
1359 when WITH_IGEN == 1.
1361 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1362 target architecture.
1364 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1365 igen. Replace with configuration variables sim_igen_flags /
1368 start-sanitize-r5900
1369 * r5900.igen: New file. Copy r5900 insns here.
1371 start-sanitize-cygnus
1372 * vr5400.igen: New file.
1374 * m16.igen: New file. Copy mips16 insns here.
1375 * mips.igen: From here.
1377 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1379 start-sanitize-cygnus
1380 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1382 * configure.in: Add mips64vr5400 target.
1383 * configure: Re-generate.
1386 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1388 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1390 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1392 * gencode.c (build_instruction): Follow sim_write's lead in using
1393 BigEndianMem instead of !ByteSwapMem.
1395 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1397 * configure.in (sim_gen): Dependent on target, select type of
1398 generator. Always select old style generator.
1400 configure: Re-generate.
1402 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1404 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1405 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1406 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1407 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1408 SIM_@sim_gen@_*, set by autoconf.
1410 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1412 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1414 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1415 CURRENT_FLOATING_POINT instead.
1417 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1418 (address_translation): Raise exception InstructionFetch when
1419 translation fails and isINSTRUCTION.
1421 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1422 sim_engine_run): Change type of of vaddr and paddr to
1424 (address_translation, prefetch, load_memory, store_memory,
1425 cache_op): Change type of vAddr and pAddr to address_word.
1427 * gencode.c (build_instruction): Change type of vaddr and paddr to
1430 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1432 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1433 macro to obtain result of ALU op.
1435 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1437 * interp.c (sim_info): Call profile_print.
1439 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1441 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1443 * sim-main.h (WITH_PROFILE): Do not define, defined in
1444 common/sim-config.h. Use sim-profile module.
1445 (simPROFILE): Delete defintion.
1447 * interp.c (PROFILE): Delete definition.
1448 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1449 (sim_close): Delete code writing profile histogram.
1450 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1452 (sim_engine_run): Delete code profiling the PC.
1454 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1456 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1458 * interp.c (sim_monitor): Make register pointers of type
1461 * sim-main.h: Make registers of type unsigned_word not
1464 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1466 start-sanitize-r5900
1467 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1468 ...): Move to sim-main.h
1471 * interp.c (sync_operation): Rename from SyncOperation, make
1472 global, add SD argument.
1473 (prefetch): Rename from Prefetch, make global, add SD argument.
1474 (decode_coproc): Make global.
1476 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1478 * gencode.c (build_instruction): Generate DecodeCoproc not
1479 decode_coproc calls.
1481 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1482 (SizeFGR): Move to sim-main.h
1483 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1484 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1485 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1487 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1488 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1489 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1490 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1491 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1492 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1494 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1496 (sim-alu.h): Include.
1497 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1498 (sim_cia): Typedef to instruction_address.
1500 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1502 * Makefile.in (interp.o): Rename generated file engine.c to
1507 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1509 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1511 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1513 * gencode.c (build_instruction): For "FPSQRT", output correct
1514 number of arguments to Recip.
1516 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1518 * Makefile.in (interp.o): Depends on sim-main.h
1520 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1522 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1523 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1524 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1525 STATE, DSSTATE): Define
1526 (GPR, FGRIDX, ..): Define.
1528 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1529 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1530 (GPR, FGRIDX, ...): Delete macros.
1532 * interp.c: Update names to match defines from sim-main.h
1534 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1536 * interp.c (sim_monitor): Add SD argument.
1537 (sim_warning): Delete. Replace calls with calls to
1539 (sim_error): Delete. Replace calls with sim_io_error.
1540 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1541 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1542 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1544 (mips_size): Rename from sim_size. Add SD argument.
1546 * interp.c (simulator): Delete global variable.
1547 (callback): Delete global variable.
1548 (mips_option_handler, sim_open, sim_write, sim_read,
1549 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1550 sim_size,sim_monitor): Use sim_io_* not callback->*.
1551 (sim_open): ZALLOC simulator struct.
1552 (PROFILE): Do not define.
1554 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1556 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1557 support.h with corresponding code.
1559 * sim-main.h (word64, uword64), support.h: Move definition to
1561 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1564 * Makefile.in: Update dependencies
1565 * interp.c: Do not include.
1567 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1569 * interp.c (address_translation, load_memory, store_memory,
1570 cache_op): Rename to from AddressTranslation et.al., make global,
1573 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1576 * interp.c (SignalException): Rename to signal_exception, make
1579 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1581 * sim-main.h (SignalException, SignalExceptionInterrupt,
1582 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1583 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1584 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1587 * interp.c, support.h: Use.
1589 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1591 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1592 to value_fpr / store_fpr. Add SD argument.
1593 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1594 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1596 * sim-main.h (ValueFPR, StoreFPR): Define.
1598 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1600 * interp.c (sim_engine_run): Check consistency between configure
1601 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1604 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1605 (mips_fpu): Configure WITH_FLOATING_POINT.
1606 (mips_endian): Configure WITH_TARGET_ENDIAN.
1607 * configure: Update.
1609 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1611 * configure: Regenerated to track ../common/aclocal.m4 changes.
1613 start-sanitize-r5900
1614 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1616 * interp.c (MAX_REG): Allow up-to 128 registers.
1617 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1618 (REGISTER_SA): Ditto.
1619 (sim_open): Initialize register_widths for r5900 specific
1621 (sim_fetch_register, sim_store_register): Check for request of
1622 r5900 specific SA register. Check for request for hi 64 bits of
1623 r5900 specific registers.
1626 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1628 * configure: Regenerated.
1630 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1632 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1634 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1636 * gencode.c (print_igen_insn_models): Assume certain architectures
1637 include all mips* instructions.
1638 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1641 * Makefile.in (tmp.igen): Add target. Generate igen input from
1644 * gencode.c (FEATURE_IGEN): Define.
1645 (main): Add --igen option. Generate output in igen format.
1646 (process_instructions): Format output according to igen option.
1647 (print_igen_insn_format): New function.
1648 (print_igen_insn_models): New function.
1649 (process_instructions): Only issue warnings and ignore
1650 instructions when no FEATURE_IGEN.
1652 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1654 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1657 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1659 * configure: Regenerated to track ../common/aclocal.m4 changes.
1661 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1663 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1664 SIM_RESERVED_BITS): Delete, moved to common.
1665 (SIM_EXTRA_CFLAGS): Update.
1667 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1669 * configure.in: Configure non-strict memory alignment.
1670 * configure: Regenerated to track ../common/aclocal.m4 changes.
1672 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1674 * configure: Regenerated to track ../common/aclocal.m4 changes.
1676 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1678 * gencode.c (SDBBP,DERET): Added (3900) insns.
1679 (RFE): Turn on for 3900.
1680 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1681 (dsstate): Made global.
1682 (SUBTARGET_R3900): Added.
1683 (CANCELDELAYSLOT): New.
1684 (SignalException): Ignore SystemCall rather than ignore and
1685 terminate. Add DebugBreakPoint handling.
1686 (decode_coproc): New insns RFE, DERET; and new registers Debug
1687 and DEPC protected by SUBTARGET_R3900.
1688 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1690 * Makefile.in,configure.in: Add mips subtarget option.
1691 * configure: Update.
1693 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1695 * gencode.c: Add r3900 (tx39).
1698 * gencode.c: Fix some configuration problems by improving
1699 the relationship between tx19 and tx39.
1702 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1704 * gencode.c (build_instruction): Don't need to subtract 4 for
1707 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1709 * interp.c: Correct some HASFPU problems.
1711 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1713 * configure: Regenerated to track ../common/aclocal.m4 changes.
1715 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1717 * interp.c (mips_options): Fix samples option short form, should
1720 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1722 * interp.c (sim_info): Enable info code. Was just returning.
1724 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1726 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1729 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1731 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1733 (build_instruction): Ditto for LL.
1736 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1738 * mips/configure.in, mips/gencode: Add tx19/r1900.
1741 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1743 * configure: Regenerated to track ../common/aclocal.m4 changes.
1745 start-sanitize-r5900
1746 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1748 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1749 for overflow due to ABS of MININT, set result to MAXINT.
1750 (build_instruction): For "psrlvw", signextend bit 31.
1753 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1755 * configure: Regenerated to track ../common/aclocal.m4 changes.
1758 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1760 * interp.c (sim_open): Add call to sim_analyze_program, update
1763 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1765 * interp.c (sim_kill): Delete.
1766 (sim_create_inferior): Add ABFD argument. Set PC from same.
1767 (sim_load): Move code initializing trap handlers from here.
1768 (sim_open): To here.
1769 (sim_load): Delete, use sim-hload.c.
1771 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1773 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1775 * configure: Regenerated to track ../common/aclocal.m4 changes.
1778 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1780 * interp.c (sim_open): Add ABFD argument.
1781 (sim_load): Move call to sim_config from here.
1782 (sim_open): To here. Check return status.
1784 start-sanitize-r5900
1785 * gencode.c (build_instruction): Do not define x8000000000000000,
1786 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1789 start-sanitize-r5900
1790 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1792 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1793 "pdivuw" check for overflow due to signed divide by -1.
1796 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1798 * gencode.c (build_instruction): Two arg MADD should
1799 not assign result to $0.
1801 start-sanitize-r5900
1802 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1804 * gencode.c (build_instruction): For "ppac5" use unsigned
1805 arrithmetic so that the sign bit doesn't smear when right shifted.
1806 (build_instruction): For "pdiv" perform sign extension when
1807 storing results in HI and LO.
1808 (build_instructions): For "pdiv" and "pdivbw" check for
1810 (build_instruction): For "pmfhl.slw" update hi part of dest
1811 register as well as low part.
1812 (build_instruction): For "pmfhl" portably handle long long values.
1813 (build_instruction): For "pmfhl.sh" correctly negative values.
1814 Store half words 2 and three in the correct place.
1815 (build_instruction): For "psllvw", sign extend value after shift.
1818 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1820 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1821 * sim/mips/configure.in: Regenerate.
1823 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1825 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1826 signed8, unsigned8 et.al. types.
1828 start-sanitize-r5900
1829 * gencode.c (build_instruction): For PMULTU* do not sign extend
1830 registers. Make generated code easier to debug.
1833 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1834 hosts when selecting subreg.
1836 start-sanitize-r5900
1837 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1839 * gencode.c (type_for_data_len): For 32bit operations concerned
1840 with overflow, perform op using 64bits.
1841 (build_instruction): For PADD, always compute operation using type
1842 returned by type_for_data_len.
1843 (build_instruction): For PSUBU, when overflow, saturate to zero as
1847 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1849 start-sanitize-r5900
1850 * gencode.c (build_instruction): Handle "pext5" according to
1851 version 1.95 of the r5900 ISA.
1853 * gencode.c (build_instruction): Handle "ppac5" according to
1854 version 1.95 of the r5900 ISA.
1857 * interp.c (sim_engine_run): Reset the ZERO register to zero
1858 regardless of FEATURE_WARN_ZERO.
1859 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1861 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1863 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1864 (SignalException): For BreakPoints ignore any mode bits and just
1866 (SignalException): Always set the CAUSE register.
1868 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1870 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1871 exception has been taken.
1873 * interp.c: Implement the ERET and mt/f sr instructions.
1875 start-sanitize-r5900
1876 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1878 * gencode.c (build_instruction): For paddu, extract unsigned
1881 * gencode.c (build_instruction): Saturate padds instead of padd
1885 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1887 * interp.c (SignalException): Don't bother restarting an
1890 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1892 * interp.c (SignalException): Really take an interrupt.
1893 (interrupt_event): Only deliver interrupts when enabled.
1895 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1897 * interp.c (sim_info): Only print info when verbose.
1898 (sim_info) Use sim_io_printf for output.
1900 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1902 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1905 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1907 * interp.c (sim_do_command): Check for common commands if a
1908 simulator specific command fails.
1910 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1912 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1913 and simBE when DEBUG is defined.
1915 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1917 * interp.c (interrupt_event): New function. Pass exception event
1918 onto exception handler.
1920 * configure.in: Check for stdlib.h.
1921 * configure: Regenerate.
1923 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1924 variable declaration.
1925 (build_instruction): Initialize memval1.
1926 (build_instruction): Add UNUSED attribute to byte, bigend,
1928 (build_operands): Ditto.
1930 * interp.c: Fix GCC warnings.
1931 (sim_get_quit_code): Delete.
1933 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1934 * Makefile.in: Ditto.
1935 * configure: Re-generate.
1937 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1939 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1941 * interp.c (mips_option_handler): New function parse argumes using
1943 (myname): Replace with STATE_MY_NAME.
1944 (sim_open): Delete check for host endianness - performed by
1946 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1947 (sim_open): Move much of the initialization from here.
1948 (sim_load): To here. After the image has been loaded and
1950 (sim_open): Move ColdReset from here.
1951 (sim_create_inferior): To here.
1952 (sim_open): Make FP check less dependant on host endianness.
1954 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1956 * interp.c (sim_set_callbacks): Delete.
1958 * interp.c (membank, membank_base, membank_size): Replace with
1959 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1960 (sim_open): Remove call to callback->init. gdb/run do this.
1964 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1966 * interp.c (big_endian_p): Delete, replaced by
1967 current_target_byte_order.
1969 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1971 * interp.c (host_read_long, host_read_word, host_swap_word,
1972 host_swap_long): Delete. Using common sim-endian.
1973 (sim_fetch_register, sim_store_register): Use H2T.
1974 (pipeline_ticks): Delete. Handled by sim-events.
1976 (sim_engine_run): Update.
1978 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1982 (SignalException): To here. Signal using sim_engine_halt.
1983 (sim_stop_reason): Delete, moved to common.
1985 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1987 * interp.c (sim_open): Add callback argument.
1988 (sim_set_callbacks): Delete SIM_DESC argument.
1991 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1993 * Makefile.in (SIM_OBJS): Add common modules.
1995 * interp.c (sim_set_callbacks): Also set SD callback.
1996 (set_endianness, xfer_*, swap_*): Delete.
1997 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1998 Change to functions using sim-endian macros.
1999 (control_c, sim_stop): Delete, use common version.
2000 (simulate): Convert into.
2001 (sim_engine_run): This function.
2002 (sim_resume): Delete.
2004 * interp.c (simulation): New variable - the simulator object.
2005 (sim_kind): Delete global - merged into simulation.
2006 (sim_load): Cleanup. Move PC assignment from here.
2007 (sim_create_inferior): To here.
2009 * sim-main.h: New file.
2010 * interp.c (sim-main.h): Include.
2012 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2014 * configure: Regenerated to track ../common/aclocal.m4 changes.
2016 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2018 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2020 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2022 * gencode.c (build_instruction): DIV instructions: check
2023 for division by zero and integer overflow before using
2024 host's division operation.
2026 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2028 * Makefile.in (SIM_OBJS): Add sim-load.o.
2029 * interp.c: #include bfd.h.
2030 (target_byte_order): Delete.
2031 (sim_kind, myname, big_endian_p): New static locals.
2032 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2033 after argument parsing. Recognize -E arg, set endianness accordingly.
2034 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2035 load file into simulator. Set PC from bfd.
2036 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2037 (set_endianness): Use big_endian_p instead of target_byte_order.
2039 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2041 * interp.c (sim_size): Delete prototype - conflicts with
2042 definition in remote-sim.h. Correct definition.
2044 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2046 * configure: Regenerated to track ../common/aclocal.m4 changes.
2049 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2051 * interp.c (sim_open): New arg `kind'.
2053 * configure: Regenerated to track ../common/aclocal.m4 changes.
2055 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2057 * configure: Regenerated to track ../common/aclocal.m4 changes.
2059 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2061 * interp.c (sim_open): Set optind to 0 before calling getopt.
2063 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2065 * configure: Regenerated to track ../common/aclocal.m4 changes.
2067 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2069 * interp.c : Replace uses of pr_addr with pr_uword64
2070 where the bit length is always 64 independent of SIM_ADDR.
2071 (pr_uword64) : added.
2073 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2075 * configure: Re-generate.
2077 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2079 * configure: Regenerate to track ../common/aclocal.m4 changes.
2081 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2083 * interp.c (sim_open): New SIM_DESC result. Argument is now
2085 (other sim_*): New SIM_DESC argument.
2087 start-sanitize-r5900
2088 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
2090 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
2091 Change values to avoid overloading DOUBLEWORD which is tested
2093 * gencode.c: reinstate "offending code".
2096 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2098 * interp.c: Fix printing of addresses for non-64-bit targets.
2099 (pr_addr): Add function to print address based on size.
2100 start-sanitize-r5900
2101 * gencode.c: #ifdef out offending code until a permanent fix
2102 can be added. Code is causing build errors for non-5900 mips targets.
2105 start-sanitize-r5900
2106 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
2108 * gencode.c (process_instructions): Correct test for ISA dependent
2109 architecture bits in isa field of MIPS_DECODE.
2112 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2114 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2116 start-sanitize-r5900
2117 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
2119 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
2123 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2125 * gencode.c (build_mips16_operands): Correct computation of base
2126 address for extended PC relative instruction.
2128 start-sanitize-r5900
2129 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
2131 * Makefile.in, configure, configure.in, gencode.c,
2132 interp.c, support.h: add r5900.
2135 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2137 * interp.c (mips16_entry): Add support for floating point cases.
2138 (SignalException): Pass floating point cases to mips16_entry.
2139 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2141 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2143 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2144 and then set the state to fmt_uninterpreted.
2145 (COP_SW): Temporarily set the state to fmt_word while calling
2148 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2150 * gencode.c (build_instruction): The high order may be set in the
2151 comparison flags at any ISA level, not just ISA 4.
2153 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2155 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2156 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2157 * configure.in: sinclude ../common/aclocal.m4.
2158 * configure: Regenerated.
2160 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2162 * configure: Rebuild after change to aclocal.m4.
2164 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2166 * configure configure.in Makefile.in: Update to new configure
2167 scheme which is more compatible with WinGDB builds.
2168 * configure.in: Improve comment on how to run autoconf.
2169 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2170 * Makefile.in: Use autoconf substitution to install common
2173 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2175 * gencode.c (build_instruction): Use BigEndianCPU instead of
2178 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2180 * interp.c (sim_monitor): Make output to stdout visible in
2181 wingdb's I/O log window.
2183 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2185 * support.h: Undo previous change to SIGTRAP
2188 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2190 * interp.c (store_word, load_word): New static functions.
2191 (mips16_entry): New static function.
2192 (SignalException): Look for mips16 entry and exit instructions.
2193 (simulate): Use the correct index when setting fpr_state after
2194 doing a pending move.
2196 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2198 * interp.c: Fix byte-swapping code throughout to work on
2199 both little- and big-endian hosts.
2201 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2203 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2204 with gdb/config/i386/xm-windows.h.
2206 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2208 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2209 that messes up arithmetic shifts.
2211 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2213 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2214 SIGTRAP and SIGQUIT for _WIN32.
2216 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2218 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2219 force a 64 bit multiplication.
2220 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2221 destination register is 0, since that is the default mips16 nop
2224 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2226 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2227 (build_endian_shift): Don't check proc64.
2228 (build_instruction): Always set memval to uword64. Cast op2 to
2229 uword64 when shifting it left in memory instructions. Always use
2230 the same code for stores--don't special case proc64.
2232 * gencode.c (build_mips16_operands): Fix base PC value for PC
2234 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2236 * interp.c (simJALDELAYSLOT): Define.
2237 (JALDELAYSLOT): Define.
2238 (INDELAYSLOT, INJALDELAYSLOT): Define.
2239 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2241 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2243 * interp.c (sim_open): add flush_cache as a PMON routine
2244 (sim_monitor): handle flush_cache by ignoring it
2246 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2248 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2250 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2251 (BigEndianMem): Rename to ByteSwapMem and change sense.
2252 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2253 BigEndianMem references to !ByteSwapMem.
2254 (set_endianness): New function, with prototype.
2255 (sim_open): Call set_endianness.
2256 (sim_info): Use simBE instead of BigEndianMem.
2257 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2258 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2259 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2260 ifdefs, keeping the prototype declaration.
2261 (swap_word): Rewrite correctly.
2262 (ColdReset): Delete references to CONFIG. Delete endianness related
2263 code; moved to set_endianness.
2265 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2267 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2268 * interp.c (CHECKHILO): Define away.
2269 (simSIGINT): New macro.
2270 (membank_size): Increase from 1MB to 2MB.
2271 (control_c): New function.
2272 (sim_resume): Rename parameter signal to signal_number. Add local
2273 variable prev. Call signal before and after simulate.
2274 (sim_stop_reason): Add simSIGINT support.
2275 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2277 (sim_warning): Delete call to SignalException. Do call printf_filtered
2279 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2280 a call to sim_warning.
2282 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2284 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2285 16 bit instructions.
2287 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2289 Add support for mips16 (16 bit MIPS implementation):
2290 * gencode.c (inst_type): Add mips16 instruction encoding types.
2291 (GETDATASIZEINSN): Define.
2292 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2293 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2295 (MIPS16_DECODE): New table, for mips16 instructions.
2296 (bitmap_val): New static function.
2297 (struct mips16_op): Define.
2298 (mips16_op_table): New table, for mips16 operands.
2299 (build_mips16_operands): New static function.
2300 (process_instructions): If PC is odd, decode a mips16
2301 instruction. Break out instruction handling into new
2302 build_instruction function.
2303 (build_instruction): New static function, broken out of
2304 process_instructions. Check modifiers rather than flags for SHIFT
2305 bit count and m[ft]{hi,lo} direction.
2306 (usage): Pass program name to fprintf.
2307 (main): Remove unused variable this_option_optind. Change
2308 ``*loptarg++'' to ``loptarg++''.
2309 (my_strtoul): Parenthesize && within ||.
2310 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2311 (simulate): If PC is odd, fetch a 16 bit instruction, and
2312 increment PC by 2 rather than 4.
2313 * configure.in: Add case for mips16*-*-*.
2314 * configure: Rebuild.
2316 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2318 * interp.c: Allow -t to enable tracing in standalone simulator.
2319 Fix garbage output in trace file and error messages.
2321 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2323 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2324 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2325 * configure.in: Simplify using macros in ../common/aclocal.m4.
2326 * configure: Regenerated.
2327 * tconfig.in: New file.
2329 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2331 * interp.c: Fix bugs in 64-bit port.
2332 Use ansi function declarations for msvc compiler.
2333 Initialize and test file pointer in trace code.
2334 Prevent duplicate definition of LAST_EMED_REGNUM.
2336 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2338 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2340 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2342 * interp.c (SignalException): Check for explicit terminating
2344 * gencode.c: Pass instruction value through SignalException()
2345 calls for Trap, Breakpoint and Syscall.
2347 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2349 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2350 only used on those hosts that provide it.
2351 * configure.in: Add sqrt() to list of functions to be checked for.
2352 * config.in: Re-generated.
2353 * configure: Re-generated.
2355 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2357 * gencode.c (process_instructions): Call build_endian_shift when
2358 expanding STORE RIGHT, to fix swr.
2359 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2360 clear the high bits.
2361 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2362 Fix float to int conversions to produce signed values.
2364 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2366 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2367 (process_instructions): Correct handling of nor instruction.
2368 Correct shift count for 32 bit shift instructions. Correct sign
2369 extension for arithmetic shifts to not shift the number of bits in
2370 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2371 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2373 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2374 It's OK to have a mult follow a mult. What's not OK is to have a
2375 mult follow an mfhi.
2376 (Convert): Comment out incorrect rounding code.
2378 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2380 * interp.c (sim_monitor): Improved monitor printf
2381 simulation. Tidied up simulator warnings, and added "--log" option
2382 for directing warning message output.
2383 * gencode.c: Use sim_warning() rather than WARNING macro.
2385 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2387 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2388 getopt1.o, rather than on gencode.c. Link objects together.
2389 Don't link against -liberty.
2390 (gencode.o, getopt.o, getopt1.o): New targets.
2391 * gencode.c: Include <ctype.h> and "ansidecl.h".
2392 (AND): Undefine after including "ansidecl.h".
2393 (ULONG_MAX): Define if not defined.
2394 (OP_*): Don't define macros; now defined in opcode/mips.h.
2395 (main): Call my_strtoul rather than strtoul.
2396 (my_strtoul): New static function.
2398 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2400 * gencode.c (process_instructions): Generate word64 and uword64
2401 instead of `long long' and `unsigned long long' data types.
2402 * interp.c: #include sysdep.h to get signals, and define default
2404 * (Convert): Work around for Visual-C++ compiler bug with type
2406 * support.h: Make things compile under Visual-C++ by using
2407 __int64 instead of `long long'. Change many refs to long long
2408 into word64/uword64 typedefs.
2410 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2412 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2413 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2415 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2416 (AC_PROG_INSTALL): Added.
2417 (AC_PROG_CC): Moved to before configure.host call.
2418 * configure: Rebuilt.
2420 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2422 * configure.in: Define @SIMCONF@ depending on mips target.
2423 * configure: Rebuild.
2424 * Makefile.in (run): Add @SIMCONF@ to control simulator
2426 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2427 * interp.c: Remove some debugging, provide more detailed error
2428 messages, update memory accesses to use LOADDRMASK.
2430 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2432 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2433 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2435 * configure: Rebuild.
2436 * config.in: New file, generated by autoheader.
2437 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2438 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2439 HAVE_ANINT and HAVE_AINT, as appropriate.
2440 * Makefile.in (run): Use @LIBS@ rather than -lm.
2441 (interp.o): Depend upon config.h.
2442 (Makefile): Just rebuild Makefile.
2443 (clean): Remove stamp-h.
2444 (mostlyclean): Make the same as clean, not as distclean.
2445 (config.h, stamp-h): New targets.
2447 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2449 * interp.c (ColdReset): Fix boolean test. Make all simulator
2452 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2454 * interp.c (xfer_direct_word, xfer_direct_long,
2455 swap_direct_word, swap_direct_long, xfer_big_word,
2456 xfer_big_long, xfer_little_word, xfer_little_long,
2457 swap_word,swap_long): Added.
2458 * interp.c (ColdReset): Provide function indirection to
2459 host<->simulated_target transfer routines.
2460 * interp.c (sim_store_register, sim_fetch_register): Updated to
2461 make use of indirected transfer routines.
2463 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2465 * gencode.c (process_instructions): Ensure FP ABS instruction
2467 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2468 system call support.
2470 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2472 * interp.c (sim_do_command): Complain if callback structure not
2475 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2477 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2478 support for Sun hosts.
2479 * Makefile.in (gencode): Ensure the host compiler and libraries
2480 used for cross-hosted build.
2482 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2484 * interp.c, gencode.c: Some more (TODO) tidying.
2486 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2488 * gencode.c, interp.c: Replaced explicit long long references with
2489 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2490 * support.h (SET64LO, SET64HI): Macros added.
2492 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2494 * configure: Regenerate with autoconf 2.7.
2496 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2498 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2499 * support.h: Remove superfluous "1" from #if.
2500 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2502 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2504 * interp.c (StoreFPR): Control UndefinedResult() call on
2505 WARN_RESULT manifest.
2507 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2509 * gencode.c: Tidied instruction decoding, and added FP instruction
2512 * interp.c: Added dineroIII, and BSD profiling support. Also
2513 run-time FP handling.
2515 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2517 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2518 gencode.c, interp.c, support.h: created.