1 2005-12-14 Chao-ying Fu <fu@mips.com>
3 * Makefile.in (SIM_OBJS): Add dsp.o.
4 (dsp.o): New dependency.
5 (IGEN_INCLUDE): Add dsp.igen.
6 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
7 mipsisa64*-*-*): Add dsp to sim_igen_machine.
8 * configure: Regenerate.
9 * mips.igen: Add dsp model and include dsp.igen.
10 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
11 because these instructions are extended in DSP ASE.
12 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
13 adding 6 DSP accumulator registers and 1 DSP control register.
14 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
15 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
16 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
17 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
18 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
19 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
20 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
21 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
22 DSPCR_CCOND_SMASK): New define.
23 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
24 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
26 2005-07-08 Ian Lance Taylor <ian@airs.com>
28 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
30 2005-06-16 David Ung <davidu@mips.com>
31 Nigel Stephens <nigel@mips.com>
33 * mips.igen: New mips16e model and include m16e.igen.
34 (check_u64): Add mips16e tag.
35 * m16e.igen: New file for MIPS16e instructions.
36 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
37 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
39 * configure: Regenerate.
41 2005-05-26 David Ung <davidu@mips.com>
43 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
44 tags to all instructions which are applicable to the new ISAs.
45 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
47 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
49 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
51 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
52 * configure: Regenerate.
54 2005-03-23 Mark Kettenis <kettenis@gnu.org>
56 * configure: Regenerate.
58 2005-01-14 Andrew Cagney <cagney@gnu.org>
60 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
61 explicit call to AC_CONFIG_HEADER.
62 * configure: Regenerate.
64 2005-01-12 Andrew Cagney <cagney@gnu.org>
66 * configure.ac: Update to use ../common/common.m4.
67 * configure: Re-generate.
69 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
71 * configure: Regenerated to track ../common/aclocal.m4 changes.
73 2005-01-07 Andrew Cagney <cagney@gnu.org>
75 * configure.ac: Rename configure.in, require autoconf 2.59.
76 * configure: Re-generate.
78 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
80 * configure: Regenerate for ../common/aclocal.m4 update.
82 2004-09-24 Monika Chaddha <monika@acmet.com>
84 Committed by Andrew Cagney.
85 * m16.igen (CMP, CMPI): Fix assembler.
87 2004-08-18 Chris Demetriou <cgd@broadcom.com>
89 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
90 * configure: Regenerate.
92 2004-06-25 Chris Demetriou <cgd@broadcom.com>
94 * configure.in (sim_m16_machine): Include mipsIII.
95 * configure: Regenerate.
97 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
99 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
101 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
103 2004-04-10 Chris Demetriou <cgd@broadcom.com>
105 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
107 2004-04-09 Chris Demetriou <cgd@broadcom.com>
109 * mips.igen (check_fmt): Remove.
110 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
111 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
112 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
113 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
114 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
115 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
116 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
117 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
118 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
119 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
121 2004-04-09 Chris Demetriou <cgd@broadcom.com>
123 * sb1.igen (check_sbx): New function.
124 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
126 2004-03-29 Chris Demetriou <cgd@broadcom.com>
127 Richard Sandiford <rsandifo@redhat.com>
129 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
130 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
131 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
132 separate implementations for mipsIV and mipsV. Use new macros to
133 determine whether the restrictions apply.
135 2004-01-19 Chris Demetriou <cgd@broadcom.com>
137 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
138 (check_mult_hilo): Improve comments.
139 (check_div_hilo): Likewise. Also, fork off a new version
140 to handle mips32/mips64 (since there are no hazards to check
143 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
145 * mips.igen (do_dmultx): Fix check for negative operands.
147 2003-05-16 Ian Lance Taylor <ian@airs.com>
149 * Makefile.in (SHELL): Make sure this is defined.
150 (various): Use $(SHELL) whenever we invoke move-if-change.
152 2003-05-03 Chris Demetriou <cgd@broadcom.com>
154 * cp1.c: Tweak attribution slightly.
157 * mdmx.igen: Likewise.
158 * mips3d.igen: Likewise.
159 * sb1.igen: Likewise.
161 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
163 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
166 2003-02-27 Andrew Cagney <cagney@redhat.com>
168 * interp.c (sim_open): Rename _bfd to bfd.
169 (sim_create_inferior): Ditto.
171 2003-01-14 Chris Demetriou <cgd@broadcom.com>
173 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
175 2003-01-14 Chris Demetriou <cgd@broadcom.com>
177 * mips.igen (EI, DI): Remove.
179 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
181 * Makefile.in (tmp-run-multi): Fix mips16 filter.
183 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
184 Andrew Cagney <ac131313@redhat.com>
185 Gavin Romig-Koch <gavin@redhat.com>
186 Graydon Hoare <graydon@redhat.com>
187 Aldy Hernandez <aldyh@redhat.com>
188 Dave Brolley <brolley@redhat.com>
189 Chris Demetriou <cgd@broadcom.com>
191 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
192 (sim_mach_default): New variable.
193 (mips64vr-*-*, mips64vrel-*-*): New configurations.
194 Add a new simulator generator, MULTI.
195 * configure: Regenerate.
196 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
197 (multi-run.o): New dependency.
198 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
199 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
200 (tmp-multi): Combine them.
201 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
202 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
203 (distclean-extra): New rule.
204 * sim-main.h: Include bfd.h.
205 (MIPS_MACH): New macro.
206 * mips.igen (vr4120, vr5400, vr5500): New models.
207 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
208 * vr.igen: Replace with new version.
210 2003-01-04 Chris Demetriou <cgd@broadcom.com>
212 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
213 * configure: Regenerate.
215 2002-12-31 Chris Demetriou <cgd@broadcom.com>
217 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
218 * mips.igen: Remove all invocations of check_branch_bug and
221 2002-12-16 Chris Demetriou <cgd@broadcom.com>
223 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
225 2002-07-30 Chris Demetriou <cgd@broadcom.com>
227 * mips.igen (do_load_double, do_store_double): New functions.
228 (LDC1, SDC1): Rename to...
229 (LDC1b, SDC1b): respectively.
230 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
232 2002-07-29 Michael Snyder <msnyder@redhat.com>
234 * cp1.c (fp_recip2): Modify initialization expression so that
235 GCC will recognize it as constant.
237 2002-06-18 Chris Demetriou <cgd@broadcom.com>
239 * mdmx.c (SD_): Delete.
240 (Unpredictable): Re-define, for now, to directly invoke
241 unpredictable_action().
242 (mdmx_acc_op): Fix error in .ob immediate handling.
244 2002-06-18 Andrew Cagney <cagney@redhat.com>
246 * interp.c (sim_firmware_command): Initialize `address'.
248 2002-06-16 Andrew Cagney <ac131313@redhat.com>
250 * configure: Regenerated to track ../common/aclocal.m4 changes.
252 2002-06-14 Chris Demetriou <cgd@broadcom.com>
253 Ed Satterthwaite <ehs@broadcom.com>
255 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
256 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
257 * mips.igen: Include mips3d.igen.
258 (mips3d): New model name for MIPS-3D ASE instructions.
259 (CVT.W.fmt): Don't use this instruction for word (source) format
261 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
262 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
263 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
264 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
265 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
266 (RSquareRoot1, RSquareRoot2): New macros.
267 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
268 (fp_rsqrt2): New functions.
269 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
270 * configure: Regenerate.
272 2002-06-13 Chris Demetriou <cgd@broadcom.com>
273 Ed Satterthwaite <ehs@broadcom.com>
275 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
276 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
277 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
278 (convert): Note that this function is not used for paired-single
280 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
281 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
282 (check_fmt_p): Enable paired-single support.
283 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
284 (PUU.PS): New instructions.
285 (CVT.S.fmt): Don't use this instruction for paired-single format
287 * sim-main.h (FP_formats): New value 'fmt_ps.'
288 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
289 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
291 2002-06-12 Chris Demetriou <cgd@broadcom.com>
293 * mips.igen: Fix formatting of function calls in
296 2002-06-12 Chris Demetriou <cgd@broadcom.com>
298 * mips.igen (MOVN, MOVZ): Trace result.
299 (TNEI): Print "tnei" as the opcode name in traces.
300 (CEIL.W): Add disassembly string for traces.
301 (RSQRT.fmt): Make location of disassembly string consistent
302 with other instructions.
304 2002-06-12 Chris Demetriou <cgd@broadcom.com>
306 * mips.igen (X): Delete unused function.
308 2002-06-08 Andrew Cagney <cagney@redhat.com>
310 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
312 2002-06-07 Chris Demetriou <cgd@broadcom.com>
313 Ed Satterthwaite <ehs@broadcom.com>
315 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
316 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
317 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
318 (fp_nmsub): New prototypes.
319 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
320 (NegMultiplySub): New defines.
321 * mips.igen (RSQRT.fmt): Use RSquareRoot().
322 (MADD.D, MADD.S): Replace with...
323 (MADD.fmt): New instruction.
324 (MSUB.D, MSUB.S): Replace with...
325 (MSUB.fmt): New instruction.
326 (NMADD.D, NMADD.S): Replace with...
327 (NMADD.fmt): New instruction.
328 (NMSUB.D, MSUB.S): Replace with...
329 (NMSUB.fmt): New instruction.
331 2002-06-07 Chris Demetriou <cgd@broadcom.com>
332 Ed Satterthwaite <ehs@broadcom.com>
334 * cp1.c: Fix more comment spelling and formatting.
335 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
336 (denorm_mode): New function.
337 (fpu_unary, fpu_binary): Round results after operation, collect
338 status from rounding operations, and update the FCSR.
339 (convert): Collect status from integer conversions and rounding
340 operations, and update the FCSR. Adjust NaN values that result
341 from conversions. Convert to use sim_io_eprintf rather than
342 fprintf, and remove some debugging code.
343 * cp1.h (fenr_FS): New define.
345 2002-06-07 Chris Demetriou <cgd@broadcom.com>
347 * cp1.c (convert): Remove unusable debugging code, and move MIPS
348 rounding mode to sim FP rounding mode flag conversion code into...
349 (rounding_mode): New function.
351 2002-06-07 Chris Demetriou <cgd@broadcom.com>
353 * cp1.c: Clean up formatting of a few comments.
354 (value_fpr): Reformat switch statement.
356 2002-06-06 Chris Demetriou <cgd@broadcom.com>
357 Ed Satterthwaite <ehs@broadcom.com>
360 * sim-main.h: Include cp1.h.
361 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
362 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
363 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
364 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
365 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
366 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
367 * cp1.c: Don't include sim-fpu.h; already included by
368 sim-main.h. Clean up formatting of some comments.
369 (NaN, Equal, Less): Remove.
370 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
371 (fp_cmp): New functions.
372 * mips.igen (do_c_cond_fmt): Remove.
373 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
374 Compare. Add result tracing.
375 (CxC1): Remove, replace with...
376 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
377 (DMxC1): Remove, replace with...
378 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
379 (MxC1): Remove, replace with...
380 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
382 2002-06-04 Chris Demetriou <cgd@broadcom.com>
384 * sim-main.h (FGRIDX): Remove, replace all uses with...
385 (FGR_BASE): New macro.
386 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
387 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
388 (NR_FGR, FGR): Likewise.
389 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
390 * mips.igen: Likewise.
392 2002-06-04 Chris Demetriou <cgd@broadcom.com>
394 * cp1.c: Add an FSF Copyright notice to this file.
396 2002-06-04 Chris Demetriou <cgd@broadcom.com>
397 Ed Satterthwaite <ehs@broadcom.com>
399 * cp1.c (Infinity): Remove.
400 * sim-main.h (Infinity): Likewise.
402 * cp1.c (fp_unary, fp_binary): New functions.
403 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
404 (fp_sqrt): New functions, implemented in terms of the above.
405 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
406 (Recip, SquareRoot): Remove (replaced by functions above).
407 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
408 (fp_recip, fp_sqrt): New prototypes.
409 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
410 (Recip, SquareRoot): Replace prototypes with #defines which
411 invoke the functions above.
413 2002-06-03 Chris Demetriou <cgd@broadcom.com>
415 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
416 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
417 file, remove PARAMS from prototypes.
418 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
419 simulator state arguments.
420 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
421 pass simulator state arguments.
422 * cp1.c (SD): Redefine as CPU_STATE(cpu).
423 (store_fpr, convert): Remove 'sd' argument.
424 (value_fpr): Likewise. Convert to use 'SD' instead.
426 2002-06-03 Chris Demetriou <cgd@broadcom.com>
428 * cp1.c (Min, Max): Remove #if 0'd functions.
429 * sim-main.h (Min, Max): Remove.
431 2002-06-03 Chris Demetriou <cgd@broadcom.com>
433 * cp1.c: fix formatting of switch case and default labels.
434 * interp.c: Likewise.
435 * sim-main.c: Likewise.
437 2002-06-03 Chris Demetriou <cgd@broadcom.com>
439 * cp1.c: Clean up comments which describe FP formats.
440 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
442 2002-06-03 Chris Demetriou <cgd@broadcom.com>
443 Ed Satterthwaite <ehs@broadcom.com>
445 * configure.in (mipsisa64sb1*-*-*): New target for supporting
446 Broadcom SiByte SB-1 processor configurations.
447 * configure: Regenerate.
448 * sb1.igen: New file.
449 * mips.igen: Include sb1.igen.
451 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
452 * mdmx.igen: Add "sb1" model to all appropriate functions and
454 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
455 (ob_func, ob_acc): Reference the above.
456 (qh_acc): Adjust to keep the same size as ob_acc.
457 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
458 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
460 2002-06-03 Chris Demetriou <cgd@broadcom.com>
462 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
464 2002-06-02 Chris Demetriou <cgd@broadcom.com>
465 Ed Satterthwaite <ehs@broadcom.com>
467 * mips.igen (mdmx): New (pseudo-)model.
468 * mdmx.c, mdmx.igen: New files.
469 * Makefile.in (SIM_OBJS): Add mdmx.o.
470 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
472 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
473 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
474 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
475 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
476 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
477 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
478 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
479 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
480 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
481 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
482 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
483 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
484 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
485 (qh_fmtsel): New macros.
486 (_sim_cpu): New member "acc".
487 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
488 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
490 2002-05-01 Chris Demetriou <cgd@broadcom.com>
492 * interp.c: Use 'deprecated' rather than 'depreciated.'
493 * sim-main.h: Likewise.
495 2002-05-01 Chris Demetriou <cgd@broadcom.com>
497 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
498 which wouldn't compile anyway.
499 * sim-main.h (unpredictable_action): New function prototype.
500 (Unpredictable): Define to call igen function unpredictable().
501 (NotWordValue): New macro to call igen function not_word_value().
502 (UndefinedResult): Remove.
503 * interp.c (undefined_result): Remove.
504 (unpredictable_action): New function.
505 * mips.igen (not_word_value, unpredictable): New functions.
506 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
507 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
508 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
509 NotWordValue() to check for unpredictable inputs, then
510 Unpredictable() to handle them.
512 2002-02-24 Chris Demetriou <cgd@broadcom.com>
514 * mips.igen: Fix formatting of calls to Unpredictable().
516 2002-04-20 Andrew Cagney <ac131313@redhat.com>
518 * interp.c (sim_open): Revert previous change.
520 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
522 * interp.c (sim_open): Disable chunk of code that wrote code in
523 vector table entries.
525 2002-03-19 Chris Demetriou <cgd@broadcom.com>
527 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
528 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
531 2002-03-19 Chris Demetriou <cgd@broadcom.com>
533 * cp1.c: Fix many formatting issues.
535 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
537 * cp1.c (fpu_format_name): New function to replace...
538 (DOFMT): This. Delete, and update all callers.
539 (fpu_rounding_mode_name): New function to replace...
540 (RMMODE): This. Delete, and update all callers.
542 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
544 * interp.c: Move FPU support routines from here to...
545 * cp1.c: Here. New file.
546 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
549 2002-03-12 Chris Demetriou <cgd@broadcom.com>
551 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
552 * mips.igen (mips32, mips64): New models, add to all instructions
553 and functions as appropriate.
554 (loadstore_ea, check_u64): New variant for model mips64.
555 (check_fmt_p): New variant for models mipsV and mips64, remove
556 mipsV model marking fro other variant.
559 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
560 for mips32 and mips64.
561 (DCLO, DCLZ): New instructions for mips64.
563 2002-03-07 Chris Demetriou <cgd@broadcom.com>
565 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
566 immediate or code as a hex value with the "%#lx" format.
567 (ANDI): Likewise, and fix printed instruction name.
569 2002-03-05 Chris Demetriou <cgd@broadcom.com>
571 * sim-main.h (UndefinedResult, Unpredictable): New macros
572 which currently do nothing.
574 2002-03-05 Chris Demetriou <cgd@broadcom.com>
576 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
577 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
578 (status_CU3): New definitions.
580 * sim-main.h (ExceptionCause): Add new values for MIPS32
581 and MIPS64: MDMX, MCheck, CacheErr. Update comments
582 for DebugBreakPoint and NMIReset to note their status in
584 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
585 (SignalExceptionCacheErr): New exception macros.
587 2002-03-05 Chris Demetriou <cgd@broadcom.com>
589 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
590 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
592 (SignalExceptionCoProcessorUnusable): Take as argument the
593 unusable coprocessor number.
595 2002-03-05 Chris Demetriou <cgd@broadcom.com>
597 * mips.igen: Fix formatting of all SignalException calls.
599 2002-03-05 Chris Demetriou <cgd@broadcom.com>
601 * sim-main.h (SIGNEXTEND): Remove.
603 2002-03-04 Chris Demetriou <cgd@broadcom.com>
605 * mips.igen: Remove gencode comment from top of file, fix
606 spelling in another comment.
608 2002-03-04 Chris Demetriou <cgd@broadcom.com>
610 * mips.igen (check_fmt, check_fmt_p): New functions to check
611 whether specific floating point formats are usable.
612 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
613 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
614 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
615 Use the new functions.
616 (do_c_cond_fmt): Remove format checks...
617 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
619 2002-03-03 Chris Demetriou <cgd@broadcom.com>
621 * mips.igen: Fix formatting of check_fpu calls.
623 2002-03-03 Chris Demetriou <cgd@broadcom.com>
625 * mips.igen (FLOOR.L.fmt): Store correct destination register.
627 2002-03-03 Chris Demetriou <cgd@broadcom.com>
629 * mips.igen: Remove whitespace at end of lines.
631 2002-03-02 Chris Demetriou <cgd@broadcom.com>
633 * mips.igen (loadstore_ea): New function to do effective
634 address calculations.
635 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
636 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
637 CACHE): Use loadstore_ea to do effective address computations.
639 2002-03-02 Chris Demetriou <cgd@broadcom.com>
641 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
642 * mips.igen (LL, CxC1, MxC1): Likewise.
644 2002-03-02 Chris Demetriou <cgd@broadcom.com>
646 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
647 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
648 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
649 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
650 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
651 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
652 Don't split opcode fields by hand, use the opcode field values
655 2002-03-01 Chris Demetriou <cgd@broadcom.com>
657 * mips.igen (do_divu): Fix spacing.
659 * mips.igen (do_dsllv): Move to be right before DSLLV,
660 to match the rest of the do_<shift> functions.
662 2002-03-01 Chris Demetriou <cgd@broadcom.com>
664 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
665 DSRL32, do_dsrlv): Trace inputs and results.
667 2002-03-01 Chris Demetriou <cgd@broadcom.com>
669 * mips.igen (CACHE): Provide instruction-printing string.
671 * interp.c (signal_exception): Comment tokens after #endif.
673 2002-02-28 Chris Demetriou <cgd@broadcom.com>
675 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
676 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
677 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
678 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
679 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
680 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
681 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
682 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
684 2002-02-28 Chris Demetriou <cgd@broadcom.com>
686 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
687 instruction-printing string.
688 (LWU): Use '64' as the filter flag.
690 2002-02-28 Chris Demetriou <cgd@broadcom.com>
692 * mips.igen (SDXC1): Fix instruction-printing string.
694 2002-02-28 Chris Demetriou <cgd@broadcom.com>
696 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
699 2002-02-27 Chris Demetriou <cgd@broadcom.com>
701 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
704 2002-02-27 Chris Demetriou <cgd@broadcom.com>
706 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
707 add a comma) so that it more closely match the MIPS ISA
708 documentation opcode partitioning.
709 (PREF): Put useful names on opcode fields, and include
710 instruction-printing string.
712 2002-02-27 Chris Demetriou <cgd@broadcom.com>
714 * mips.igen (check_u64): New function which in the future will
715 check whether 64-bit instructions are usable and signal an
716 exception if not. Currently a no-op.
717 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
718 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
719 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
720 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
722 * mips.igen (check_fpu): New function which in the future will
723 check whether FPU instructions are usable and signal an exception
724 if not. Currently a no-op.
725 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
726 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
727 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
728 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
729 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
730 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
731 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
732 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
734 2002-02-27 Chris Demetriou <cgd@broadcom.com>
736 * mips.igen (do_load_left, do_load_right): Move to be immediately
738 (do_store_left, do_store_right): Move to be immediately following
741 2002-02-27 Chris Demetriou <cgd@broadcom.com>
743 * mips.igen (mipsV): New model name. Also, add it to
744 all instructions and functions where it is appropriate.
746 2002-02-18 Chris Demetriou <cgd@broadcom.com>
748 * mips.igen: For all functions and instructions, list model
749 names that support that instruction one per line.
751 2002-02-11 Chris Demetriou <cgd@broadcom.com>
753 * mips.igen: Add some additional comments about supported
754 models, and about which instructions go where.
755 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
756 order as is used in the rest of the file.
758 2002-02-11 Chris Demetriou <cgd@broadcom.com>
760 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
761 indicating that ALU32_END or ALU64_END are there to check
763 (DADD): Likewise, but also remove previous comment about
766 2002-02-10 Chris Demetriou <cgd@broadcom.com>
768 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
769 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
770 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
771 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
772 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
773 fields (i.e., add and move commas) so that they more closely
774 match the MIPS ISA documentation opcode partitioning.
776 2002-02-10 Chris Demetriou <cgd@broadcom.com>
778 * mips.igen (ADDI): Print immediate value.
780 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
781 (SLL): Print "nop" specially, and don't run the code
782 that does the shift for the "nop" case.
784 2001-11-17 Fred Fish <fnf@redhat.com>
786 * sim-main.h (float_operation): Move enum declaration outside
787 of _sim_cpu struct declaration.
789 2001-04-12 Jim Blandy <jimb@redhat.com>
791 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
792 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
794 * sim-main.h (COCIDX): Remove definition; this isn't supported by
795 PENDING_FILL, and you can get the intended effect gracefully by
796 calling PENDING_SCHED directly.
798 2001-02-23 Ben Elliston <bje@redhat.com>
800 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
801 already defined elsewhere.
803 2001-02-19 Ben Elliston <bje@redhat.com>
805 * sim-main.h (sim_monitor): Return an int.
806 * interp.c (sim_monitor): Add return values.
807 (signal_exception): Handle error conditions from sim_monitor.
809 2001-02-08 Ben Elliston <bje@redhat.com>
811 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
812 (store_memory): Likewise, pass cia to sim_core_write*.
814 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
816 On advice from Chris G. Demetriou <cgd@sibyte.com>:
817 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
819 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
821 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
822 * Makefile.in: Don't delete *.igen when cleaning directory.
824 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
826 * m16.igen (break): Call SignalException not sim_engine_halt.
828 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
831 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
833 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
835 * mips.igen (MxC1, DMxC1): Fix printf formatting.
837 2000-05-24 Michael Hayes <mhayes@cygnus.com>
839 * mips.igen (do_dmultx): Fix typo.
841 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
843 * configure: Regenerated to track ../common/aclocal.m4 changes.
845 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
847 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
849 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
851 * sim-main.h (GPR_CLEAR): Define macro.
853 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
855 * interp.c (decode_coproc): Output long using %lx and not %s.
857 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
859 * interp.c (sim_open): Sort & extend dummy memory regions for
860 --board=jmr3904 for eCos.
862 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
864 * configure: Regenerated.
866 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
868 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
869 calls, conditional on the simulator being in verbose mode.
871 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
873 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
874 cache don't get ReservedInstruction traps.
876 1999-11-29 Mark Salter <msalter@cygnus.com>
878 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
879 to clear status bits in sdisr register. This is how the hardware works.
881 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
882 being used by cygmon.
884 1999-11-11 Andrew Haley <aph@cygnus.com>
886 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
889 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
891 * mips.igen (MULT): Correct previous mis-applied patch.
893 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
895 * mips.igen (delayslot32): Handle sequence like
896 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
897 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
898 (MULT): Actually pass the third register...
900 1999-09-03 Mark Salter <msalter@cygnus.com>
902 * interp.c (sim_open): Added more memory aliases for additional
903 hardware being touched by cygmon on jmr3904 board.
905 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
907 * configure: Regenerated to track ../common/aclocal.m4 changes.
909 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
911 * interp.c (sim_store_register): Handle case where client - GDB -
912 specifies that a 4 byte register is 8 bytes in size.
913 (sim_fetch_register): Ditto.
915 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
917 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
918 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
919 (idt_monitor_base): Base address for IDT monitor traps.
920 (pmon_monitor_base): Ditto for PMON.
921 (lsipmon_monitor_base): Ditto for LSI PMON.
922 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
923 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
924 (sim_firmware_command): New function.
925 (mips_option_handler): Call it for OPTION_FIRMWARE.
926 (sim_open): Allocate memory for idt_monitor region. If "--board"
927 option was given, add no monitor by default. Add BREAK hooks only if
928 monitors are also there.
930 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
932 * interp.c (sim_monitor): Flush output before reading input.
934 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
936 * tconfig.in (SIM_HANDLES_LMA): Always define.
938 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
940 From Mark Salter <msalter@cygnus.com>:
941 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
942 (sim_open): Add setup for BSP board.
944 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
946 * mips.igen (MULT, MULTU): Add syntax for two operand version.
947 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
948 them as unimplemented.
950 1999-05-08 Felix Lee <flee@cygnus.com>
952 * configure: Regenerated to track ../common/aclocal.m4 changes.
954 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
956 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
958 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
960 * configure.in: Any mips64vr5*-*-* target should have
961 -DTARGET_ENABLE_FR=1.
962 (default_endian): Any mips64vr*el-*-* target should default to
964 * configure: Re-generate.
966 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
968 * mips.igen (ldl): Extend from _16_, not 32.
970 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
972 * interp.c (sim_store_register): Force registers written to by GDB
973 into an un-interpreted state.
975 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
977 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
978 CPU, start periodic background I/O polls.
979 (tx3904sio_poll): New function: periodic I/O poller.
981 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
983 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
985 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
987 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
990 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
992 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
993 (load_word): Call SIM_CORE_SIGNAL hook on error.
994 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
995 starting. For exception dispatching, pass PC instead of NULL_CIA.
996 (decode_coproc): Use COP0_BADVADDR to store faulting address.
997 * sim-main.h (COP0_BADVADDR): Define.
998 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
999 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1000 (_sim_cpu): Add exc_* fields to store register value snapshots.
1001 * mips.igen (*): Replace memory-related SignalException* calls
1002 with references to SIM_CORE_SIGNAL hook.
1004 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1006 * sim-main.c (*): Minor warning cleanups.
1008 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1010 * m16.igen (DADDIU5): Correct type-o.
1012 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1014 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1017 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1019 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1021 (interp.o): Add dependency on itable.h
1022 (oengine.c, gencode): Delete remaining references.
1023 (BUILT_SRC_FROM_GEN): Clean up.
1025 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1028 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1029 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1030 tmp-run-hack) : New.
1031 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1032 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1033 Drop the "64" qualifier to get the HACK generator working.
1034 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1035 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1036 qualifier to get the hack generator working.
1037 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1038 (DSLL): Use do_dsll.
1039 (DSLLV): Use do_dsllv.
1040 (DSRA): Use do_dsra.
1041 (DSRL): Use do_dsrl.
1042 (DSRLV): Use do_dsrlv.
1043 (BC1): Move *vr4100 to get the HACK generator working.
1044 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1045 get the HACK generator working.
1046 (MACC) Rename to get the HACK generator working.
1047 (DMACC,MACCS,DMACCS): Add the 64.
1049 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1051 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1052 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1054 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1056 * mips/interp.c (DEBUG): Cleanups.
1058 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1060 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1061 (tx3904sio_tickle): fflush after a stdout character output.
1063 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1065 * interp.c (sim_close): Uninstall modules.
1067 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1069 * sim-main.h, interp.c (sim_monitor): Change to global
1072 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1074 * configure.in (vr4100): Only include vr4100 instructions in
1076 * configure: Re-generate.
1077 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1079 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1081 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1082 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1085 * configure.in (sim_default_gen, sim_use_gen): Replace with
1087 (--enable-sim-igen): Delete config option. Always using IGEN.
1088 * configure: Re-generate.
1090 * Makefile.in (gencode): Kill, kill, kill.
1093 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1095 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1096 bit mips16 igen simulator.
1097 * configure: Re-generate.
1099 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1100 as part of vr4100 ISA.
1101 * vr.igen: Mark all instructions as 64 bit only.
1103 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1105 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1108 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1110 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1111 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1112 * configure: Re-generate.
1114 * m16.igen (BREAK): Define breakpoint instruction.
1115 (JALX32): Mark instruction as mips16 and not r3900.
1116 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1118 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1120 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1122 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1123 insn as a debug breakpoint.
1125 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1127 (PENDING_SCHED): Clean up trace statement.
1128 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1129 (PENDING_FILL): Delay write by only one cycle.
1130 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1132 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1134 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1136 (pending_tick): Move incrementing of index to FOR statement.
1137 (pending_tick): Only update PENDING_OUT after a write has occured.
1139 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1141 * configure: Re-generate.
1143 * interp.c (sim_engine_run OLD): Delete explicit call to
1144 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1146 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1148 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1149 interrupt level number to match changed SignalExceptionInterrupt
1152 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1154 * interp.c: #include "itable.h" if WITH_IGEN.
1155 (get_insn_name): New function.
1156 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1157 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1159 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1161 * configure: Rebuilt to inhale new common/aclocal.m4.
1163 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1165 * dv-tx3904sio.c: Include sim-assert.h.
1167 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1169 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1170 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1171 Reorganize target-specific sim-hardware checks.
1172 * configure: rebuilt.
1173 * interp.c (sim_open): For tx39 target boards, set
1174 OPERATING_ENVIRONMENT, add tx3904sio devices.
1175 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1176 ROM executables. Install dv-sockser into sim-modules list.
1178 * dv-tx3904irc.c: Compiler warning clean-up.
1179 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1180 frequent hw-trace messages.
1182 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1184 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1186 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1188 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1190 * vr.igen: New file.
1191 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1192 * mips.igen: Define vr4100 model. Include vr.igen.
1193 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1195 * mips.igen (check_mf_hilo): Correct check.
1197 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1199 * sim-main.h (interrupt_event): Add prototype.
1201 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1202 register_ptr, register_value.
1203 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1205 * sim-main.h (tracefh): Make extern.
1207 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1209 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1210 Reduce unnecessarily high timer event frequency.
1211 * dv-tx3904cpu.c: Ditto for interrupt event.
1213 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1215 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1217 (interrupt_event): Made non-static.
1219 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1220 interchange of configuration values for external vs. internal
1223 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1225 * mips.igen (BREAK): Moved code to here for
1226 simulator-reserved break instructions.
1227 * gencode.c (build_instruction): Ditto.
1228 * interp.c (signal_exception): Code moved from here. Non-
1229 reserved instructions now use exception vector, rather
1231 * sim-main.h: Moved magic constants to here.
1233 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1235 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1236 register upon non-zero interrupt event level, clear upon zero
1238 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1239 by passing zero event value.
1240 (*_io_{read,write}_buffer): Endianness fixes.
1241 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1242 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1244 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1245 serial I/O and timer module at base address 0xFFFF0000.
1247 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1249 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1252 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1254 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1256 * configure: Update.
1258 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1260 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1261 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1262 * configure.in: Include tx3904tmr in hw_device list.
1263 * configure: Rebuilt.
1264 * interp.c (sim_open): Instantiate three timer instances.
1265 Fix address typo of tx3904irc instance.
1267 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1269 * interp.c (signal_exception): SystemCall exception now uses
1270 the exception vector.
1272 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1274 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1277 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1279 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1281 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1283 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1285 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1286 sim-main.h. Declare a struct hw_descriptor instead of struct
1287 hw_device_descriptor.
1289 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1291 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1292 right bits and then re-align left hand bytes to correct byte
1293 lanes. Fix incorrect computation in do_store_left when loading
1294 bytes from second word.
1296 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1298 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1299 * interp.c (sim_open): Only create a device tree when HW is
1302 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1303 * interp.c (signal_exception): Ditto.
1305 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1307 * gencode.c: Mark BEGEZALL as LIKELY.
1309 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1311 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1312 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1314 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1316 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1317 modules. Recognize TX39 target with "mips*tx39" pattern.
1318 * configure: Rebuilt.
1319 * sim-main.h (*): Added many macros defining bits in
1320 TX39 control registers.
1321 (SignalInterrupt): Send actual PC instead of NULL.
1322 (SignalNMIReset): New exception type.
1323 * interp.c (board): New variable for future use to identify
1324 a particular board being simulated.
1325 (mips_option_handler,mips_options): Added "--board" option.
1326 (interrupt_event): Send actual PC.
1327 (sim_open): Make memory layout conditional on board setting.
1328 (signal_exception): Initial implementation of hardware interrupt
1329 handling. Accept another break instruction variant for simulator
1331 (decode_coproc): Implement RFE instruction for TX39.
1332 (mips.igen): Decode RFE instruction as such.
1333 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1334 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1335 bbegin to implement memory map.
1336 * dv-tx3904cpu.c: New file.
1337 * dv-tx3904irc.c: New file.
1339 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1341 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1343 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1345 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1346 with calls to check_div_hilo.
1348 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1350 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1351 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1352 Add special r3900 version of do_mult_hilo.
1353 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1354 with calls to check_mult_hilo.
1355 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1356 with calls to check_div_hilo.
1358 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1360 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1361 Document a replacement.
1363 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1365 * interp.c (sim_monitor): Make mon_printf work.
1367 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1369 * sim-main.h (INSN_NAME): New arg `cpu'.
1371 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1373 * configure: Regenerated to track ../common/aclocal.m4 changes.
1375 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1377 * configure: Regenerated to track ../common/aclocal.m4 changes.
1380 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1382 * acconfig.h: New file.
1383 * configure.in: Reverted change of Apr 24; use sinclude again.
1385 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1387 * configure: Regenerated to track ../common/aclocal.m4 changes.
1390 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1392 * configure.in: Don't call sinclude.
1394 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1396 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1398 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1400 * mips.igen (ERET): Implement.
1402 * interp.c (decode_coproc): Return sign-extended EPC.
1404 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1406 * interp.c (signal_exception): Do not ignore Trap.
1407 (signal_exception): On TRAP, restart at exception address.
1408 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1409 (signal_exception): Update.
1410 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1411 so that TRAP instructions are caught.
1413 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1415 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1416 contains HI/LO access history.
1417 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1418 (HIACCESS, LOACCESS): Delete, replace with
1419 (HIHISTORY, LOHISTORY): New macros.
1420 (CHECKHILO): Delete all, moved to mips.igen
1422 * gencode.c (build_instruction): Do not generate checks for
1423 correct HI/LO register usage.
1425 * interp.c (old_engine_run): Delete checks for correct HI/LO
1428 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1429 check_mf_cycles): New functions.
1430 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1431 do_divu, domultx, do_mult, do_multu): Use.
1433 * tx.igen ("madd", "maddu"): Use.
1435 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1437 * mips.igen (DSRAV): Use function do_dsrav.
1438 (SRAV): Use new function do_srav.
1440 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1441 (B): Sign extend 11 bit immediate.
1442 (EXT-B*): Shift 16 bit immediate left by 1.
1443 (ADDIU*): Don't sign extend immediate value.
1445 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1449 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1452 * mips.igen (delayslot32, nullify_next_insn): New functions.
1453 (m16.igen): Always include.
1454 (do_*): Add more tracing.
1456 * m16.igen (delayslot16): Add NIA argument, could be called by a
1457 32 bit MIPS16 instruction.
1459 * interp.c (ifetch16): Move function from here.
1460 * sim-main.c (ifetch16): To here.
1462 * sim-main.c (ifetch16, ifetch32): Update to match current
1463 implementations of LH, LW.
1464 (signal_exception): Don't print out incorrect hex value of illegal
1467 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1469 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1472 * m16.igen: Implement MIPS16 instructions.
1474 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1475 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1476 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1477 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1478 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1479 bodies of corresponding code from 32 bit insn to these. Also used
1480 by MIPS16 versions of functions.
1482 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1483 (IMEM16): Drop NR argument from macro.
1485 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1487 * Makefile.in (SIM_OBJS): Add sim-main.o.
1489 * sim-main.h (address_translation, load_memory, store_memory,
1490 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1492 (pr_addr, pr_uword64): Declare.
1493 (sim-main.c): Include when H_REVEALS_MODULE_P.
1495 * interp.c (address_translation, load_memory, store_memory,
1496 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1498 * sim-main.c: To here. Fix compilation problems.
1500 * configure.in: Enable inlining.
1501 * configure: Re-config.
1503 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1505 * configure: Regenerated to track ../common/aclocal.m4 changes.
1507 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1509 * mips.igen: Include tx.igen.
1510 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1511 * tx.igen: New file, contains MADD and MADDU.
1513 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1514 the hardwired constant `7'.
1515 (store_memory): Ditto.
1516 (LOADDRMASK): Move definition to sim-main.h.
1518 mips.igen (MTC0): Enable for r3900.
1521 mips.igen (do_load_byte): Delete.
1522 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1523 do_store_right): New functions.
1524 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1526 configure.in: Let the tx39 use igen again.
1529 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1531 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1532 not an address sized quantity. Return zero for cache sizes.
1534 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1536 * mips.igen (r3900): r3900 does not support 64 bit integer
1539 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1541 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1543 * configure : Rebuild.
1545 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1547 * configure: Regenerated to track ../common/aclocal.m4 changes.
1549 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1551 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1553 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1555 * configure: Regenerated to track ../common/aclocal.m4 changes.
1556 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1558 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1560 * configure: Regenerated to track ../common/aclocal.m4 changes.
1562 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1564 * interp.c (Max, Min): Comment out functions. Not yet used.
1566 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1568 * configure: Regenerated to track ../common/aclocal.m4 changes.
1570 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1572 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1573 configurable settings for stand-alone simulator.
1575 * configure.in: Added X11 search, just in case.
1577 * configure: Regenerated.
1579 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1581 * interp.c (sim_write, sim_read, load_memory, store_memory):
1582 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1584 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1586 * sim-main.h (GETFCC): Return an unsigned value.
1588 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1590 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1591 (DADD): Result destination is RD not RT.
1593 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1595 * sim-main.h (HIACCESS, LOACCESS): Always define.
1597 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1599 * interp.c (sim_info): Delete.
1601 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1603 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1604 (mips_option_handler): New argument `cpu'.
1605 (sim_open): Update call to sim_add_option_table.
1607 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1609 * mips.igen (CxC1): Add tracing.
1611 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1613 * sim-main.h (Max, Min): Declare.
1615 * interp.c (Max, Min): New functions.
1617 * mips.igen (BC1): Add tracing.
1619 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1621 * interp.c Added memory map for stack in vr4100
1623 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1625 * interp.c (load_memory): Add missing "break"'s.
1627 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1629 * interp.c (sim_store_register, sim_fetch_register): Pass in
1630 length parameter. Return -1.
1632 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1634 * interp.c: Added hardware init hook, fixed warnings.
1636 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1638 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1640 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1642 * interp.c (ifetch16): New function.
1644 * sim-main.h (IMEM32): Rename IMEM.
1645 (IMEM16_IMMED): Define.
1647 (DELAY_SLOT): Update.
1649 * m16run.c (sim_engine_run): New file.
1651 * m16.igen: All instructions except LB.
1652 (LB): Call do_load_byte.
1653 * mips.igen (do_load_byte): New function.
1654 (LB): Call do_load_byte.
1656 * mips.igen: Move spec for insn bit size and high bit from here.
1657 * Makefile.in (tmp-igen, tmp-m16): To here.
1659 * m16.dc: New file, decode mips16 instructions.
1661 * Makefile.in (SIM_NO_ALL): Define.
1662 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1664 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1666 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1667 point unit to 32 bit registers.
1668 * configure: Re-generate.
1670 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1672 * configure.in (sim_use_gen): Make IGEN the default simulator
1673 generator for generic 32 and 64 bit mips targets.
1674 * configure: Re-generate.
1676 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1678 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1681 * interp.c (sim_fetch_register, sim_store_register): Read/write
1682 FGR from correct location.
1683 (sim_open): Set size of FGR's according to
1684 WITH_TARGET_FLOATING_POINT_BITSIZE.
1686 * sim-main.h (FGR): Store floating point registers in a separate
1689 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1691 * configure: Regenerated to track ../common/aclocal.m4 changes.
1693 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1695 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1697 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1699 * interp.c (pending_tick): New function. Deliver pending writes.
1701 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1702 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1703 it can handle mixed sized quantites and single bits.
1705 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1707 * interp.c (oengine.h): Do not include when building with IGEN.
1708 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1709 (sim_info): Ditto for PROCESSOR_64BIT.
1710 (sim_monitor): Replace ut_reg with unsigned_word.
1711 (*): Ditto for t_reg.
1712 (LOADDRMASK): Define.
1713 (sim_open): Remove defunct check that host FP is IEEE compliant,
1714 using software to emulate floating point.
1715 (value_fpr, ...): Always compile, was conditional on HASFPU.
1717 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1719 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1722 * interp.c (SD, CPU): Define.
1723 (mips_option_handler): Set flags in each CPU.
1724 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1725 (sim_close): Do not clear STATE, deleted anyway.
1726 (sim_write, sim_read): Assume CPU zero's vm should be used for
1728 (sim_create_inferior): Set the PC for all processors.
1729 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1731 (mips16_entry): Pass correct nr of args to store_word, load_word.
1732 (ColdReset): Cold reset all cpu's.
1733 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1734 (sim_monitor, load_memory, store_memory, signal_exception): Use
1735 `CPU' instead of STATE_CPU.
1738 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1741 * sim-main.h (signal_exception): Add sim_cpu arg.
1742 (SignalException*): Pass both SD and CPU to signal_exception.
1743 * interp.c (signal_exception): Update.
1745 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1747 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1748 address_translation): Ditto
1749 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1751 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1753 * configure: Regenerated to track ../common/aclocal.m4 changes.
1755 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1757 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1759 * mips.igen (model): Map processor names onto BFD name.
1761 * sim-main.h (CPU_CIA): Delete.
1762 (SET_CIA, GET_CIA): Define
1764 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1766 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1769 * configure.in (default_endian): Configure a big-endian simulator
1771 * configure: Re-generate.
1773 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1775 * configure: Regenerated to track ../common/aclocal.m4 changes.
1777 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1779 * interp.c (sim_monitor): Handle Densan monitor outbyte
1780 and inbyte functions.
1782 1997-12-29 Felix Lee <flee@cygnus.com>
1784 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1786 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1788 * Makefile.in (tmp-igen): Arrange for $zero to always be
1789 reset to zero after every instruction.
1791 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1793 * configure: Regenerated to track ../common/aclocal.m4 changes.
1796 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1798 * mips.igen (MSUB): Fix to work like MADD.
1799 * gencode.c (MSUB): Similarly.
1801 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1803 * configure: Regenerated to track ../common/aclocal.m4 changes.
1805 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1807 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1809 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1811 * sim-main.h (sim-fpu.h): Include.
1813 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1814 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1815 using host independant sim_fpu module.
1817 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1819 * interp.c (signal_exception): Report internal errors with SIGABRT
1822 * sim-main.h (C0_CONFIG): New register.
1823 (signal.h): No longer include.
1825 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1827 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1829 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1831 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1833 * mips.igen: Tag vr5000 instructions.
1834 (ANDI): Was missing mipsIV model, fix assembler syntax.
1835 (do_c_cond_fmt): New function.
1836 (C.cond.fmt): Handle mips I-III which do not support CC field
1838 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1839 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1841 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1842 vr5000 which saves LO in a GPR separatly.
1844 * configure.in (enable-sim-igen): For vr5000, select vr5000
1845 specific instructions.
1846 * configure: Re-generate.
1848 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1850 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1852 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1853 fmt_uninterpreted_64 bit cases to switch. Convert to
1856 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1858 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1859 as specified in IV3.2 spec.
1860 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1862 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1864 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1865 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1866 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1867 PENDING_FILL versions of instructions. Simplify.
1869 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1871 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1873 (MTHI, MFHI): Disable code checking HI-LO.
1875 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1877 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1879 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1881 * gencode.c (build_mips16_operands): Replace IPC with cia.
1883 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1884 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1886 (UndefinedResult): Replace function with macro/function
1888 (sim_engine_run): Don't save PC in IPC.
1890 * sim-main.h (IPC): Delete.
1893 * interp.c (signal_exception, store_word, load_word,
1894 address_translation, load_memory, store_memory, cache_op,
1895 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1896 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1897 current instruction address - cia - argument.
1898 (sim_read, sim_write): Call address_translation directly.
1899 (sim_engine_run): Rename variable vaddr to cia.
1900 (signal_exception): Pass cia to sim_monitor
1902 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1903 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1904 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1906 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1907 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1910 * interp.c (signal_exception): Pass restart address to
1913 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1914 idecode.o): Add dependency.
1916 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1918 (DELAY_SLOT): Update NIA not PC with branch address.
1919 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1921 * mips.igen: Use CIA not PC in branch calculations.
1922 (illegal): Call SignalException.
1923 (BEQ, ADDIU): Fix assembler.
1925 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927 * m16.igen (JALX): Was missing.
1929 * configure.in (enable-sim-igen): New configuration option.
1930 * configure: Re-generate.
1932 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1934 * interp.c (load_memory, store_memory): Delete parameter RAW.
1935 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1936 bypassing {load,store}_memory.
1938 * sim-main.h (ByteSwapMem): Delete definition.
1940 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1942 * interp.c (sim_do_command, sim_commands): Delete mips specific
1943 commands. Handled by module sim-options.
1945 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1946 (WITH_MODULO_MEMORY): Define.
1948 * interp.c (sim_info): Delete code printing memory size.
1950 * interp.c (mips_size): Nee sim_size, delete function.
1952 (monitor, monitor_base, monitor_size): Delete global variables.
1953 (sim_open, sim_close): Delete code creating monitor and other
1954 memory regions. Use sim-memopts module, via sim_do_commandf, to
1955 manage memory regions.
1956 (load_memory, store_memory): Use sim-core for memory model.
1958 * interp.c (address_translation): Delete all memory map code
1959 except line forcing 32 bit addresses.
1961 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1963 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1966 * interp.c (logfh, logfile): Delete globals.
1967 (sim_open, sim_close): Delete code opening & closing log file.
1968 (mips_option_handler): Delete -l and -n options.
1969 (OPTION mips_options): Ditto.
1971 * interp.c (OPTION mips_options): Rename option trace to dinero.
1972 (mips_option_handler): Update.
1974 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1976 * interp.c (fetch_str): New function.
1977 (sim_monitor): Rewrite using sim_read & sim_write.
1978 (sim_open): Check magic number.
1979 (sim_open): Write monitor vectors into memory using sim_write.
1980 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1981 (sim_read, sim_write): Simplify - transfer data one byte at a
1983 (load_memory, store_memory): Clarify meaning of parameter RAW.
1985 * sim-main.h (isHOST): Defete definition.
1986 (isTARGET): Mark as depreciated.
1987 (address_translation): Delete parameter HOST.
1989 * interp.c (address_translation): Delete parameter HOST.
1991 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1995 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1996 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1998 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2000 * mips.igen: Add model filter field to records.
2002 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2004 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2006 interp.c (sim_engine_run): Do not compile function sim_engine_run
2007 when WITH_IGEN == 1.
2009 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2010 target architecture.
2012 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2013 igen. Replace with configuration variables sim_igen_flags /
2016 * m16.igen: New file. Copy mips16 insns here.
2017 * mips.igen: From here.
2019 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2021 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2023 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2025 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2027 * gencode.c (build_instruction): Follow sim_write's lead in using
2028 BigEndianMem instead of !ByteSwapMem.
2030 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2032 * configure.in (sim_gen): Dependent on target, select type of
2033 generator. Always select old style generator.
2035 configure: Re-generate.
2037 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2039 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2040 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2041 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2042 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2043 SIM_@sim_gen@_*, set by autoconf.
2045 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2047 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2049 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2050 CURRENT_FLOATING_POINT instead.
2052 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2053 (address_translation): Raise exception InstructionFetch when
2054 translation fails and isINSTRUCTION.
2056 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2057 sim_engine_run): Change type of of vaddr and paddr to
2059 (address_translation, prefetch, load_memory, store_memory,
2060 cache_op): Change type of vAddr and pAddr to address_word.
2062 * gencode.c (build_instruction): Change type of vaddr and paddr to
2065 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2067 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2068 macro to obtain result of ALU op.
2070 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2072 * interp.c (sim_info): Call profile_print.
2074 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2076 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2078 * sim-main.h (WITH_PROFILE): Do not define, defined in
2079 common/sim-config.h. Use sim-profile module.
2080 (simPROFILE): Delete defintion.
2082 * interp.c (PROFILE): Delete definition.
2083 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2084 (sim_close): Delete code writing profile histogram.
2085 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2087 (sim_engine_run): Delete code profiling the PC.
2089 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2091 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2093 * interp.c (sim_monitor): Make register pointers of type
2096 * sim-main.h: Make registers of type unsigned_word not
2099 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101 * interp.c (sync_operation): Rename from SyncOperation, make
2102 global, add SD argument.
2103 (prefetch): Rename from Prefetch, make global, add SD argument.
2104 (decode_coproc): Make global.
2106 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2108 * gencode.c (build_instruction): Generate DecodeCoproc not
2109 decode_coproc calls.
2111 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2112 (SizeFGR): Move to sim-main.h
2113 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2114 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2115 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2117 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2118 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2119 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2120 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2121 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2122 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2124 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2126 (sim-alu.h): Include.
2127 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2128 (sim_cia): Typedef to instruction_address.
2130 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132 * Makefile.in (interp.o): Rename generated file engine.c to
2137 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2139 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2141 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2143 * gencode.c (build_instruction): For "FPSQRT", output correct
2144 number of arguments to Recip.
2146 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2148 * Makefile.in (interp.o): Depends on sim-main.h
2150 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2152 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2153 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2154 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2155 STATE, DSSTATE): Define
2156 (GPR, FGRIDX, ..): Define.
2158 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2159 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2160 (GPR, FGRIDX, ...): Delete macros.
2162 * interp.c: Update names to match defines from sim-main.h
2164 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2166 * interp.c (sim_monitor): Add SD argument.
2167 (sim_warning): Delete. Replace calls with calls to
2169 (sim_error): Delete. Replace calls with sim_io_error.
2170 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2171 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2172 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2174 (mips_size): Rename from sim_size. Add SD argument.
2176 * interp.c (simulator): Delete global variable.
2177 (callback): Delete global variable.
2178 (mips_option_handler, sim_open, sim_write, sim_read,
2179 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2180 sim_size,sim_monitor): Use sim_io_* not callback->*.
2181 (sim_open): ZALLOC simulator struct.
2182 (PROFILE): Do not define.
2184 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2186 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2187 support.h with corresponding code.
2189 * sim-main.h (word64, uword64), support.h: Move definition to
2191 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2194 * Makefile.in: Update dependencies
2195 * interp.c: Do not include.
2197 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2199 * interp.c (address_translation, load_memory, store_memory,
2200 cache_op): Rename to from AddressTranslation et.al., make global,
2203 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2206 * interp.c (SignalException): Rename to signal_exception, make
2209 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2211 * sim-main.h (SignalException, SignalExceptionInterrupt,
2212 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2213 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2214 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2217 * interp.c, support.h: Use.
2219 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2221 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2222 to value_fpr / store_fpr. Add SD argument.
2223 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2224 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2226 * sim-main.h (ValueFPR, StoreFPR): Define.
2228 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2230 * interp.c (sim_engine_run): Check consistency between configure
2231 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2234 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2235 (mips_fpu): Configure WITH_FLOATING_POINT.
2236 (mips_endian): Configure WITH_TARGET_ENDIAN.
2237 * configure: Update.
2239 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2241 * configure: Regenerated to track ../common/aclocal.m4 changes.
2243 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2245 * configure: Regenerated.
2247 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2249 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2251 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2253 * gencode.c (print_igen_insn_models): Assume certain architectures
2254 include all mips* instructions.
2255 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2258 * Makefile.in (tmp.igen): Add target. Generate igen input from
2261 * gencode.c (FEATURE_IGEN): Define.
2262 (main): Add --igen option. Generate output in igen format.
2263 (process_instructions): Format output according to igen option.
2264 (print_igen_insn_format): New function.
2265 (print_igen_insn_models): New function.
2266 (process_instructions): Only issue warnings and ignore
2267 instructions when no FEATURE_IGEN.
2269 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2271 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2274 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2276 * configure: Regenerated to track ../common/aclocal.m4 changes.
2278 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2280 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2281 SIM_RESERVED_BITS): Delete, moved to common.
2282 (SIM_EXTRA_CFLAGS): Update.
2284 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2286 * configure.in: Configure non-strict memory alignment.
2287 * configure: Regenerated to track ../common/aclocal.m4 changes.
2289 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2291 * configure: Regenerated to track ../common/aclocal.m4 changes.
2293 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2295 * gencode.c (SDBBP,DERET): Added (3900) insns.
2296 (RFE): Turn on for 3900.
2297 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2298 (dsstate): Made global.
2299 (SUBTARGET_R3900): Added.
2300 (CANCELDELAYSLOT): New.
2301 (SignalException): Ignore SystemCall rather than ignore and
2302 terminate. Add DebugBreakPoint handling.
2303 (decode_coproc): New insns RFE, DERET; and new registers Debug
2304 and DEPC protected by SUBTARGET_R3900.
2305 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2307 * Makefile.in,configure.in: Add mips subtarget option.
2308 * configure: Update.
2310 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2312 * gencode.c: Add r3900 (tx39).
2315 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2317 * gencode.c (build_instruction): Don't need to subtract 4 for
2320 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2322 * interp.c: Correct some HASFPU problems.
2324 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2326 * configure: Regenerated to track ../common/aclocal.m4 changes.
2328 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2330 * interp.c (mips_options): Fix samples option short form, should
2333 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2335 * interp.c (sim_info): Enable info code. Was just returning.
2337 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2339 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2342 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2344 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2346 (build_instruction): Ditto for LL.
2348 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2350 * configure: Regenerated to track ../common/aclocal.m4 changes.
2352 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2354 * configure: Regenerated to track ../common/aclocal.m4 changes.
2357 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2359 * interp.c (sim_open): Add call to sim_analyze_program, update
2362 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2364 * interp.c (sim_kill): Delete.
2365 (sim_create_inferior): Add ABFD argument. Set PC from same.
2366 (sim_load): Move code initializing trap handlers from here.
2367 (sim_open): To here.
2368 (sim_load): Delete, use sim-hload.c.
2370 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2372 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2374 * configure: Regenerated to track ../common/aclocal.m4 changes.
2377 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2379 * interp.c (sim_open): Add ABFD argument.
2380 (sim_load): Move call to sim_config from here.
2381 (sim_open): To here. Check return status.
2383 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2385 * gencode.c (build_instruction): Two arg MADD should
2386 not assign result to $0.
2388 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2390 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2391 * sim/mips/configure.in: Regenerate.
2393 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2395 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2396 signed8, unsigned8 et.al. types.
2398 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2399 hosts when selecting subreg.
2401 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2403 * interp.c (sim_engine_run): Reset the ZERO register to zero
2404 regardless of FEATURE_WARN_ZERO.
2405 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2407 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2409 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2410 (SignalException): For BreakPoints ignore any mode bits and just
2412 (SignalException): Always set the CAUSE register.
2414 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2416 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2417 exception has been taken.
2419 * interp.c: Implement the ERET and mt/f sr instructions.
2421 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2423 * interp.c (SignalException): Don't bother restarting an
2426 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2428 * interp.c (SignalException): Really take an interrupt.
2429 (interrupt_event): Only deliver interrupts when enabled.
2431 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2433 * interp.c (sim_info): Only print info when verbose.
2434 (sim_info) Use sim_io_printf for output.
2436 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2438 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2441 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2443 * interp.c (sim_do_command): Check for common commands if a
2444 simulator specific command fails.
2446 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2448 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2449 and simBE when DEBUG is defined.
2451 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2453 * interp.c (interrupt_event): New function. Pass exception event
2454 onto exception handler.
2456 * configure.in: Check for stdlib.h.
2457 * configure: Regenerate.
2459 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2460 variable declaration.
2461 (build_instruction): Initialize memval1.
2462 (build_instruction): Add UNUSED attribute to byte, bigend,
2464 (build_operands): Ditto.
2466 * interp.c: Fix GCC warnings.
2467 (sim_get_quit_code): Delete.
2469 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2470 * Makefile.in: Ditto.
2471 * configure: Re-generate.
2473 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2475 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2477 * interp.c (mips_option_handler): New function parse argumes using
2479 (myname): Replace with STATE_MY_NAME.
2480 (sim_open): Delete check for host endianness - performed by
2482 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2483 (sim_open): Move much of the initialization from here.
2484 (sim_load): To here. After the image has been loaded and
2486 (sim_open): Move ColdReset from here.
2487 (sim_create_inferior): To here.
2488 (sim_open): Make FP check less dependant on host endianness.
2490 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2492 * interp.c (sim_set_callbacks): Delete.
2494 * interp.c (membank, membank_base, membank_size): Replace with
2495 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2496 (sim_open): Remove call to callback->init. gdb/run do this.
2500 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2502 * interp.c (big_endian_p): Delete, replaced by
2503 current_target_byte_order.
2505 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2507 * interp.c (host_read_long, host_read_word, host_swap_word,
2508 host_swap_long): Delete. Using common sim-endian.
2509 (sim_fetch_register, sim_store_register): Use H2T.
2510 (pipeline_ticks): Delete. Handled by sim-events.
2512 (sim_engine_run): Update.
2514 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2516 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2518 (SignalException): To here. Signal using sim_engine_halt.
2519 (sim_stop_reason): Delete, moved to common.
2521 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2523 * interp.c (sim_open): Add callback argument.
2524 (sim_set_callbacks): Delete SIM_DESC argument.
2527 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2529 * Makefile.in (SIM_OBJS): Add common modules.
2531 * interp.c (sim_set_callbacks): Also set SD callback.
2532 (set_endianness, xfer_*, swap_*): Delete.
2533 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2534 Change to functions using sim-endian macros.
2535 (control_c, sim_stop): Delete, use common version.
2536 (simulate): Convert into.
2537 (sim_engine_run): This function.
2538 (sim_resume): Delete.
2540 * interp.c (simulation): New variable - the simulator object.
2541 (sim_kind): Delete global - merged into simulation.
2542 (sim_load): Cleanup. Move PC assignment from here.
2543 (sim_create_inferior): To here.
2545 * sim-main.h: New file.
2546 * interp.c (sim-main.h): Include.
2548 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2550 * configure: Regenerated to track ../common/aclocal.m4 changes.
2552 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2554 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2556 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2558 * gencode.c (build_instruction): DIV instructions: check
2559 for division by zero and integer overflow before using
2560 host's division operation.
2562 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2564 * Makefile.in (SIM_OBJS): Add sim-load.o.
2565 * interp.c: #include bfd.h.
2566 (target_byte_order): Delete.
2567 (sim_kind, myname, big_endian_p): New static locals.
2568 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2569 after argument parsing. Recognize -E arg, set endianness accordingly.
2570 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2571 load file into simulator. Set PC from bfd.
2572 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2573 (set_endianness): Use big_endian_p instead of target_byte_order.
2575 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2577 * interp.c (sim_size): Delete prototype - conflicts with
2578 definition in remote-sim.h. Correct definition.
2580 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2582 * configure: Regenerated to track ../common/aclocal.m4 changes.
2585 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2587 * interp.c (sim_open): New arg `kind'.
2589 * configure: Regenerated to track ../common/aclocal.m4 changes.
2591 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2593 * configure: Regenerated to track ../common/aclocal.m4 changes.
2595 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2597 * interp.c (sim_open): Set optind to 0 before calling getopt.
2599 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2601 * configure: Regenerated to track ../common/aclocal.m4 changes.
2603 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2605 * interp.c : Replace uses of pr_addr with pr_uword64
2606 where the bit length is always 64 independent of SIM_ADDR.
2607 (pr_uword64) : added.
2609 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2611 * configure: Re-generate.
2613 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2615 * configure: Regenerate to track ../common/aclocal.m4 changes.
2617 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2619 * interp.c (sim_open): New SIM_DESC result. Argument is now
2621 (other sim_*): New SIM_DESC argument.
2623 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2625 * interp.c: Fix printing of addresses for non-64-bit targets.
2626 (pr_addr): Add function to print address based on size.
2628 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2630 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2632 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2634 * gencode.c (build_mips16_operands): Correct computation of base
2635 address for extended PC relative instruction.
2637 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2639 * interp.c (mips16_entry): Add support for floating point cases.
2640 (SignalException): Pass floating point cases to mips16_entry.
2641 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2643 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2645 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2646 and then set the state to fmt_uninterpreted.
2647 (COP_SW): Temporarily set the state to fmt_word while calling
2650 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2652 * gencode.c (build_instruction): The high order may be set in the
2653 comparison flags at any ISA level, not just ISA 4.
2655 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2657 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2658 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2659 * configure.in: sinclude ../common/aclocal.m4.
2660 * configure: Regenerated.
2662 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2664 * configure: Rebuild after change to aclocal.m4.
2666 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2668 * configure configure.in Makefile.in: Update to new configure
2669 scheme which is more compatible with WinGDB builds.
2670 * configure.in: Improve comment on how to run autoconf.
2671 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2672 * Makefile.in: Use autoconf substitution to install common
2675 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2677 * gencode.c (build_instruction): Use BigEndianCPU instead of
2680 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2682 * interp.c (sim_monitor): Make output to stdout visible in
2683 wingdb's I/O log window.
2685 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2687 * support.h: Undo previous change to SIGTRAP
2690 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2692 * interp.c (store_word, load_word): New static functions.
2693 (mips16_entry): New static function.
2694 (SignalException): Look for mips16 entry and exit instructions.
2695 (simulate): Use the correct index when setting fpr_state after
2696 doing a pending move.
2698 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2700 * interp.c: Fix byte-swapping code throughout to work on
2701 both little- and big-endian hosts.
2703 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2705 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2706 with gdb/config/i386/xm-windows.h.
2708 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2710 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2711 that messes up arithmetic shifts.
2713 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2715 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2716 SIGTRAP and SIGQUIT for _WIN32.
2718 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2720 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2721 force a 64 bit multiplication.
2722 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2723 destination register is 0, since that is the default mips16 nop
2726 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2728 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2729 (build_endian_shift): Don't check proc64.
2730 (build_instruction): Always set memval to uword64. Cast op2 to
2731 uword64 when shifting it left in memory instructions. Always use
2732 the same code for stores--don't special case proc64.
2734 * gencode.c (build_mips16_operands): Fix base PC value for PC
2736 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2738 * interp.c (simJALDELAYSLOT): Define.
2739 (JALDELAYSLOT): Define.
2740 (INDELAYSLOT, INJALDELAYSLOT): Define.
2741 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2743 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2745 * interp.c (sim_open): add flush_cache as a PMON routine
2746 (sim_monitor): handle flush_cache by ignoring it
2748 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2750 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2752 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2753 (BigEndianMem): Rename to ByteSwapMem and change sense.
2754 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2755 BigEndianMem references to !ByteSwapMem.
2756 (set_endianness): New function, with prototype.
2757 (sim_open): Call set_endianness.
2758 (sim_info): Use simBE instead of BigEndianMem.
2759 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2760 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2761 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2762 ifdefs, keeping the prototype declaration.
2763 (swap_word): Rewrite correctly.
2764 (ColdReset): Delete references to CONFIG. Delete endianness related
2765 code; moved to set_endianness.
2767 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2769 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2770 * interp.c (CHECKHILO): Define away.
2771 (simSIGINT): New macro.
2772 (membank_size): Increase from 1MB to 2MB.
2773 (control_c): New function.
2774 (sim_resume): Rename parameter signal to signal_number. Add local
2775 variable prev. Call signal before and after simulate.
2776 (sim_stop_reason): Add simSIGINT support.
2777 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2779 (sim_warning): Delete call to SignalException. Do call printf_filtered
2781 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2782 a call to sim_warning.
2784 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2786 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2787 16 bit instructions.
2789 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2791 Add support for mips16 (16 bit MIPS implementation):
2792 * gencode.c (inst_type): Add mips16 instruction encoding types.
2793 (GETDATASIZEINSN): Define.
2794 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2795 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2797 (MIPS16_DECODE): New table, for mips16 instructions.
2798 (bitmap_val): New static function.
2799 (struct mips16_op): Define.
2800 (mips16_op_table): New table, for mips16 operands.
2801 (build_mips16_operands): New static function.
2802 (process_instructions): If PC is odd, decode a mips16
2803 instruction. Break out instruction handling into new
2804 build_instruction function.
2805 (build_instruction): New static function, broken out of
2806 process_instructions. Check modifiers rather than flags for SHIFT
2807 bit count and m[ft]{hi,lo} direction.
2808 (usage): Pass program name to fprintf.
2809 (main): Remove unused variable this_option_optind. Change
2810 ``*loptarg++'' to ``loptarg++''.
2811 (my_strtoul): Parenthesize && within ||.
2812 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2813 (simulate): If PC is odd, fetch a 16 bit instruction, and
2814 increment PC by 2 rather than 4.
2815 * configure.in: Add case for mips16*-*-*.
2816 * configure: Rebuild.
2818 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2820 * interp.c: Allow -t to enable tracing in standalone simulator.
2821 Fix garbage output in trace file and error messages.
2823 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2825 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2826 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2827 * configure.in: Simplify using macros in ../common/aclocal.m4.
2828 * configure: Regenerated.
2829 * tconfig.in: New file.
2831 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2833 * interp.c: Fix bugs in 64-bit port.
2834 Use ansi function declarations for msvc compiler.
2835 Initialize and test file pointer in trace code.
2836 Prevent duplicate definition of LAST_EMED_REGNUM.
2838 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2840 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2842 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2844 * interp.c (SignalException): Check for explicit terminating
2846 * gencode.c: Pass instruction value through SignalException()
2847 calls for Trap, Breakpoint and Syscall.
2849 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2851 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2852 only used on those hosts that provide it.
2853 * configure.in: Add sqrt() to list of functions to be checked for.
2854 * config.in: Re-generated.
2855 * configure: Re-generated.
2857 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2859 * gencode.c (process_instructions): Call build_endian_shift when
2860 expanding STORE RIGHT, to fix swr.
2861 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2862 clear the high bits.
2863 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2864 Fix float to int conversions to produce signed values.
2866 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2868 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2869 (process_instructions): Correct handling of nor instruction.
2870 Correct shift count for 32 bit shift instructions. Correct sign
2871 extension for arithmetic shifts to not shift the number of bits in
2872 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2873 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2875 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2876 It's OK to have a mult follow a mult. What's not OK is to have a
2877 mult follow an mfhi.
2878 (Convert): Comment out incorrect rounding code.
2880 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2882 * interp.c (sim_monitor): Improved monitor printf
2883 simulation. Tidied up simulator warnings, and added "--log" option
2884 for directing warning message output.
2885 * gencode.c: Use sim_warning() rather than WARNING macro.
2887 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2889 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2890 getopt1.o, rather than on gencode.c. Link objects together.
2891 Don't link against -liberty.
2892 (gencode.o, getopt.o, getopt1.o): New targets.
2893 * gencode.c: Include <ctype.h> and "ansidecl.h".
2894 (AND): Undefine after including "ansidecl.h".
2895 (ULONG_MAX): Define if not defined.
2896 (OP_*): Don't define macros; now defined in opcode/mips.h.
2897 (main): Call my_strtoul rather than strtoul.
2898 (my_strtoul): New static function.
2900 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2902 * gencode.c (process_instructions): Generate word64 and uword64
2903 instead of `long long' and `unsigned long long' data types.
2904 * interp.c: #include sysdep.h to get signals, and define default
2906 * (Convert): Work around for Visual-C++ compiler bug with type
2908 * support.h: Make things compile under Visual-C++ by using
2909 __int64 instead of `long long'. Change many refs to long long
2910 into word64/uword64 typedefs.
2912 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2914 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2915 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2917 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2918 (AC_PROG_INSTALL): Added.
2919 (AC_PROG_CC): Moved to before configure.host call.
2920 * configure: Rebuilt.
2922 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2924 * configure.in: Define @SIMCONF@ depending on mips target.
2925 * configure: Rebuild.
2926 * Makefile.in (run): Add @SIMCONF@ to control simulator
2928 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2929 * interp.c: Remove some debugging, provide more detailed error
2930 messages, update memory accesses to use LOADDRMASK.
2932 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2934 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2935 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2937 * configure: Rebuild.
2938 * config.in: New file, generated by autoheader.
2939 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2940 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2941 HAVE_ANINT and HAVE_AINT, as appropriate.
2942 * Makefile.in (run): Use @LIBS@ rather than -lm.
2943 (interp.o): Depend upon config.h.
2944 (Makefile): Just rebuild Makefile.
2945 (clean): Remove stamp-h.
2946 (mostlyclean): Make the same as clean, not as distclean.
2947 (config.h, stamp-h): New targets.
2949 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2951 * interp.c (ColdReset): Fix boolean test. Make all simulator
2954 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2956 * interp.c (xfer_direct_word, xfer_direct_long,
2957 swap_direct_word, swap_direct_long, xfer_big_word,
2958 xfer_big_long, xfer_little_word, xfer_little_long,
2959 swap_word,swap_long): Added.
2960 * interp.c (ColdReset): Provide function indirection to
2961 host<->simulated_target transfer routines.
2962 * interp.c (sim_store_register, sim_fetch_register): Updated to
2963 make use of indirected transfer routines.
2965 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2967 * gencode.c (process_instructions): Ensure FP ABS instruction
2969 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2970 system call support.
2972 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2974 * interp.c (sim_do_command): Complain if callback structure not
2977 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2979 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2980 support for Sun hosts.
2981 * Makefile.in (gencode): Ensure the host compiler and libraries
2982 used for cross-hosted build.
2984 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2986 * interp.c, gencode.c: Some more (TODO) tidying.
2988 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2990 * gencode.c, interp.c: Replaced explicit long long references with
2991 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2992 * support.h (SET64LO, SET64HI): Macros added.
2994 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2996 * configure: Regenerate with autoconf 2.7.
2998 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3000 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3001 * support.h: Remove superfluous "1" from #if.
3002 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3004 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3006 * interp.c (StoreFPR): Control UndefinedResult() call on
3007 WARN_RESULT manifest.
3009 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3011 * gencode.c: Tidied instruction decoding, and added FP instruction
3014 * interp.c: Added dineroIII, and BSD profiling support. Also
3015 run-time FP handling.
3017 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3019 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3020 gencode.c, interp.c, support.h: created.