1 2005-07-08 Ian Lance Taylor <ian@airs.com>
3 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
5 2005-06-16 David Ung <davidu@mips.com>
6 Nigel Stephens <nigel@mips.com>
8 * mips.igen: New mips16e model and include m16e.igen.
9 (check_u64): Add mips16e tag.
10 * m16e.igen: New file for MIPS16e instructions.
11 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
12 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
14 * configure: Regenerate.
16 2005-05-26 David Ung <davidu@mips.com>
18 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
19 tags to all instructions which are applicable to the new ISAs.
20 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
22 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
24 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
26 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
27 * configure: Regenerate.
29 2005-03-23 Mark Kettenis <kettenis@gnu.org>
31 * configure: Regenerate.
33 2005-01-14 Andrew Cagney <cagney@gnu.org>
35 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
36 explicit call to AC_CONFIG_HEADER.
37 * configure: Regenerate.
39 2005-01-12 Andrew Cagney <cagney@gnu.org>
41 * configure.ac: Update to use ../common/common.m4.
42 * configure: Re-generate.
44 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
46 * configure: Regenerated to track ../common/aclocal.m4 changes.
48 2005-01-07 Andrew Cagney <cagney@gnu.org>
50 * configure.ac: Rename configure.in, require autoconf 2.59.
51 * configure: Re-generate.
53 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
55 * configure: Regenerate for ../common/aclocal.m4 update.
57 2004-09-24 Monika Chaddha <monika@acmet.com>
59 Committed by Andrew Cagney.
60 * m16.igen (CMP, CMPI): Fix assembler.
62 2004-08-18 Chris Demetriou <cgd@broadcom.com>
64 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
65 * configure: Regenerate.
67 2004-06-25 Chris Demetriou <cgd@broadcom.com>
69 * configure.in (sim_m16_machine): Include mipsIII.
70 * configure: Regenerate.
72 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
74 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
76 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
78 2004-04-10 Chris Demetriou <cgd@broadcom.com>
80 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
82 2004-04-09 Chris Demetriou <cgd@broadcom.com>
84 * mips.igen (check_fmt): Remove.
85 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
86 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
87 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
88 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
89 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
90 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
91 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
92 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
93 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
94 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
96 2004-04-09 Chris Demetriou <cgd@broadcom.com>
98 * sb1.igen (check_sbx): New function.
99 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
101 2004-03-29 Chris Demetriou <cgd@broadcom.com>
102 Richard Sandiford <rsandifo@redhat.com>
104 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
105 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
106 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
107 separate implementations for mipsIV and mipsV. Use new macros to
108 determine whether the restrictions apply.
110 2004-01-19 Chris Demetriou <cgd@broadcom.com>
112 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
113 (check_mult_hilo): Improve comments.
114 (check_div_hilo): Likewise. Also, fork off a new version
115 to handle mips32/mips64 (since there are no hazards to check
118 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
120 * mips.igen (do_dmultx): Fix check for negative operands.
122 2003-05-16 Ian Lance Taylor <ian@airs.com>
124 * Makefile.in (SHELL): Make sure this is defined.
125 (various): Use $(SHELL) whenever we invoke move-if-change.
127 2003-05-03 Chris Demetriou <cgd@broadcom.com>
129 * cp1.c: Tweak attribution slightly.
132 * mdmx.igen: Likewise.
133 * mips3d.igen: Likewise.
134 * sb1.igen: Likewise.
136 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
138 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
141 2003-02-27 Andrew Cagney <cagney@redhat.com>
143 * interp.c (sim_open): Rename _bfd to bfd.
144 (sim_create_inferior): Ditto.
146 2003-01-14 Chris Demetriou <cgd@broadcom.com>
148 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
150 2003-01-14 Chris Demetriou <cgd@broadcom.com>
152 * mips.igen (EI, DI): Remove.
154 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
156 * Makefile.in (tmp-run-multi): Fix mips16 filter.
158 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
159 Andrew Cagney <ac131313@redhat.com>
160 Gavin Romig-Koch <gavin@redhat.com>
161 Graydon Hoare <graydon@redhat.com>
162 Aldy Hernandez <aldyh@redhat.com>
163 Dave Brolley <brolley@redhat.com>
164 Chris Demetriou <cgd@broadcom.com>
166 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
167 (sim_mach_default): New variable.
168 (mips64vr-*-*, mips64vrel-*-*): New configurations.
169 Add a new simulator generator, MULTI.
170 * configure: Regenerate.
171 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
172 (multi-run.o): New dependency.
173 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
174 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
175 (tmp-multi): Combine them.
176 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
177 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
178 (distclean-extra): New rule.
179 * sim-main.h: Include bfd.h.
180 (MIPS_MACH): New macro.
181 * mips.igen (vr4120, vr5400, vr5500): New models.
182 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
183 * vr.igen: Replace with new version.
185 2003-01-04 Chris Demetriou <cgd@broadcom.com>
187 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
188 * configure: Regenerate.
190 2002-12-31 Chris Demetriou <cgd@broadcom.com>
192 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
193 * mips.igen: Remove all invocations of check_branch_bug and
196 2002-12-16 Chris Demetriou <cgd@broadcom.com>
198 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
200 2002-07-30 Chris Demetriou <cgd@broadcom.com>
202 * mips.igen (do_load_double, do_store_double): New functions.
203 (LDC1, SDC1): Rename to...
204 (LDC1b, SDC1b): respectively.
205 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
207 2002-07-29 Michael Snyder <msnyder@redhat.com>
209 * cp1.c (fp_recip2): Modify initialization expression so that
210 GCC will recognize it as constant.
212 2002-06-18 Chris Demetriou <cgd@broadcom.com>
214 * mdmx.c (SD_): Delete.
215 (Unpredictable): Re-define, for now, to directly invoke
216 unpredictable_action().
217 (mdmx_acc_op): Fix error in .ob immediate handling.
219 2002-06-18 Andrew Cagney <cagney@redhat.com>
221 * interp.c (sim_firmware_command): Initialize `address'.
223 2002-06-16 Andrew Cagney <ac131313@redhat.com>
225 * configure: Regenerated to track ../common/aclocal.m4 changes.
227 2002-06-14 Chris Demetriou <cgd@broadcom.com>
228 Ed Satterthwaite <ehs@broadcom.com>
230 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
231 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
232 * mips.igen: Include mips3d.igen.
233 (mips3d): New model name for MIPS-3D ASE instructions.
234 (CVT.W.fmt): Don't use this instruction for word (source) format
236 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
237 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
238 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
239 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
240 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
241 (RSquareRoot1, RSquareRoot2): New macros.
242 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
243 (fp_rsqrt2): New functions.
244 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
245 * configure: Regenerate.
247 2002-06-13 Chris Demetriou <cgd@broadcom.com>
248 Ed Satterthwaite <ehs@broadcom.com>
250 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
251 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
252 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
253 (convert): Note that this function is not used for paired-single
255 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
256 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
257 (check_fmt_p): Enable paired-single support.
258 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
259 (PUU.PS): New instructions.
260 (CVT.S.fmt): Don't use this instruction for paired-single format
262 * sim-main.h (FP_formats): New value 'fmt_ps.'
263 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
264 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
266 2002-06-12 Chris Demetriou <cgd@broadcom.com>
268 * mips.igen: Fix formatting of function calls in
271 2002-06-12 Chris Demetriou <cgd@broadcom.com>
273 * mips.igen (MOVN, MOVZ): Trace result.
274 (TNEI): Print "tnei" as the opcode name in traces.
275 (CEIL.W): Add disassembly string for traces.
276 (RSQRT.fmt): Make location of disassembly string consistent
277 with other instructions.
279 2002-06-12 Chris Demetriou <cgd@broadcom.com>
281 * mips.igen (X): Delete unused function.
283 2002-06-08 Andrew Cagney <cagney@redhat.com>
285 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
287 2002-06-07 Chris Demetriou <cgd@broadcom.com>
288 Ed Satterthwaite <ehs@broadcom.com>
290 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
291 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
292 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
293 (fp_nmsub): New prototypes.
294 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
295 (NegMultiplySub): New defines.
296 * mips.igen (RSQRT.fmt): Use RSquareRoot().
297 (MADD.D, MADD.S): Replace with...
298 (MADD.fmt): New instruction.
299 (MSUB.D, MSUB.S): Replace with...
300 (MSUB.fmt): New instruction.
301 (NMADD.D, NMADD.S): Replace with...
302 (NMADD.fmt): New instruction.
303 (NMSUB.D, MSUB.S): Replace with...
304 (NMSUB.fmt): New instruction.
306 2002-06-07 Chris Demetriou <cgd@broadcom.com>
307 Ed Satterthwaite <ehs@broadcom.com>
309 * cp1.c: Fix more comment spelling and formatting.
310 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
311 (denorm_mode): New function.
312 (fpu_unary, fpu_binary): Round results after operation, collect
313 status from rounding operations, and update the FCSR.
314 (convert): Collect status from integer conversions and rounding
315 operations, and update the FCSR. Adjust NaN values that result
316 from conversions. Convert to use sim_io_eprintf rather than
317 fprintf, and remove some debugging code.
318 * cp1.h (fenr_FS): New define.
320 2002-06-07 Chris Demetriou <cgd@broadcom.com>
322 * cp1.c (convert): Remove unusable debugging code, and move MIPS
323 rounding mode to sim FP rounding mode flag conversion code into...
324 (rounding_mode): New function.
326 2002-06-07 Chris Demetriou <cgd@broadcom.com>
328 * cp1.c: Clean up formatting of a few comments.
329 (value_fpr): Reformat switch statement.
331 2002-06-06 Chris Demetriou <cgd@broadcom.com>
332 Ed Satterthwaite <ehs@broadcom.com>
335 * sim-main.h: Include cp1.h.
336 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
337 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
338 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
339 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
340 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
341 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
342 * cp1.c: Don't include sim-fpu.h; already included by
343 sim-main.h. Clean up formatting of some comments.
344 (NaN, Equal, Less): Remove.
345 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
346 (fp_cmp): New functions.
347 * mips.igen (do_c_cond_fmt): Remove.
348 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
349 Compare. Add result tracing.
350 (CxC1): Remove, replace with...
351 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
352 (DMxC1): Remove, replace with...
353 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
354 (MxC1): Remove, replace with...
355 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
357 2002-06-04 Chris Demetriou <cgd@broadcom.com>
359 * sim-main.h (FGRIDX): Remove, replace all uses with...
360 (FGR_BASE): New macro.
361 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
362 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
363 (NR_FGR, FGR): Likewise.
364 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
365 * mips.igen: Likewise.
367 2002-06-04 Chris Demetriou <cgd@broadcom.com>
369 * cp1.c: Add an FSF Copyright notice to this file.
371 2002-06-04 Chris Demetriou <cgd@broadcom.com>
372 Ed Satterthwaite <ehs@broadcom.com>
374 * cp1.c (Infinity): Remove.
375 * sim-main.h (Infinity): Likewise.
377 * cp1.c (fp_unary, fp_binary): New functions.
378 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
379 (fp_sqrt): New functions, implemented in terms of the above.
380 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
381 (Recip, SquareRoot): Remove (replaced by functions above).
382 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
383 (fp_recip, fp_sqrt): New prototypes.
384 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
385 (Recip, SquareRoot): Replace prototypes with #defines which
386 invoke the functions above.
388 2002-06-03 Chris Demetriou <cgd@broadcom.com>
390 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
391 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
392 file, remove PARAMS from prototypes.
393 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
394 simulator state arguments.
395 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
396 pass simulator state arguments.
397 * cp1.c (SD): Redefine as CPU_STATE(cpu).
398 (store_fpr, convert): Remove 'sd' argument.
399 (value_fpr): Likewise. Convert to use 'SD' instead.
401 2002-06-03 Chris Demetriou <cgd@broadcom.com>
403 * cp1.c (Min, Max): Remove #if 0'd functions.
404 * sim-main.h (Min, Max): Remove.
406 2002-06-03 Chris Demetriou <cgd@broadcom.com>
408 * cp1.c: fix formatting of switch case and default labels.
409 * interp.c: Likewise.
410 * sim-main.c: Likewise.
412 2002-06-03 Chris Demetriou <cgd@broadcom.com>
414 * cp1.c: Clean up comments which describe FP formats.
415 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
417 2002-06-03 Chris Demetriou <cgd@broadcom.com>
418 Ed Satterthwaite <ehs@broadcom.com>
420 * configure.in (mipsisa64sb1*-*-*): New target for supporting
421 Broadcom SiByte SB-1 processor configurations.
422 * configure: Regenerate.
423 * sb1.igen: New file.
424 * mips.igen: Include sb1.igen.
426 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
427 * mdmx.igen: Add "sb1" model to all appropriate functions and
429 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
430 (ob_func, ob_acc): Reference the above.
431 (qh_acc): Adjust to keep the same size as ob_acc.
432 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
433 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
435 2002-06-03 Chris Demetriou <cgd@broadcom.com>
437 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
439 2002-06-02 Chris Demetriou <cgd@broadcom.com>
440 Ed Satterthwaite <ehs@broadcom.com>
442 * mips.igen (mdmx): New (pseudo-)model.
443 * mdmx.c, mdmx.igen: New files.
444 * Makefile.in (SIM_OBJS): Add mdmx.o.
445 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
447 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
448 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
449 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
450 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
451 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
452 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
453 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
454 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
455 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
456 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
457 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
458 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
459 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
460 (qh_fmtsel): New macros.
461 (_sim_cpu): New member "acc".
462 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
463 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
465 2002-05-01 Chris Demetriou <cgd@broadcom.com>
467 * interp.c: Use 'deprecated' rather than 'depreciated.'
468 * sim-main.h: Likewise.
470 2002-05-01 Chris Demetriou <cgd@broadcom.com>
472 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
473 which wouldn't compile anyway.
474 * sim-main.h (unpredictable_action): New function prototype.
475 (Unpredictable): Define to call igen function unpredictable().
476 (NotWordValue): New macro to call igen function not_word_value().
477 (UndefinedResult): Remove.
478 * interp.c (undefined_result): Remove.
479 (unpredictable_action): New function.
480 * mips.igen (not_word_value, unpredictable): New functions.
481 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
482 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
483 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
484 NotWordValue() to check for unpredictable inputs, then
485 Unpredictable() to handle them.
487 2002-02-24 Chris Demetriou <cgd@broadcom.com>
489 * mips.igen: Fix formatting of calls to Unpredictable().
491 2002-04-20 Andrew Cagney <ac131313@redhat.com>
493 * interp.c (sim_open): Revert previous change.
495 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
497 * interp.c (sim_open): Disable chunk of code that wrote code in
498 vector table entries.
500 2002-03-19 Chris Demetriou <cgd@broadcom.com>
502 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
503 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
506 2002-03-19 Chris Demetriou <cgd@broadcom.com>
508 * cp1.c: Fix many formatting issues.
510 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
512 * cp1.c (fpu_format_name): New function to replace...
513 (DOFMT): This. Delete, and update all callers.
514 (fpu_rounding_mode_name): New function to replace...
515 (RMMODE): This. Delete, and update all callers.
517 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
519 * interp.c: Move FPU support routines from here to...
520 * cp1.c: Here. New file.
521 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
524 2002-03-12 Chris Demetriou <cgd@broadcom.com>
526 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
527 * mips.igen (mips32, mips64): New models, add to all instructions
528 and functions as appropriate.
529 (loadstore_ea, check_u64): New variant for model mips64.
530 (check_fmt_p): New variant for models mipsV and mips64, remove
531 mipsV model marking fro other variant.
534 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
535 for mips32 and mips64.
536 (DCLO, DCLZ): New instructions for mips64.
538 2002-03-07 Chris Demetriou <cgd@broadcom.com>
540 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
541 immediate or code as a hex value with the "%#lx" format.
542 (ANDI): Likewise, and fix printed instruction name.
544 2002-03-05 Chris Demetriou <cgd@broadcom.com>
546 * sim-main.h (UndefinedResult, Unpredictable): New macros
547 which currently do nothing.
549 2002-03-05 Chris Demetriou <cgd@broadcom.com>
551 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
552 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
553 (status_CU3): New definitions.
555 * sim-main.h (ExceptionCause): Add new values for MIPS32
556 and MIPS64: MDMX, MCheck, CacheErr. Update comments
557 for DebugBreakPoint and NMIReset to note their status in
559 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
560 (SignalExceptionCacheErr): New exception macros.
562 2002-03-05 Chris Demetriou <cgd@broadcom.com>
564 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
565 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
567 (SignalExceptionCoProcessorUnusable): Take as argument the
568 unusable coprocessor number.
570 2002-03-05 Chris Demetriou <cgd@broadcom.com>
572 * mips.igen: Fix formatting of all SignalException calls.
574 2002-03-05 Chris Demetriou <cgd@broadcom.com>
576 * sim-main.h (SIGNEXTEND): Remove.
578 2002-03-04 Chris Demetriou <cgd@broadcom.com>
580 * mips.igen: Remove gencode comment from top of file, fix
581 spelling in another comment.
583 2002-03-04 Chris Demetriou <cgd@broadcom.com>
585 * mips.igen (check_fmt, check_fmt_p): New functions to check
586 whether specific floating point formats are usable.
587 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
588 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
589 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
590 Use the new functions.
591 (do_c_cond_fmt): Remove format checks...
592 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
594 2002-03-03 Chris Demetriou <cgd@broadcom.com>
596 * mips.igen: Fix formatting of check_fpu calls.
598 2002-03-03 Chris Demetriou <cgd@broadcom.com>
600 * mips.igen (FLOOR.L.fmt): Store correct destination register.
602 2002-03-03 Chris Demetriou <cgd@broadcom.com>
604 * mips.igen: Remove whitespace at end of lines.
606 2002-03-02 Chris Demetriou <cgd@broadcom.com>
608 * mips.igen (loadstore_ea): New function to do effective
609 address calculations.
610 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
611 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
612 CACHE): Use loadstore_ea to do effective address computations.
614 2002-03-02 Chris Demetriou <cgd@broadcom.com>
616 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
617 * mips.igen (LL, CxC1, MxC1): Likewise.
619 2002-03-02 Chris Demetriou <cgd@broadcom.com>
621 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
622 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
623 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
624 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
625 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
626 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
627 Don't split opcode fields by hand, use the opcode field values
630 2002-03-01 Chris Demetriou <cgd@broadcom.com>
632 * mips.igen (do_divu): Fix spacing.
634 * mips.igen (do_dsllv): Move to be right before DSLLV,
635 to match the rest of the do_<shift> functions.
637 2002-03-01 Chris Demetriou <cgd@broadcom.com>
639 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
640 DSRL32, do_dsrlv): Trace inputs and results.
642 2002-03-01 Chris Demetriou <cgd@broadcom.com>
644 * mips.igen (CACHE): Provide instruction-printing string.
646 * interp.c (signal_exception): Comment tokens after #endif.
648 2002-02-28 Chris Demetriou <cgd@broadcom.com>
650 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
651 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
652 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
653 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
654 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
655 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
656 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
657 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
659 2002-02-28 Chris Demetriou <cgd@broadcom.com>
661 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
662 instruction-printing string.
663 (LWU): Use '64' as the filter flag.
665 2002-02-28 Chris Demetriou <cgd@broadcom.com>
667 * mips.igen (SDXC1): Fix instruction-printing string.
669 2002-02-28 Chris Demetriou <cgd@broadcom.com>
671 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
674 2002-02-27 Chris Demetriou <cgd@broadcom.com>
676 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
679 2002-02-27 Chris Demetriou <cgd@broadcom.com>
681 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
682 add a comma) so that it more closely match the MIPS ISA
683 documentation opcode partitioning.
684 (PREF): Put useful names on opcode fields, and include
685 instruction-printing string.
687 2002-02-27 Chris Demetriou <cgd@broadcom.com>
689 * mips.igen (check_u64): New function which in the future will
690 check whether 64-bit instructions are usable and signal an
691 exception if not. Currently a no-op.
692 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
693 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
694 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
695 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
697 * mips.igen (check_fpu): New function which in the future will
698 check whether FPU instructions are usable and signal an exception
699 if not. Currently a no-op.
700 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
701 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
702 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
703 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
704 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
705 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
706 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
707 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
709 2002-02-27 Chris Demetriou <cgd@broadcom.com>
711 * mips.igen (do_load_left, do_load_right): Move to be immediately
713 (do_store_left, do_store_right): Move to be immediately following
716 2002-02-27 Chris Demetriou <cgd@broadcom.com>
718 * mips.igen (mipsV): New model name. Also, add it to
719 all instructions and functions where it is appropriate.
721 2002-02-18 Chris Demetriou <cgd@broadcom.com>
723 * mips.igen: For all functions and instructions, list model
724 names that support that instruction one per line.
726 2002-02-11 Chris Demetriou <cgd@broadcom.com>
728 * mips.igen: Add some additional comments about supported
729 models, and about which instructions go where.
730 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
731 order as is used in the rest of the file.
733 2002-02-11 Chris Demetriou <cgd@broadcom.com>
735 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
736 indicating that ALU32_END or ALU64_END are there to check
738 (DADD): Likewise, but also remove previous comment about
741 2002-02-10 Chris Demetriou <cgd@broadcom.com>
743 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
744 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
745 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
746 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
747 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
748 fields (i.e., add and move commas) so that they more closely
749 match the MIPS ISA documentation opcode partitioning.
751 2002-02-10 Chris Demetriou <cgd@broadcom.com>
753 * mips.igen (ADDI): Print immediate value.
755 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
756 (SLL): Print "nop" specially, and don't run the code
757 that does the shift for the "nop" case.
759 2001-11-17 Fred Fish <fnf@redhat.com>
761 * sim-main.h (float_operation): Move enum declaration outside
762 of _sim_cpu struct declaration.
764 2001-04-12 Jim Blandy <jimb@redhat.com>
766 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
767 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
769 * sim-main.h (COCIDX): Remove definition; this isn't supported by
770 PENDING_FILL, and you can get the intended effect gracefully by
771 calling PENDING_SCHED directly.
773 2001-02-23 Ben Elliston <bje@redhat.com>
775 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
776 already defined elsewhere.
778 2001-02-19 Ben Elliston <bje@redhat.com>
780 * sim-main.h (sim_monitor): Return an int.
781 * interp.c (sim_monitor): Add return values.
782 (signal_exception): Handle error conditions from sim_monitor.
784 2001-02-08 Ben Elliston <bje@redhat.com>
786 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
787 (store_memory): Likewise, pass cia to sim_core_write*.
789 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
791 On advice from Chris G. Demetriou <cgd@sibyte.com>:
792 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
794 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
796 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
797 * Makefile.in: Don't delete *.igen when cleaning directory.
799 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
801 * m16.igen (break): Call SignalException not sim_engine_halt.
803 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
806 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
808 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
810 * mips.igen (MxC1, DMxC1): Fix printf formatting.
812 2000-05-24 Michael Hayes <mhayes@cygnus.com>
814 * mips.igen (do_dmultx): Fix typo.
816 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
818 * configure: Regenerated to track ../common/aclocal.m4 changes.
820 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
822 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
824 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
826 * sim-main.h (GPR_CLEAR): Define macro.
828 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
830 * interp.c (decode_coproc): Output long using %lx and not %s.
832 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
834 * interp.c (sim_open): Sort & extend dummy memory regions for
835 --board=jmr3904 for eCos.
837 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
839 * configure: Regenerated.
841 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
843 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
844 calls, conditional on the simulator being in verbose mode.
846 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
848 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
849 cache don't get ReservedInstruction traps.
851 1999-11-29 Mark Salter <msalter@cygnus.com>
853 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
854 to clear status bits in sdisr register. This is how the hardware works.
856 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
857 being used by cygmon.
859 1999-11-11 Andrew Haley <aph@cygnus.com>
861 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
864 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
866 * mips.igen (MULT): Correct previous mis-applied patch.
868 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
870 * mips.igen (delayslot32): Handle sequence like
871 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
872 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
873 (MULT): Actually pass the third register...
875 1999-09-03 Mark Salter <msalter@cygnus.com>
877 * interp.c (sim_open): Added more memory aliases for additional
878 hardware being touched by cygmon on jmr3904 board.
880 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
882 * configure: Regenerated to track ../common/aclocal.m4 changes.
884 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
886 * interp.c (sim_store_register): Handle case where client - GDB -
887 specifies that a 4 byte register is 8 bytes in size.
888 (sim_fetch_register): Ditto.
890 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
892 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
893 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
894 (idt_monitor_base): Base address for IDT monitor traps.
895 (pmon_monitor_base): Ditto for PMON.
896 (lsipmon_monitor_base): Ditto for LSI PMON.
897 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
898 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
899 (sim_firmware_command): New function.
900 (mips_option_handler): Call it for OPTION_FIRMWARE.
901 (sim_open): Allocate memory for idt_monitor region. If "--board"
902 option was given, add no monitor by default. Add BREAK hooks only if
903 monitors are also there.
905 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
907 * interp.c (sim_monitor): Flush output before reading input.
909 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
911 * tconfig.in (SIM_HANDLES_LMA): Always define.
913 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
915 From Mark Salter <msalter@cygnus.com>:
916 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
917 (sim_open): Add setup for BSP board.
919 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
921 * mips.igen (MULT, MULTU): Add syntax for two operand version.
922 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
923 them as unimplemented.
925 1999-05-08 Felix Lee <flee@cygnus.com>
927 * configure: Regenerated to track ../common/aclocal.m4 changes.
929 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
931 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
933 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
935 * configure.in: Any mips64vr5*-*-* target should have
936 -DTARGET_ENABLE_FR=1.
937 (default_endian): Any mips64vr*el-*-* target should default to
939 * configure: Re-generate.
941 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
943 * mips.igen (ldl): Extend from _16_, not 32.
945 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
947 * interp.c (sim_store_register): Force registers written to by GDB
948 into an un-interpreted state.
950 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
952 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
953 CPU, start periodic background I/O polls.
954 (tx3904sio_poll): New function: periodic I/O poller.
956 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
958 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
960 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
962 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
965 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
967 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
968 (load_word): Call SIM_CORE_SIGNAL hook on error.
969 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
970 starting. For exception dispatching, pass PC instead of NULL_CIA.
971 (decode_coproc): Use COP0_BADVADDR to store faulting address.
972 * sim-main.h (COP0_BADVADDR): Define.
973 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
974 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
975 (_sim_cpu): Add exc_* fields to store register value snapshots.
976 * mips.igen (*): Replace memory-related SignalException* calls
977 with references to SIM_CORE_SIGNAL hook.
979 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
981 * sim-main.c (*): Minor warning cleanups.
983 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
985 * m16.igen (DADDIU5): Correct type-o.
987 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
989 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
992 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
994 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
996 (interp.o): Add dependency on itable.h
997 (oengine.c, gencode): Delete remaining references.
998 (BUILT_SRC_FROM_GEN): Clean up.
1000 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1003 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1004 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1005 tmp-run-hack) : New.
1006 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1007 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1008 Drop the "64" qualifier to get the HACK generator working.
1009 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1010 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1011 qualifier to get the hack generator working.
1012 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1013 (DSLL): Use do_dsll.
1014 (DSLLV): Use do_dsllv.
1015 (DSRA): Use do_dsra.
1016 (DSRL): Use do_dsrl.
1017 (DSRLV): Use do_dsrlv.
1018 (BC1): Move *vr4100 to get the HACK generator working.
1019 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1020 get the HACK generator working.
1021 (MACC) Rename to get the HACK generator working.
1022 (DMACC,MACCS,DMACCS): Add the 64.
1024 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1026 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1027 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1029 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1031 * mips/interp.c (DEBUG): Cleanups.
1033 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1035 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1036 (tx3904sio_tickle): fflush after a stdout character output.
1038 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1040 * interp.c (sim_close): Uninstall modules.
1042 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1044 * sim-main.h, interp.c (sim_monitor): Change to global
1047 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1049 * configure.in (vr4100): Only include vr4100 instructions in
1051 * configure: Re-generate.
1052 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1054 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1056 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1057 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1060 * configure.in (sim_default_gen, sim_use_gen): Replace with
1062 (--enable-sim-igen): Delete config option. Always using IGEN.
1063 * configure: Re-generate.
1065 * Makefile.in (gencode): Kill, kill, kill.
1068 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1070 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1071 bit mips16 igen simulator.
1072 * configure: Re-generate.
1074 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1075 as part of vr4100 ISA.
1076 * vr.igen: Mark all instructions as 64 bit only.
1078 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1080 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1083 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1085 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1086 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1087 * configure: Re-generate.
1089 * m16.igen (BREAK): Define breakpoint instruction.
1090 (JALX32): Mark instruction as mips16 and not r3900.
1091 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1093 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1095 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1097 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1098 insn as a debug breakpoint.
1100 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1102 (PENDING_SCHED): Clean up trace statement.
1103 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1104 (PENDING_FILL): Delay write by only one cycle.
1105 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1107 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1109 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1111 (pending_tick): Move incrementing of index to FOR statement.
1112 (pending_tick): Only update PENDING_OUT after a write has occured.
1114 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1116 * configure: Re-generate.
1118 * interp.c (sim_engine_run OLD): Delete explicit call to
1119 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1121 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1123 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1124 interrupt level number to match changed SignalExceptionInterrupt
1127 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1129 * interp.c: #include "itable.h" if WITH_IGEN.
1130 (get_insn_name): New function.
1131 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1132 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1134 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1136 * configure: Rebuilt to inhale new common/aclocal.m4.
1138 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1140 * dv-tx3904sio.c: Include sim-assert.h.
1142 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1144 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1145 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1146 Reorganize target-specific sim-hardware checks.
1147 * configure: rebuilt.
1148 * interp.c (sim_open): For tx39 target boards, set
1149 OPERATING_ENVIRONMENT, add tx3904sio devices.
1150 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1151 ROM executables. Install dv-sockser into sim-modules list.
1153 * dv-tx3904irc.c: Compiler warning clean-up.
1154 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1155 frequent hw-trace messages.
1157 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1159 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1161 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1163 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1165 * vr.igen: New file.
1166 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1167 * mips.igen: Define vr4100 model. Include vr.igen.
1168 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1170 * mips.igen (check_mf_hilo): Correct check.
1172 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1174 * sim-main.h (interrupt_event): Add prototype.
1176 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1177 register_ptr, register_value.
1178 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1180 * sim-main.h (tracefh): Make extern.
1182 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1184 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1185 Reduce unnecessarily high timer event frequency.
1186 * dv-tx3904cpu.c: Ditto for interrupt event.
1188 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1190 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1192 (interrupt_event): Made non-static.
1194 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1195 interchange of configuration values for external vs. internal
1198 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1200 * mips.igen (BREAK): Moved code to here for
1201 simulator-reserved break instructions.
1202 * gencode.c (build_instruction): Ditto.
1203 * interp.c (signal_exception): Code moved from here. Non-
1204 reserved instructions now use exception vector, rather
1206 * sim-main.h: Moved magic constants to here.
1208 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1210 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1211 register upon non-zero interrupt event level, clear upon zero
1213 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1214 by passing zero event value.
1215 (*_io_{read,write}_buffer): Endianness fixes.
1216 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1217 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1219 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1220 serial I/O and timer module at base address 0xFFFF0000.
1222 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1224 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1227 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1229 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1231 * configure: Update.
1233 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1235 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1236 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1237 * configure.in: Include tx3904tmr in hw_device list.
1238 * configure: Rebuilt.
1239 * interp.c (sim_open): Instantiate three timer instances.
1240 Fix address typo of tx3904irc instance.
1242 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1244 * interp.c (signal_exception): SystemCall exception now uses
1245 the exception vector.
1247 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1249 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1252 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1254 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1256 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1258 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1260 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1261 sim-main.h. Declare a struct hw_descriptor instead of struct
1262 hw_device_descriptor.
1264 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1266 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1267 right bits and then re-align left hand bytes to correct byte
1268 lanes. Fix incorrect computation in do_store_left when loading
1269 bytes from second word.
1271 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1273 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1274 * interp.c (sim_open): Only create a device tree when HW is
1277 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1278 * interp.c (signal_exception): Ditto.
1280 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1282 * gencode.c: Mark BEGEZALL as LIKELY.
1284 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1286 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1287 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1289 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1291 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1292 modules. Recognize TX39 target with "mips*tx39" pattern.
1293 * configure: Rebuilt.
1294 * sim-main.h (*): Added many macros defining bits in
1295 TX39 control registers.
1296 (SignalInterrupt): Send actual PC instead of NULL.
1297 (SignalNMIReset): New exception type.
1298 * interp.c (board): New variable for future use to identify
1299 a particular board being simulated.
1300 (mips_option_handler,mips_options): Added "--board" option.
1301 (interrupt_event): Send actual PC.
1302 (sim_open): Make memory layout conditional on board setting.
1303 (signal_exception): Initial implementation of hardware interrupt
1304 handling. Accept another break instruction variant for simulator
1306 (decode_coproc): Implement RFE instruction for TX39.
1307 (mips.igen): Decode RFE instruction as such.
1308 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1309 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1310 bbegin to implement memory map.
1311 * dv-tx3904cpu.c: New file.
1312 * dv-tx3904irc.c: New file.
1314 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1316 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1318 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1320 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1321 with calls to check_div_hilo.
1323 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1325 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1326 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1327 Add special r3900 version of do_mult_hilo.
1328 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1329 with calls to check_mult_hilo.
1330 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1331 with calls to check_div_hilo.
1333 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1335 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1336 Document a replacement.
1338 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1340 * interp.c (sim_monitor): Make mon_printf work.
1342 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1344 * sim-main.h (INSN_NAME): New arg `cpu'.
1346 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1348 * configure: Regenerated to track ../common/aclocal.m4 changes.
1350 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1352 * configure: Regenerated to track ../common/aclocal.m4 changes.
1355 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1357 * acconfig.h: New file.
1358 * configure.in: Reverted change of Apr 24; use sinclude again.
1360 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1362 * configure: Regenerated to track ../common/aclocal.m4 changes.
1365 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1367 * configure.in: Don't call sinclude.
1369 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1371 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1373 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1375 * mips.igen (ERET): Implement.
1377 * interp.c (decode_coproc): Return sign-extended EPC.
1379 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1381 * interp.c (signal_exception): Do not ignore Trap.
1382 (signal_exception): On TRAP, restart at exception address.
1383 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1384 (signal_exception): Update.
1385 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1386 so that TRAP instructions are caught.
1388 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1390 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1391 contains HI/LO access history.
1392 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1393 (HIACCESS, LOACCESS): Delete, replace with
1394 (HIHISTORY, LOHISTORY): New macros.
1395 (CHECKHILO): Delete all, moved to mips.igen
1397 * gencode.c (build_instruction): Do not generate checks for
1398 correct HI/LO register usage.
1400 * interp.c (old_engine_run): Delete checks for correct HI/LO
1403 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1404 check_mf_cycles): New functions.
1405 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1406 do_divu, domultx, do_mult, do_multu): Use.
1408 * tx.igen ("madd", "maddu"): Use.
1410 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1412 * mips.igen (DSRAV): Use function do_dsrav.
1413 (SRAV): Use new function do_srav.
1415 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1416 (B): Sign extend 11 bit immediate.
1417 (EXT-B*): Shift 16 bit immediate left by 1.
1418 (ADDIU*): Don't sign extend immediate value.
1420 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1422 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1424 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1427 * mips.igen (delayslot32, nullify_next_insn): New functions.
1428 (m16.igen): Always include.
1429 (do_*): Add more tracing.
1431 * m16.igen (delayslot16): Add NIA argument, could be called by a
1432 32 bit MIPS16 instruction.
1434 * interp.c (ifetch16): Move function from here.
1435 * sim-main.c (ifetch16): To here.
1437 * sim-main.c (ifetch16, ifetch32): Update to match current
1438 implementations of LH, LW.
1439 (signal_exception): Don't print out incorrect hex value of illegal
1442 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1444 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1447 * m16.igen: Implement MIPS16 instructions.
1449 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1450 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1451 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1452 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1453 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1454 bodies of corresponding code from 32 bit insn to these. Also used
1455 by MIPS16 versions of functions.
1457 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1458 (IMEM16): Drop NR argument from macro.
1460 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1462 * Makefile.in (SIM_OBJS): Add sim-main.o.
1464 * sim-main.h (address_translation, load_memory, store_memory,
1465 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1467 (pr_addr, pr_uword64): Declare.
1468 (sim-main.c): Include when H_REVEALS_MODULE_P.
1470 * interp.c (address_translation, load_memory, store_memory,
1471 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1473 * sim-main.c: To here. Fix compilation problems.
1475 * configure.in: Enable inlining.
1476 * configure: Re-config.
1478 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1480 * configure: Regenerated to track ../common/aclocal.m4 changes.
1482 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1484 * mips.igen: Include tx.igen.
1485 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1486 * tx.igen: New file, contains MADD and MADDU.
1488 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1489 the hardwired constant `7'.
1490 (store_memory): Ditto.
1491 (LOADDRMASK): Move definition to sim-main.h.
1493 mips.igen (MTC0): Enable for r3900.
1496 mips.igen (do_load_byte): Delete.
1497 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1498 do_store_right): New functions.
1499 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1501 configure.in: Let the tx39 use igen again.
1504 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1506 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1507 not an address sized quantity. Return zero for cache sizes.
1509 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1511 * mips.igen (r3900): r3900 does not support 64 bit integer
1514 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1516 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1518 * configure : Rebuild.
1520 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1522 * configure: Regenerated to track ../common/aclocal.m4 changes.
1524 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1526 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1528 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1530 * configure: Regenerated to track ../common/aclocal.m4 changes.
1531 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1533 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1535 * configure: Regenerated to track ../common/aclocal.m4 changes.
1537 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1539 * interp.c (Max, Min): Comment out functions. Not yet used.
1541 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1543 * configure: Regenerated to track ../common/aclocal.m4 changes.
1545 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1547 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1548 configurable settings for stand-alone simulator.
1550 * configure.in: Added X11 search, just in case.
1552 * configure: Regenerated.
1554 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1556 * interp.c (sim_write, sim_read, load_memory, store_memory):
1557 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1559 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1561 * sim-main.h (GETFCC): Return an unsigned value.
1563 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1565 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1566 (DADD): Result destination is RD not RT.
1568 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1570 * sim-main.h (HIACCESS, LOACCESS): Always define.
1572 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1574 * interp.c (sim_info): Delete.
1576 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1578 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1579 (mips_option_handler): New argument `cpu'.
1580 (sim_open): Update call to sim_add_option_table.
1582 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1584 * mips.igen (CxC1): Add tracing.
1586 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1588 * sim-main.h (Max, Min): Declare.
1590 * interp.c (Max, Min): New functions.
1592 * mips.igen (BC1): Add tracing.
1594 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1596 * interp.c Added memory map for stack in vr4100
1598 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1600 * interp.c (load_memory): Add missing "break"'s.
1602 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1604 * interp.c (sim_store_register, sim_fetch_register): Pass in
1605 length parameter. Return -1.
1607 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1609 * interp.c: Added hardware init hook, fixed warnings.
1611 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1613 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1615 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1617 * interp.c (ifetch16): New function.
1619 * sim-main.h (IMEM32): Rename IMEM.
1620 (IMEM16_IMMED): Define.
1622 (DELAY_SLOT): Update.
1624 * m16run.c (sim_engine_run): New file.
1626 * m16.igen: All instructions except LB.
1627 (LB): Call do_load_byte.
1628 * mips.igen (do_load_byte): New function.
1629 (LB): Call do_load_byte.
1631 * mips.igen: Move spec for insn bit size and high bit from here.
1632 * Makefile.in (tmp-igen, tmp-m16): To here.
1634 * m16.dc: New file, decode mips16 instructions.
1636 * Makefile.in (SIM_NO_ALL): Define.
1637 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1639 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1641 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1642 point unit to 32 bit registers.
1643 * configure: Re-generate.
1645 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1647 * configure.in (sim_use_gen): Make IGEN the default simulator
1648 generator for generic 32 and 64 bit mips targets.
1649 * configure: Re-generate.
1651 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1653 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1656 * interp.c (sim_fetch_register, sim_store_register): Read/write
1657 FGR from correct location.
1658 (sim_open): Set size of FGR's according to
1659 WITH_TARGET_FLOATING_POINT_BITSIZE.
1661 * sim-main.h (FGR): Store floating point registers in a separate
1664 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1666 * configure: Regenerated to track ../common/aclocal.m4 changes.
1668 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1670 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1672 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1674 * interp.c (pending_tick): New function. Deliver pending writes.
1676 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1677 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1678 it can handle mixed sized quantites and single bits.
1680 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1682 * interp.c (oengine.h): Do not include when building with IGEN.
1683 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1684 (sim_info): Ditto for PROCESSOR_64BIT.
1685 (sim_monitor): Replace ut_reg with unsigned_word.
1686 (*): Ditto for t_reg.
1687 (LOADDRMASK): Define.
1688 (sim_open): Remove defunct check that host FP is IEEE compliant,
1689 using software to emulate floating point.
1690 (value_fpr, ...): Always compile, was conditional on HASFPU.
1692 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1694 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1697 * interp.c (SD, CPU): Define.
1698 (mips_option_handler): Set flags in each CPU.
1699 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1700 (sim_close): Do not clear STATE, deleted anyway.
1701 (sim_write, sim_read): Assume CPU zero's vm should be used for
1703 (sim_create_inferior): Set the PC for all processors.
1704 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1706 (mips16_entry): Pass correct nr of args to store_word, load_word.
1707 (ColdReset): Cold reset all cpu's.
1708 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1709 (sim_monitor, load_memory, store_memory, signal_exception): Use
1710 `CPU' instead of STATE_CPU.
1713 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1716 * sim-main.h (signal_exception): Add sim_cpu arg.
1717 (SignalException*): Pass both SD and CPU to signal_exception.
1718 * interp.c (signal_exception): Update.
1720 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1722 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1723 address_translation): Ditto
1724 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1726 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1728 * configure: Regenerated to track ../common/aclocal.m4 changes.
1730 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1732 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1734 * mips.igen (model): Map processor names onto BFD name.
1736 * sim-main.h (CPU_CIA): Delete.
1737 (SET_CIA, GET_CIA): Define
1739 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1741 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1744 * configure.in (default_endian): Configure a big-endian simulator
1746 * configure: Re-generate.
1748 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1750 * configure: Regenerated to track ../common/aclocal.m4 changes.
1752 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1754 * interp.c (sim_monitor): Handle Densan monitor outbyte
1755 and inbyte functions.
1757 1997-12-29 Felix Lee <flee@cygnus.com>
1759 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1761 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1763 * Makefile.in (tmp-igen): Arrange for $zero to always be
1764 reset to zero after every instruction.
1766 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1768 * configure: Regenerated to track ../common/aclocal.m4 changes.
1771 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1773 * mips.igen (MSUB): Fix to work like MADD.
1774 * gencode.c (MSUB): Similarly.
1776 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1778 * configure: Regenerated to track ../common/aclocal.m4 changes.
1780 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1782 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1784 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1786 * sim-main.h (sim-fpu.h): Include.
1788 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1789 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1790 using host independant sim_fpu module.
1792 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1794 * interp.c (signal_exception): Report internal errors with SIGABRT
1797 * sim-main.h (C0_CONFIG): New register.
1798 (signal.h): No longer include.
1800 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1802 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1804 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1806 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1808 * mips.igen: Tag vr5000 instructions.
1809 (ANDI): Was missing mipsIV model, fix assembler syntax.
1810 (do_c_cond_fmt): New function.
1811 (C.cond.fmt): Handle mips I-III which do not support CC field
1813 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1814 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1816 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1817 vr5000 which saves LO in a GPR separatly.
1819 * configure.in (enable-sim-igen): For vr5000, select vr5000
1820 specific instructions.
1821 * configure: Re-generate.
1823 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1825 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1827 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1828 fmt_uninterpreted_64 bit cases to switch. Convert to
1831 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1833 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1834 as specified in IV3.2 spec.
1835 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1837 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1839 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1840 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1841 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1842 PENDING_FILL versions of instructions. Simplify.
1844 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1846 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1848 (MTHI, MFHI): Disable code checking HI-LO.
1850 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1852 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1854 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1856 * gencode.c (build_mips16_operands): Replace IPC with cia.
1858 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1859 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1861 (UndefinedResult): Replace function with macro/function
1863 (sim_engine_run): Don't save PC in IPC.
1865 * sim-main.h (IPC): Delete.
1868 * interp.c (signal_exception, store_word, load_word,
1869 address_translation, load_memory, store_memory, cache_op,
1870 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1871 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1872 current instruction address - cia - argument.
1873 (sim_read, sim_write): Call address_translation directly.
1874 (sim_engine_run): Rename variable vaddr to cia.
1875 (signal_exception): Pass cia to sim_monitor
1877 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1878 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1879 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1881 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1882 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1885 * interp.c (signal_exception): Pass restart address to
1888 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1889 idecode.o): Add dependency.
1891 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1893 (DELAY_SLOT): Update NIA not PC with branch address.
1894 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1896 * mips.igen: Use CIA not PC in branch calculations.
1897 (illegal): Call SignalException.
1898 (BEQ, ADDIU): Fix assembler.
1900 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1902 * m16.igen (JALX): Was missing.
1904 * configure.in (enable-sim-igen): New configuration option.
1905 * configure: Re-generate.
1907 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1909 * interp.c (load_memory, store_memory): Delete parameter RAW.
1910 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1911 bypassing {load,store}_memory.
1913 * sim-main.h (ByteSwapMem): Delete definition.
1915 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1917 * interp.c (sim_do_command, sim_commands): Delete mips specific
1918 commands. Handled by module sim-options.
1920 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1921 (WITH_MODULO_MEMORY): Define.
1923 * interp.c (sim_info): Delete code printing memory size.
1925 * interp.c (mips_size): Nee sim_size, delete function.
1927 (monitor, monitor_base, monitor_size): Delete global variables.
1928 (sim_open, sim_close): Delete code creating monitor and other
1929 memory regions. Use sim-memopts module, via sim_do_commandf, to
1930 manage memory regions.
1931 (load_memory, store_memory): Use sim-core for memory model.
1933 * interp.c (address_translation): Delete all memory map code
1934 except line forcing 32 bit addresses.
1936 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1938 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1941 * interp.c (logfh, logfile): Delete globals.
1942 (sim_open, sim_close): Delete code opening & closing log file.
1943 (mips_option_handler): Delete -l and -n options.
1944 (OPTION mips_options): Ditto.
1946 * interp.c (OPTION mips_options): Rename option trace to dinero.
1947 (mips_option_handler): Update.
1949 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1951 * interp.c (fetch_str): New function.
1952 (sim_monitor): Rewrite using sim_read & sim_write.
1953 (sim_open): Check magic number.
1954 (sim_open): Write monitor vectors into memory using sim_write.
1955 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1956 (sim_read, sim_write): Simplify - transfer data one byte at a
1958 (load_memory, store_memory): Clarify meaning of parameter RAW.
1960 * sim-main.h (isHOST): Defete definition.
1961 (isTARGET): Mark as depreciated.
1962 (address_translation): Delete parameter HOST.
1964 * interp.c (address_translation): Delete parameter HOST.
1966 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1970 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1971 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1973 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1975 * mips.igen: Add model filter field to records.
1977 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1979 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1981 interp.c (sim_engine_run): Do not compile function sim_engine_run
1982 when WITH_IGEN == 1.
1984 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1985 target architecture.
1987 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1988 igen. Replace with configuration variables sim_igen_flags /
1991 * m16.igen: New file. Copy mips16 insns here.
1992 * mips.igen: From here.
1994 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1996 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1998 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2000 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2002 * gencode.c (build_instruction): Follow sim_write's lead in using
2003 BigEndianMem instead of !ByteSwapMem.
2005 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2007 * configure.in (sim_gen): Dependent on target, select type of
2008 generator. Always select old style generator.
2010 configure: Re-generate.
2012 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2014 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2015 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2016 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2017 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2018 SIM_@sim_gen@_*, set by autoconf.
2020 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2022 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2024 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2025 CURRENT_FLOATING_POINT instead.
2027 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2028 (address_translation): Raise exception InstructionFetch when
2029 translation fails and isINSTRUCTION.
2031 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2032 sim_engine_run): Change type of of vaddr and paddr to
2034 (address_translation, prefetch, load_memory, store_memory,
2035 cache_op): Change type of vAddr and pAddr to address_word.
2037 * gencode.c (build_instruction): Change type of vaddr and paddr to
2040 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2042 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2043 macro to obtain result of ALU op.
2045 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2047 * interp.c (sim_info): Call profile_print.
2049 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2051 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2053 * sim-main.h (WITH_PROFILE): Do not define, defined in
2054 common/sim-config.h. Use sim-profile module.
2055 (simPROFILE): Delete defintion.
2057 * interp.c (PROFILE): Delete definition.
2058 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2059 (sim_close): Delete code writing profile histogram.
2060 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2062 (sim_engine_run): Delete code profiling the PC.
2064 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2066 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2068 * interp.c (sim_monitor): Make register pointers of type
2071 * sim-main.h: Make registers of type unsigned_word not
2074 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2076 * interp.c (sync_operation): Rename from SyncOperation, make
2077 global, add SD argument.
2078 (prefetch): Rename from Prefetch, make global, add SD argument.
2079 (decode_coproc): Make global.
2081 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2083 * gencode.c (build_instruction): Generate DecodeCoproc not
2084 decode_coproc calls.
2086 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2087 (SizeFGR): Move to sim-main.h
2088 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2089 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2090 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2092 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2093 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2094 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2095 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2096 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2097 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2099 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2101 (sim-alu.h): Include.
2102 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2103 (sim_cia): Typedef to instruction_address.
2105 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2107 * Makefile.in (interp.o): Rename generated file engine.c to
2112 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2114 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2116 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2118 * gencode.c (build_instruction): For "FPSQRT", output correct
2119 number of arguments to Recip.
2121 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2123 * Makefile.in (interp.o): Depends on sim-main.h
2125 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2127 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2128 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2129 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2130 STATE, DSSTATE): Define
2131 (GPR, FGRIDX, ..): Define.
2133 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2134 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2135 (GPR, FGRIDX, ...): Delete macros.
2137 * interp.c: Update names to match defines from sim-main.h
2139 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2141 * interp.c (sim_monitor): Add SD argument.
2142 (sim_warning): Delete. Replace calls with calls to
2144 (sim_error): Delete. Replace calls with sim_io_error.
2145 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2146 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2147 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2149 (mips_size): Rename from sim_size. Add SD argument.
2151 * interp.c (simulator): Delete global variable.
2152 (callback): Delete global variable.
2153 (mips_option_handler, sim_open, sim_write, sim_read,
2154 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2155 sim_size,sim_monitor): Use sim_io_* not callback->*.
2156 (sim_open): ZALLOC simulator struct.
2157 (PROFILE): Do not define.
2159 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2161 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2162 support.h with corresponding code.
2164 * sim-main.h (word64, uword64), support.h: Move definition to
2166 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2169 * Makefile.in: Update dependencies
2170 * interp.c: Do not include.
2172 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2174 * interp.c (address_translation, load_memory, store_memory,
2175 cache_op): Rename to from AddressTranslation et.al., make global,
2178 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2181 * interp.c (SignalException): Rename to signal_exception, make
2184 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2186 * sim-main.h (SignalException, SignalExceptionInterrupt,
2187 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2188 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2189 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2192 * interp.c, support.h: Use.
2194 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2196 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2197 to value_fpr / store_fpr. Add SD argument.
2198 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2199 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2201 * sim-main.h (ValueFPR, StoreFPR): Define.
2203 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2205 * interp.c (sim_engine_run): Check consistency between configure
2206 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2209 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2210 (mips_fpu): Configure WITH_FLOATING_POINT.
2211 (mips_endian): Configure WITH_TARGET_ENDIAN.
2212 * configure: Update.
2214 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2216 * configure: Regenerated to track ../common/aclocal.m4 changes.
2218 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2220 * configure: Regenerated.
2222 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2224 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2226 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2228 * gencode.c (print_igen_insn_models): Assume certain architectures
2229 include all mips* instructions.
2230 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2233 * Makefile.in (tmp.igen): Add target. Generate igen input from
2236 * gencode.c (FEATURE_IGEN): Define.
2237 (main): Add --igen option. Generate output in igen format.
2238 (process_instructions): Format output according to igen option.
2239 (print_igen_insn_format): New function.
2240 (print_igen_insn_models): New function.
2241 (process_instructions): Only issue warnings and ignore
2242 instructions when no FEATURE_IGEN.
2244 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2246 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2249 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2251 * configure: Regenerated to track ../common/aclocal.m4 changes.
2253 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2255 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2256 SIM_RESERVED_BITS): Delete, moved to common.
2257 (SIM_EXTRA_CFLAGS): Update.
2259 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2261 * configure.in: Configure non-strict memory alignment.
2262 * configure: Regenerated to track ../common/aclocal.m4 changes.
2264 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2266 * configure: Regenerated to track ../common/aclocal.m4 changes.
2268 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2270 * gencode.c (SDBBP,DERET): Added (3900) insns.
2271 (RFE): Turn on for 3900.
2272 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2273 (dsstate): Made global.
2274 (SUBTARGET_R3900): Added.
2275 (CANCELDELAYSLOT): New.
2276 (SignalException): Ignore SystemCall rather than ignore and
2277 terminate. Add DebugBreakPoint handling.
2278 (decode_coproc): New insns RFE, DERET; and new registers Debug
2279 and DEPC protected by SUBTARGET_R3900.
2280 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2282 * Makefile.in,configure.in: Add mips subtarget option.
2283 * configure: Update.
2285 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2287 * gencode.c: Add r3900 (tx39).
2290 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2292 * gencode.c (build_instruction): Don't need to subtract 4 for
2295 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2297 * interp.c: Correct some HASFPU problems.
2299 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301 * configure: Regenerated to track ../common/aclocal.m4 changes.
2303 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2305 * interp.c (mips_options): Fix samples option short form, should
2308 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2310 * interp.c (sim_info): Enable info code. Was just returning.
2312 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2314 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2317 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2319 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2321 (build_instruction): Ditto for LL.
2323 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2325 * configure: Regenerated to track ../common/aclocal.m4 changes.
2327 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2329 * configure: Regenerated to track ../common/aclocal.m4 changes.
2332 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2334 * interp.c (sim_open): Add call to sim_analyze_program, update
2337 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2339 * interp.c (sim_kill): Delete.
2340 (sim_create_inferior): Add ABFD argument. Set PC from same.
2341 (sim_load): Move code initializing trap handlers from here.
2342 (sim_open): To here.
2343 (sim_load): Delete, use sim-hload.c.
2345 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2347 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2349 * configure: Regenerated to track ../common/aclocal.m4 changes.
2352 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2354 * interp.c (sim_open): Add ABFD argument.
2355 (sim_load): Move call to sim_config from here.
2356 (sim_open): To here. Check return status.
2358 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2360 * gencode.c (build_instruction): Two arg MADD should
2361 not assign result to $0.
2363 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2365 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2366 * sim/mips/configure.in: Regenerate.
2368 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2370 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2371 signed8, unsigned8 et.al. types.
2373 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2374 hosts when selecting subreg.
2376 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2378 * interp.c (sim_engine_run): Reset the ZERO register to zero
2379 regardless of FEATURE_WARN_ZERO.
2380 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2382 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2384 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2385 (SignalException): For BreakPoints ignore any mode bits and just
2387 (SignalException): Always set the CAUSE register.
2389 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2391 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2392 exception has been taken.
2394 * interp.c: Implement the ERET and mt/f sr instructions.
2396 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2398 * interp.c (SignalException): Don't bother restarting an
2401 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2403 * interp.c (SignalException): Really take an interrupt.
2404 (interrupt_event): Only deliver interrupts when enabled.
2406 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2408 * interp.c (sim_info): Only print info when verbose.
2409 (sim_info) Use sim_io_printf for output.
2411 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2413 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2416 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2418 * interp.c (sim_do_command): Check for common commands if a
2419 simulator specific command fails.
2421 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2423 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2424 and simBE when DEBUG is defined.
2426 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2428 * interp.c (interrupt_event): New function. Pass exception event
2429 onto exception handler.
2431 * configure.in: Check for stdlib.h.
2432 * configure: Regenerate.
2434 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2435 variable declaration.
2436 (build_instruction): Initialize memval1.
2437 (build_instruction): Add UNUSED attribute to byte, bigend,
2439 (build_operands): Ditto.
2441 * interp.c: Fix GCC warnings.
2442 (sim_get_quit_code): Delete.
2444 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2445 * Makefile.in: Ditto.
2446 * configure: Re-generate.
2448 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2450 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2452 * interp.c (mips_option_handler): New function parse argumes using
2454 (myname): Replace with STATE_MY_NAME.
2455 (sim_open): Delete check for host endianness - performed by
2457 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2458 (sim_open): Move much of the initialization from here.
2459 (sim_load): To here. After the image has been loaded and
2461 (sim_open): Move ColdReset from here.
2462 (sim_create_inferior): To here.
2463 (sim_open): Make FP check less dependant on host endianness.
2465 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2467 * interp.c (sim_set_callbacks): Delete.
2469 * interp.c (membank, membank_base, membank_size): Replace with
2470 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2471 (sim_open): Remove call to callback->init. gdb/run do this.
2475 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2477 * interp.c (big_endian_p): Delete, replaced by
2478 current_target_byte_order.
2480 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2482 * interp.c (host_read_long, host_read_word, host_swap_word,
2483 host_swap_long): Delete. Using common sim-endian.
2484 (sim_fetch_register, sim_store_register): Use H2T.
2485 (pipeline_ticks): Delete. Handled by sim-events.
2487 (sim_engine_run): Update.
2489 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2491 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2493 (SignalException): To here. Signal using sim_engine_halt.
2494 (sim_stop_reason): Delete, moved to common.
2496 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2498 * interp.c (sim_open): Add callback argument.
2499 (sim_set_callbacks): Delete SIM_DESC argument.
2502 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2504 * Makefile.in (SIM_OBJS): Add common modules.
2506 * interp.c (sim_set_callbacks): Also set SD callback.
2507 (set_endianness, xfer_*, swap_*): Delete.
2508 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2509 Change to functions using sim-endian macros.
2510 (control_c, sim_stop): Delete, use common version.
2511 (simulate): Convert into.
2512 (sim_engine_run): This function.
2513 (sim_resume): Delete.
2515 * interp.c (simulation): New variable - the simulator object.
2516 (sim_kind): Delete global - merged into simulation.
2517 (sim_load): Cleanup. Move PC assignment from here.
2518 (sim_create_inferior): To here.
2520 * sim-main.h: New file.
2521 * interp.c (sim-main.h): Include.
2523 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2525 * configure: Regenerated to track ../common/aclocal.m4 changes.
2527 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2529 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2531 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2533 * gencode.c (build_instruction): DIV instructions: check
2534 for division by zero and integer overflow before using
2535 host's division operation.
2537 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2539 * Makefile.in (SIM_OBJS): Add sim-load.o.
2540 * interp.c: #include bfd.h.
2541 (target_byte_order): Delete.
2542 (sim_kind, myname, big_endian_p): New static locals.
2543 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2544 after argument parsing. Recognize -E arg, set endianness accordingly.
2545 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2546 load file into simulator. Set PC from bfd.
2547 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2548 (set_endianness): Use big_endian_p instead of target_byte_order.
2550 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2552 * interp.c (sim_size): Delete prototype - conflicts with
2553 definition in remote-sim.h. Correct definition.
2555 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2557 * configure: Regenerated to track ../common/aclocal.m4 changes.
2560 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2562 * interp.c (sim_open): New arg `kind'.
2564 * configure: Regenerated to track ../common/aclocal.m4 changes.
2566 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2568 * configure: Regenerated to track ../common/aclocal.m4 changes.
2570 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2572 * interp.c (sim_open): Set optind to 0 before calling getopt.
2574 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2576 * configure: Regenerated to track ../common/aclocal.m4 changes.
2578 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2580 * interp.c : Replace uses of pr_addr with pr_uword64
2581 where the bit length is always 64 independent of SIM_ADDR.
2582 (pr_uword64) : added.
2584 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2586 * configure: Re-generate.
2588 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2590 * configure: Regenerate to track ../common/aclocal.m4 changes.
2592 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2594 * interp.c (sim_open): New SIM_DESC result. Argument is now
2596 (other sim_*): New SIM_DESC argument.
2598 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2600 * interp.c: Fix printing of addresses for non-64-bit targets.
2601 (pr_addr): Add function to print address based on size.
2603 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2605 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2607 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2609 * gencode.c (build_mips16_operands): Correct computation of base
2610 address for extended PC relative instruction.
2612 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2614 * interp.c (mips16_entry): Add support for floating point cases.
2615 (SignalException): Pass floating point cases to mips16_entry.
2616 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2618 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2620 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2621 and then set the state to fmt_uninterpreted.
2622 (COP_SW): Temporarily set the state to fmt_word while calling
2625 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2627 * gencode.c (build_instruction): The high order may be set in the
2628 comparison flags at any ISA level, not just ISA 4.
2630 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2632 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2633 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2634 * configure.in: sinclude ../common/aclocal.m4.
2635 * configure: Regenerated.
2637 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2639 * configure: Rebuild after change to aclocal.m4.
2641 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2643 * configure configure.in Makefile.in: Update to new configure
2644 scheme which is more compatible with WinGDB builds.
2645 * configure.in: Improve comment on how to run autoconf.
2646 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2647 * Makefile.in: Use autoconf substitution to install common
2650 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2652 * gencode.c (build_instruction): Use BigEndianCPU instead of
2655 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2657 * interp.c (sim_monitor): Make output to stdout visible in
2658 wingdb's I/O log window.
2660 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2662 * support.h: Undo previous change to SIGTRAP
2665 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2667 * interp.c (store_word, load_word): New static functions.
2668 (mips16_entry): New static function.
2669 (SignalException): Look for mips16 entry and exit instructions.
2670 (simulate): Use the correct index when setting fpr_state after
2671 doing a pending move.
2673 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2675 * interp.c: Fix byte-swapping code throughout to work on
2676 both little- and big-endian hosts.
2678 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2680 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2681 with gdb/config/i386/xm-windows.h.
2683 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2685 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2686 that messes up arithmetic shifts.
2688 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2690 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2691 SIGTRAP and SIGQUIT for _WIN32.
2693 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2695 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2696 force a 64 bit multiplication.
2697 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2698 destination register is 0, since that is the default mips16 nop
2701 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2703 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2704 (build_endian_shift): Don't check proc64.
2705 (build_instruction): Always set memval to uword64. Cast op2 to
2706 uword64 when shifting it left in memory instructions. Always use
2707 the same code for stores--don't special case proc64.
2709 * gencode.c (build_mips16_operands): Fix base PC value for PC
2711 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2713 * interp.c (simJALDELAYSLOT): Define.
2714 (JALDELAYSLOT): Define.
2715 (INDELAYSLOT, INJALDELAYSLOT): Define.
2716 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2718 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2720 * interp.c (sim_open): add flush_cache as a PMON routine
2721 (sim_monitor): handle flush_cache by ignoring it
2723 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2725 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2727 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2728 (BigEndianMem): Rename to ByteSwapMem and change sense.
2729 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2730 BigEndianMem references to !ByteSwapMem.
2731 (set_endianness): New function, with prototype.
2732 (sim_open): Call set_endianness.
2733 (sim_info): Use simBE instead of BigEndianMem.
2734 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2735 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2736 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2737 ifdefs, keeping the prototype declaration.
2738 (swap_word): Rewrite correctly.
2739 (ColdReset): Delete references to CONFIG. Delete endianness related
2740 code; moved to set_endianness.
2742 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2744 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2745 * interp.c (CHECKHILO): Define away.
2746 (simSIGINT): New macro.
2747 (membank_size): Increase from 1MB to 2MB.
2748 (control_c): New function.
2749 (sim_resume): Rename parameter signal to signal_number. Add local
2750 variable prev. Call signal before and after simulate.
2751 (sim_stop_reason): Add simSIGINT support.
2752 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2754 (sim_warning): Delete call to SignalException. Do call printf_filtered
2756 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2757 a call to sim_warning.
2759 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2761 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2762 16 bit instructions.
2764 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2766 Add support for mips16 (16 bit MIPS implementation):
2767 * gencode.c (inst_type): Add mips16 instruction encoding types.
2768 (GETDATASIZEINSN): Define.
2769 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2770 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2772 (MIPS16_DECODE): New table, for mips16 instructions.
2773 (bitmap_val): New static function.
2774 (struct mips16_op): Define.
2775 (mips16_op_table): New table, for mips16 operands.
2776 (build_mips16_operands): New static function.
2777 (process_instructions): If PC is odd, decode a mips16
2778 instruction. Break out instruction handling into new
2779 build_instruction function.
2780 (build_instruction): New static function, broken out of
2781 process_instructions. Check modifiers rather than flags for SHIFT
2782 bit count and m[ft]{hi,lo} direction.
2783 (usage): Pass program name to fprintf.
2784 (main): Remove unused variable this_option_optind. Change
2785 ``*loptarg++'' to ``loptarg++''.
2786 (my_strtoul): Parenthesize && within ||.
2787 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2788 (simulate): If PC is odd, fetch a 16 bit instruction, and
2789 increment PC by 2 rather than 4.
2790 * configure.in: Add case for mips16*-*-*.
2791 * configure: Rebuild.
2793 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2795 * interp.c: Allow -t to enable tracing in standalone simulator.
2796 Fix garbage output in trace file and error messages.
2798 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2800 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2801 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2802 * configure.in: Simplify using macros in ../common/aclocal.m4.
2803 * configure: Regenerated.
2804 * tconfig.in: New file.
2806 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2808 * interp.c: Fix bugs in 64-bit port.
2809 Use ansi function declarations for msvc compiler.
2810 Initialize and test file pointer in trace code.
2811 Prevent duplicate definition of LAST_EMED_REGNUM.
2813 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2815 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2817 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2819 * interp.c (SignalException): Check for explicit terminating
2821 * gencode.c: Pass instruction value through SignalException()
2822 calls for Trap, Breakpoint and Syscall.
2824 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2826 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2827 only used on those hosts that provide it.
2828 * configure.in: Add sqrt() to list of functions to be checked for.
2829 * config.in: Re-generated.
2830 * configure: Re-generated.
2832 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2834 * gencode.c (process_instructions): Call build_endian_shift when
2835 expanding STORE RIGHT, to fix swr.
2836 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2837 clear the high bits.
2838 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2839 Fix float to int conversions to produce signed values.
2841 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2843 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2844 (process_instructions): Correct handling of nor instruction.
2845 Correct shift count for 32 bit shift instructions. Correct sign
2846 extension for arithmetic shifts to not shift the number of bits in
2847 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2848 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2850 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2851 It's OK to have a mult follow a mult. What's not OK is to have a
2852 mult follow an mfhi.
2853 (Convert): Comment out incorrect rounding code.
2855 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2857 * interp.c (sim_monitor): Improved monitor printf
2858 simulation. Tidied up simulator warnings, and added "--log" option
2859 for directing warning message output.
2860 * gencode.c: Use sim_warning() rather than WARNING macro.
2862 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2864 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2865 getopt1.o, rather than on gencode.c. Link objects together.
2866 Don't link against -liberty.
2867 (gencode.o, getopt.o, getopt1.o): New targets.
2868 * gencode.c: Include <ctype.h> and "ansidecl.h".
2869 (AND): Undefine after including "ansidecl.h".
2870 (ULONG_MAX): Define if not defined.
2871 (OP_*): Don't define macros; now defined in opcode/mips.h.
2872 (main): Call my_strtoul rather than strtoul.
2873 (my_strtoul): New static function.
2875 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2877 * gencode.c (process_instructions): Generate word64 and uword64
2878 instead of `long long' and `unsigned long long' data types.
2879 * interp.c: #include sysdep.h to get signals, and define default
2881 * (Convert): Work around for Visual-C++ compiler bug with type
2883 * support.h: Make things compile under Visual-C++ by using
2884 __int64 instead of `long long'. Change many refs to long long
2885 into word64/uword64 typedefs.
2887 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2889 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2890 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2892 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2893 (AC_PROG_INSTALL): Added.
2894 (AC_PROG_CC): Moved to before configure.host call.
2895 * configure: Rebuilt.
2897 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2899 * configure.in: Define @SIMCONF@ depending on mips target.
2900 * configure: Rebuild.
2901 * Makefile.in (run): Add @SIMCONF@ to control simulator
2903 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2904 * interp.c: Remove some debugging, provide more detailed error
2905 messages, update memory accesses to use LOADDRMASK.
2907 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2909 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2910 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2912 * configure: Rebuild.
2913 * config.in: New file, generated by autoheader.
2914 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2915 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2916 HAVE_ANINT and HAVE_AINT, as appropriate.
2917 * Makefile.in (run): Use @LIBS@ rather than -lm.
2918 (interp.o): Depend upon config.h.
2919 (Makefile): Just rebuild Makefile.
2920 (clean): Remove stamp-h.
2921 (mostlyclean): Make the same as clean, not as distclean.
2922 (config.h, stamp-h): New targets.
2924 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2926 * interp.c (ColdReset): Fix boolean test. Make all simulator
2929 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2931 * interp.c (xfer_direct_word, xfer_direct_long,
2932 swap_direct_word, swap_direct_long, xfer_big_word,
2933 xfer_big_long, xfer_little_word, xfer_little_long,
2934 swap_word,swap_long): Added.
2935 * interp.c (ColdReset): Provide function indirection to
2936 host<->simulated_target transfer routines.
2937 * interp.c (sim_store_register, sim_fetch_register): Updated to
2938 make use of indirected transfer routines.
2940 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2942 * gencode.c (process_instructions): Ensure FP ABS instruction
2944 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2945 system call support.
2947 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2949 * interp.c (sim_do_command): Complain if callback structure not
2952 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2954 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2955 support for Sun hosts.
2956 * Makefile.in (gencode): Ensure the host compiler and libraries
2957 used for cross-hosted build.
2959 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2961 * interp.c, gencode.c: Some more (TODO) tidying.
2963 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2965 * gencode.c, interp.c: Replaced explicit long long references with
2966 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2967 * support.h (SET64LO, SET64HI): Macros added.
2969 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2971 * configure: Regenerate with autoconf 2.7.
2973 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2975 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2976 * support.h: Remove superfluous "1" from #if.
2977 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2979 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2981 * interp.c (StoreFPR): Control UndefinedResult() call on
2982 WARN_RESULT manifest.
2984 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2986 * gencode.c: Tidied instruction decoding, and added FP instruction
2989 * interp.c: Added dineroIII, and BSD profiling support. Also
2990 run-time FP handling.
2992 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2994 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2995 gencode.c, interp.c, support.h: created.