1 2002-03-01 Chris Demetriou <cgd@broadcom.com>
3 * mips.igen (CACHE): Provide instruction-printing string.
5 * interp.c (signal_exception): Comment tokens after #endif.
7 2002-02-28 Chris Demetriou <cgd@broadcom.com>
9 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
10 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
11 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
12 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
13 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
14 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
15 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
16 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
18 2002-02-28 Chris Demetriou <cgd@broadcom.com>
20 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
21 instruction-printing string.
22 (LWU): Use '64' as the filter flag.
24 2002-02-28 Chris Demetriou <cgd@broadcom.com>
26 * mips.igen (SDXC1): Fix instruction-printing string.
28 2002-02-28 Chris Demetriou <cgd@broadcom.com>
30 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
33 2002-02-27 Chris Demetriou <cgd@broadcom.com>
35 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
38 2002-02-27 Chris Demetriou <cgd@broadcom.com>
40 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
41 add a comma) so that it more closely match the MIPS ISA
42 documentation opcode partitioning.
43 (PREF): Put useful names on opcode fields, and include
44 instruction-printing string.
46 2002-02-27 Chris Demetriou <cgd@broadcom.com>
48 * mips.igen (check_u64): New function which in the future will
49 check whether 64-bit instructions are usable and signal an
50 exception if not. Currently a no-op.
51 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
52 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
53 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
54 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
56 * mips.igen (check_fpu): New function which in the future will
57 check whether FPU instructions are usable and signal an exception
58 if not. Currently a no-op.
59 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
60 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
61 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
62 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
63 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
64 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
65 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
66 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
68 2002-02-27 Chris Demetriou <cgd@broadcom.com>
70 * mips.igen (do_load_left, do_load_right): Move to be immediately
72 (do_store_left, do_store_right): Move to be immediately following
75 2002-02-27 Chris Demetriou <cgd@broadcom.com>
77 * mips.igen (mipsV): New model name. Also, add it to
78 all instructions and functions where it is appropriate.
80 2002-02-18 Chris Demetriou <cgd@broadcom.com>
82 * mips.igen: For all functions and instructions, list model
83 names that support that instruction one per line.
85 2002-02-11 Chris Demetriou <cgd@broadcom.com>
87 * mips.igen: Add some additional comments about supported
88 models, and about which instructions go where.
89 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
90 order as is used in the rest of the file.
92 2002-02-11 Chris Demetriou <cgd@broadcom.com>
94 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
95 indicating that ALU32_END or ALU64_END are there to check
97 (DADD): Likewise, but also remove previous comment about
100 2002-02-10 Chris Demetriou <cgd@broadcom.com>
102 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
103 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
104 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
105 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
106 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
107 fields (i.e., add and move commas) so that they more closely
108 match the MIPS ISA documentation opcode partitioning.
110 2002-02-10 Chris Demetriou <cgd@broadcom.com>
112 * mips.igen (ADDI): Print immediate value.
114 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
115 (SLL): Print "nop" specially, and don't run the code
116 that does the shift for the "nop" case.
118 2001-11-17 Fred Fish <fnf@redhat.com>
120 * sim-main.h (float_operation): Move enum declaration outside
121 of _sim_cpu struct declaration.
123 2001-04-12 Jim Blandy <jimb@redhat.com>
125 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
126 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
128 * sim-main.h (COCIDX): Remove definition; this isn't supported by
129 PENDING_FILL, and you can get the intended effect gracefully by
130 calling PENDING_SCHED directly.
132 2001-02-23 Ben Elliston <bje@redhat.com>
134 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
135 already defined elsewhere.
137 2001-02-19 Ben Elliston <bje@redhat.com>
139 * sim-main.h (sim_monitor): Return an int.
140 * interp.c (sim_monitor): Add return values.
141 (signal_exception): Handle error conditions from sim_monitor.
143 2001-02-08 Ben Elliston <bje@redhat.com>
145 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
146 (store_memory): Likewise, pass cia to sim_core_write*.
148 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
150 On advice from Chris G. Demetriou <cgd@sibyte.com>:
151 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
153 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
155 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
156 * Makefile.in: Don't delete *.igen when cleaning directory.
158 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
160 * m16.igen (break): Call SignalException not sim_engine_halt.
162 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
165 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
167 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
169 * mips.igen (MxC1, DMxC1): Fix printf formatting.
171 2000-05-24 Michael Hayes <mhayes@cygnus.com>
173 * mips.igen (do_dmultx): Fix typo.
175 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
177 * configure: Regenerated to track ../common/aclocal.m4 changes.
179 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
181 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
183 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
185 * sim-main.h (GPR_CLEAR): Define macro.
187 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
189 * interp.c (decode_coproc): Output long using %lx and not %s.
191 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
193 * interp.c (sim_open): Sort & extend dummy memory regions for
194 --board=jmr3904 for eCos.
196 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
198 * configure: Regenerated.
200 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
202 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
203 calls, conditional on the simulator being in verbose mode.
205 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
207 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
208 cache don't get ReservedInstruction traps.
210 1999-11-29 Mark Salter <msalter@cygnus.com>
212 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
213 to clear status bits in sdisr register. This is how the hardware works.
215 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
216 being used by cygmon.
218 1999-11-11 Andrew Haley <aph@cygnus.com>
220 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
223 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
225 * mips.igen (MULT): Correct previous mis-applied patch.
227 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
229 * mips.igen (delayslot32): Handle sequence like
230 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
231 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
232 (MULT): Actually pass the third register...
234 1999-09-03 Mark Salter <msalter@cygnus.com>
236 * interp.c (sim_open): Added more memory aliases for additional
237 hardware being touched by cygmon on jmr3904 board.
239 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
241 * configure: Regenerated to track ../common/aclocal.m4 changes.
243 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
245 * interp.c (sim_store_register): Handle case where client - GDB -
246 specifies that a 4 byte register is 8 bytes in size.
247 (sim_fetch_register): Ditto.
249 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
251 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
252 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
253 (idt_monitor_base): Base address for IDT monitor traps.
254 (pmon_monitor_base): Ditto for PMON.
255 (lsipmon_monitor_base): Ditto for LSI PMON.
256 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
257 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
258 (sim_firmware_command): New function.
259 (mips_option_handler): Call it for OPTION_FIRMWARE.
260 (sim_open): Allocate memory for idt_monitor region. If "--board"
261 option was given, add no monitor by default. Add BREAK hooks only if
262 monitors are also there.
264 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
266 * interp.c (sim_monitor): Flush output before reading input.
268 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
270 * tconfig.in (SIM_HANDLES_LMA): Always define.
272 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
274 From Mark Salter <msalter@cygnus.com>:
275 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
276 (sim_open): Add setup for BSP board.
278 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
280 * mips.igen (MULT, MULTU): Add syntax for two operand version.
281 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
282 them as unimplemented.
284 1999-05-08 Felix Lee <flee@cygnus.com>
286 * configure: Regenerated to track ../common/aclocal.m4 changes.
288 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
290 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
292 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
294 * configure.in: Any mips64vr5*-*-* target should have
295 -DTARGET_ENABLE_FR=1.
296 (default_endian): Any mips64vr*el-*-* target should default to
298 * configure: Re-generate.
300 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
302 * mips.igen (ldl): Extend from _16_, not 32.
304 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
306 * interp.c (sim_store_register): Force registers written to by GDB
307 into an un-interpreted state.
309 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
311 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
312 CPU, start periodic background I/O polls.
313 (tx3904sio_poll): New function: periodic I/O poller.
315 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
317 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
319 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
321 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
324 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
326 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
327 (load_word): Call SIM_CORE_SIGNAL hook on error.
328 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
329 starting. For exception dispatching, pass PC instead of NULL_CIA.
330 (decode_coproc): Use COP0_BADVADDR to store faulting address.
331 * sim-main.h (COP0_BADVADDR): Define.
332 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
333 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
334 (_sim_cpu): Add exc_* fields to store register value snapshots.
335 * mips.igen (*): Replace memory-related SignalException* calls
336 with references to SIM_CORE_SIGNAL hook.
338 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
340 * sim-main.c (*): Minor warning cleanups.
342 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
344 * m16.igen (DADDIU5): Correct type-o.
346 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
348 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
351 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
353 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
355 (interp.o): Add dependency on itable.h
356 (oengine.c, gencode): Delete remaining references.
357 (BUILT_SRC_FROM_GEN): Clean up.
359 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
362 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
363 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
365 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
366 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
367 Drop the "64" qualifier to get the HACK generator working.
368 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
369 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
370 qualifier to get the hack generator working.
371 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
373 (DSLLV): Use do_dsllv.
376 (DSRLV): Use do_dsrlv.
377 (BC1): Move *vr4100 to get the HACK generator working.
378 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
379 get the HACK generator working.
380 (MACC) Rename to get the HACK generator working.
381 (DMACC,MACCS,DMACCS): Add the 64.
383 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
385 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
386 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
388 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
390 * mips/interp.c (DEBUG): Cleanups.
392 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
394 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
395 (tx3904sio_tickle): fflush after a stdout character output.
397 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
399 * interp.c (sim_close): Uninstall modules.
401 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
403 * sim-main.h, interp.c (sim_monitor): Change to global
406 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
408 * configure.in (vr4100): Only include vr4100 instructions in
410 * configure: Re-generate.
411 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
413 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
415 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
416 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
419 * configure.in (sim_default_gen, sim_use_gen): Replace with
421 (--enable-sim-igen): Delete config option. Always using IGEN.
422 * configure: Re-generate.
424 * Makefile.in (gencode): Kill, kill, kill.
427 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
429 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
430 bit mips16 igen simulator.
431 * configure: Re-generate.
433 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
434 as part of vr4100 ISA.
435 * vr.igen: Mark all instructions as 64 bit only.
437 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
439 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
442 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
444 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
445 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
446 * configure: Re-generate.
448 * m16.igen (BREAK): Define breakpoint instruction.
449 (JALX32): Mark instruction as mips16 and not r3900.
450 * mips.igen (C.cond.fmt): Fix typo in instruction format.
452 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
454 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
456 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
457 insn as a debug breakpoint.
459 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
461 (PENDING_SCHED): Clean up trace statement.
462 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
463 (PENDING_FILL): Delay write by only one cycle.
464 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
466 * sim-main.c (pending_tick): Clean up trace statements. Add trace
468 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
470 (pending_tick): Move incrementing of index to FOR statement.
471 (pending_tick): Only update PENDING_OUT after a write has occured.
473 * configure.in: Add explicit mips-lsi-* target. Use gencode to
475 * configure: Re-generate.
477 * interp.c (sim_engine_run OLD): Delete explicit call to
478 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
480 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
482 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
483 interrupt level number to match changed SignalExceptionInterrupt
486 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
488 * interp.c: #include "itable.h" if WITH_IGEN.
489 (get_insn_name): New function.
490 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
491 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
493 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
495 * configure: Rebuilt to inhale new common/aclocal.m4.
497 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
499 * dv-tx3904sio.c: Include sim-assert.h.
501 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
503 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
504 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
505 Reorganize target-specific sim-hardware checks.
506 * configure: rebuilt.
507 * interp.c (sim_open): For tx39 target boards, set
508 OPERATING_ENVIRONMENT, add tx3904sio devices.
509 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
510 ROM executables. Install dv-sockser into sim-modules list.
512 * dv-tx3904irc.c: Compiler warning clean-up.
513 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
514 frequent hw-trace messages.
516 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
518 * vr.igen (MulAcc): Identify as a vr4100 specific function.
520 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
522 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
525 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
526 * mips.igen: Define vr4100 model. Include vr.igen.
527 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
529 * mips.igen (check_mf_hilo): Correct check.
531 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
533 * sim-main.h (interrupt_event): Add prototype.
535 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
536 register_ptr, register_value.
537 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
539 * sim-main.h (tracefh): Make extern.
541 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
543 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
544 Reduce unnecessarily high timer event frequency.
545 * dv-tx3904cpu.c: Ditto for interrupt event.
547 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
549 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
551 (interrupt_event): Made non-static.
553 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
554 interchange of configuration values for external vs. internal
557 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
559 * mips.igen (BREAK): Moved code to here for
560 simulator-reserved break instructions.
561 * gencode.c (build_instruction): Ditto.
562 * interp.c (signal_exception): Code moved from here. Non-
563 reserved instructions now use exception vector, rather
565 * sim-main.h: Moved magic constants to here.
567 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
569 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
570 register upon non-zero interrupt event level, clear upon zero
572 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
573 by passing zero event value.
574 (*_io_{read,write}_buffer): Endianness fixes.
575 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
576 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
578 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
579 serial I/O and timer module at base address 0xFFFF0000.
581 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
583 * mips.igen (SWC1) : Correct the handling of ReverseEndian
586 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
588 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
592 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
594 * dv-tx3904tmr.c: New file - implements tx3904 timer.
595 * dv-tx3904{irc,cpu}.c: Mild reformatting.
596 * configure.in: Include tx3904tmr in hw_device list.
597 * configure: Rebuilt.
598 * interp.c (sim_open): Instantiate three timer instances.
599 Fix address typo of tx3904irc instance.
601 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
603 * interp.c (signal_exception): SystemCall exception now uses
604 the exception vector.
606 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
608 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
611 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
613 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
615 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
617 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
619 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
620 sim-main.h. Declare a struct hw_descriptor instead of struct
621 hw_device_descriptor.
623 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
625 * mips.igen (do_store_left, do_load_left): Compute nr of left and
626 right bits and then re-align left hand bytes to correct byte
627 lanes. Fix incorrect computation in do_store_left when loading
628 bytes from second word.
630 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
632 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
633 * interp.c (sim_open): Only create a device tree when HW is
636 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
637 * interp.c (signal_exception): Ditto.
639 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
641 * gencode.c: Mark BEGEZALL as LIKELY.
643 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
645 * sim-main.h (ALU32_END): Sign extend 32 bit results.
646 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
648 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
650 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
651 modules. Recognize TX39 target with "mips*tx39" pattern.
652 * configure: Rebuilt.
653 * sim-main.h (*): Added many macros defining bits in
654 TX39 control registers.
655 (SignalInterrupt): Send actual PC instead of NULL.
656 (SignalNMIReset): New exception type.
657 * interp.c (board): New variable for future use to identify
658 a particular board being simulated.
659 (mips_option_handler,mips_options): Added "--board" option.
660 (interrupt_event): Send actual PC.
661 (sim_open): Make memory layout conditional on board setting.
662 (signal_exception): Initial implementation of hardware interrupt
663 handling. Accept another break instruction variant for simulator
665 (decode_coproc): Implement RFE instruction for TX39.
666 (mips.igen): Decode RFE instruction as such.
667 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
668 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
669 bbegin to implement memory map.
670 * dv-tx3904cpu.c: New file.
671 * dv-tx3904irc.c: New file.
673 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
675 * mips.igen (check_mt_hilo): Create a separate r3900 version.
677 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
679 * tx.igen (madd,maddu): Replace calls to check_op_hilo
680 with calls to check_div_hilo.
682 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
684 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
685 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
686 Add special r3900 version of do_mult_hilo.
687 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
688 with calls to check_mult_hilo.
689 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
690 with calls to check_div_hilo.
692 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
694 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
695 Document a replacement.
697 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
699 * interp.c (sim_monitor): Make mon_printf work.
701 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
703 * sim-main.h (INSN_NAME): New arg `cpu'.
705 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
707 * configure: Regenerated to track ../common/aclocal.m4 changes.
709 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
711 * configure: Regenerated to track ../common/aclocal.m4 changes.
714 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
716 * acconfig.h: New file.
717 * configure.in: Reverted change of Apr 24; use sinclude again.
719 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
721 * configure: Regenerated to track ../common/aclocal.m4 changes.
724 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
726 * configure.in: Don't call sinclude.
728 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
730 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
732 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
734 * mips.igen (ERET): Implement.
736 * interp.c (decode_coproc): Return sign-extended EPC.
738 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
740 * interp.c (signal_exception): Do not ignore Trap.
741 (signal_exception): On TRAP, restart at exception address.
742 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
743 (signal_exception): Update.
744 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
745 so that TRAP instructions are caught.
747 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
749 * sim-main.h (struct hilo_access, struct hilo_history): Define,
750 contains HI/LO access history.
751 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
752 (HIACCESS, LOACCESS): Delete, replace with
753 (HIHISTORY, LOHISTORY): New macros.
754 (CHECKHILO): Delete all, moved to mips.igen
756 * gencode.c (build_instruction): Do not generate checks for
757 correct HI/LO register usage.
759 * interp.c (old_engine_run): Delete checks for correct HI/LO
762 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
763 check_mf_cycles): New functions.
764 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
765 do_divu, domultx, do_mult, do_multu): Use.
767 * tx.igen ("madd", "maddu"): Use.
769 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
771 * mips.igen (DSRAV): Use function do_dsrav.
772 (SRAV): Use new function do_srav.
774 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
775 (B): Sign extend 11 bit immediate.
776 (EXT-B*): Shift 16 bit immediate left by 1.
777 (ADDIU*): Don't sign extend immediate value.
779 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
781 * m16run.c (sim_engine_run): Restore CIA after handling an event.
783 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
786 * mips.igen (delayslot32, nullify_next_insn): New functions.
787 (m16.igen): Always include.
788 (do_*): Add more tracing.
790 * m16.igen (delayslot16): Add NIA argument, could be called by a
791 32 bit MIPS16 instruction.
793 * interp.c (ifetch16): Move function from here.
794 * sim-main.c (ifetch16): To here.
796 * sim-main.c (ifetch16, ifetch32): Update to match current
797 implementations of LH, LW.
798 (signal_exception): Don't print out incorrect hex value of illegal
801 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
803 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
806 * m16.igen: Implement MIPS16 instructions.
808 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
809 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
810 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
811 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
812 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
813 bodies of corresponding code from 32 bit insn to these. Also used
814 by MIPS16 versions of functions.
816 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
817 (IMEM16): Drop NR argument from macro.
819 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
821 * Makefile.in (SIM_OBJS): Add sim-main.o.
823 * sim-main.h (address_translation, load_memory, store_memory,
824 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
826 (pr_addr, pr_uword64): Declare.
827 (sim-main.c): Include when H_REVEALS_MODULE_P.
829 * interp.c (address_translation, load_memory, store_memory,
830 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
832 * sim-main.c: To here. Fix compilation problems.
834 * configure.in: Enable inlining.
835 * configure: Re-config.
837 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
839 * configure: Regenerated to track ../common/aclocal.m4 changes.
841 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
843 * mips.igen: Include tx.igen.
844 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
845 * tx.igen: New file, contains MADD and MADDU.
847 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
848 the hardwired constant `7'.
849 (store_memory): Ditto.
850 (LOADDRMASK): Move definition to sim-main.h.
852 mips.igen (MTC0): Enable for r3900.
855 mips.igen (do_load_byte): Delete.
856 (do_load, do_store, do_load_left, do_load_write, do_store_left,
857 do_store_right): New functions.
858 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
860 configure.in: Let the tx39 use igen again.
863 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
865 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
866 not an address sized quantity. Return zero for cache sizes.
868 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
870 * mips.igen (r3900): r3900 does not support 64 bit integer
873 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
875 * configure.in (mipstx39*-*-*): Use gencode simulator rather
877 * configure : Rebuild.
879 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
881 * configure: Regenerated to track ../common/aclocal.m4 changes.
883 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
885 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
887 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
889 * configure: Regenerated to track ../common/aclocal.m4 changes.
890 * config.in: Regenerated to track ../common/aclocal.m4 changes.
892 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
894 * configure: Regenerated to track ../common/aclocal.m4 changes.
896 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
898 * interp.c (Max, Min): Comment out functions. Not yet used.
900 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
902 * configure: Regenerated to track ../common/aclocal.m4 changes.
904 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
906 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
907 configurable settings for stand-alone simulator.
909 * configure.in: Added X11 search, just in case.
911 * configure: Regenerated.
913 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
915 * interp.c (sim_write, sim_read, load_memory, store_memory):
916 Replace sim_core_*_map with read_map, write_map, exec_map resp.
918 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
920 * sim-main.h (GETFCC): Return an unsigned value.
922 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
924 * mips.igen (DIV): Fix check for -1 / MIN_INT.
925 (DADD): Result destination is RD not RT.
927 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
929 * sim-main.h (HIACCESS, LOACCESS): Always define.
931 * mdmx.igen (Maxi, Mini): Rename Max, Min.
933 * interp.c (sim_info): Delete.
935 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
937 * interp.c (DECLARE_OPTION_HANDLER): Use it.
938 (mips_option_handler): New argument `cpu'.
939 (sim_open): Update call to sim_add_option_table.
941 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
943 * mips.igen (CxC1): Add tracing.
945 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
947 * sim-main.h (Max, Min): Declare.
949 * interp.c (Max, Min): New functions.
951 * mips.igen (BC1): Add tracing.
953 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
955 * interp.c Added memory map for stack in vr4100
957 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
959 * interp.c (load_memory): Add missing "break"'s.
961 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
963 * interp.c (sim_store_register, sim_fetch_register): Pass in
964 length parameter. Return -1.
966 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
968 * interp.c: Added hardware init hook, fixed warnings.
970 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
972 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
974 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
976 * interp.c (ifetch16): New function.
978 * sim-main.h (IMEM32): Rename IMEM.
979 (IMEM16_IMMED): Define.
981 (DELAY_SLOT): Update.
983 * m16run.c (sim_engine_run): New file.
985 * m16.igen: All instructions except LB.
986 (LB): Call do_load_byte.
987 * mips.igen (do_load_byte): New function.
988 (LB): Call do_load_byte.
990 * mips.igen: Move spec for insn bit size and high bit from here.
991 * Makefile.in (tmp-igen, tmp-m16): To here.
993 * m16.dc: New file, decode mips16 instructions.
995 * Makefile.in (SIM_NO_ALL): Define.
996 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
998 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1000 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1001 point unit to 32 bit registers.
1002 * configure: Re-generate.
1004 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1006 * configure.in (sim_use_gen): Make IGEN the default simulator
1007 generator for generic 32 and 64 bit mips targets.
1008 * configure: Re-generate.
1010 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1012 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1015 * interp.c (sim_fetch_register, sim_store_register): Read/write
1016 FGR from correct location.
1017 (sim_open): Set size of FGR's according to
1018 WITH_TARGET_FLOATING_POINT_BITSIZE.
1020 * sim-main.h (FGR): Store floating point registers in a separate
1023 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1025 * configure: Regenerated to track ../common/aclocal.m4 changes.
1027 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1029 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1031 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1033 * interp.c (pending_tick): New function. Deliver pending writes.
1035 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1036 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1037 it can handle mixed sized quantites and single bits.
1039 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1041 * interp.c (oengine.h): Do not include when building with IGEN.
1042 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1043 (sim_info): Ditto for PROCESSOR_64BIT.
1044 (sim_monitor): Replace ut_reg with unsigned_word.
1045 (*): Ditto for t_reg.
1046 (LOADDRMASK): Define.
1047 (sim_open): Remove defunct check that host FP is IEEE compliant,
1048 using software to emulate floating point.
1049 (value_fpr, ...): Always compile, was conditional on HASFPU.
1051 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1053 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1056 * interp.c (SD, CPU): Define.
1057 (mips_option_handler): Set flags in each CPU.
1058 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1059 (sim_close): Do not clear STATE, deleted anyway.
1060 (sim_write, sim_read): Assume CPU zero's vm should be used for
1062 (sim_create_inferior): Set the PC for all processors.
1063 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1065 (mips16_entry): Pass correct nr of args to store_word, load_word.
1066 (ColdReset): Cold reset all cpu's.
1067 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1068 (sim_monitor, load_memory, store_memory, signal_exception): Use
1069 `CPU' instead of STATE_CPU.
1072 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1075 * sim-main.h (signal_exception): Add sim_cpu arg.
1076 (SignalException*): Pass both SD and CPU to signal_exception.
1077 * interp.c (signal_exception): Update.
1079 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1081 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1082 address_translation): Ditto
1083 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1085 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1087 * configure: Regenerated to track ../common/aclocal.m4 changes.
1089 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1091 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1093 * mips.igen (model): Map processor names onto BFD name.
1095 * sim-main.h (CPU_CIA): Delete.
1096 (SET_CIA, GET_CIA): Define
1098 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1100 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1103 * configure.in (default_endian): Configure a big-endian simulator
1105 * configure: Re-generate.
1107 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1109 * configure: Regenerated to track ../common/aclocal.m4 changes.
1111 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1113 * interp.c (sim_monitor): Handle Densan monitor outbyte
1114 and inbyte functions.
1116 1997-12-29 Felix Lee <flee@cygnus.com>
1118 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1120 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1122 * Makefile.in (tmp-igen): Arrange for $zero to always be
1123 reset to zero after every instruction.
1125 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1127 * configure: Regenerated to track ../common/aclocal.m4 changes.
1130 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1132 * mips.igen (MSUB): Fix to work like MADD.
1133 * gencode.c (MSUB): Similarly.
1135 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1137 * configure: Regenerated to track ../common/aclocal.m4 changes.
1139 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1141 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1143 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1145 * sim-main.h (sim-fpu.h): Include.
1147 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1148 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1149 using host independant sim_fpu module.
1151 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1153 * interp.c (signal_exception): Report internal errors with SIGABRT
1156 * sim-main.h (C0_CONFIG): New register.
1157 (signal.h): No longer include.
1159 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1161 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1163 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1165 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1167 * mips.igen: Tag vr5000 instructions.
1168 (ANDI): Was missing mipsIV model, fix assembler syntax.
1169 (do_c_cond_fmt): New function.
1170 (C.cond.fmt): Handle mips I-III which do not support CC field
1172 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1173 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1175 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1176 vr5000 which saves LO in a GPR separatly.
1178 * configure.in (enable-sim-igen): For vr5000, select vr5000
1179 specific instructions.
1180 * configure: Re-generate.
1182 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1184 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1186 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1187 fmt_uninterpreted_64 bit cases to switch. Convert to
1190 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1192 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1193 as specified in IV3.2 spec.
1194 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1196 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1198 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1199 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1200 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1201 PENDING_FILL versions of instructions. Simplify.
1203 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1205 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1207 (MTHI, MFHI): Disable code checking HI-LO.
1209 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1211 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1213 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1215 * gencode.c (build_mips16_operands): Replace IPC with cia.
1217 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1218 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1220 (UndefinedResult): Replace function with macro/function
1222 (sim_engine_run): Don't save PC in IPC.
1224 * sim-main.h (IPC): Delete.
1227 * interp.c (signal_exception, store_word, load_word,
1228 address_translation, load_memory, store_memory, cache_op,
1229 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1230 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1231 current instruction address - cia - argument.
1232 (sim_read, sim_write): Call address_translation directly.
1233 (sim_engine_run): Rename variable vaddr to cia.
1234 (signal_exception): Pass cia to sim_monitor
1236 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1237 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1238 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1240 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1241 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1244 * interp.c (signal_exception): Pass restart address to
1247 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1248 idecode.o): Add dependency.
1250 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1252 (DELAY_SLOT): Update NIA not PC with branch address.
1253 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1255 * mips.igen: Use CIA not PC in branch calculations.
1256 (illegal): Call SignalException.
1257 (BEQ, ADDIU): Fix assembler.
1259 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1261 * m16.igen (JALX): Was missing.
1263 * configure.in (enable-sim-igen): New configuration option.
1264 * configure: Re-generate.
1266 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1268 * interp.c (load_memory, store_memory): Delete parameter RAW.
1269 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1270 bypassing {load,store}_memory.
1272 * sim-main.h (ByteSwapMem): Delete definition.
1274 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1276 * interp.c (sim_do_command, sim_commands): Delete mips specific
1277 commands. Handled by module sim-options.
1279 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1280 (WITH_MODULO_MEMORY): Define.
1282 * interp.c (sim_info): Delete code printing memory size.
1284 * interp.c (mips_size): Nee sim_size, delete function.
1286 (monitor, monitor_base, monitor_size): Delete global variables.
1287 (sim_open, sim_close): Delete code creating monitor and other
1288 memory regions. Use sim-memopts module, via sim_do_commandf, to
1289 manage memory regions.
1290 (load_memory, store_memory): Use sim-core for memory model.
1292 * interp.c (address_translation): Delete all memory map code
1293 except line forcing 32 bit addresses.
1295 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1297 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1300 * interp.c (logfh, logfile): Delete globals.
1301 (sim_open, sim_close): Delete code opening & closing log file.
1302 (mips_option_handler): Delete -l and -n options.
1303 (OPTION mips_options): Ditto.
1305 * interp.c (OPTION mips_options): Rename option trace to dinero.
1306 (mips_option_handler): Update.
1308 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1310 * interp.c (fetch_str): New function.
1311 (sim_monitor): Rewrite using sim_read & sim_write.
1312 (sim_open): Check magic number.
1313 (sim_open): Write monitor vectors into memory using sim_write.
1314 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1315 (sim_read, sim_write): Simplify - transfer data one byte at a
1317 (load_memory, store_memory): Clarify meaning of parameter RAW.
1319 * sim-main.h (isHOST): Defete definition.
1320 (isTARGET): Mark as depreciated.
1321 (address_translation): Delete parameter HOST.
1323 * interp.c (address_translation): Delete parameter HOST.
1325 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1329 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1330 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1332 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1334 * mips.igen: Add model filter field to records.
1336 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1338 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1340 interp.c (sim_engine_run): Do not compile function sim_engine_run
1341 when WITH_IGEN == 1.
1343 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1344 target architecture.
1346 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1347 igen. Replace with configuration variables sim_igen_flags /
1350 * m16.igen: New file. Copy mips16 insns here.
1351 * mips.igen: From here.
1353 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1355 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1357 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1359 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1361 * gencode.c (build_instruction): Follow sim_write's lead in using
1362 BigEndianMem instead of !ByteSwapMem.
1364 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1366 * configure.in (sim_gen): Dependent on target, select type of
1367 generator. Always select old style generator.
1369 configure: Re-generate.
1371 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1373 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1374 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1375 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1376 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1377 SIM_@sim_gen@_*, set by autoconf.
1379 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1381 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1383 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1384 CURRENT_FLOATING_POINT instead.
1386 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1387 (address_translation): Raise exception InstructionFetch when
1388 translation fails and isINSTRUCTION.
1390 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1391 sim_engine_run): Change type of of vaddr and paddr to
1393 (address_translation, prefetch, load_memory, store_memory,
1394 cache_op): Change type of vAddr and pAddr to address_word.
1396 * gencode.c (build_instruction): Change type of vaddr and paddr to
1399 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1401 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1402 macro to obtain result of ALU op.
1404 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1406 * interp.c (sim_info): Call profile_print.
1408 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1410 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1412 * sim-main.h (WITH_PROFILE): Do not define, defined in
1413 common/sim-config.h. Use sim-profile module.
1414 (simPROFILE): Delete defintion.
1416 * interp.c (PROFILE): Delete definition.
1417 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1418 (sim_close): Delete code writing profile histogram.
1419 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1421 (sim_engine_run): Delete code profiling the PC.
1423 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1425 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1427 * interp.c (sim_monitor): Make register pointers of type
1430 * sim-main.h: Make registers of type unsigned_word not
1433 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1435 * interp.c (sync_operation): Rename from SyncOperation, make
1436 global, add SD argument.
1437 (prefetch): Rename from Prefetch, make global, add SD argument.
1438 (decode_coproc): Make global.
1440 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1442 * gencode.c (build_instruction): Generate DecodeCoproc not
1443 decode_coproc calls.
1445 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1446 (SizeFGR): Move to sim-main.h
1447 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1448 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1449 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1451 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1452 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1453 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1454 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1455 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1456 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1458 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1460 (sim-alu.h): Include.
1461 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1462 (sim_cia): Typedef to instruction_address.
1464 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1466 * Makefile.in (interp.o): Rename generated file engine.c to
1471 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1473 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1475 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477 * gencode.c (build_instruction): For "FPSQRT", output correct
1478 number of arguments to Recip.
1480 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1482 * Makefile.in (interp.o): Depends on sim-main.h
1484 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1486 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1487 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1488 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1489 STATE, DSSTATE): Define
1490 (GPR, FGRIDX, ..): Define.
1492 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1493 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1494 (GPR, FGRIDX, ...): Delete macros.
1496 * interp.c: Update names to match defines from sim-main.h
1498 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1500 * interp.c (sim_monitor): Add SD argument.
1501 (sim_warning): Delete. Replace calls with calls to
1503 (sim_error): Delete. Replace calls with sim_io_error.
1504 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1505 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1506 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1508 (mips_size): Rename from sim_size. Add SD argument.
1510 * interp.c (simulator): Delete global variable.
1511 (callback): Delete global variable.
1512 (mips_option_handler, sim_open, sim_write, sim_read,
1513 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1514 sim_size,sim_monitor): Use sim_io_* not callback->*.
1515 (sim_open): ZALLOC simulator struct.
1516 (PROFILE): Do not define.
1518 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1520 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1521 support.h with corresponding code.
1523 * sim-main.h (word64, uword64), support.h: Move definition to
1525 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1528 * Makefile.in: Update dependencies
1529 * interp.c: Do not include.
1531 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1533 * interp.c (address_translation, load_memory, store_memory,
1534 cache_op): Rename to from AddressTranslation et.al., make global,
1537 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1540 * interp.c (SignalException): Rename to signal_exception, make
1543 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1545 * sim-main.h (SignalException, SignalExceptionInterrupt,
1546 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1547 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1548 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1551 * interp.c, support.h: Use.
1553 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1555 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1556 to value_fpr / store_fpr. Add SD argument.
1557 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1558 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1560 * sim-main.h (ValueFPR, StoreFPR): Define.
1562 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1564 * interp.c (sim_engine_run): Check consistency between configure
1565 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1568 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1569 (mips_fpu): Configure WITH_FLOATING_POINT.
1570 (mips_endian): Configure WITH_TARGET_ENDIAN.
1571 * configure: Update.
1573 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1575 * configure: Regenerated to track ../common/aclocal.m4 changes.
1577 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1579 * configure: Regenerated.
1581 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1583 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1585 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1587 * gencode.c (print_igen_insn_models): Assume certain architectures
1588 include all mips* instructions.
1589 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1592 * Makefile.in (tmp.igen): Add target. Generate igen input from
1595 * gencode.c (FEATURE_IGEN): Define.
1596 (main): Add --igen option. Generate output in igen format.
1597 (process_instructions): Format output according to igen option.
1598 (print_igen_insn_format): New function.
1599 (print_igen_insn_models): New function.
1600 (process_instructions): Only issue warnings and ignore
1601 instructions when no FEATURE_IGEN.
1603 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1605 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1608 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1610 * configure: Regenerated to track ../common/aclocal.m4 changes.
1612 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1615 SIM_RESERVED_BITS): Delete, moved to common.
1616 (SIM_EXTRA_CFLAGS): Update.
1618 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1620 * configure.in: Configure non-strict memory alignment.
1621 * configure: Regenerated to track ../common/aclocal.m4 changes.
1623 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1625 * configure: Regenerated to track ../common/aclocal.m4 changes.
1627 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1629 * gencode.c (SDBBP,DERET): Added (3900) insns.
1630 (RFE): Turn on for 3900.
1631 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1632 (dsstate): Made global.
1633 (SUBTARGET_R3900): Added.
1634 (CANCELDELAYSLOT): New.
1635 (SignalException): Ignore SystemCall rather than ignore and
1636 terminate. Add DebugBreakPoint handling.
1637 (decode_coproc): New insns RFE, DERET; and new registers Debug
1638 and DEPC protected by SUBTARGET_R3900.
1639 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1641 * Makefile.in,configure.in: Add mips subtarget option.
1642 * configure: Update.
1644 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1646 * gencode.c: Add r3900 (tx39).
1649 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1651 * gencode.c (build_instruction): Don't need to subtract 4 for
1654 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1656 * interp.c: Correct some HASFPU problems.
1658 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1660 * configure: Regenerated to track ../common/aclocal.m4 changes.
1662 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1664 * interp.c (mips_options): Fix samples option short form, should
1667 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1669 * interp.c (sim_info): Enable info code. Was just returning.
1671 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1673 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1676 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1678 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1680 (build_instruction): Ditto for LL.
1682 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1684 * configure: Regenerated to track ../common/aclocal.m4 changes.
1686 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1688 * configure: Regenerated to track ../common/aclocal.m4 changes.
1691 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1693 * interp.c (sim_open): Add call to sim_analyze_program, update
1696 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1698 * interp.c (sim_kill): Delete.
1699 (sim_create_inferior): Add ABFD argument. Set PC from same.
1700 (sim_load): Move code initializing trap handlers from here.
1701 (sim_open): To here.
1702 (sim_load): Delete, use sim-hload.c.
1704 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1706 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1708 * configure: Regenerated to track ../common/aclocal.m4 changes.
1711 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1713 * interp.c (sim_open): Add ABFD argument.
1714 (sim_load): Move call to sim_config from here.
1715 (sim_open): To here. Check return status.
1717 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1719 * gencode.c (build_instruction): Two arg MADD should
1720 not assign result to $0.
1722 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1724 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1725 * sim/mips/configure.in: Regenerate.
1727 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1729 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1730 signed8, unsigned8 et.al. types.
1732 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1733 hosts when selecting subreg.
1735 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1737 * interp.c (sim_engine_run): Reset the ZERO register to zero
1738 regardless of FEATURE_WARN_ZERO.
1739 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1741 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1743 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1744 (SignalException): For BreakPoints ignore any mode bits and just
1746 (SignalException): Always set the CAUSE register.
1748 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1750 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1751 exception has been taken.
1753 * interp.c: Implement the ERET and mt/f sr instructions.
1755 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1757 * interp.c (SignalException): Don't bother restarting an
1760 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1762 * interp.c (SignalException): Really take an interrupt.
1763 (interrupt_event): Only deliver interrupts when enabled.
1765 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1767 * interp.c (sim_info): Only print info when verbose.
1768 (sim_info) Use sim_io_printf for output.
1770 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1772 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1775 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1777 * interp.c (sim_do_command): Check for common commands if a
1778 simulator specific command fails.
1780 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1782 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1783 and simBE when DEBUG is defined.
1785 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1787 * interp.c (interrupt_event): New function. Pass exception event
1788 onto exception handler.
1790 * configure.in: Check for stdlib.h.
1791 * configure: Regenerate.
1793 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1794 variable declaration.
1795 (build_instruction): Initialize memval1.
1796 (build_instruction): Add UNUSED attribute to byte, bigend,
1798 (build_operands): Ditto.
1800 * interp.c: Fix GCC warnings.
1801 (sim_get_quit_code): Delete.
1803 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1804 * Makefile.in: Ditto.
1805 * configure: Re-generate.
1807 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1809 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1811 * interp.c (mips_option_handler): New function parse argumes using
1813 (myname): Replace with STATE_MY_NAME.
1814 (sim_open): Delete check for host endianness - performed by
1816 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1817 (sim_open): Move much of the initialization from here.
1818 (sim_load): To here. After the image has been loaded and
1820 (sim_open): Move ColdReset from here.
1821 (sim_create_inferior): To here.
1822 (sim_open): Make FP check less dependant on host endianness.
1824 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1826 * interp.c (sim_set_callbacks): Delete.
1828 * interp.c (membank, membank_base, membank_size): Replace with
1829 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1830 (sim_open): Remove call to callback->init. gdb/run do this.
1834 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1836 * interp.c (big_endian_p): Delete, replaced by
1837 current_target_byte_order.
1839 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1841 * interp.c (host_read_long, host_read_word, host_swap_word,
1842 host_swap_long): Delete. Using common sim-endian.
1843 (sim_fetch_register, sim_store_register): Use H2T.
1844 (pipeline_ticks): Delete. Handled by sim-events.
1846 (sim_engine_run): Update.
1848 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1850 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1852 (SignalException): To here. Signal using sim_engine_halt.
1853 (sim_stop_reason): Delete, moved to common.
1855 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1857 * interp.c (sim_open): Add callback argument.
1858 (sim_set_callbacks): Delete SIM_DESC argument.
1861 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1863 * Makefile.in (SIM_OBJS): Add common modules.
1865 * interp.c (sim_set_callbacks): Also set SD callback.
1866 (set_endianness, xfer_*, swap_*): Delete.
1867 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1868 Change to functions using sim-endian macros.
1869 (control_c, sim_stop): Delete, use common version.
1870 (simulate): Convert into.
1871 (sim_engine_run): This function.
1872 (sim_resume): Delete.
1874 * interp.c (simulation): New variable - the simulator object.
1875 (sim_kind): Delete global - merged into simulation.
1876 (sim_load): Cleanup. Move PC assignment from here.
1877 (sim_create_inferior): To here.
1879 * sim-main.h: New file.
1880 * interp.c (sim-main.h): Include.
1882 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1884 * configure: Regenerated to track ../common/aclocal.m4 changes.
1886 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1888 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1890 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1892 * gencode.c (build_instruction): DIV instructions: check
1893 for division by zero and integer overflow before using
1894 host's division operation.
1896 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1898 * Makefile.in (SIM_OBJS): Add sim-load.o.
1899 * interp.c: #include bfd.h.
1900 (target_byte_order): Delete.
1901 (sim_kind, myname, big_endian_p): New static locals.
1902 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1903 after argument parsing. Recognize -E arg, set endianness accordingly.
1904 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1905 load file into simulator. Set PC from bfd.
1906 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1907 (set_endianness): Use big_endian_p instead of target_byte_order.
1909 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1911 * interp.c (sim_size): Delete prototype - conflicts with
1912 definition in remote-sim.h. Correct definition.
1914 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1916 * configure: Regenerated to track ../common/aclocal.m4 changes.
1919 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1921 * interp.c (sim_open): New arg `kind'.
1923 * configure: Regenerated to track ../common/aclocal.m4 changes.
1925 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1927 * configure: Regenerated to track ../common/aclocal.m4 changes.
1929 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1931 * interp.c (sim_open): Set optind to 0 before calling getopt.
1933 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1935 * configure: Regenerated to track ../common/aclocal.m4 changes.
1937 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1939 * interp.c : Replace uses of pr_addr with pr_uword64
1940 where the bit length is always 64 independent of SIM_ADDR.
1941 (pr_uword64) : added.
1943 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1945 * configure: Re-generate.
1947 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1949 * configure: Regenerate to track ../common/aclocal.m4 changes.
1951 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1953 * interp.c (sim_open): New SIM_DESC result. Argument is now
1955 (other sim_*): New SIM_DESC argument.
1957 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1959 * interp.c: Fix printing of addresses for non-64-bit targets.
1960 (pr_addr): Add function to print address based on size.
1962 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1964 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1966 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1968 * gencode.c (build_mips16_operands): Correct computation of base
1969 address for extended PC relative instruction.
1971 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1973 * interp.c (mips16_entry): Add support for floating point cases.
1974 (SignalException): Pass floating point cases to mips16_entry.
1975 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1977 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1979 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
1980 and then set the state to fmt_uninterpreted.
1981 (COP_SW): Temporarily set the state to fmt_word while calling
1984 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
1986 * gencode.c (build_instruction): The high order may be set in the
1987 comparison flags at any ISA level, not just ISA 4.
1989 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
1991 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
1992 COMMON_{PRE,POST}_CONFIG_FRAG instead.
1993 * configure.in: sinclude ../common/aclocal.m4.
1994 * configure: Regenerated.
1996 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
1998 * configure: Rebuild after change to aclocal.m4.
2000 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2002 * configure configure.in Makefile.in: Update to new configure
2003 scheme which is more compatible with WinGDB builds.
2004 * configure.in: Improve comment on how to run autoconf.
2005 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2006 * Makefile.in: Use autoconf substitution to install common
2009 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2011 * gencode.c (build_instruction): Use BigEndianCPU instead of
2014 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2016 * interp.c (sim_monitor): Make output to stdout visible in
2017 wingdb's I/O log window.
2019 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2021 * support.h: Undo previous change to SIGTRAP
2024 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2026 * interp.c (store_word, load_word): New static functions.
2027 (mips16_entry): New static function.
2028 (SignalException): Look for mips16 entry and exit instructions.
2029 (simulate): Use the correct index when setting fpr_state after
2030 doing a pending move.
2032 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2034 * interp.c: Fix byte-swapping code throughout to work on
2035 both little- and big-endian hosts.
2037 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2039 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2040 with gdb/config/i386/xm-windows.h.
2042 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2044 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2045 that messes up arithmetic shifts.
2047 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2049 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2050 SIGTRAP and SIGQUIT for _WIN32.
2052 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2054 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2055 force a 64 bit multiplication.
2056 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2057 destination register is 0, since that is the default mips16 nop
2060 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2062 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2063 (build_endian_shift): Don't check proc64.
2064 (build_instruction): Always set memval to uword64. Cast op2 to
2065 uword64 when shifting it left in memory instructions. Always use
2066 the same code for stores--don't special case proc64.
2068 * gencode.c (build_mips16_operands): Fix base PC value for PC
2070 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2072 * interp.c (simJALDELAYSLOT): Define.
2073 (JALDELAYSLOT): Define.
2074 (INDELAYSLOT, INJALDELAYSLOT): Define.
2075 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2077 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2079 * interp.c (sim_open): add flush_cache as a PMON routine
2080 (sim_monitor): handle flush_cache by ignoring it
2082 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2084 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2086 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2087 (BigEndianMem): Rename to ByteSwapMem and change sense.
2088 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2089 BigEndianMem references to !ByteSwapMem.
2090 (set_endianness): New function, with prototype.
2091 (sim_open): Call set_endianness.
2092 (sim_info): Use simBE instead of BigEndianMem.
2093 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2094 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2095 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2096 ifdefs, keeping the prototype declaration.
2097 (swap_word): Rewrite correctly.
2098 (ColdReset): Delete references to CONFIG. Delete endianness related
2099 code; moved to set_endianness.
2101 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2103 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2104 * interp.c (CHECKHILO): Define away.
2105 (simSIGINT): New macro.
2106 (membank_size): Increase from 1MB to 2MB.
2107 (control_c): New function.
2108 (sim_resume): Rename parameter signal to signal_number. Add local
2109 variable prev. Call signal before and after simulate.
2110 (sim_stop_reason): Add simSIGINT support.
2111 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2113 (sim_warning): Delete call to SignalException. Do call printf_filtered
2115 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2116 a call to sim_warning.
2118 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2120 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2121 16 bit instructions.
2123 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2125 Add support for mips16 (16 bit MIPS implementation):
2126 * gencode.c (inst_type): Add mips16 instruction encoding types.
2127 (GETDATASIZEINSN): Define.
2128 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2129 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2131 (MIPS16_DECODE): New table, for mips16 instructions.
2132 (bitmap_val): New static function.
2133 (struct mips16_op): Define.
2134 (mips16_op_table): New table, for mips16 operands.
2135 (build_mips16_operands): New static function.
2136 (process_instructions): If PC is odd, decode a mips16
2137 instruction. Break out instruction handling into new
2138 build_instruction function.
2139 (build_instruction): New static function, broken out of
2140 process_instructions. Check modifiers rather than flags for SHIFT
2141 bit count and m[ft]{hi,lo} direction.
2142 (usage): Pass program name to fprintf.
2143 (main): Remove unused variable this_option_optind. Change
2144 ``*loptarg++'' to ``loptarg++''.
2145 (my_strtoul): Parenthesize && within ||.
2146 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2147 (simulate): If PC is odd, fetch a 16 bit instruction, and
2148 increment PC by 2 rather than 4.
2149 * configure.in: Add case for mips16*-*-*.
2150 * configure: Rebuild.
2152 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2154 * interp.c: Allow -t to enable tracing in standalone simulator.
2155 Fix garbage output in trace file and error messages.
2157 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2159 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2160 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2161 * configure.in: Simplify using macros in ../common/aclocal.m4.
2162 * configure: Regenerated.
2163 * tconfig.in: New file.
2165 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2167 * interp.c: Fix bugs in 64-bit port.
2168 Use ansi function declarations for msvc compiler.
2169 Initialize and test file pointer in trace code.
2170 Prevent duplicate definition of LAST_EMED_REGNUM.
2172 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2174 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2176 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2178 * interp.c (SignalException): Check for explicit terminating
2180 * gencode.c: Pass instruction value through SignalException()
2181 calls for Trap, Breakpoint and Syscall.
2183 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2185 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2186 only used on those hosts that provide it.
2187 * configure.in: Add sqrt() to list of functions to be checked for.
2188 * config.in: Re-generated.
2189 * configure: Re-generated.
2191 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2193 * gencode.c (process_instructions): Call build_endian_shift when
2194 expanding STORE RIGHT, to fix swr.
2195 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2196 clear the high bits.
2197 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2198 Fix float to int conversions to produce signed values.
2200 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2202 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2203 (process_instructions): Correct handling of nor instruction.
2204 Correct shift count for 32 bit shift instructions. Correct sign
2205 extension for arithmetic shifts to not shift the number of bits in
2206 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2207 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2209 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2210 It's OK to have a mult follow a mult. What's not OK is to have a
2211 mult follow an mfhi.
2212 (Convert): Comment out incorrect rounding code.
2214 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2216 * interp.c (sim_monitor): Improved monitor printf
2217 simulation. Tidied up simulator warnings, and added "--log" option
2218 for directing warning message output.
2219 * gencode.c: Use sim_warning() rather than WARNING macro.
2221 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2223 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2224 getopt1.o, rather than on gencode.c. Link objects together.
2225 Don't link against -liberty.
2226 (gencode.o, getopt.o, getopt1.o): New targets.
2227 * gencode.c: Include <ctype.h> and "ansidecl.h".
2228 (AND): Undefine after including "ansidecl.h".
2229 (ULONG_MAX): Define if not defined.
2230 (OP_*): Don't define macros; now defined in opcode/mips.h.
2231 (main): Call my_strtoul rather than strtoul.
2232 (my_strtoul): New static function.
2234 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2236 * gencode.c (process_instructions): Generate word64 and uword64
2237 instead of `long long' and `unsigned long long' data types.
2238 * interp.c: #include sysdep.h to get signals, and define default
2240 * (Convert): Work around for Visual-C++ compiler bug with type
2242 * support.h: Make things compile under Visual-C++ by using
2243 __int64 instead of `long long'. Change many refs to long long
2244 into word64/uword64 typedefs.
2246 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2248 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2249 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2251 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2252 (AC_PROG_INSTALL): Added.
2253 (AC_PROG_CC): Moved to before configure.host call.
2254 * configure: Rebuilt.
2256 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2258 * configure.in: Define @SIMCONF@ depending on mips target.
2259 * configure: Rebuild.
2260 * Makefile.in (run): Add @SIMCONF@ to control simulator
2262 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2263 * interp.c: Remove some debugging, provide more detailed error
2264 messages, update memory accesses to use LOADDRMASK.
2266 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2268 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2269 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2271 * configure: Rebuild.
2272 * config.in: New file, generated by autoheader.
2273 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2274 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2275 HAVE_ANINT and HAVE_AINT, as appropriate.
2276 * Makefile.in (run): Use @LIBS@ rather than -lm.
2277 (interp.o): Depend upon config.h.
2278 (Makefile): Just rebuild Makefile.
2279 (clean): Remove stamp-h.
2280 (mostlyclean): Make the same as clean, not as distclean.
2281 (config.h, stamp-h): New targets.
2283 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2285 * interp.c (ColdReset): Fix boolean test. Make all simulator
2288 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2290 * interp.c (xfer_direct_word, xfer_direct_long,
2291 swap_direct_word, swap_direct_long, xfer_big_word,
2292 xfer_big_long, xfer_little_word, xfer_little_long,
2293 swap_word,swap_long): Added.
2294 * interp.c (ColdReset): Provide function indirection to
2295 host<->simulated_target transfer routines.
2296 * interp.c (sim_store_register, sim_fetch_register): Updated to
2297 make use of indirected transfer routines.
2299 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2301 * gencode.c (process_instructions): Ensure FP ABS instruction
2303 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2304 system call support.
2306 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2308 * interp.c (sim_do_command): Complain if callback structure not
2311 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2313 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2314 support for Sun hosts.
2315 * Makefile.in (gencode): Ensure the host compiler and libraries
2316 used for cross-hosted build.
2318 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2320 * interp.c, gencode.c: Some more (TODO) tidying.
2322 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2324 * gencode.c, interp.c: Replaced explicit long long references with
2325 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2326 * support.h (SET64LO, SET64HI): Macros added.
2328 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2330 * configure: Regenerate with autoconf 2.7.
2332 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2334 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2335 * support.h: Remove superfluous "1" from #if.
2336 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2338 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2340 * interp.c (StoreFPR): Control UndefinedResult() call on
2341 WARN_RESULT manifest.
2343 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2345 * gencode.c: Tidied instruction decoding, and added FP instruction
2348 * interp.c: Added dineroIII, and BSD profiling support. Also
2349 run-time FP handling.
2351 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2353 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2354 gencode.c, interp.c, support.h: created.