1 2011-07-08 Hans-Peter Nilsson <hp@axis.com>
3 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
5 (tmp-mach-multi): Exit early when igen fails.
7 2011-07-05 Mike Frysinger <vapier@gentoo.org>
9 * interp.c (sim_do_command): Delete.
11 2011-02-14 Mike Frysinger <vapier@gentoo.org>
13 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
14 (tx3904sio_fifo_reset): Likewise.
15 * interp.c (sim_monitor): Likewise.
17 2010-04-14 Mike Frysinger <vapier@gentoo.org>
19 * interp.c (sim_write): Add const to buffer arg.
21 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
23 * interp.c: Don't include sysdep.h
25 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
27 * configure: Regenerate.
29 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
31 * config.in: Regenerate.
32 * configure: Likewise.
34 * configure: Regenerate.
36 2008-07-11 Hans-Peter Nilsson <hp@axis.com>
38 * configure: Regenerate to track ../common/common.m4 changes.
41 2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
42 Daniel Jacobowitz <dan@codesourcery.com>
43 Joseph Myers <joseph@codesourcery.com>
45 * configure: Regenerate.
47 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
49 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
50 that unconditionally allows fmt_ps.
51 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
52 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
53 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
54 filter from 64,f to 32,f.
55 (PREFX): Change filter from 64 to 32.
56 (LDXC1, LUXC1): Provide separate mips32r2 implementations
57 that use do_load_double instead of do_load. Make both LUXC1
58 versions unpredictable if SizeFGR () != 64.
59 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
60 instead of do_store. Remove unused variable. Make both SUXC1
61 versions unpredictable if SizeFGR () != 64.
63 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
65 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
66 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
69 2007-09-04 Nick Clifton <nickc@redhat.com>
71 * interp.c (options enum): Add OPTION_INFO_MEMORY.
72 (display_mem_info): New static variable.
73 (mips_option_handler): Handle OPTION_INFO_MEMORY.
74 (mips_options): Add info-memory and memory-info.
75 (sim_open): After processing the command line and board
76 specification, check display_mem_info. If it is set then
77 call the real handler for the --memory-info command line
80 2007-08-24 Joel Brobecker <brobecker@adacore.com>
82 * configure.ac: Change license of multi-run.c to GPL version 3.
83 * configure: Regenerate.
85 2007-06-28 Richard Sandiford <richard@codesourcery.com>
87 * configure.ac, configure: Revert last patch.
89 2007-06-26 Richard Sandiford <richard@codesourcery.com>
91 * configure.ac (sim_mipsisa3264_configs): New variable.
92 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
93 every configuration support all four targets, using the triplet to
94 determine the default.
95 * configure: Regenerate.
97 2007-06-25 Richard Sandiford <richard@codesourcery.com>
99 * Makefile.in (m16run.o): New rule.
101 2007-05-15 Thiemo Seufer <ths@mips.com>
103 * mips3264r2.igen (DSHD): Fix compile warning.
105 2007-05-14 Thiemo Seufer <ths@mips.com>
107 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
108 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
109 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
110 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
113 2007-03-01 Thiemo Seufer <ths@mips.com>
115 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
118 2007-02-20 Thiemo Seufer <ths@mips.com>
120 * dsp.igen: Update copyright notice.
121 * dsp2.igen: Fix copyright notice.
123 2007-02-20 Thiemo Seufer <ths@mips.com>
124 Chao-Ying Fu <fu@mips.com>
126 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
127 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
128 Add dsp2 to sim_igen_machine.
129 * configure: Regenerate.
130 * dsp.igen (do_ph_op): Add MUL support when op = 2.
131 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
132 (mulq_rs.ph): Use do_ph_mulq.
133 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
134 * mips.igen: Add dsp2 model and include dsp2.igen.
135 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
136 for *mips32r2, *mips64r2, *dsp.
137 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
138 for *mips32r2, *mips64r2, *dsp2.
139 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
141 2007-02-19 Thiemo Seufer <ths@mips.com>
142 Nigel Stephens <nigel@mips.com>
144 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
145 jumps with hazard barrier.
147 2007-02-19 Thiemo Seufer <ths@mips.com>
148 Nigel Stephens <nigel@mips.com>
150 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
151 after each call to sim_io_write.
153 2007-02-19 Thiemo Seufer <ths@mips.com>
154 Nigel Stephens <nigel@mips.com>
156 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
157 supported by this simulator.
158 (decode_coproc): Recognise additional CP0 Config registers
161 2007-02-19 Thiemo Seufer <ths@mips.com>
162 Nigel Stephens <nigel@mips.com>
163 David Ung <davidu@mips.com>
165 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
166 uninterpreted formats. If fmt is one of the uninterpreted types
167 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
168 fmt_word, and fmt_uninterpreted_64 like fmt_long.
169 (store_fpr): When writing an invalid odd register, set the
170 matching even register to fmt_unknown, not the following register.
171 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
172 the the memory window at offset 0 set by --memory-size command
174 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
176 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
178 (sim_monitor): When returning the memory size to the MIPS
179 application, use the value in STATE_MEM_SIZE, not an arbitrary
181 (cop_lw): Don' mess around with FPR_STATE, just pass
182 fmt_uninterpreted_32 to StoreFPR.
184 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
186 * mips.igen (not_word_value): Single version for mips32, mips64
189 2007-02-19 Thiemo Seufer <ths@mips.com>
190 Nigel Stephens <nigel@mips.com>
192 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
195 2007-02-17 Thiemo Seufer <ths@mips.com>
197 * configure.ac (mips*-sde-elf*): Move in front of generic machine
199 * configure: Regenerate.
201 2007-02-17 Thiemo Seufer <ths@mips.com>
203 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
204 Add mdmx to sim_igen_machine.
205 (mipsisa64*-*-*): Likewise. Remove dsp.
206 (mipsisa32*-*-*): Remove dsp.
207 * configure: Regenerate.
209 2007-02-13 Thiemo Seufer <ths@mips.com>
211 * configure.ac: Add mips*-sde-elf* target.
212 * configure: Regenerate.
214 2006-12-21 Hans-Peter Nilsson <hp@axis.com>
216 * acconfig.h: Remove.
217 * config.in, configure: Regenerate.
219 2006-11-07 Thiemo Seufer <ths@mips.com>
221 * dsp.igen (do_w_op): Fix compiler warning.
223 2006-08-29 Thiemo Seufer <ths@mips.com>
224 David Ung <davidu@mips.com>
226 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
228 * configure: Regenerate.
229 * mips.igen (model): Add smartmips.
230 (MADDU): Increment ACX if carry.
231 (do_mult): Clear ACX.
232 (ROR,RORV): Add smartmips.
233 (include): Include smartmips.igen.
234 * sim-main.h (ACX): Set to REGISTERS[89].
235 * smartmips.igen: New file.
237 2006-08-29 Thiemo Seufer <ths@mips.com>
238 David Ung <davidu@mips.com>
240 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
241 mips3264r2.igen. Add missing dependency rules.
242 * m16e.igen: Support for mips16e save/restore instructions.
244 2006-06-13 Richard Earnshaw <rearnsha@arm.com>
246 * configure: Regenerated.
248 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
250 * configure: Regenerated.
252 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
254 * configure: Regenerated.
256 2006-05-15 Chao-ying Fu <fu@mips.com>
258 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
260 2006-04-18 Nick Clifton <nickc@redhat.com>
262 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
265 2006-03-29 Hans-Peter Nilsson <hp@axis.com>
267 * configure: Regenerate.
269 2005-12-14 Chao-ying Fu <fu@mips.com>
271 * Makefile.in (SIM_OBJS): Add dsp.o.
272 (dsp.o): New dependency.
273 (IGEN_INCLUDE): Add dsp.igen.
274 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
275 mipsisa64*-*-*): Add dsp to sim_igen_machine.
276 * configure: Regenerate.
277 * mips.igen: Add dsp model and include dsp.igen.
278 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
279 because these instructions are extended in DSP ASE.
280 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
281 adding 6 DSP accumulator registers and 1 DSP control register.
282 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
283 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
284 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
285 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
286 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
287 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
288 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
289 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
290 DSPCR_CCOND_SMASK): New define.
291 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
292 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
294 2005-07-08 Ian Lance Taylor <ian@airs.com>
296 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
298 2005-06-16 David Ung <davidu@mips.com>
299 Nigel Stephens <nigel@mips.com>
301 * mips.igen: New mips16e model and include m16e.igen.
302 (check_u64): Add mips16e tag.
303 * m16e.igen: New file for MIPS16e instructions.
304 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
305 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
307 * configure: Regenerate.
309 2005-05-26 David Ung <davidu@mips.com>
311 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
312 tags to all instructions which are applicable to the new ISAs.
313 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
315 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
317 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
319 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
320 * configure: Regenerate.
322 2005-03-23 Mark Kettenis <kettenis@gnu.org>
324 * configure: Regenerate.
326 2005-01-14 Andrew Cagney <cagney@gnu.org>
328 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
329 explicit call to AC_CONFIG_HEADER.
330 * configure: Regenerate.
332 2005-01-12 Andrew Cagney <cagney@gnu.org>
334 * configure.ac: Update to use ../common/common.m4.
335 * configure: Re-generate.
337 2005-01-11 Andrew Cagney <cagney@localhost.localdomain>
339 * configure: Regenerated to track ../common/aclocal.m4 changes.
341 2005-01-07 Andrew Cagney <cagney@gnu.org>
343 * configure.ac: Rename configure.in, require autoconf 2.59.
344 * configure: Re-generate.
346 2004-12-08 Hans-Peter Nilsson <hp@axis.com>
348 * configure: Regenerate for ../common/aclocal.m4 update.
350 2004-09-24 Monika Chaddha <monika@acmet.com>
352 Committed by Andrew Cagney.
353 * m16.igen (CMP, CMPI): Fix assembler.
355 2004-08-18 Chris Demetriou <cgd@broadcom.com>
357 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
358 * configure: Regenerate.
360 2004-06-25 Chris Demetriou <cgd@broadcom.com>
362 * configure.in (sim_m16_machine): Include mipsIII.
363 * configure: Regenerate.
365 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
367 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
369 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
371 2004-04-10 Chris Demetriou <cgd@broadcom.com>
373 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
375 2004-04-09 Chris Demetriou <cgd@broadcom.com>
377 * mips.igen (check_fmt): Remove.
378 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
379 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
380 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
381 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
382 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
383 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
384 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
385 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
386 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
387 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
389 2004-04-09 Chris Demetriou <cgd@broadcom.com>
391 * sb1.igen (check_sbx): New function.
392 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
394 2004-03-29 Chris Demetriou <cgd@broadcom.com>
395 Richard Sandiford <rsandifo@redhat.com>
397 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
398 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
399 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
400 separate implementations for mipsIV and mipsV. Use new macros to
401 determine whether the restrictions apply.
403 2004-01-19 Chris Demetriou <cgd@broadcom.com>
405 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
406 (check_mult_hilo): Improve comments.
407 (check_div_hilo): Likewise. Also, fork off a new version
408 to handle mips32/mips64 (since there are no hazards to check
411 2003-06-17 Richard Sandiford <rsandifo@redhat.com>
413 * mips.igen (do_dmultx): Fix check for negative operands.
415 2003-05-16 Ian Lance Taylor <ian@airs.com>
417 * Makefile.in (SHELL): Make sure this is defined.
418 (various): Use $(SHELL) whenever we invoke move-if-change.
420 2003-05-03 Chris Demetriou <cgd@broadcom.com>
422 * cp1.c: Tweak attribution slightly.
425 * mdmx.igen: Likewise.
426 * mips3d.igen: Likewise.
427 * sb1.igen: Likewise.
429 2003-04-15 Richard Sandiford <rsandifo@redhat.com>
431 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
434 2003-02-27 Andrew Cagney <cagney@redhat.com>
436 * interp.c (sim_open): Rename _bfd to bfd.
437 (sim_create_inferior): Ditto.
439 2003-01-14 Chris Demetriou <cgd@broadcom.com>
441 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
443 2003-01-14 Chris Demetriou <cgd@broadcom.com>
445 * mips.igen (EI, DI): Remove.
447 2003-01-05 Richard Sandiford <rsandifo@redhat.com>
449 * Makefile.in (tmp-run-multi): Fix mips16 filter.
451 2003-01-04 Richard Sandiford <rsandifo@redhat.com>
452 Andrew Cagney <ac131313@redhat.com>
453 Gavin Romig-Koch <gavin@redhat.com>
454 Graydon Hoare <graydon@redhat.com>
455 Aldy Hernandez <aldyh@redhat.com>
456 Dave Brolley <brolley@redhat.com>
457 Chris Demetriou <cgd@broadcom.com>
459 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
460 (sim_mach_default): New variable.
461 (mips64vr-*-*, mips64vrel-*-*): New configurations.
462 Add a new simulator generator, MULTI.
463 * configure: Regenerate.
464 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
465 (multi-run.o): New dependency.
466 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
467 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
468 (tmp-multi): Combine them.
469 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
470 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
471 (distclean-extra): New rule.
472 * sim-main.h: Include bfd.h.
473 (MIPS_MACH): New macro.
474 * mips.igen (vr4120, vr5400, vr5500): New models.
475 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
476 * vr.igen: Replace with new version.
478 2003-01-04 Chris Demetriou <cgd@broadcom.com>
480 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
481 * configure: Regenerate.
483 2002-12-31 Chris Demetriou <cgd@broadcom.com>
485 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
486 * mips.igen: Remove all invocations of check_branch_bug and
489 2002-12-16 Chris Demetriou <cgd@broadcom.com>
491 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
493 2002-07-30 Chris Demetriou <cgd@broadcom.com>
495 * mips.igen (do_load_double, do_store_double): New functions.
496 (LDC1, SDC1): Rename to...
497 (LDC1b, SDC1b): respectively.
498 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
500 2002-07-29 Michael Snyder <msnyder@redhat.com>
502 * cp1.c (fp_recip2): Modify initialization expression so that
503 GCC will recognize it as constant.
505 2002-06-18 Chris Demetriou <cgd@broadcom.com>
507 * mdmx.c (SD_): Delete.
508 (Unpredictable): Re-define, for now, to directly invoke
509 unpredictable_action().
510 (mdmx_acc_op): Fix error in .ob immediate handling.
512 2002-06-18 Andrew Cagney <cagney@redhat.com>
514 * interp.c (sim_firmware_command): Initialize `address'.
516 2002-06-16 Andrew Cagney <ac131313@redhat.com>
518 * configure: Regenerated to track ../common/aclocal.m4 changes.
520 2002-06-14 Chris Demetriou <cgd@broadcom.com>
521 Ed Satterthwaite <ehs@broadcom.com>
523 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
524 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
525 * mips.igen: Include mips3d.igen.
526 (mips3d): New model name for MIPS-3D ASE instructions.
527 (CVT.W.fmt): Don't use this instruction for word (source) format
529 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
530 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
531 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
532 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
533 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
534 (RSquareRoot1, RSquareRoot2): New macros.
535 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
536 (fp_rsqrt2): New functions.
537 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
538 * configure: Regenerate.
540 2002-06-13 Chris Demetriou <cgd@broadcom.com>
541 Ed Satterthwaite <ehs@broadcom.com>
543 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
544 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
545 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
546 (convert): Note that this function is not used for paired-single
548 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
549 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
550 (check_fmt_p): Enable paired-single support.
551 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
552 (PUU.PS): New instructions.
553 (CVT.S.fmt): Don't use this instruction for paired-single format
555 * sim-main.h (FP_formats): New value 'fmt_ps.'
556 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
557 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
559 2002-06-12 Chris Demetriou <cgd@broadcom.com>
561 * mips.igen: Fix formatting of function calls in
564 2002-06-12 Chris Demetriou <cgd@broadcom.com>
566 * mips.igen (MOVN, MOVZ): Trace result.
567 (TNEI): Print "tnei" as the opcode name in traces.
568 (CEIL.W): Add disassembly string for traces.
569 (RSQRT.fmt): Make location of disassembly string consistent
570 with other instructions.
572 2002-06-12 Chris Demetriou <cgd@broadcom.com>
574 * mips.igen (X): Delete unused function.
576 2002-06-08 Andrew Cagney <cagney@redhat.com>
578 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
580 2002-06-07 Chris Demetriou <cgd@broadcom.com>
581 Ed Satterthwaite <ehs@broadcom.com>
583 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
584 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
585 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
586 (fp_nmsub): New prototypes.
587 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
588 (NegMultiplySub): New defines.
589 * mips.igen (RSQRT.fmt): Use RSquareRoot().
590 (MADD.D, MADD.S): Replace with...
591 (MADD.fmt): New instruction.
592 (MSUB.D, MSUB.S): Replace with...
593 (MSUB.fmt): New instruction.
594 (NMADD.D, NMADD.S): Replace with...
595 (NMADD.fmt): New instruction.
596 (NMSUB.D, MSUB.S): Replace with...
597 (NMSUB.fmt): New instruction.
599 2002-06-07 Chris Demetriou <cgd@broadcom.com>
600 Ed Satterthwaite <ehs@broadcom.com>
602 * cp1.c: Fix more comment spelling and formatting.
603 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
604 (denorm_mode): New function.
605 (fpu_unary, fpu_binary): Round results after operation, collect
606 status from rounding operations, and update the FCSR.
607 (convert): Collect status from integer conversions and rounding
608 operations, and update the FCSR. Adjust NaN values that result
609 from conversions. Convert to use sim_io_eprintf rather than
610 fprintf, and remove some debugging code.
611 * cp1.h (fenr_FS): New define.
613 2002-06-07 Chris Demetriou <cgd@broadcom.com>
615 * cp1.c (convert): Remove unusable debugging code, and move MIPS
616 rounding mode to sim FP rounding mode flag conversion code into...
617 (rounding_mode): New function.
619 2002-06-07 Chris Demetriou <cgd@broadcom.com>
621 * cp1.c: Clean up formatting of a few comments.
622 (value_fpr): Reformat switch statement.
624 2002-06-06 Chris Demetriou <cgd@broadcom.com>
625 Ed Satterthwaite <ehs@broadcom.com>
628 * sim-main.h: Include cp1.h.
629 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
630 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
631 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
632 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
633 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
634 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
635 * cp1.c: Don't include sim-fpu.h; already included by
636 sim-main.h. Clean up formatting of some comments.
637 (NaN, Equal, Less): Remove.
638 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
639 (fp_cmp): New functions.
640 * mips.igen (do_c_cond_fmt): Remove.
641 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
642 Compare. Add result tracing.
643 (CxC1): Remove, replace with...
644 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
645 (DMxC1): Remove, replace with...
646 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
647 (MxC1): Remove, replace with...
648 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
650 2002-06-04 Chris Demetriou <cgd@broadcom.com>
652 * sim-main.h (FGRIDX): Remove, replace all uses with...
653 (FGR_BASE): New macro.
654 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
655 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
656 (NR_FGR, FGR): Likewise.
657 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
658 * mips.igen: Likewise.
660 2002-06-04 Chris Demetriou <cgd@broadcom.com>
662 * cp1.c: Add an FSF Copyright notice to this file.
664 2002-06-04 Chris Demetriou <cgd@broadcom.com>
665 Ed Satterthwaite <ehs@broadcom.com>
667 * cp1.c (Infinity): Remove.
668 * sim-main.h (Infinity): Likewise.
670 * cp1.c (fp_unary, fp_binary): New functions.
671 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
672 (fp_sqrt): New functions, implemented in terms of the above.
673 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
674 (Recip, SquareRoot): Remove (replaced by functions above).
675 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
676 (fp_recip, fp_sqrt): New prototypes.
677 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
678 (Recip, SquareRoot): Replace prototypes with #defines which
679 invoke the functions above.
681 2002-06-03 Chris Demetriou <cgd@broadcom.com>
683 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
684 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
685 file, remove PARAMS from prototypes.
686 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
687 simulator state arguments.
688 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
689 pass simulator state arguments.
690 * cp1.c (SD): Redefine as CPU_STATE(cpu).
691 (store_fpr, convert): Remove 'sd' argument.
692 (value_fpr): Likewise. Convert to use 'SD' instead.
694 2002-06-03 Chris Demetriou <cgd@broadcom.com>
696 * cp1.c (Min, Max): Remove #if 0'd functions.
697 * sim-main.h (Min, Max): Remove.
699 2002-06-03 Chris Demetriou <cgd@broadcom.com>
701 * cp1.c: fix formatting of switch case and default labels.
702 * interp.c: Likewise.
703 * sim-main.c: Likewise.
705 2002-06-03 Chris Demetriou <cgd@broadcom.com>
707 * cp1.c: Clean up comments which describe FP formats.
708 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
710 2002-06-03 Chris Demetriou <cgd@broadcom.com>
711 Ed Satterthwaite <ehs@broadcom.com>
713 * configure.in (mipsisa64sb1*-*-*): New target for supporting
714 Broadcom SiByte SB-1 processor configurations.
715 * configure: Regenerate.
716 * sb1.igen: New file.
717 * mips.igen: Include sb1.igen.
719 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
720 * mdmx.igen: Add "sb1" model to all appropriate functions and
722 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
723 (ob_func, ob_acc): Reference the above.
724 (qh_acc): Adjust to keep the same size as ob_acc.
725 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
726 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
728 2002-06-03 Chris Demetriou <cgd@broadcom.com>
730 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
732 2002-06-02 Chris Demetriou <cgd@broadcom.com>
733 Ed Satterthwaite <ehs@broadcom.com>
735 * mips.igen (mdmx): New (pseudo-)model.
736 * mdmx.c, mdmx.igen: New files.
737 * Makefile.in (SIM_OBJS): Add mdmx.o.
738 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
740 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
741 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
742 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
743 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
744 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
745 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
746 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
747 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
748 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
749 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
750 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
751 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
752 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
753 (qh_fmtsel): New macros.
754 (_sim_cpu): New member "acc".
755 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
756 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
758 2002-05-01 Chris Demetriou <cgd@broadcom.com>
760 * interp.c: Use 'deprecated' rather than 'depreciated.'
761 * sim-main.h: Likewise.
763 2002-05-01 Chris Demetriou <cgd@broadcom.com>
765 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
766 which wouldn't compile anyway.
767 * sim-main.h (unpredictable_action): New function prototype.
768 (Unpredictable): Define to call igen function unpredictable().
769 (NotWordValue): New macro to call igen function not_word_value().
770 (UndefinedResult): Remove.
771 * interp.c (undefined_result): Remove.
772 (unpredictable_action): New function.
773 * mips.igen (not_word_value, unpredictable): New functions.
774 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
775 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
776 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
777 NotWordValue() to check for unpredictable inputs, then
778 Unpredictable() to handle them.
780 2002-02-24 Chris Demetriou <cgd@broadcom.com>
782 * mips.igen: Fix formatting of calls to Unpredictable().
784 2002-04-20 Andrew Cagney <ac131313@redhat.com>
786 * interp.c (sim_open): Revert previous change.
788 2002-04-18 Alexandre Oliva <aoliva@redhat.com>
790 * interp.c (sim_open): Disable chunk of code that wrote code in
791 vector table entries.
793 2002-03-19 Chris Demetriou <cgd@broadcom.com>
795 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
796 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
799 2002-03-19 Chris Demetriou <cgd@broadcom.com>
801 * cp1.c: Fix many formatting issues.
803 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
805 * cp1.c (fpu_format_name): New function to replace...
806 (DOFMT): This. Delete, and update all callers.
807 (fpu_rounding_mode_name): New function to replace...
808 (RMMODE): This. Delete, and update all callers.
810 2002-03-19 Chris G. Demetriou <cgd@broadcom.com>
812 * interp.c: Move FPU support routines from here to...
813 * cp1.c: Here. New file.
814 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
817 2002-03-12 Chris Demetriou <cgd@broadcom.com>
819 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
820 * mips.igen (mips32, mips64): New models, add to all instructions
821 and functions as appropriate.
822 (loadstore_ea, check_u64): New variant for model mips64.
823 (check_fmt_p): New variant for models mipsV and mips64, remove
824 mipsV model marking fro other variant.
827 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
828 for mips32 and mips64.
829 (DCLO, DCLZ): New instructions for mips64.
831 2002-03-07 Chris Demetriou <cgd@broadcom.com>
833 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
834 immediate or code as a hex value with the "%#lx" format.
835 (ANDI): Likewise, and fix printed instruction name.
837 2002-03-05 Chris Demetriou <cgd@broadcom.com>
839 * sim-main.h (UndefinedResult, Unpredictable): New macros
840 which currently do nothing.
842 2002-03-05 Chris Demetriou <cgd@broadcom.com>
844 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
845 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
846 (status_CU3): New definitions.
848 * sim-main.h (ExceptionCause): Add new values for MIPS32
849 and MIPS64: MDMX, MCheck, CacheErr. Update comments
850 for DebugBreakPoint and NMIReset to note their status in
852 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
853 (SignalExceptionCacheErr): New exception macros.
855 2002-03-05 Chris Demetriou <cgd@broadcom.com>
857 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
858 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
860 (SignalExceptionCoProcessorUnusable): Take as argument the
861 unusable coprocessor number.
863 2002-03-05 Chris Demetriou <cgd@broadcom.com>
865 * mips.igen: Fix formatting of all SignalException calls.
867 2002-03-05 Chris Demetriou <cgd@broadcom.com>
869 * sim-main.h (SIGNEXTEND): Remove.
871 2002-03-04 Chris Demetriou <cgd@broadcom.com>
873 * mips.igen: Remove gencode comment from top of file, fix
874 spelling in another comment.
876 2002-03-04 Chris Demetriou <cgd@broadcom.com>
878 * mips.igen (check_fmt, check_fmt_p): New functions to check
879 whether specific floating point formats are usable.
880 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
881 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
882 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
883 Use the new functions.
884 (do_c_cond_fmt): Remove format checks...
885 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
887 2002-03-03 Chris Demetriou <cgd@broadcom.com>
889 * mips.igen: Fix formatting of check_fpu calls.
891 2002-03-03 Chris Demetriou <cgd@broadcom.com>
893 * mips.igen (FLOOR.L.fmt): Store correct destination register.
895 2002-03-03 Chris Demetriou <cgd@broadcom.com>
897 * mips.igen: Remove whitespace at end of lines.
899 2002-03-02 Chris Demetriou <cgd@broadcom.com>
901 * mips.igen (loadstore_ea): New function to do effective
902 address calculations.
903 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
904 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
905 CACHE): Use loadstore_ea to do effective address computations.
907 2002-03-02 Chris Demetriou <cgd@broadcom.com>
909 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
910 * mips.igen (LL, CxC1, MxC1): Likewise.
912 2002-03-02 Chris Demetriou <cgd@broadcom.com>
914 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
915 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
916 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
917 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
918 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
919 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
920 Don't split opcode fields by hand, use the opcode field values
923 2002-03-01 Chris Demetriou <cgd@broadcom.com>
925 * mips.igen (do_divu): Fix spacing.
927 * mips.igen (do_dsllv): Move to be right before DSLLV,
928 to match the rest of the do_<shift> functions.
930 2002-03-01 Chris Demetriou <cgd@broadcom.com>
932 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
933 DSRL32, do_dsrlv): Trace inputs and results.
935 2002-03-01 Chris Demetriou <cgd@broadcom.com>
937 * mips.igen (CACHE): Provide instruction-printing string.
939 * interp.c (signal_exception): Comment tokens after #endif.
941 2002-02-28 Chris Demetriou <cgd@broadcom.com>
943 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
944 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
945 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
946 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
947 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
948 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
949 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
950 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
952 2002-02-28 Chris Demetriou <cgd@broadcom.com>
954 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
955 instruction-printing string.
956 (LWU): Use '64' as the filter flag.
958 2002-02-28 Chris Demetriou <cgd@broadcom.com>
960 * mips.igen (SDXC1): Fix instruction-printing string.
962 2002-02-28 Chris Demetriou <cgd@broadcom.com>
964 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
967 2002-02-27 Chris Demetriou <cgd@broadcom.com>
969 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
972 2002-02-27 Chris Demetriou <cgd@broadcom.com>
974 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
975 add a comma) so that it more closely match the MIPS ISA
976 documentation opcode partitioning.
977 (PREF): Put useful names on opcode fields, and include
978 instruction-printing string.
980 2002-02-27 Chris Demetriou <cgd@broadcom.com>
982 * mips.igen (check_u64): New function which in the future will
983 check whether 64-bit instructions are usable and signal an
984 exception if not. Currently a no-op.
985 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
986 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
987 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
988 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
990 * mips.igen (check_fpu): New function which in the future will
991 check whether FPU instructions are usable and signal an exception
992 if not. Currently a no-op.
993 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
994 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
995 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
996 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
997 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
998 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
999 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1000 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1002 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1004 * mips.igen (do_load_left, do_load_right): Move to be immediately
1006 (do_store_left, do_store_right): Move to be immediately following
1009 2002-02-27 Chris Demetriou <cgd@broadcom.com>
1011 * mips.igen (mipsV): New model name. Also, add it to
1012 all instructions and functions where it is appropriate.
1014 2002-02-18 Chris Demetriou <cgd@broadcom.com>
1016 * mips.igen: For all functions and instructions, list model
1017 names that support that instruction one per line.
1019 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1021 * mips.igen: Add some additional comments about supported
1022 models, and about which instructions go where.
1023 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1024 order as is used in the rest of the file.
1026 2002-02-11 Chris Demetriou <cgd@broadcom.com>
1028 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1029 indicating that ALU32_END or ALU64_END are there to check
1031 (DADD): Likewise, but also remove previous comment about
1034 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1036 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1037 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1038 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1039 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1040 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1041 fields (i.e., add and move commas) so that they more closely
1042 match the MIPS ISA documentation opcode partitioning.
1044 2002-02-10 Chris Demetriou <cgd@broadcom.com>
1046 * mips.igen (ADDI): Print immediate value.
1047 (BREAK): Print code.
1048 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1049 (SLL): Print "nop" specially, and don't run the code
1050 that does the shift for the "nop" case.
1052 2001-11-17 Fred Fish <fnf@redhat.com>
1054 * sim-main.h (float_operation): Move enum declaration outside
1055 of _sim_cpu struct declaration.
1057 2001-04-12 Jim Blandy <jimb@redhat.com>
1059 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1060 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1062 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1063 PENDING_FILL, and you can get the intended effect gracefully by
1064 calling PENDING_SCHED directly.
1066 2001-02-23 Ben Elliston <bje@redhat.com>
1068 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1069 already defined elsewhere.
1071 2001-02-19 Ben Elliston <bje@redhat.com>
1073 * sim-main.h (sim_monitor): Return an int.
1074 * interp.c (sim_monitor): Add return values.
1075 (signal_exception): Handle error conditions from sim_monitor.
1077 2001-02-08 Ben Elliston <bje@redhat.com>
1079 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1080 (store_memory): Likewise, pass cia to sim_core_write*.
1082 2000-10-19 Frank Ch. Eigler <fche@redhat.com>
1084 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1085 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1087 Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1089 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1090 * Makefile.in: Don't delete *.igen when cleaning directory.
1092 Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1094 * m16.igen (break): Call SignalException not sim_engine_halt.
1096 Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1098 From Jason Eckhardt:
1099 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1101 Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1103 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1105 2000-05-24 Michael Hayes <mhayes@cygnus.com>
1107 * mips.igen (do_dmultx): Fix typo.
1109 Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1111 * configure: Regenerated to track ../common/aclocal.m4 changes.
1113 Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1115 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1117 2000-04-12 Frank Ch. Eigler <fche@redhat.com>
1119 * sim-main.h (GPR_CLEAR): Define macro.
1121 Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1123 * interp.c (decode_coproc): Output long using %lx and not %s.
1125 2000-03-21 Frank Ch. Eigler <fche@redhat.com>
1127 * interp.c (sim_open): Sort & extend dummy memory regions for
1128 --board=jmr3904 for eCos.
1130 2000-03-02 Frank Ch. Eigler <fche@redhat.com>
1132 * configure: Regenerated.
1134 Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1136 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1137 calls, conditional on the simulator being in verbose mode.
1139 Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1141 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1142 cache don't get ReservedInstruction traps.
1144 1999-11-29 Mark Salter <msalter@cygnus.com>
1146 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1147 to clear status bits in sdisr register. This is how the hardware works.
1149 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1150 being used by cygmon.
1152 1999-11-11 Andrew Haley <aph@cygnus.com>
1154 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1157 Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1159 * mips.igen (MULT): Correct previous mis-applied patch.
1161 Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1163 * mips.igen (delayslot32): Handle sequence like
1164 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1165 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1166 (MULT): Actually pass the third register...
1168 1999-09-03 Mark Salter <msalter@cygnus.com>
1170 * interp.c (sim_open): Added more memory aliases for additional
1171 hardware being touched by cygmon on jmr3904 board.
1173 Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1175 * configure: Regenerated to track ../common/aclocal.m4 changes.
1177 Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1179 * interp.c (sim_store_register): Handle case where client - GDB -
1180 specifies that a 4 byte register is 8 bytes in size.
1181 (sim_fetch_register): Ditto.
1183 1999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1185 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1186 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1187 (idt_monitor_base): Base address for IDT monitor traps.
1188 (pmon_monitor_base): Ditto for PMON.
1189 (lsipmon_monitor_base): Ditto for LSI PMON.
1190 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1191 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1192 (sim_firmware_command): New function.
1193 (mips_option_handler): Call it for OPTION_FIRMWARE.
1194 (sim_open): Allocate memory for idt_monitor region. If "--board"
1195 option was given, add no monitor by default. Add BREAK hooks only if
1196 monitors are also there.
1198 Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1200 * interp.c (sim_monitor): Flush output before reading input.
1202 Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1204 * tconfig.in (SIM_HANDLES_LMA): Always define.
1206 Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1208 From Mark Salter <msalter@cygnus.com>:
1209 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1210 (sim_open): Add setup for BSP board.
1212 Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1214 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1215 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1216 them as unimplemented.
1218 1999-05-08 Felix Lee <flee@cygnus.com>
1220 * configure: Regenerated to track ../common/aclocal.m4 changes.
1222 1999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1224 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1226 Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1228 * configure.in: Any mips64vr5*-*-* target should have
1229 -DTARGET_ENABLE_FR=1.
1230 (default_endian): Any mips64vr*el-*-* target should default to
1232 * configure: Re-generate.
1234 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1236 * mips.igen (ldl): Extend from _16_, not 32.
1238 Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1240 * interp.c (sim_store_register): Force registers written to by GDB
1241 into an un-interpreted state.
1243 1999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1245 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1246 CPU, start periodic background I/O polls.
1247 (tx3904sio_poll): New function: periodic I/O poller.
1249 1998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1251 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1253 Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1255 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1258 1998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1260 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1261 (load_word): Call SIM_CORE_SIGNAL hook on error.
1262 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1263 starting. For exception dispatching, pass PC instead of NULL_CIA.
1264 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1265 * sim-main.h (COP0_BADVADDR): Define.
1266 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1267 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1268 (_sim_cpu): Add exc_* fields to store register value snapshots.
1269 * mips.igen (*): Replace memory-related SignalException* calls
1270 with references to SIM_CORE_SIGNAL hook.
1272 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1274 * sim-main.c (*): Minor warning cleanups.
1276 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1278 * m16.igen (DADDIU5): Correct type-o.
1280 Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1282 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1285 Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1287 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1289 (interp.o): Add dependency on itable.h
1290 (oengine.c, gencode): Delete remaining references.
1291 (BUILT_SRC_FROM_GEN): Clean up.
1293 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1296 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1297 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1298 tmp-run-hack) : New.
1299 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1300 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1301 Drop the "64" qualifier to get the HACK generator working.
1302 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1303 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1304 qualifier to get the hack generator working.
1305 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1306 (DSLL): Use do_dsll.
1307 (DSLLV): Use do_dsllv.
1308 (DSRA): Use do_dsra.
1309 (DSRL): Use do_dsrl.
1310 (DSRLV): Use do_dsrlv.
1311 (BC1): Move *vr4100 to get the HACK generator working.
1312 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1313 get the HACK generator working.
1314 (MACC) Rename to get the HACK generator working.
1315 (DMACC,MACCS,DMACCS): Add the 64.
1317 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1319 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1320 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1322 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1324 * mips/interp.c (DEBUG): Cleanups.
1326 1998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1328 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1329 (tx3904sio_tickle): fflush after a stdout character output.
1331 1998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1333 * interp.c (sim_close): Uninstall modules.
1335 Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1337 * sim-main.h, interp.c (sim_monitor): Change to global
1340 Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1342 * configure.in (vr4100): Only include vr4100 instructions in
1344 * configure: Re-generate.
1345 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1347 Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1349 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1350 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1353 * configure.in (sim_default_gen, sim_use_gen): Replace with
1355 (--enable-sim-igen): Delete config option. Always using IGEN.
1356 * configure: Re-generate.
1358 * Makefile.in (gencode): Kill, kill, kill.
1361 Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1363 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1364 bit mips16 igen simulator.
1365 * configure: Re-generate.
1367 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1368 as part of vr4100 ISA.
1369 * vr.igen: Mark all instructions as 64 bit only.
1371 Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1373 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1376 Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1378 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1379 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1380 * configure: Re-generate.
1382 * m16.igen (BREAK): Define breakpoint instruction.
1383 (JALX32): Mark instruction as mips16 and not r3900.
1384 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1386 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1388 Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1390 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1391 insn as a debug breakpoint.
1393 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1395 (PENDING_SCHED): Clean up trace statement.
1396 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1397 (PENDING_FILL): Delay write by only one cycle.
1398 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1400 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1402 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1404 (pending_tick): Move incrementing of index to FOR statement.
1405 (pending_tick): Only update PENDING_OUT after a write has occured.
1407 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1409 * configure: Re-generate.
1411 * interp.c (sim_engine_run OLD): Delete explicit call to
1412 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1414 Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1416 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1417 interrupt level number to match changed SignalExceptionInterrupt
1420 Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1422 * interp.c: #include "itable.h" if WITH_IGEN.
1423 (get_insn_name): New function.
1424 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1425 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1427 Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1429 * configure: Rebuilt to inhale new common/aclocal.m4.
1431 Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1433 * dv-tx3904sio.c: Include sim-assert.h.
1435 Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1437 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1438 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1439 Reorganize target-specific sim-hardware checks.
1440 * configure: rebuilt.
1441 * interp.c (sim_open): For tx39 target boards, set
1442 OPERATING_ENVIRONMENT, add tx3904sio devices.
1443 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1444 ROM executables. Install dv-sockser into sim-modules list.
1446 * dv-tx3904irc.c: Compiler warning clean-up.
1447 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1448 frequent hw-trace messages.
1450 Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1452 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1454 Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1456 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1458 * vr.igen: New file.
1459 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1460 * mips.igen: Define vr4100 model. Include vr.igen.
1461 Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1463 * mips.igen (check_mf_hilo): Correct check.
1465 Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1467 * sim-main.h (interrupt_event): Add prototype.
1469 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1470 register_ptr, register_value.
1471 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1473 * sim-main.h (tracefh): Make extern.
1475 Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1477 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1478 Reduce unnecessarily high timer event frequency.
1479 * dv-tx3904cpu.c: Ditto for interrupt event.
1481 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1483 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1485 (interrupt_event): Made non-static.
1487 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1488 interchange of configuration values for external vs. internal
1491 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1493 * mips.igen (BREAK): Moved code to here for
1494 simulator-reserved break instructions.
1495 * gencode.c (build_instruction): Ditto.
1496 * interp.c (signal_exception): Code moved from here. Non-
1497 reserved instructions now use exception vector, rather
1499 * sim-main.h: Moved magic constants to here.
1501 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1503 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1504 register upon non-zero interrupt event level, clear upon zero
1506 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1507 by passing zero event value.
1508 (*_io_{read,write}_buffer): Endianness fixes.
1509 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1510 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1512 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1513 serial I/O and timer module at base address 0xFFFF0000.
1515 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1517 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1520 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1522 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1524 * configure: Update.
1526 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1528 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1529 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1530 * configure.in: Include tx3904tmr in hw_device list.
1531 * configure: Rebuilt.
1532 * interp.c (sim_open): Instantiate three timer instances.
1533 Fix address typo of tx3904irc instance.
1535 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1537 * interp.c (signal_exception): SystemCall exception now uses
1538 the exception vector.
1540 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1542 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1545 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1547 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1549 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1551 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1553 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1554 sim-main.h. Declare a struct hw_descriptor instead of struct
1555 hw_device_descriptor.
1557 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1559 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1560 right bits and then re-align left hand bytes to correct byte
1561 lanes. Fix incorrect computation in do_store_left when loading
1562 bytes from second word.
1564 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1566 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1567 * interp.c (sim_open): Only create a device tree when HW is
1570 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1571 * interp.c (signal_exception): Ditto.
1573 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1575 * gencode.c: Mark BEGEZALL as LIKELY.
1577 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1579 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1580 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1582 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1584 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1585 modules. Recognize TX39 target with "mips*tx39" pattern.
1586 * configure: Rebuilt.
1587 * sim-main.h (*): Added many macros defining bits in
1588 TX39 control registers.
1589 (SignalInterrupt): Send actual PC instead of NULL.
1590 (SignalNMIReset): New exception type.
1591 * interp.c (board): New variable for future use to identify
1592 a particular board being simulated.
1593 (mips_option_handler,mips_options): Added "--board" option.
1594 (interrupt_event): Send actual PC.
1595 (sim_open): Make memory layout conditional on board setting.
1596 (signal_exception): Initial implementation of hardware interrupt
1597 handling. Accept another break instruction variant for simulator
1599 (decode_coproc): Implement RFE instruction for TX39.
1600 (mips.igen): Decode RFE instruction as such.
1601 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1602 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1603 bbegin to implement memory map.
1604 * dv-tx3904cpu.c: New file.
1605 * dv-tx3904irc.c: New file.
1607 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1609 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1611 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1613 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1614 with calls to check_div_hilo.
1616 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1618 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1619 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1620 Add special r3900 version of do_mult_hilo.
1621 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1622 with calls to check_mult_hilo.
1623 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1624 with calls to check_div_hilo.
1626 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1628 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1629 Document a replacement.
1631 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1633 * interp.c (sim_monitor): Make mon_printf work.
1635 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1637 * sim-main.h (INSN_NAME): New arg `cpu'.
1639 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1641 * configure: Regenerated to track ../common/aclocal.m4 changes.
1643 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1645 * configure: Regenerated to track ../common/aclocal.m4 changes.
1648 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1650 * acconfig.h: New file.
1651 * configure.in: Reverted change of Apr 24; use sinclude again.
1653 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1655 * configure: Regenerated to track ../common/aclocal.m4 changes.
1658 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1660 * configure.in: Don't call sinclude.
1662 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1664 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1666 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1668 * mips.igen (ERET): Implement.
1670 * interp.c (decode_coproc): Return sign-extended EPC.
1672 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1674 * interp.c (signal_exception): Do not ignore Trap.
1675 (signal_exception): On TRAP, restart at exception address.
1676 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1677 (signal_exception): Update.
1678 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1679 so that TRAP instructions are caught.
1681 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1683 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1684 contains HI/LO access history.
1685 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1686 (HIACCESS, LOACCESS): Delete, replace with
1687 (HIHISTORY, LOHISTORY): New macros.
1688 (CHECKHILO): Delete all, moved to mips.igen
1690 * gencode.c (build_instruction): Do not generate checks for
1691 correct HI/LO register usage.
1693 * interp.c (old_engine_run): Delete checks for correct HI/LO
1696 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1697 check_mf_cycles): New functions.
1698 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1699 do_divu, domultx, do_mult, do_multu): Use.
1701 * tx.igen ("madd", "maddu"): Use.
1703 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1705 * mips.igen (DSRAV): Use function do_dsrav.
1706 (SRAV): Use new function do_srav.
1708 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1709 (B): Sign extend 11 bit immediate.
1710 (EXT-B*): Shift 16 bit immediate left by 1.
1711 (ADDIU*): Don't sign extend immediate value.
1713 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1715 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1717 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1720 * mips.igen (delayslot32, nullify_next_insn): New functions.
1721 (m16.igen): Always include.
1722 (do_*): Add more tracing.
1724 * m16.igen (delayslot16): Add NIA argument, could be called by a
1725 32 bit MIPS16 instruction.
1727 * interp.c (ifetch16): Move function from here.
1728 * sim-main.c (ifetch16): To here.
1730 * sim-main.c (ifetch16, ifetch32): Update to match current
1731 implementations of LH, LW.
1732 (signal_exception): Don't print out incorrect hex value of illegal
1735 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1737 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1740 * m16.igen: Implement MIPS16 instructions.
1742 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1743 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1744 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1745 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1746 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1747 bodies of corresponding code from 32 bit insn to these. Also used
1748 by MIPS16 versions of functions.
1750 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1751 (IMEM16): Drop NR argument from macro.
1753 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1755 * Makefile.in (SIM_OBJS): Add sim-main.o.
1757 * sim-main.h (address_translation, load_memory, store_memory,
1758 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1760 (pr_addr, pr_uword64): Declare.
1761 (sim-main.c): Include when H_REVEALS_MODULE_P.
1763 * interp.c (address_translation, load_memory, store_memory,
1764 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1766 * sim-main.c: To here. Fix compilation problems.
1768 * configure.in: Enable inlining.
1769 * configure: Re-config.
1771 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1773 * configure: Regenerated to track ../common/aclocal.m4 changes.
1775 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1777 * mips.igen: Include tx.igen.
1778 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1779 * tx.igen: New file, contains MADD and MADDU.
1781 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1782 the hardwired constant `7'.
1783 (store_memory): Ditto.
1784 (LOADDRMASK): Move definition to sim-main.h.
1786 mips.igen (MTC0): Enable for r3900.
1789 mips.igen (do_load_byte): Delete.
1790 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1791 do_store_right): New functions.
1792 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1794 configure.in: Let the tx39 use igen again.
1797 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1799 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1800 not an address sized quantity. Return zero for cache sizes.
1802 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1804 * mips.igen (r3900): r3900 does not support 64 bit integer
1807 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1809 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1811 * configure : Rebuild.
1813 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1815 * configure: Regenerated to track ../common/aclocal.m4 changes.
1817 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1819 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1821 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1823 * configure: Regenerated to track ../common/aclocal.m4 changes.
1824 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1826 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1828 * configure: Regenerated to track ../common/aclocal.m4 changes.
1830 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1832 * interp.c (Max, Min): Comment out functions. Not yet used.
1834 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1836 * configure: Regenerated to track ../common/aclocal.m4 changes.
1838 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1840 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1841 configurable settings for stand-alone simulator.
1843 * configure.in: Added X11 search, just in case.
1845 * configure: Regenerated.
1847 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1849 * interp.c (sim_write, sim_read, load_memory, store_memory):
1850 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1852 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1854 * sim-main.h (GETFCC): Return an unsigned value.
1856 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1858 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1859 (DADD): Result destination is RD not RT.
1861 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1863 * sim-main.h (HIACCESS, LOACCESS): Always define.
1865 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1867 * interp.c (sim_info): Delete.
1869 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1871 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1872 (mips_option_handler): New argument `cpu'.
1873 (sim_open): Update call to sim_add_option_table.
1875 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877 * mips.igen (CxC1): Add tracing.
1879 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1881 * sim-main.h (Max, Min): Declare.
1883 * interp.c (Max, Min): New functions.
1885 * mips.igen (BC1): Add tracing.
1887 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1889 * interp.c Added memory map for stack in vr4100
1891 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1893 * interp.c (load_memory): Add missing "break"'s.
1895 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1897 * interp.c (sim_store_register, sim_fetch_register): Pass in
1898 length parameter. Return -1.
1900 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1902 * interp.c: Added hardware init hook, fixed warnings.
1904 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1906 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1908 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1910 * interp.c (ifetch16): New function.
1912 * sim-main.h (IMEM32): Rename IMEM.
1913 (IMEM16_IMMED): Define.
1915 (DELAY_SLOT): Update.
1917 * m16run.c (sim_engine_run): New file.
1919 * m16.igen: All instructions except LB.
1920 (LB): Call do_load_byte.
1921 * mips.igen (do_load_byte): New function.
1922 (LB): Call do_load_byte.
1924 * mips.igen: Move spec for insn bit size and high bit from here.
1925 * Makefile.in (tmp-igen, tmp-m16): To here.
1927 * m16.dc: New file, decode mips16 instructions.
1929 * Makefile.in (SIM_NO_ALL): Define.
1930 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1932 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1934 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1935 point unit to 32 bit registers.
1936 * configure: Re-generate.
1938 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1940 * configure.in (sim_use_gen): Make IGEN the default simulator
1941 generator for generic 32 and 64 bit mips targets.
1942 * configure: Re-generate.
1944 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1946 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1949 * interp.c (sim_fetch_register, sim_store_register): Read/write
1950 FGR from correct location.
1951 (sim_open): Set size of FGR's according to
1952 WITH_TARGET_FLOATING_POINT_BITSIZE.
1954 * sim-main.h (FGR): Store floating point registers in a separate
1957 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1959 * configure: Regenerated to track ../common/aclocal.m4 changes.
1961 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1963 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1965 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1967 * interp.c (pending_tick): New function. Deliver pending writes.
1969 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1970 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1971 it can handle mixed sized quantites and single bits.
1973 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1975 * interp.c (oengine.h): Do not include when building with IGEN.
1976 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1977 (sim_info): Ditto for PROCESSOR_64BIT.
1978 (sim_monitor): Replace ut_reg with unsigned_word.
1979 (*): Ditto for t_reg.
1980 (LOADDRMASK): Define.
1981 (sim_open): Remove defunct check that host FP is IEEE compliant,
1982 using software to emulate floating point.
1983 (value_fpr, ...): Always compile, was conditional on HASFPU.
1985 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1987 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1990 * interp.c (SD, CPU): Define.
1991 (mips_option_handler): Set flags in each CPU.
1992 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1993 (sim_close): Do not clear STATE, deleted anyway.
1994 (sim_write, sim_read): Assume CPU zero's vm should be used for
1996 (sim_create_inferior): Set the PC for all processors.
1997 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1999 (mips16_entry): Pass correct nr of args to store_word, load_word.
2000 (ColdReset): Cold reset all cpu's.
2001 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2002 (sim_monitor, load_memory, store_memory, signal_exception): Use
2003 `CPU' instead of STATE_CPU.
2006 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2009 * sim-main.h (signal_exception): Add sim_cpu arg.
2010 (SignalException*): Pass both SD and CPU to signal_exception.
2011 * interp.c (signal_exception): Update.
2013 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2015 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2016 address_translation): Ditto
2017 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2019 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2021 * configure: Regenerated to track ../common/aclocal.m4 changes.
2023 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2025 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2027 * mips.igen (model): Map processor names onto BFD name.
2029 * sim-main.h (CPU_CIA): Delete.
2030 (SET_CIA, GET_CIA): Define
2032 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2034 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2037 * configure.in (default_endian): Configure a big-endian simulator
2039 * configure: Re-generate.
2041 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2043 * configure: Regenerated to track ../common/aclocal.m4 changes.
2045 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2047 * interp.c (sim_monitor): Handle Densan monitor outbyte
2048 and inbyte functions.
2050 1997-12-29 Felix Lee <flee@cygnus.com>
2052 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2054 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2056 * Makefile.in (tmp-igen): Arrange for $zero to always be
2057 reset to zero after every instruction.
2059 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2061 * configure: Regenerated to track ../common/aclocal.m4 changes.
2064 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2066 * mips.igen (MSUB): Fix to work like MADD.
2067 * gencode.c (MSUB): Similarly.
2069 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2071 * configure: Regenerated to track ../common/aclocal.m4 changes.
2073 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2075 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2077 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2079 * sim-main.h (sim-fpu.h): Include.
2081 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2082 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2083 using host independant sim_fpu module.
2085 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2087 * interp.c (signal_exception): Report internal errors with SIGABRT
2090 * sim-main.h (C0_CONFIG): New register.
2091 (signal.h): No longer include.
2093 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2095 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2097 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2099 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101 * mips.igen: Tag vr5000 instructions.
2102 (ANDI): Was missing mipsIV model, fix assembler syntax.
2103 (do_c_cond_fmt): New function.
2104 (C.cond.fmt): Handle mips I-III which do not support CC field
2106 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2107 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2109 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2110 vr5000 which saves LO in a GPR separatly.
2112 * configure.in (enable-sim-igen): For vr5000, select vr5000
2113 specific instructions.
2114 * configure: Re-generate.
2116 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2118 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2120 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2121 fmt_uninterpreted_64 bit cases to switch. Convert to
2124 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2126 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2127 as specified in IV3.2 spec.
2128 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2130 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2133 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2134 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2135 PENDING_FILL versions of instructions. Simplify.
2137 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2139 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2141 (MTHI, MFHI): Disable code checking HI-LO.
2143 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2145 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2147 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2149 * gencode.c (build_mips16_operands): Replace IPC with cia.
2151 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2152 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2154 (UndefinedResult): Replace function with macro/function
2156 (sim_engine_run): Don't save PC in IPC.
2158 * sim-main.h (IPC): Delete.
2161 * interp.c (signal_exception, store_word, load_word,
2162 address_translation, load_memory, store_memory, cache_op,
2163 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2164 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2165 current instruction address - cia - argument.
2166 (sim_read, sim_write): Call address_translation directly.
2167 (sim_engine_run): Rename variable vaddr to cia.
2168 (signal_exception): Pass cia to sim_monitor
2170 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2171 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2172 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2174 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2175 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2178 * interp.c (signal_exception): Pass restart address to
2181 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2182 idecode.o): Add dependency.
2184 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2186 (DELAY_SLOT): Update NIA not PC with branch address.
2187 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2189 * mips.igen: Use CIA not PC in branch calculations.
2190 (illegal): Call SignalException.
2191 (BEQ, ADDIU): Fix assembler.
2193 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2195 * m16.igen (JALX): Was missing.
2197 * configure.in (enable-sim-igen): New configuration option.
2198 * configure: Re-generate.
2200 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2202 * interp.c (load_memory, store_memory): Delete parameter RAW.
2203 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2204 bypassing {load,store}_memory.
2206 * sim-main.h (ByteSwapMem): Delete definition.
2208 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2210 * interp.c (sim_do_command, sim_commands): Delete mips specific
2211 commands. Handled by module sim-options.
2213 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2214 (WITH_MODULO_MEMORY): Define.
2216 * interp.c (sim_info): Delete code printing memory size.
2218 * interp.c (mips_size): Nee sim_size, delete function.
2220 (monitor, monitor_base, monitor_size): Delete global variables.
2221 (sim_open, sim_close): Delete code creating monitor and other
2222 memory regions. Use sim-memopts module, via sim_do_commandf, to
2223 manage memory regions.
2224 (load_memory, store_memory): Use sim-core for memory model.
2226 * interp.c (address_translation): Delete all memory map code
2227 except line forcing 32 bit addresses.
2229 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2231 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2234 * interp.c (logfh, logfile): Delete globals.
2235 (sim_open, sim_close): Delete code opening & closing log file.
2236 (mips_option_handler): Delete -l and -n options.
2237 (OPTION mips_options): Ditto.
2239 * interp.c (OPTION mips_options): Rename option trace to dinero.
2240 (mips_option_handler): Update.
2242 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2244 * interp.c (fetch_str): New function.
2245 (sim_monitor): Rewrite using sim_read & sim_write.
2246 (sim_open): Check magic number.
2247 (sim_open): Write monitor vectors into memory using sim_write.
2248 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2249 (sim_read, sim_write): Simplify - transfer data one byte at a
2251 (load_memory, store_memory): Clarify meaning of parameter RAW.
2253 * sim-main.h (isHOST): Defete definition.
2254 (isTARGET): Mark as depreciated.
2255 (address_translation): Delete parameter HOST.
2257 * interp.c (address_translation): Delete parameter HOST.
2259 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2263 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2264 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2266 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2268 * mips.igen: Add model filter field to records.
2270 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2272 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2274 interp.c (sim_engine_run): Do not compile function sim_engine_run
2275 when WITH_IGEN == 1.
2277 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2278 target architecture.
2280 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2281 igen. Replace with configuration variables sim_igen_flags /
2284 * m16.igen: New file. Copy mips16 insns here.
2285 * mips.igen: From here.
2287 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2289 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2291 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2293 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2295 * gencode.c (build_instruction): Follow sim_write's lead in using
2296 BigEndianMem instead of !ByteSwapMem.
2298 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2300 * configure.in (sim_gen): Dependent on target, select type of
2301 generator. Always select old style generator.
2303 configure: Re-generate.
2305 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2307 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2308 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2309 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2310 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2311 SIM_@sim_gen@_*, set by autoconf.
2313 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2315 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2317 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2318 CURRENT_FLOATING_POINT instead.
2320 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2321 (address_translation): Raise exception InstructionFetch when
2322 translation fails and isINSTRUCTION.
2324 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2325 sim_engine_run): Change type of of vaddr and paddr to
2327 (address_translation, prefetch, load_memory, store_memory,
2328 cache_op): Change type of vAddr and pAddr to address_word.
2330 * gencode.c (build_instruction): Change type of vaddr and paddr to
2333 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2335 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2336 macro to obtain result of ALU op.
2338 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2340 * interp.c (sim_info): Call profile_print.
2342 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2344 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2346 * sim-main.h (WITH_PROFILE): Do not define, defined in
2347 common/sim-config.h. Use sim-profile module.
2348 (simPROFILE): Delete defintion.
2350 * interp.c (PROFILE): Delete definition.
2351 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2352 (sim_close): Delete code writing profile histogram.
2353 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2355 (sim_engine_run): Delete code profiling the PC.
2357 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2359 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2361 * interp.c (sim_monitor): Make register pointers of type
2364 * sim-main.h: Make registers of type unsigned_word not
2367 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2369 * interp.c (sync_operation): Rename from SyncOperation, make
2370 global, add SD argument.
2371 (prefetch): Rename from Prefetch, make global, add SD argument.
2372 (decode_coproc): Make global.
2374 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2376 * gencode.c (build_instruction): Generate DecodeCoproc not
2377 decode_coproc calls.
2379 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2380 (SizeFGR): Move to sim-main.h
2381 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2382 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2383 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2385 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2386 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2387 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2388 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2389 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2390 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2392 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2394 (sim-alu.h): Include.
2395 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2396 (sim_cia): Typedef to instruction_address.
2398 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2400 * Makefile.in (interp.o): Rename generated file engine.c to
2405 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2407 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2409 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2411 * gencode.c (build_instruction): For "FPSQRT", output correct
2412 number of arguments to Recip.
2414 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2416 * Makefile.in (interp.o): Depends on sim-main.h
2418 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2420 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2421 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2422 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2423 STATE, DSSTATE): Define
2424 (GPR, FGRIDX, ..): Define.
2426 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2427 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2428 (GPR, FGRIDX, ...): Delete macros.
2430 * interp.c: Update names to match defines from sim-main.h
2432 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2434 * interp.c (sim_monitor): Add SD argument.
2435 (sim_warning): Delete. Replace calls with calls to
2437 (sim_error): Delete. Replace calls with sim_io_error.
2438 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2439 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2440 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2442 (mips_size): Rename from sim_size. Add SD argument.
2444 * interp.c (simulator): Delete global variable.
2445 (callback): Delete global variable.
2446 (mips_option_handler, sim_open, sim_write, sim_read,
2447 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2448 sim_size,sim_monitor): Use sim_io_* not callback->*.
2449 (sim_open): ZALLOC simulator struct.
2450 (PROFILE): Do not define.
2452 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2454 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2455 support.h with corresponding code.
2457 * sim-main.h (word64, uword64), support.h: Move definition to
2459 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2462 * Makefile.in: Update dependencies
2463 * interp.c: Do not include.
2465 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2467 * interp.c (address_translation, load_memory, store_memory,
2468 cache_op): Rename to from AddressTranslation et.al., make global,
2471 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2474 * interp.c (SignalException): Rename to signal_exception, make
2477 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2479 * sim-main.h (SignalException, SignalExceptionInterrupt,
2480 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2481 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2482 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2485 * interp.c, support.h: Use.
2487 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2489 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2490 to value_fpr / store_fpr. Add SD argument.
2491 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2492 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2494 * sim-main.h (ValueFPR, StoreFPR): Define.
2496 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2498 * interp.c (sim_engine_run): Check consistency between configure
2499 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2502 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2503 (mips_fpu): Configure WITH_FLOATING_POINT.
2504 (mips_endian): Configure WITH_TARGET_ENDIAN.
2505 * configure: Update.
2507 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2509 * configure: Regenerated to track ../common/aclocal.m4 changes.
2511 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2513 * configure: Regenerated.
2515 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2517 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2519 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2521 * gencode.c (print_igen_insn_models): Assume certain architectures
2522 include all mips* instructions.
2523 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2526 * Makefile.in (tmp.igen): Add target. Generate igen input from
2529 * gencode.c (FEATURE_IGEN): Define.
2530 (main): Add --igen option. Generate output in igen format.
2531 (process_instructions): Format output according to igen option.
2532 (print_igen_insn_format): New function.
2533 (print_igen_insn_models): New function.
2534 (process_instructions): Only issue warnings and ignore
2535 instructions when no FEATURE_IGEN.
2537 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2539 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2542 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2544 * configure: Regenerated to track ../common/aclocal.m4 changes.
2546 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2548 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2549 SIM_RESERVED_BITS): Delete, moved to common.
2550 (SIM_EXTRA_CFLAGS): Update.
2552 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2554 * configure.in: Configure non-strict memory alignment.
2555 * configure: Regenerated to track ../common/aclocal.m4 changes.
2557 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2559 * configure: Regenerated to track ../common/aclocal.m4 changes.
2561 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2563 * gencode.c (SDBBP,DERET): Added (3900) insns.
2564 (RFE): Turn on for 3900.
2565 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2566 (dsstate): Made global.
2567 (SUBTARGET_R3900): Added.
2568 (CANCELDELAYSLOT): New.
2569 (SignalException): Ignore SystemCall rather than ignore and
2570 terminate. Add DebugBreakPoint handling.
2571 (decode_coproc): New insns RFE, DERET; and new registers Debug
2572 and DEPC protected by SUBTARGET_R3900.
2573 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2575 * Makefile.in,configure.in: Add mips subtarget option.
2576 * configure: Update.
2578 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2580 * gencode.c: Add r3900 (tx39).
2583 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2585 * gencode.c (build_instruction): Don't need to subtract 4 for
2588 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2590 * interp.c: Correct some HASFPU problems.
2592 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2594 * configure: Regenerated to track ../common/aclocal.m4 changes.
2596 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2598 * interp.c (mips_options): Fix samples option short form, should
2601 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2603 * interp.c (sim_info): Enable info code. Was just returning.
2605 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2607 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2610 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2612 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2614 (build_instruction): Ditto for LL.
2616 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2618 * configure: Regenerated to track ../common/aclocal.m4 changes.
2620 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2622 * configure: Regenerated to track ../common/aclocal.m4 changes.
2625 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2627 * interp.c (sim_open): Add call to sim_analyze_program, update
2630 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2632 * interp.c (sim_kill): Delete.
2633 (sim_create_inferior): Add ABFD argument. Set PC from same.
2634 (sim_load): Move code initializing trap handlers from here.
2635 (sim_open): To here.
2636 (sim_load): Delete, use sim-hload.c.
2638 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2640 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2642 * configure: Regenerated to track ../common/aclocal.m4 changes.
2645 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2647 * interp.c (sim_open): Add ABFD argument.
2648 (sim_load): Move call to sim_config from here.
2649 (sim_open): To here. Check return status.
2651 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2653 * gencode.c (build_instruction): Two arg MADD should
2654 not assign result to $0.
2656 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2658 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2659 * sim/mips/configure.in: Regenerate.
2661 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2663 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2664 signed8, unsigned8 et.al. types.
2666 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2667 hosts when selecting subreg.
2669 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2671 * interp.c (sim_engine_run): Reset the ZERO register to zero
2672 regardless of FEATURE_WARN_ZERO.
2673 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2675 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2677 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2678 (SignalException): For BreakPoints ignore any mode bits and just
2680 (SignalException): Always set the CAUSE register.
2682 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2684 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2685 exception has been taken.
2687 * interp.c: Implement the ERET and mt/f sr instructions.
2689 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2691 * interp.c (SignalException): Don't bother restarting an
2694 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2696 * interp.c (SignalException): Really take an interrupt.
2697 (interrupt_event): Only deliver interrupts when enabled.
2699 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2701 * interp.c (sim_info): Only print info when verbose.
2702 (sim_info) Use sim_io_printf for output.
2704 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2706 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2709 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2711 * interp.c (sim_do_command): Check for common commands if a
2712 simulator specific command fails.
2714 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2716 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2717 and simBE when DEBUG is defined.
2719 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2721 * interp.c (interrupt_event): New function. Pass exception event
2722 onto exception handler.
2724 * configure.in: Check for stdlib.h.
2725 * configure: Regenerate.
2727 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2728 variable declaration.
2729 (build_instruction): Initialize memval1.
2730 (build_instruction): Add UNUSED attribute to byte, bigend,
2732 (build_operands): Ditto.
2734 * interp.c: Fix GCC warnings.
2735 (sim_get_quit_code): Delete.
2737 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2738 * Makefile.in: Ditto.
2739 * configure: Re-generate.
2741 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2743 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2745 * interp.c (mips_option_handler): New function parse argumes using
2747 (myname): Replace with STATE_MY_NAME.
2748 (sim_open): Delete check for host endianness - performed by
2750 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2751 (sim_open): Move much of the initialization from here.
2752 (sim_load): To here. After the image has been loaded and
2754 (sim_open): Move ColdReset from here.
2755 (sim_create_inferior): To here.
2756 (sim_open): Make FP check less dependant on host endianness.
2758 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2760 * interp.c (sim_set_callbacks): Delete.
2762 * interp.c (membank, membank_base, membank_size): Replace with
2763 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2764 (sim_open): Remove call to callback->init. gdb/run do this.
2768 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2770 * interp.c (big_endian_p): Delete, replaced by
2771 current_target_byte_order.
2773 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2775 * interp.c (host_read_long, host_read_word, host_swap_word,
2776 host_swap_long): Delete. Using common sim-endian.
2777 (sim_fetch_register, sim_store_register): Use H2T.
2778 (pipeline_ticks): Delete. Handled by sim-events.
2780 (sim_engine_run): Update.
2782 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2784 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2786 (SignalException): To here. Signal using sim_engine_halt.
2787 (sim_stop_reason): Delete, moved to common.
2789 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2791 * interp.c (sim_open): Add callback argument.
2792 (sim_set_callbacks): Delete SIM_DESC argument.
2795 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2797 * Makefile.in (SIM_OBJS): Add common modules.
2799 * interp.c (sim_set_callbacks): Also set SD callback.
2800 (set_endianness, xfer_*, swap_*): Delete.
2801 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2802 Change to functions using sim-endian macros.
2803 (control_c, sim_stop): Delete, use common version.
2804 (simulate): Convert into.
2805 (sim_engine_run): This function.
2806 (sim_resume): Delete.
2808 * interp.c (simulation): New variable - the simulator object.
2809 (sim_kind): Delete global - merged into simulation.
2810 (sim_load): Cleanup. Move PC assignment from here.
2811 (sim_create_inferior): To here.
2813 * sim-main.h: New file.
2814 * interp.c (sim-main.h): Include.
2816 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2818 * configure: Regenerated to track ../common/aclocal.m4 changes.
2820 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2822 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2824 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2826 * gencode.c (build_instruction): DIV instructions: check
2827 for division by zero and integer overflow before using
2828 host's division operation.
2830 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2832 * Makefile.in (SIM_OBJS): Add sim-load.o.
2833 * interp.c: #include bfd.h.
2834 (target_byte_order): Delete.
2835 (sim_kind, myname, big_endian_p): New static locals.
2836 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2837 after argument parsing. Recognize -E arg, set endianness accordingly.
2838 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2839 load file into simulator. Set PC from bfd.
2840 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2841 (set_endianness): Use big_endian_p instead of target_byte_order.
2843 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2845 * interp.c (sim_size): Delete prototype - conflicts with
2846 definition in remote-sim.h. Correct definition.
2848 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2850 * configure: Regenerated to track ../common/aclocal.m4 changes.
2853 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2855 * interp.c (sim_open): New arg `kind'.
2857 * configure: Regenerated to track ../common/aclocal.m4 changes.
2859 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2861 * configure: Regenerated to track ../common/aclocal.m4 changes.
2863 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2865 * interp.c (sim_open): Set optind to 0 before calling getopt.
2867 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2869 * configure: Regenerated to track ../common/aclocal.m4 changes.
2871 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2873 * interp.c : Replace uses of pr_addr with pr_uword64
2874 where the bit length is always 64 independent of SIM_ADDR.
2875 (pr_uword64) : added.
2877 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2879 * configure: Re-generate.
2881 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2883 * configure: Regenerate to track ../common/aclocal.m4 changes.
2885 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2887 * interp.c (sim_open): New SIM_DESC result. Argument is now
2889 (other sim_*): New SIM_DESC argument.
2891 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2893 * interp.c: Fix printing of addresses for non-64-bit targets.
2894 (pr_addr): Add function to print address based on size.
2896 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2898 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2900 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2902 * gencode.c (build_mips16_operands): Correct computation of base
2903 address for extended PC relative instruction.
2905 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2907 * interp.c (mips16_entry): Add support for floating point cases.
2908 (SignalException): Pass floating point cases to mips16_entry.
2909 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2911 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2913 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2914 and then set the state to fmt_uninterpreted.
2915 (COP_SW): Temporarily set the state to fmt_word while calling
2918 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2920 * gencode.c (build_instruction): The high order may be set in the
2921 comparison flags at any ISA level, not just ISA 4.
2923 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2925 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2926 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2927 * configure.in: sinclude ../common/aclocal.m4.
2928 * configure: Regenerated.
2930 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2932 * configure: Rebuild after change to aclocal.m4.
2934 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2936 * configure configure.in Makefile.in: Update to new configure
2937 scheme which is more compatible with WinGDB builds.
2938 * configure.in: Improve comment on how to run autoconf.
2939 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2940 * Makefile.in: Use autoconf substitution to install common
2943 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2945 * gencode.c (build_instruction): Use BigEndianCPU instead of
2948 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2950 * interp.c (sim_monitor): Make output to stdout visible in
2951 wingdb's I/O log window.
2953 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2955 * support.h: Undo previous change to SIGTRAP
2958 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2960 * interp.c (store_word, load_word): New static functions.
2961 (mips16_entry): New static function.
2962 (SignalException): Look for mips16 entry and exit instructions.
2963 (simulate): Use the correct index when setting fpr_state after
2964 doing a pending move.
2966 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2968 * interp.c: Fix byte-swapping code throughout to work on
2969 both little- and big-endian hosts.
2971 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2973 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2974 with gdb/config/i386/xm-windows.h.
2976 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2978 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2979 that messes up arithmetic shifts.
2981 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2983 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2984 SIGTRAP and SIGQUIT for _WIN32.
2986 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2988 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2989 force a 64 bit multiplication.
2990 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2991 destination register is 0, since that is the default mips16 nop
2994 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2996 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2997 (build_endian_shift): Don't check proc64.
2998 (build_instruction): Always set memval to uword64. Cast op2 to
2999 uword64 when shifting it left in memory instructions. Always use
3000 the same code for stores--don't special case proc64.
3002 * gencode.c (build_mips16_operands): Fix base PC value for PC
3004 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3006 * interp.c (simJALDELAYSLOT): Define.
3007 (JALDELAYSLOT): Define.
3008 (INDELAYSLOT, INJALDELAYSLOT): Define.
3009 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3011 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3013 * interp.c (sim_open): add flush_cache as a PMON routine
3014 (sim_monitor): handle flush_cache by ignoring it
3016 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3018 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3020 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3021 (BigEndianMem): Rename to ByteSwapMem and change sense.
3022 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3023 BigEndianMem references to !ByteSwapMem.
3024 (set_endianness): New function, with prototype.
3025 (sim_open): Call set_endianness.
3026 (sim_info): Use simBE instead of BigEndianMem.
3027 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3028 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3029 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3030 ifdefs, keeping the prototype declaration.
3031 (swap_word): Rewrite correctly.
3032 (ColdReset): Delete references to CONFIG. Delete endianness related
3033 code; moved to set_endianness.
3035 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3037 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3038 * interp.c (CHECKHILO): Define away.
3039 (simSIGINT): New macro.
3040 (membank_size): Increase from 1MB to 2MB.
3041 (control_c): New function.
3042 (sim_resume): Rename parameter signal to signal_number. Add local
3043 variable prev. Call signal before and after simulate.
3044 (sim_stop_reason): Add simSIGINT support.
3045 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3047 (sim_warning): Delete call to SignalException. Do call printf_filtered
3049 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3050 a call to sim_warning.
3052 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3054 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3055 16 bit instructions.
3057 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3059 Add support for mips16 (16 bit MIPS implementation):
3060 * gencode.c (inst_type): Add mips16 instruction encoding types.
3061 (GETDATASIZEINSN): Define.
3062 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3063 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3065 (MIPS16_DECODE): New table, for mips16 instructions.
3066 (bitmap_val): New static function.
3067 (struct mips16_op): Define.
3068 (mips16_op_table): New table, for mips16 operands.
3069 (build_mips16_operands): New static function.
3070 (process_instructions): If PC is odd, decode a mips16
3071 instruction. Break out instruction handling into new
3072 build_instruction function.
3073 (build_instruction): New static function, broken out of
3074 process_instructions. Check modifiers rather than flags for SHIFT
3075 bit count and m[ft]{hi,lo} direction.
3076 (usage): Pass program name to fprintf.
3077 (main): Remove unused variable this_option_optind. Change
3078 ``*loptarg++'' to ``loptarg++''.
3079 (my_strtoul): Parenthesize && within ||.
3080 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3081 (simulate): If PC is odd, fetch a 16 bit instruction, and
3082 increment PC by 2 rather than 4.
3083 * configure.in: Add case for mips16*-*-*.
3084 * configure: Rebuild.
3086 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3088 * interp.c: Allow -t to enable tracing in standalone simulator.
3089 Fix garbage output in trace file and error messages.
3091 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3093 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3094 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3095 * configure.in: Simplify using macros in ../common/aclocal.m4.
3096 * configure: Regenerated.
3097 * tconfig.in: New file.
3099 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3101 * interp.c: Fix bugs in 64-bit port.
3102 Use ansi function declarations for msvc compiler.
3103 Initialize and test file pointer in trace code.
3104 Prevent duplicate definition of LAST_EMED_REGNUM.
3106 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3108 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3110 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3112 * interp.c (SignalException): Check for explicit terminating
3114 * gencode.c: Pass instruction value through SignalException()
3115 calls for Trap, Breakpoint and Syscall.
3117 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3119 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3120 only used on those hosts that provide it.
3121 * configure.in: Add sqrt() to list of functions to be checked for.
3122 * config.in: Re-generated.
3123 * configure: Re-generated.
3125 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3127 * gencode.c (process_instructions): Call build_endian_shift when
3128 expanding STORE RIGHT, to fix swr.
3129 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3130 clear the high bits.
3131 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3132 Fix float to int conversions to produce signed values.
3134 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3136 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3137 (process_instructions): Correct handling of nor instruction.
3138 Correct shift count for 32 bit shift instructions. Correct sign
3139 extension for arithmetic shifts to not shift the number of bits in
3140 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3141 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3143 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3144 It's OK to have a mult follow a mult. What's not OK is to have a
3145 mult follow an mfhi.
3146 (Convert): Comment out incorrect rounding code.
3148 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3150 * interp.c (sim_monitor): Improved monitor printf
3151 simulation. Tidied up simulator warnings, and added "--log" option
3152 for directing warning message output.
3153 * gencode.c: Use sim_warning() rather than WARNING macro.
3155 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3157 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3158 getopt1.o, rather than on gencode.c. Link objects together.
3159 Don't link against -liberty.
3160 (gencode.o, getopt.o, getopt1.o): New targets.
3161 * gencode.c: Include <ctype.h> and "ansidecl.h".
3162 (AND): Undefine after including "ansidecl.h".
3163 (ULONG_MAX): Define if not defined.
3164 (OP_*): Don't define macros; now defined in opcode/mips.h.
3165 (main): Call my_strtoul rather than strtoul.
3166 (my_strtoul): New static function.
3168 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3170 * gencode.c (process_instructions): Generate word64 and uword64
3171 instead of `long long' and `unsigned long long' data types.
3172 * interp.c: #include sysdep.h to get signals, and define default
3174 * (Convert): Work around for Visual-C++ compiler bug with type
3176 * support.h: Make things compile under Visual-C++ by using
3177 __int64 instead of `long long'. Change many refs to long long
3178 into word64/uword64 typedefs.
3180 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3182 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3183 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3185 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3186 (AC_PROG_INSTALL): Added.
3187 (AC_PROG_CC): Moved to before configure.host call.
3188 * configure: Rebuilt.
3190 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3192 * configure.in: Define @SIMCONF@ depending on mips target.
3193 * configure: Rebuild.
3194 * Makefile.in (run): Add @SIMCONF@ to control simulator
3196 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3197 * interp.c: Remove some debugging, provide more detailed error
3198 messages, update memory accesses to use LOADDRMASK.
3200 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3202 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3203 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3205 * configure: Rebuild.
3206 * config.in: New file, generated by autoheader.
3207 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3208 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3209 HAVE_ANINT and HAVE_AINT, as appropriate.
3210 * Makefile.in (run): Use @LIBS@ rather than -lm.
3211 (interp.o): Depend upon config.h.
3212 (Makefile): Just rebuild Makefile.
3213 (clean): Remove stamp-h.
3214 (mostlyclean): Make the same as clean, not as distclean.
3215 (config.h, stamp-h): New targets.
3217 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3219 * interp.c (ColdReset): Fix boolean test. Make all simulator
3222 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3224 * interp.c (xfer_direct_word, xfer_direct_long,
3225 swap_direct_word, swap_direct_long, xfer_big_word,
3226 xfer_big_long, xfer_little_word, xfer_little_long,
3227 swap_word,swap_long): Added.
3228 * interp.c (ColdReset): Provide function indirection to
3229 host<->simulated_target transfer routines.
3230 * interp.c (sim_store_register, sim_fetch_register): Updated to
3231 make use of indirected transfer routines.
3233 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3235 * gencode.c (process_instructions): Ensure FP ABS instruction
3237 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3238 system call support.
3240 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3242 * interp.c (sim_do_command): Complain if callback structure not
3245 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3247 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3248 support for Sun hosts.
3249 * Makefile.in (gencode): Ensure the host compiler and libraries
3250 used for cross-hosted build.
3252 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3254 * interp.c, gencode.c: Some more (TODO) tidying.
3256 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3258 * gencode.c, interp.c: Replaced explicit long long references with
3259 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3260 * support.h (SET64LO, SET64HI): Macros added.
3262 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3264 * configure: Regenerate with autoconf 2.7.
3266 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3268 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3269 * support.h: Remove superfluous "1" from #if.
3270 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3272 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3274 * interp.c (StoreFPR): Control UndefinedResult() call on
3275 WARN_RESULT manifest.
3277 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3279 * gencode.c: Tidied instruction decoding, and added FP instruction
3282 * interp.c: Added dineroIII, and BSD profiling support. Also
3283 run-time FP handling.
3285 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3287 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3288 gencode.c, interp.c, support.h: created.