sim/mips/ChangeLog

   1 2007-02-20  Thiemo Seufer  <ths@mips.com>
   2             Chao-Ying Fu  <fu@mips.com>
   3
   4         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
   5         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
   6         Add dsp2 to sim_igen_machine.
   7         * configure: Regenerate.
   8         * dsp.igen (do_ph_op): Add MUL support when op = 2.
   9         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
  10         (mulq_rs.ph): Use do_ph_mulq.
  11         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
  12         * mips.igen: Add dsp2 model and include dsp2.igen.
  13         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
  14         for *mips32r2, *mips64r2, *dsp.
  15         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
  16         for *mips32r2, *mips64r2, *dsp2.
  17         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
  18
  19 2007-02-19  Thiemo Seufer  <ths@mips.com>
  20             Nigel Stephens  <nigel@mips.com>
  21
  22         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
  23         jumps with hazard barrier.
  24
  25 2007-02-19  Thiemo Seufer  <ths@mips.com>
  26             Nigel Stephens  <nigel@mips.com>
  27
  28         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
  29         after each call to sim_io_write.
  30
  31 2007-02-19  Thiemo Seufer  <ths@mips.com>
  32             Nigel Stephens  <nigel@mips.com>
  33
  34         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
  35         supported by this simulator.
  36         (decode_coproc): Recognise additional CP0 Config registers
  37         correctly.
  38
  39 2007-02-19  Thiemo Seufer  <ths@mips.com>
  40             Nigel Stephens  <nigel@mips.com>
  41             David Ung  <davidu@mips.com>
  42
  43         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
  44         uninterpreted formats. If fmt is one of the uninterpreted types
  45         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
  46         fmt_word, and fmt_uninterpreted_64 like fmt_long.
  47         (store_fpr): When writing an invalid odd register, set the
  48         matching even register to fmt_unknown, not the following register.
  49         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
  50         the the memory window at offset 0 set by --memory-size command
  51         line option.
  52         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
  53         point register.
  54         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
  55         register.
  56         (sim_monitor): When returning the memory size to the MIPS
  57         application, use the value in STATE_MEM_SIZE, not an arbitrary
  58         hardcoded value.
  59         (cop_lw): Don' mess around with FPR_STATE, just pass
  60         fmt_uninterpreted_32 to StoreFPR.
  61         (cop_sw): Similarly.
  62         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
  63         (cop_sd): Similarly.
  64         * mips.igen (not_word_value): Single version for mips32, mips64
  65         and mips16.
  66
  67 2007-02-19  Thiemo Seufer <ths@mips.com>
  68             Nigel Stephens  <nigel@mips.com>
  69
  70         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
  71         MBytes.
  72
  73 2007-02-17  Thiemo Seufer  <ths@mips.com>
  74
  75         * configure.ac (mips*-sde-elf*): Move in front of generic machine
  76         configuration.
  77         * configure: Regenerate.
  78
  79 2007-02-17  Thiemo Seufer  <ths@mips.com>
  80
  81         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
  82         Add mdmx to sim_igen_machine.
  83         (mipsisa64*-*-*): Likewise. Remove dsp.
  84         (mipsisa32*-*-*): Remove dsp.
  85         * configure: Regenerate.
  86
  87 2007-02-13  Thiemo Seufer  <ths@mips.com>
  88
  89         * configure.ac: Add mips*-sde-elf* target.
  90         * configure: Regenerate.
  91
  92 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
  93
  94         * acconfig.h: Remove.
  95         * config.in, configure: Regenerate.
  96
  97 2006-11-07  Thiemo Seufer  <ths@mips.com>
  98
  99         * dsp.igen (do_w_op): Fix compiler warning.
 100
 101 2006-08-29  Thiemo Seufer  <ths@mips.com>
 102             David Ung  <davidu@mips.com>
 103
 104         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 105         sim_igen_machine.
 106         * configure: Regenerate.
 107         * mips.igen (model): Add smartmips.
 108         (MADDU): Increment ACX if carry.
 109         (do_mult): Clear ACX.
 110         (ROR,RORV): Add smartmips.
 111         (include): Include smartmips.igen.
 112         * sim-main.h (ACX): Set to REGISTERS[89].
 113         * smartmips.igen: New file.
 114
 115 2006-08-29  Thiemo Seufer  <ths@mips.com>
 116             David Ung  <davidu@mips.com>
 117
 118         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 119         mips3264r2.igen. Add missing dependency rules.
 120         * m16e.igen: Support for mips16e save/restore instructions.
 121
 122 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 123
 124         * configure: Regenerated.
 125
 126 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 127
 128         * configure: Regenerated.
 129
 130 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 131
 132         * configure: Regenerated.
 133
 134 2006-05-15 Chao-ying Fu  <fu@mips.com>
 135
 136         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 137
 138 2006-04-18  Nick Clifton  <nickc@redhat.com>
 139
 140         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 141         statement.
 142
 143 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 144
 145         * configure: Regenerate.
 146
 147 2005-12-14  Chao-ying Fu  <fu@mips.com>
 148
 149         * Makefile.in (SIM_OBJS): Add dsp.o.
 150         (dsp.o): New dependency.
 151         (IGEN_INCLUDE): Add dsp.igen.
 152         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 153         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 154         * configure: Regenerate.
 155         * mips.igen: Add dsp model and include dsp.igen.
 156         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 157         because these instructions are extended in DSP ASE.
 158         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 159         adding 6 DSP accumulator registers and 1 DSP control register.
 160         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 161         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 162         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 163         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 164         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 165         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 166         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 167         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 168         DSPCR_CCOND_SMASK): New define.
 169         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 170         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 171
 172 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 173
 174         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 175
 176 2005-06-16  David Ung  <davidu@mips.com>
 177             Nigel Stephens  <nigel@mips.com>
 178
 179         * mips.igen: New mips16e model and include m16e.igen.
 180         (check_u64): Add mips16e tag.
 181         * m16e.igen: New file for MIPS16e instructions.
 182         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 183         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 184         models.
 185         * configure: Regenerate.
 186
 187 2005-05-26  David Ung  <davidu@mips.com>
 188
 189         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 190         tags to all instructions which are applicable to the new ISAs.
 191         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 192         vr.igen.
 193         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 194         instructions.
 195         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 196         to mips.igen.
 197         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 198         * configure: Regenerate.
 199
 200 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 201
 202         * configure: Regenerate.
 203
 204 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 205
 206         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 207         explicit call to AC_CONFIG_HEADER.
 208         * configure: Regenerate.
 209
 210 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 211
 212         * configure.ac: Update to use ../common/common.m4.
 213         * configure: Re-generate.
 214
 215 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 216
 217         * configure: Regenerated to track ../common/aclocal.m4 changes.
 218
 219 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 220
 221         * configure.ac: Rename configure.in, require autoconf 2.59.
 222         * configure: Re-generate.
 223
 224 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 225
 226         * configure: Regenerate for ../common/aclocal.m4 update.
 227
 228 2004-09-24  Monika Chaddha  <monika@acmet.com>
 229
 230         Committed by Andrew Cagney.
 231         * m16.igen (CMP, CMPI): Fix assembler.
 232
 233 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 234
 235         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 236         * configure: Regenerate.
 237
 238 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 239
 240         * configure.in (sim_m16_machine): Include mipsIII.
 241         * configure: Regenerate.
 242
 243 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 244
 245         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 246         from COP0_BADVADDR.
 247         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 248
 249 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 250
 251         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 252
 253 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 254
 255         * mips.igen (check_fmt): Remove.
 256         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 257         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 258         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 259         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 260         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 261         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 262         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 263         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 264         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 265         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 266
 267 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 268
 269         * sb1.igen (check_sbx): New function.
 270         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 271
 272 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 273             Richard Sandiford  <rsandifo@redhat.com>
 274
 275         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 276         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 277         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 278         separate implementations for mipsIV and mipsV.  Use new macros to
 279         determine whether the restrictions apply.
 280
 281 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 282
 283         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 284         (check_mult_hilo): Improve comments.
 285         (check_div_hilo): Likewise.  Also, fork off a new version
 286         to handle mips32/mips64 (since there are no hazards to check
 287         in MIPS32/MIPS64).
 288
 289 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 290
 291         * mips.igen (do_dmultx): Fix check for negative operands.
 292
 293 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 294
 295         * Makefile.in (SHELL): Make sure this is defined.
 296         (various): Use $(SHELL) whenever we invoke move-if-change.
 297
 298 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 299
 300         * cp1.c: Tweak attribution slightly.
 301         * cp1.h: Likewise.
 302         * mdmx.c: Likewise.
 303         * mdmx.igen: Likewise.
 304         * mips3d.igen: Likewise.
 305         * sb1.igen: Likewise.
 306
 307 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 308
 309         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 310         unsigned operands.
 311
 312 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 313
 314         * interp.c (sim_open): Rename _bfd to bfd.
 315         (sim_create_inferior): Ditto.
 316
 317 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 318
 319         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 320
 321 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 322
 323         * mips.igen (EI, DI): Remove.
 324
 325 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 326
 327         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 328
 329 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 330             Andrew Cagney  <ac131313@redhat.com>
 331             Gavin Romig-Koch  <gavin@redhat.com>
 332             Graydon Hoare  <graydon@redhat.com>
 333             Aldy Hernandez  <aldyh@redhat.com>
 334             Dave Brolley  <brolley@redhat.com>
 335             Chris Demetriou  <cgd@broadcom.com>
 336
 337         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 338         (sim_mach_default): New variable.
 339         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 340         Add a new simulator generator, MULTI.
 341         * configure: Regenerate.
 342         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 343         (multi-run.o): New dependency.
 344         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 345         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 346         (tmp-multi): Combine them.
 347         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 348         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 349         (distclean-extra): New rule.
 350         * sim-main.h: Include bfd.h.
 351         (MIPS_MACH): New macro.
 352         * mips.igen (vr4120, vr5400, vr5500): New models.
 353         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 354         * vr.igen: Replace with new version.
 355
 356 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 357
 358         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 359         * configure: Regenerate.
 360
 361 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 362
 363         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 364         * mips.igen: Remove all invocations of check_branch_bug and
 365         mark_branch_bug.
 366
 367 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 368
 369         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 370
 371 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 372
 373         * mips.igen (do_load_double, do_store_double): New functions.
 374         (LDC1, SDC1): Rename to...
 375         (LDC1b, SDC1b): respectively.
 376         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 377
 378 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 379
 380         * cp1.c (fp_recip2): Modify initialization expression so that
 381         GCC will recognize it as constant.
 382
 383 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 384
 385         * mdmx.c (SD_): Delete.
 386         (Unpredictable): Re-define, for now, to directly invoke
 387         unpredictable_action().
 388         (mdmx_acc_op): Fix error in .ob immediate handling.
 389
 390 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 391
 392         * interp.c (sim_firmware_command): Initialize `address'.
 393
 394 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 395
 396         * configure: Regenerated to track ../common/aclocal.m4 changes.
 397
 398 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 399             Ed Satterthwaite  <ehs@broadcom.com>
 400
 401         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 402         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 403         * mips.igen: Include mips3d.igen.
 404         (mips3d): New model name for MIPS-3D ASE instructions.
 405         (CVT.W.fmt): Don't use this instruction for word (source) format
 406         instructions.
 407         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 408         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 409         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 410         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 411         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 412         (RSquareRoot1, RSquareRoot2): New macros.
 413         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 414         (fp_rsqrt2): New functions.
 415         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 416         * configure: Regenerate.
 417
 418 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 419             Ed Satterthwaite  <ehs@broadcom.com>
 420
 421         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 422         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 423         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 424         (convert): Note that this function is not used for paired-single
 425         format conversions.
 426         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 427         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 428         (check_fmt_p): Enable paired-single support.
 429         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 430         (PUU.PS): New instructions.
 431         (CVT.S.fmt): Don't use this instruction for paired-single format
 432         destinations.
 433         * sim-main.h (FP_formats): New value 'fmt_ps.'
 434         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 435         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 436
 437 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 438
 439         * mips.igen: Fix formatting of function calls in
 440         many FP operations.
 441
 442 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 443
 444         * mips.igen (MOVN, MOVZ): Trace result.
 445         (TNEI): Print "tnei" as the opcode name in traces.
 446         (CEIL.W): Add disassembly string for traces.
 447         (RSQRT.fmt): Make location of disassembly string consistent
 448         with other instructions.
 449
 450 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 451
 452         * mips.igen (X): Delete unused function.
 453
 454 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 455
 456         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 457
 458 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 459             Ed Satterthwaite  <ehs@broadcom.com>
 460
 461         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 462         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 463         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 464         (fp_nmsub): New prototypes.
 465         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 466         (NegMultiplySub): New defines.
 467         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 468         (MADD.D, MADD.S): Replace with...
 469         (MADD.fmt): New instruction.
 470         (MSUB.D, MSUB.S): Replace with...
 471         (MSUB.fmt): New instruction.
 472         (NMADD.D, NMADD.S): Replace with...
 473         (NMADD.fmt): New instruction.
 474         (NMSUB.D, MSUB.S): Replace with...
 475         (NMSUB.fmt): New instruction.
 476
 477 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 478             Ed Satterthwaite  <ehs@broadcom.com>
 479
 480         * cp1.c: Fix more comment spelling and formatting.
 481         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 482         (denorm_mode): New function.
 483         (fpu_unary, fpu_binary): Round results after operation, collect
 484         status from rounding operations, and update the FCSR.
 485         (convert): Collect status from integer conversions and rounding
 486         operations, and update the FCSR.  Adjust NaN values that result
 487         from conversions.  Convert to use sim_io_eprintf rather than
 488         fprintf, and remove some debugging code.
 489         * cp1.h (fenr_FS): New define.
 490
 491 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 492
 493         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 494         rounding mode to sim FP rounding mode flag conversion code into...
 495         (rounding_mode): New function.
 496
 497 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 498
 499         * cp1.c: Clean up formatting of a few comments.
 500         (value_fpr): Reformat switch statement.
 501
 502 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 503             Ed Satterthwaite  <ehs@broadcom.com>
 504
 505         * cp1.h: New file.
 506         * sim-main.h: Include cp1.h.
 507         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 508         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 509         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 510         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 511         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 512         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 513         * cp1.c: Don't include sim-fpu.h; already included by
 514         sim-main.h.  Clean up formatting of some comments.
 515         (NaN, Equal, Less): Remove.
 516         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 517         (fp_cmp): New functions.
 518         * mips.igen (do_c_cond_fmt): Remove.
 519         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 520         Compare.  Add result tracing.
 521         (CxC1): Remove, replace with...
 522         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 523         (DMxC1): Remove, replace with...
 524         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 525         (MxC1): Remove, replace with...
 526         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 527
 528 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 529
 530         * sim-main.h (FGRIDX): Remove, replace all uses with...
 531         (FGR_BASE): New macro.
 532         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 533         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 534         (NR_FGR, FGR): Likewise.
 535         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 536         * mips.igen: Likewise.
 537
 538 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 539
 540         * cp1.c: Add an FSF Copyright notice to this file.
 541
 542 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 543             Ed Satterthwaite  <ehs@broadcom.com>
 544
 545         * cp1.c (Infinity): Remove.
 546         * sim-main.h (Infinity): Likewise.
 547
 548         * cp1.c (fp_unary, fp_binary): New functions.
 549         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 550         (fp_sqrt): New functions, implemented in terms of the above.
 551         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 552         (Recip, SquareRoot): Remove (replaced by functions above).
 553         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 554         (fp_recip, fp_sqrt): New prototypes.
 555         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 556         (Recip, SquareRoot): Replace prototypes with #defines which
 557         invoke the functions above.
 558
 559 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 560
 561         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 562         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 563         file, remove PARAMS from prototypes.
 564         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 565         simulator state arguments.
 566         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 567         pass simulator state arguments.
 568         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 569         (store_fpr, convert): Remove 'sd' argument.
 570         (value_fpr): Likewise.  Convert to use 'SD' instead.
 571
 572 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 573
 574         * cp1.c (Min, Max): Remove #if 0'd functions.
 575         * sim-main.h (Min, Max): Remove.
 576
 577 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 578
 579         * cp1.c: fix formatting of switch case and default labels.
 580         * interp.c: Likewise.
 581         * sim-main.c: Likewise.
 582
 583 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 584
 585         * cp1.c: Clean up comments which describe FP formats.
 586          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 587
 588 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 589             Ed Satterthwaite  <ehs@broadcom.com>
 590
 591         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 592         Broadcom SiByte SB-1 processor configurations.
 593         * configure: Regenerate.
 594         * sb1.igen: New file.
 595         * mips.igen: Include sb1.igen.
 596         (sb1): New model.
 597         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 598         * mdmx.igen: Add "sb1" model to all appropriate functions and
 599         instructions.
 600         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 601         (ob_func, ob_acc): Reference the above.
 602         (qh_acc): Adjust to keep the same size as ob_acc.
 603         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 604         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 605
 606 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 607
 608         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 609
 610 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 611             Ed Satterthwaite  <ehs@broadcom.com>
 612
 613         * mips.igen (mdmx): New (pseudo-)model.
 614         * mdmx.c, mdmx.igen: New files.
 615         * Makefile.in (SIM_OBJS): Add mdmx.o.
 616         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 617         New typedefs.
 618         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 619         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 620         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 621         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 622         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 623         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 624         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 625         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 626         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 627         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 628         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 629         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 630         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 631         (qh_fmtsel): New macros.
 632         (_sim_cpu): New member "acc".
 633         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 634         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 635
 636 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 637
 638         * interp.c: Use 'deprecated' rather than 'depreciated.'
 639         * sim-main.h: Likewise.
 640
 641 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 642
 643         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 644         which wouldn't compile anyway.
 645         * sim-main.h (unpredictable_action): New function prototype.
 646         (Unpredictable): Define to call igen function unpredictable().
 647         (NotWordValue): New macro to call igen function not_word_value().
 648         (UndefinedResult): Remove.
 649         * interp.c (undefined_result): Remove.
 650         (unpredictable_action): New function.
 651         * mips.igen (not_word_value, unpredictable): New functions.
 652         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 653         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 654         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 655         NotWordValue() to check for unpredictable inputs, then
 656         Unpredictable() to handle them.
 657
 658 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 659
 660         * mips.igen: Fix formatting of calls to Unpredictable().
 661
 662 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 663
 664         * interp.c (sim_open): Revert previous change.
 665
 666 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 667
 668         * interp.c (sim_open): Disable chunk of code that wrote code in
 669         vector table entries.
 670
 671 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 672
 673         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 674         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 675         unused definitions.
 676
 677 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 678
 679         * cp1.c: Fix many formatting issues.
 680
 681 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 682
 683         * cp1.c (fpu_format_name): New function to replace...
 684         (DOFMT): This.  Delete, and update all callers.
 685         (fpu_rounding_mode_name): New function to replace...
 686         (RMMODE): This.  Delete, and update all callers.
 687
 688 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 689
 690         * interp.c: Move FPU support routines from here to...
 691         * cp1.c: Here.  New file.
 692         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 693         (cp1.o): New target.
 694
 695 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 696
 697         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 698         * mips.igen (mips32, mips64): New models, add to all instructions
 699         and functions as appropriate.
 700         (loadstore_ea, check_u64): New variant for model mips64.
 701         (check_fmt_p): New variant for models mipsV and mips64, remove
 702         mipsV model marking fro other variant.
 703         (SLL) Rename to...
 704         (SLLa) this.
 705         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 706         for mips32 and mips64.
 707         (DCLO, DCLZ): New instructions for mips64.
 708
 709 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 710
 711         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 712         immediate or code as a hex value with the "%#lx" format.
 713         (ANDI): Likewise, and fix printed instruction name.
 714
 715 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 716
 717         * sim-main.h (UndefinedResult, Unpredictable): New macros
 718         which currently do nothing.
 719
 720 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 721
 722         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 723         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 724         (status_CU3): New definitions.
 725
 726         * sim-main.h (ExceptionCause): Add new values for MIPS32
 727         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 728         for DebugBreakPoint and NMIReset to note their status in
 729         MIPS32 and MIPS64.
 730         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 731         (SignalExceptionCacheErr): New exception macros.
 732
 733 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 734
 735         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 736         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 737         is always enabled.
 738         (SignalExceptionCoProcessorUnusable): Take as argument the
 739         unusable coprocessor number.
 740
 741 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 742
 743         * mips.igen: Fix formatting of all SignalException calls.
 744
 745 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 746
 747         * sim-main.h (SIGNEXTEND): Remove.
 748
 749 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 750
 751         * mips.igen: Remove gencode comment from top of file, fix
 752         spelling in another comment.
 753
 754 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 755
 756         * mips.igen (check_fmt, check_fmt_p): New functions to check
 757         whether specific floating point formats are usable.
 758         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 759         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 760         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 761         Use the new functions.
 762         (do_c_cond_fmt): Remove format checks...
 763         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 764
 765 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 766
 767         * mips.igen: Fix formatting of check_fpu calls.
 768
 769 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 770
 771         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 772
 773 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 774
 775         * mips.igen: Remove whitespace at end of lines.
 776
 777 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 778
 779         * mips.igen (loadstore_ea): New function to do effective
 780         address calculations.
 781         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 782         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 783         CACHE): Use loadstore_ea to do effective address computations.
 784
 785 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 786
 787         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 788         * mips.igen (LL, CxC1, MxC1): Likewise.
 789
 790 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 791
 792         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 793         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 794         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 795         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 796         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 797         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 798         Don't split opcode fields by hand, use the opcode field values
 799         provided by igen.
 800
 801 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 802
 803         * mips.igen (do_divu): Fix spacing.
 804
 805         * mips.igen (do_dsllv): Move to be right before DSLLV,
 806         to match the rest of the do_<shift> functions.
 807
 808 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 809
 810         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 811         DSRL32, do_dsrlv): Trace inputs and results.
 812
 813 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 814
 815         * mips.igen (CACHE): Provide instruction-printing string.
 816
 817         * interp.c (signal_exception): Comment tokens after #endif.
 818
 819 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 820
 821         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 822         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 823         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 824         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 825         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 826         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 827         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 828         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 829
 830 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 831
 832         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 833         instruction-printing string.
 834         (LWU): Use '64' as the filter flag.
 835
 836 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 837
 838         * mips.igen (SDXC1): Fix instruction-printing string.
 839
 840 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 841
 842         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 843         filter flags "32,f".
 844
 845 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 846
 847         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 848         as the filter flag.
 849
 850 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 851
 852         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 853         add a comma) so that it more closely match the MIPS ISA
 854         documentation opcode partitioning.
 855         (PREF): Put useful names on opcode fields, and include
 856         instruction-printing string.
 857
 858 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 859
 860         * mips.igen (check_u64): New function which in the future will
 861         check whether 64-bit instructions are usable and signal an
 862         exception if not.  Currently a no-op.
 863         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 864         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 865         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 866         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 867
 868         * mips.igen (check_fpu): New function which in the future will
 869         check whether FPU instructions are usable and signal an exception
 870         if not.  Currently a no-op.
 871         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 872         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 873         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 874         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 875         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 876         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 877         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 878         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 879
 880 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 881
 882         * mips.igen (do_load_left, do_load_right): Move to be immediately
 883         following do_load.
 884         (do_store_left, do_store_right): Move to be immediately following
 885         do_store.
 886
 887 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 888
 889         * mips.igen (mipsV): New model name.  Also, add it to
 890         all instructions and functions where it is appropriate.
 891
 892 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 893
 894         * mips.igen: For all functions and instructions, list model
 895         names that support that instruction one per line.
 896
 897 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 898
 899         * mips.igen: Add some additional comments about supported
 900         models, and about which instructions go where.
 901         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 902         order as is used in the rest of the file.
 903
 904 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 905
 906         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 907         indicating that ALU32_END or ALU64_END are there to check
 908         for overflow.
 909         (DADD): Likewise, but also remove previous comment about
 910         overflow checking.
 911
 912 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 913
 914         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 915         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 916         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 917         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 918         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 919         fields (i.e., add and move commas) so that they more closely
 920         match the MIPS ISA documentation opcode partitioning.
 921
 922 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 923
 924         * mips.igen (ADDI): Print immediate value.
 925         (BREAK): Print code.
 926         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 927         (SLL): Print "nop" specially, and don't run the code
 928         that does the shift for the "nop" case.
 929
 930 2001-11-17  Fred Fish  <fnf@redhat.com>
 931
 932         * sim-main.h (float_operation): Move enum declaration outside
 933         of _sim_cpu struct declaration.
 934
 935 2001-04-12  Jim Blandy  <jimb@redhat.com>
 936
 937         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 938         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 939         set of the FCSR.
 940         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 941         PENDING_FILL, and you can get the intended effect gracefully by
 942         calling PENDING_SCHED directly.
 943
 944 2001-02-23  Ben Elliston  <bje@redhat.com>
 945
 946         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 947         already defined elsewhere.
 948
 949 2001-02-19  Ben Elliston  <bje@redhat.com>
 950
 951         * sim-main.h (sim_monitor): Return an int.
 952         * interp.c (sim_monitor): Add return values.
 953         (signal_exception): Handle error conditions from sim_monitor.
 954
 955 2001-02-08  Ben Elliston  <bje@redhat.com>
 956
 957         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 958         (store_memory): Likewise, pass cia to sim_core_write*.
 959
 960 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 961
 962         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 963         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 964
 965 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 966
 967         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 968         * Makefile.in: Don't delete *.igen when cleaning directory.
 969
 970 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 971
 972         * m16.igen (break): Call SignalException not sim_engine_halt.
 973
 974 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 975
 976         From Jason Eckhardt:
 977         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
 978
 979 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 980
 981         * mips.igen (MxC1, DMxC1): Fix printf formatting.
 982
 983 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
 984
 985         * mips.igen (do_dmultx): Fix typo.
 986
 987 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 988
 989         * configure: Regenerated to track ../common/aclocal.m4 changes.
 990
 991 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 992
 993         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
 994
 995 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
 996
 997         * sim-main.h (GPR_CLEAR): Define macro.
 998
 999 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1000
1001         * interp.c (decode_coproc): Output long using %lx and not %s.
1002
1003 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1004
1005         * interp.c (sim_open): Sort & extend dummy memory regions for
1006         --board=jmr3904 for eCos.
1007
1008 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1009
1010         * configure: Regenerated.
1011
1012 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1013
1014         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1015         calls, conditional on the simulator being in verbose mode.
1016
1017 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1018
1019         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1020         cache don't get ReservedInstruction traps.
1021
1022 1999-11-29  Mark Salter  <msalter@cygnus.com>
1023
1024         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1025         to clear status bits in sdisr register. This is how the hardware works.
1026
1027         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1028         being used by cygmon.
1029
1030 1999-11-11  Andrew Haley  <aph@cygnus.com>
1031
1032         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1033         instructions.
1034
1035 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1036
1037         * mips.igen (MULT): Correct previous mis-applied patch.
1038
1039 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1040
1041         * mips.igen (delayslot32): Handle sequence like
1042         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1043         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1044         (MULT): Actually pass the third register...
1045
1046 1999-09-03  Mark Salter  <msalter@cygnus.com>
1047
1048         * interp.c (sim_open): Added more memory aliases for additional
1049         hardware being touched by cygmon on jmr3904 board.
1050
1051 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1052
1053         * configure: Regenerated to track ../common/aclocal.m4 changes.
1054
1055 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1056
1057         * interp.c (sim_store_register): Handle case where client - GDB -
1058         specifies that a 4 byte register is 8 bytes in size.
1059         (sim_fetch_register): Ditto.
1060
1061 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1062
1063         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1064         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1065         (idt_monitor_base): Base address for IDT monitor traps.
1066         (pmon_monitor_base): Ditto for PMON.
1067         (lsipmon_monitor_base): Ditto for LSI PMON.
1068         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1069         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1070         (sim_firmware_command): New function.
1071         (mips_option_handler): Call it for OPTION_FIRMWARE.
1072         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1073         option was given, add no monitor by default.  Add BREAK hooks only if
1074         monitors are also there.
1075
1076 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1077
1078         * interp.c (sim_monitor): Flush output before reading input.
1079
1080 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1081
1082         * tconfig.in (SIM_HANDLES_LMA): Always define.
1083
1084 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1085
1086         From Mark Salter <msalter@cygnus.com>:
1087         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1088         (sim_open): Add setup for BSP board.
1089
1090 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1091
1092         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1093         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1094         them as unimplemented.
1095
1096 1999-05-08  Felix Lee  <flee@cygnus.com>
1097
1098         * configure: Regenerated to track ../common/aclocal.m4 changes.
1099
1100 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1101
1102         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1103
1104 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1105
1106         * configure.in: Any mips64vr5*-*-* target should have
1107         -DTARGET_ENABLE_FR=1.
1108         (default_endian): Any mips64vr*el-*-* target should default to
1109         LITTLE_ENDIAN.
1110         * configure: Re-generate.
1111
1112 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1113
1114         * mips.igen (ldl): Extend from _16_, not 32.
1115
1116 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1117
1118         * interp.c (sim_store_register): Force registers written to by GDB
1119         into an un-interpreted state.
1120
1121 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1122
1123         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1124         CPU, start periodic background I/O polls.
1125         (tx3904sio_poll): New function: periodic I/O poller.
1126
1127 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1128
1129         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1130
1131 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1132
1133         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1134         case statement.
1135
1136 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1137
1138         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1139         (load_word): Call SIM_CORE_SIGNAL hook on error.
1140         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1141         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1142         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1143         * sim-main.h (COP0_BADVADDR): Define.
1144         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1145         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1146         (_sim_cpu): Add exc_* fields to store register value snapshots.
1147         * mips.igen (*): Replace memory-related SignalException* calls
1148         with references to SIM_CORE_SIGNAL hook.
1149
1150         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1151         fix.
1152         * sim-main.c (*): Minor warning cleanups.
1153
1154 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1155
1156         * m16.igen (DADDIU5): Correct type-o.
1157
1158 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1159
1160         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1161         variables.
1162
1163 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1164
1165         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1166         to include path.
1167         (interp.o): Add dependency on itable.h
1168         (oengine.c, gencode): Delete remaining references.
1169         (BUILT_SRC_FROM_GEN): Clean up.
1170
1171 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1172
1173         * vr4run.c: New.
1174         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1175         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1176         tmp-run-hack) : New.
1177         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1178         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1179         Drop the "64" qualifier to get the HACK generator working.
1180         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1181         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1182         qualifier to get the hack generator working.
1183         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1184         (DSLL): Use do_dsll.
1185         (DSLLV): Use do_dsllv.
1186         (DSRA): Use do_dsra.
1187         (DSRL): Use do_dsrl.
1188         (DSRLV): Use do_dsrlv.
1189         (BC1): Move *vr4100 to get the HACK generator working.
1190         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1191         get the HACK generator working.
1192         (MACC) Rename to get the HACK generator working.
1193         (DMACC,MACCS,DMACCS): Add the 64.
1194
1195 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1196
1197         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1198         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1199
1200 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1201
1202     * mips/interp.c (DEBUG): Cleanups.
1203
1204 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1205
1206         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1207         (tx3904sio_tickle): fflush after a stdout character output.
1208
1209 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1210
1211         * interp.c (sim_close): Uninstall modules.
1212
1213 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1214
1215         * sim-main.h, interp.c (sim_monitor): Change to global
1216         function.
1217
1218 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1219
1220         * configure.in (vr4100): Only include vr4100 instructions in
1221         simulator.
1222         * configure: Re-generate.
1223         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1224
1225 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1226
1227         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1228         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1229         true alternative.
1230
1231         * configure.in (sim_default_gen, sim_use_gen): Replace with
1232         sim_gen.
1233         (--enable-sim-igen): Delete config option. Always using IGEN.
1234         * configure: Re-generate.
1235
1236         * Makefile.in (gencode): Kill, kill, kill.
1237         * gencode.c: Ditto.
1238
1239 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1240
1241         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1242         bit mips16 igen simulator.
1243         * configure: Re-generate.
1244
1245         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1246         as part of vr4100 ISA.
1247         * vr.igen: Mark all instructions as 64 bit only.
1248
1249 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1250
1251         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1252         Pacify GCC.
1253
1254 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1255
1256         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1257         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1258         * configure: Re-generate.
1259
1260         * m16.igen (BREAK): Define breakpoint instruction.
1261         (JALX32): Mark instruction as mips16 and not r3900.
1262         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1263
1264         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1265
1266 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1267
1268         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1269         insn as a debug breakpoint.
1270
1271         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1272         pending.slot_size.
1273         (PENDING_SCHED): Clean up trace statement.
1274         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1275         (PENDING_FILL): Delay write by only one cycle.
1276         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1277
1278         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1279         of pending writes.
1280         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1281         32 & 64.
1282         (pending_tick): Move incrementing of index to FOR statement.
1283         (pending_tick): Only update PENDING_OUT after a write has occured.
1284
1285         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1286         build simulator.
1287         * configure: Re-generate.
1288
1289         * interp.c (sim_engine_run OLD): Delete explicit call to
1290         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1291
1292 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1293
1294         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1295         interrupt level number to match changed SignalExceptionInterrupt
1296         macro.
1297
1298 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1299
1300         * interp.c: #include "itable.h" if WITH_IGEN.
1301         (get_insn_name): New function.
1302         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1303         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1304
1305 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1306
1307         * configure: Rebuilt to inhale new common/aclocal.m4.
1308
1309 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1310
1311         * dv-tx3904sio.c: Include sim-assert.h.
1312
1313 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1314
1315         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1316         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1317         Reorganize target-specific sim-hardware checks.
1318         * configure: rebuilt.
1319         * interp.c (sim_open): For tx39 target boards, set
1320         OPERATING_ENVIRONMENT, add tx3904sio devices.
1321         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1322         ROM executables.  Install dv-sockser into sim-modules list.
1323
1324         * dv-tx3904irc.c: Compiler warning clean-up.
1325         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1326         frequent hw-trace messages.
1327
1328 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1329
1330         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1331
1332 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1333
1334         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1335
1336         * vr.igen: New file.
1337         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1338         * mips.igen: Define vr4100 model. Include vr.igen.
1339 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1340
1341         * mips.igen (check_mf_hilo): Correct check.
1342
1343 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1344
1345         * sim-main.h (interrupt_event): Add prototype.
1346
1347         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1348         register_ptr, register_value.
1349         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1350
1351         * sim-main.h (tracefh): Make extern.
1352
1353 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1354
1355         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1356         Reduce unnecessarily high timer event frequency.
1357         * dv-tx3904cpu.c: Ditto for interrupt event.
1358
1359 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1360
1361         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1362         to allay warnings.
1363         (interrupt_event): Made non-static.
1364
1365         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1366         interchange of configuration values for external vs. internal
1367         clock dividers.
1368
1369 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1370
1371         * mips.igen (BREAK): Moved code to here for
1372         simulator-reserved break instructions.
1373         * gencode.c (build_instruction): Ditto.
1374         * interp.c (signal_exception): Code moved from here.  Non-
1375         reserved instructions now use exception vector, rather
1376         than halting sim.
1377         * sim-main.h: Moved magic constants to here.
1378
1379 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1380
1381         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1382         register upon non-zero interrupt event level, clear upon zero
1383         event value.
1384         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1385         by passing zero event value.
1386         (*_io_{read,write}_buffer): Endianness fixes.
1387         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1388         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1389
1390         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1391         serial I/O and timer module at base address 0xFFFF0000.
1392
1393 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1394
1395         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1396         and BigEndianCPU.
1397
1398 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1399
1400         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1401         parts.
1402         * configure: Update.
1403
1404 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1405
1406         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1407         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1408         * configure.in: Include tx3904tmr in hw_device list.
1409         * configure: Rebuilt.
1410         * interp.c (sim_open): Instantiate three timer instances.
1411         Fix address typo of tx3904irc instance.
1412
1413 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1414
1415         * interp.c (signal_exception): SystemCall exception now uses
1416         the exception vector.
1417
1418 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1419
1420         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1421         to allay warnings.
1422
1423 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1424
1425         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1426
1427 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1428
1429         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1430
1431         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1432         sim-main.h. Declare a struct hw_descriptor instead of struct
1433         hw_device_descriptor.
1434
1435 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1436
1437         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1438         right bits and then re-align left hand bytes to correct byte
1439         lanes.  Fix incorrect computation in do_store_left when loading
1440         bytes from second word.
1441
1442 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1443
1444         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1445         * interp.c (sim_open): Only create a device tree when HW is
1446         enabled.
1447
1448         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1449         * interp.c (signal_exception): Ditto.
1450
1451 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1452
1453         * gencode.c: Mark BEGEZALL as LIKELY.
1454
1455 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1456
1457         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1458         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1459
1460 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1461
1462         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1463         modules.  Recognize TX39 target with "mips*tx39" pattern.
1464         * configure: Rebuilt.
1465         * sim-main.h (*): Added many macros defining bits in
1466         TX39 control registers.
1467         (SignalInterrupt): Send actual PC instead of NULL.
1468         (SignalNMIReset): New exception type.
1469         * interp.c (board): New variable for future use to identify
1470         a particular board being simulated.
1471         (mips_option_handler,mips_options): Added "--board" option.
1472         (interrupt_event): Send actual PC.
1473         (sim_open): Make memory layout conditional on board setting.
1474         (signal_exception): Initial implementation of hardware interrupt
1475         handling.  Accept another break instruction variant for simulator
1476         exit.
1477         (decode_coproc): Implement RFE instruction for TX39.
1478         (mips.igen): Decode RFE instruction as such.
1479         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1480         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1481         bbegin to implement memory map.
1482         * dv-tx3904cpu.c: New file.
1483         * dv-tx3904irc.c: New file.
1484
1485 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1486
1487         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1488
1489 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1490
1491         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1492         with calls to check_div_hilo.
1493
1494 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1495
1496         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1497         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1498         Add special r3900 version of do_mult_hilo.
1499         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1500         with calls to check_mult_hilo.
1501         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1502         with calls to check_div_hilo.
1503
1504 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1505
1506         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1507         Document a replacement.
1508
1509 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1510
1511         * interp.c (sim_monitor): Make mon_printf work.
1512
1513 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1514
1515         * sim-main.h (INSN_NAME): New arg `cpu'.
1516
1517 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1518
1519         * configure: Regenerated to track ../common/aclocal.m4 changes.
1520
1521 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1522
1523         * configure: Regenerated to track ../common/aclocal.m4 changes.
1524         * config.in: Ditto.
1525
1526 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1527
1528         * acconfig.h: New file.
1529         * configure.in: Reverted change of Apr 24; use sinclude again.
1530
1531 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1532
1533         * configure: Regenerated to track ../common/aclocal.m4 changes.
1534         * config.in: Ditto.
1535
1536 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1537
1538         * configure.in: Don't call sinclude.
1539
1540 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1541
1542         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1543
1544 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1545
1546         * mips.igen (ERET): Implement.
1547
1548         * interp.c (decode_coproc): Return sign-extended EPC.
1549
1550         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1551
1552         * interp.c (signal_exception): Do not ignore Trap.
1553         (signal_exception): On TRAP, restart at exception address.
1554         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1555         (signal_exception): Update.
1556         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1557         so that TRAP instructions are caught.
1558
1559 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1560
1561         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1562         contains HI/LO access history.
1563         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1564         (HIACCESS, LOACCESS): Delete, replace with
1565         (HIHISTORY, LOHISTORY): New macros.
1566         (CHECKHILO): Delete all, moved to mips.igen
1567
1568         * gencode.c (build_instruction): Do not generate checks for
1569         correct HI/LO register usage.
1570
1571         * interp.c (old_engine_run): Delete checks for correct HI/LO
1572         register usage.
1573
1574         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1575         check_mf_cycles): New functions.
1576         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1577         do_divu, domultx, do_mult, do_multu): Use.
1578
1579         * tx.igen ("madd", "maddu"): Use.
1580
1581 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1582
1583         * mips.igen (DSRAV): Use function do_dsrav.
1584         (SRAV): Use new function do_srav.
1585
1586         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1587         (B): Sign extend 11 bit immediate.
1588         (EXT-B*): Shift 16 bit immediate left by 1.
1589         (ADDIU*): Don't sign extend immediate value.
1590
1591 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1592
1593         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1594
1595         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1596         functions.
1597
1598         * mips.igen (delayslot32, nullify_next_insn): New functions.
1599         (m16.igen): Always include.
1600         (do_*): Add more tracing.
1601
1602         * m16.igen (delayslot16): Add NIA argument, could be called by a
1603         32 bit MIPS16 instruction.
1604
1605         * interp.c (ifetch16): Move function from here.
1606         * sim-main.c (ifetch16): To here.
1607
1608         * sim-main.c (ifetch16, ifetch32): Update to match current
1609         implementations of LH, LW.
1610         (signal_exception): Don't print out incorrect hex value of illegal
1611         instruction.
1612
1613 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1614
1615         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1616         instruction.
1617
1618         * m16.igen: Implement MIPS16 instructions.
1619
1620         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1621         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1622         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1623         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1624         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1625         bodies of corresponding code from 32 bit insn to these.  Also used
1626         by MIPS16 versions of functions.
1627
1628         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1629         (IMEM16): Drop NR argument from macro.
1630
1631 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1632
1633         * Makefile.in (SIM_OBJS): Add sim-main.o.
1634
1635         * sim-main.h (address_translation, load_memory, store_memory,
1636         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1637         as INLINE_SIM_MAIN.
1638         (pr_addr, pr_uword64): Declare.
1639         (sim-main.c): Include when H_REVEALS_MODULE_P.
1640
1641         * interp.c (address_translation, load_memory, store_memory,
1642         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1643         from here.
1644         * sim-main.c: To here. Fix compilation problems.
1645
1646         * configure.in: Enable inlining.
1647         * configure: Re-config.
1648
1649 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1650
1651         * configure: Regenerated to track ../common/aclocal.m4 changes.
1652
1653 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1654
1655         * mips.igen: Include tx.igen.
1656         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1657         * tx.igen: New file, contains MADD and MADDU.
1658
1659         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1660         the hardwired constant `7'.
1661         (store_memory): Ditto.
1662         (LOADDRMASK): Move definition to sim-main.h.
1663
1664         mips.igen (MTC0): Enable for r3900.
1665         (ADDU): Add trace.
1666
1667         mips.igen (do_load_byte): Delete.
1668         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1669         do_store_right): New functions.
1670         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1671
1672         configure.in: Let the tx39 use igen again.
1673         configure: Update.
1674
1675 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1676
1677         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1678         not an address sized quantity.  Return zero for cache sizes.
1679
1680 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1681
1682         * mips.igen (r3900): r3900 does not support 64 bit integer
1683         operations.
1684
1685 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1686
1687         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1688         than igen one.
1689         * configure : Rebuild.
1690
1691 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1692
1693         * configure: Regenerated to track ../common/aclocal.m4 changes.
1694
1695 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1696
1697         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1698
1699 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1700
1701         * configure: Regenerated to track ../common/aclocal.m4 changes.
1702         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1703
1704 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1705
1706         * configure: Regenerated to track ../common/aclocal.m4 changes.
1707
1708 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1709
1710         * interp.c (Max, Min): Comment out functions. Not yet used.
1711
1712 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1713
1714         * configure: Regenerated to track ../common/aclocal.m4 changes.
1715
1716 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1717
1718         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1719         configurable settings for stand-alone simulator.
1720
1721         * configure.in: Added X11 search, just in case.
1722
1723         * configure: Regenerated.
1724
1725 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1726
1727         * interp.c (sim_write, sim_read, load_memory, store_memory):
1728         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1729
1730 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1731
1732         * sim-main.h (GETFCC): Return an unsigned value.
1733
1734 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1735
1736         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1737         (DADD): Result destination is RD not RT.
1738
1739 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1740
1741         * sim-main.h (HIACCESS, LOACCESS): Always define.
1742
1743         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1744
1745         * interp.c (sim_info): Delete.
1746
1747 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1748
1749         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1750         (mips_option_handler): New argument `cpu'.
1751         (sim_open): Update call to sim_add_option_table.
1752
1753 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1754
1755         * mips.igen (CxC1): Add tracing.
1756
1757 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1758
1759         * sim-main.h (Max, Min): Declare.
1760
1761         * interp.c (Max, Min): New functions.
1762
1763         * mips.igen (BC1): Add tracing.
1764
1765 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1766
1767         * interp.c Added memory map for stack in vr4100
1768
1769 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1770
1771         * interp.c (load_memory): Add missing "break"'s.
1772
1773 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1774
1775         * interp.c (sim_store_register, sim_fetch_register): Pass in
1776         length parameter.  Return -1.
1777
1778 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1779
1780         * interp.c: Added hardware init hook, fixed warnings.
1781
1782 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1783
1784         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1785
1786 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1787
1788         * interp.c (ifetch16): New function.
1789
1790         * sim-main.h (IMEM32): Rename IMEM.
1791         (IMEM16_IMMED): Define.
1792         (IMEM16): Define.
1793         (DELAY_SLOT): Update.
1794
1795         * m16run.c (sim_engine_run): New file.
1796
1797         * m16.igen: All instructions except LB.
1798         (LB): Call do_load_byte.
1799         * mips.igen (do_load_byte): New function.
1800         (LB): Call do_load_byte.
1801
1802         * mips.igen: Move spec for insn bit size and high bit from here.
1803         * Makefile.in (tmp-igen, tmp-m16): To here.
1804
1805         * m16.dc: New file, decode mips16 instructions.
1806
1807         * Makefile.in (SIM_NO_ALL): Define.
1808         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1809
1810 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1811
1812         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1813         point unit to 32 bit registers.
1814         * configure: Re-generate.
1815
1816 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1817
1818         * configure.in (sim_use_gen): Make IGEN the default simulator
1819         generator for generic 32 and 64 bit mips targets.
1820         * configure: Re-generate.
1821
1822 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1823
1824         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1825         bitsize.
1826
1827         * interp.c (sim_fetch_register, sim_store_register): Read/write
1828         FGR from correct location.
1829         (sim_open): Set size of FGR's according to
1830         WITH_TARGET_FLOATING_POINT_BITSIZE.
1831
1832         * sim-main.h (FGR): Store floating point registers in a separate
1833         array.
1834
1835 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1836
1837         * configure: Regenerated to track ../common/aclocal.m4 changes.
1838
1839 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1840
1841         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1842
1843         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1844
1845         * interp.c (pending_tick): New function.  Deliver pending writes.
1846
1847         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1848         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1849         it can handle mixed sized quantites and single bits.
1850
1851 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1852
1853         * interp.c (oengine.h): Do not include when building with IGEN.
1854         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1855         (sim_info): Ditto for PROCESSOR_64BIT.
1856         (sim_monitor): Replace ut_reg with unsigned_word.
1857         (*): Ditto for t_reg.
1858         (LOADDRMASK): Define.
1859         (sim_open): Remove defunct check that host FP is IEEE compliant,
1860         using software to emulate floating point.
1861         (value_fpr, ...): Always compile, was conditional on HASFPU.
1862
1863 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1864
1865         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1866         size.
1867
1868         * interp.c (SD, CPU): Define.
1869         (mips_option_handler): Set flags in each CPU.
1870         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1871         (sim_close): Do not clear STATE, deleted anyway.
1872         (sim_write, sim_read): Assume CPU zero's vm should be used for
1873         data transfers.
1874         (sim_create_inferior): Set the PC for all processors.
1875         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1876         argument.
1877         (mips16_entry): Pass correct nr of args to store_word, load_word.
1878         (ColdReset): Cold reset all cpu's.
1879         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1880         (sim_monitor, load_memory, store_memory, signal_exception): Use
1881         `CPU' instead of STATE_CPU.
1882
1883
1884         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1885         SD or CPU_.
1886
1887         * sim-main.h (signal_exception): Add sim_cpu arg.
1888         (SignalException*): Pass both SD and CPU to signal_exception.
1889         * interp.c (signal_exception): Update.
1890
1891         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1892         Ditto
1893         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1894         address_translation): Ditto
1895         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1896
1897 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1898
1899         * configure: Regenerated to track ../common/aclocal.m4 changes.
1900
1901 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1902
1903         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1904
1905         * mips.igen (model): Map processor names onto BFD name.
1906
1907         * sim-main.h (CPU_CIA): Delete.
1908         (SET_CIA, GET_CIA): Define
1909
1910 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1911
1912         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1913         regiser.
1914
1915         * configure.in (default_endian): Configure a big-endian simulator
1916         by default.
1917         * configure: Re-generate.
1918
1919 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1920
1921         * configure: Regenerated to track ../common/aclocal.m4 changes.
1922
1923 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1924
1925         * interp.c (sim_monitor): Handle Densan monitor outbyte
1926         and inbyte functions.
1927
1928 1997-12-29  Felix Lee  <flee@cygnus.com>
1929
1930         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1931
1932 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1933
1934         * Makefile.in (tmp-igen): Arrange for $zero to always be
1935         reset to zero after every instruction.
1936
1937 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1938
1939         * configure: Regenerated to track ../common/aclocal.m4 changes.
1940         * config.in: Ditto.
1941
1942 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1943
1944         * mips.igen (MSUB): Fix to work like MADD.
1945         * gencode.c (MSUB): Similarly.
1946
1947 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1948
1949         * configure: Regenerated to track ../common/aclocal.m4 changes.
1950
1951 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1952
1953         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1954
1955 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1956
1957         * sim-main.h (sim-fpu.h): Include.
1958
1959         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1960         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1961         using host independant sim_fpu module.
1962
1963 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1964
1965         * interp.c (signal_exception): Report internal errors with SIGABRT
1966         not SIGQUIT.
1967
1968         * sim-main.h (C0_CONFIG): New register.
1969         (signal.h): No longer include.
1970
1971         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1972
1973 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
1974
1975         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1976
1977 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1978
1979         * mips.igen: Tag vr5000 instructions.
1980         (ANDI): Was missing mipsIV model, fix assembler syntax.
1981         (do_c_cond_fmt): New function.
1982         (C.cond.fmt): Handle mips I-III which do not support CC field
1983         separatly.
1984         (bc1): Handle mips IV which do not have a delaed FCC separatly.
1985         (SDR): Mask paddr when BigEndianMem, not the converse as specified
1986         in IV3.2 spec.
1987         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
1988         vr5000 which saves LO in a GPR separatly.
1989
1990         * configure.in (enable-sim-igen): For vr5000, select vr5000
1991         specific instructions.
1992         * configure: Re-generate.
1993
1994 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1995
1996         * Makefile.in (SIM_OBJS): Add sim-fpu module.
1997
1998         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1999         fmt_uninterpreted_64 bit cases to switch.  Convert to
2000         fmt_formatted,
2001
2002         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2003
2004         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2005         as specified in IV3.2 spec.
2006         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2007
2008 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2009
2010         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2011         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2012         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2013         PENDING_FILL versions of instructions.  Simplify.
2014         (X): New function.
2015         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2016         instructions.
2017         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2018         a signed value.
2019         (MTHI, MFHI): Disable code checking HI-LO.
2020
2021         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2022         global.
2023         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2024
2025 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2026
2027         * gencode.c (build_mips16_operands): Replace IPC with cia.
2028
2029         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2030         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2031         IPC to `cia'.
2032         (UndefinedResult): Replace function with macro/function
2033         combination.
2034         (sim_engine_run): Don't save PC in IPC.
2035
2036         * sim-main.h (IPC): Delete.
2037
2038
2039         * interp.c (signal_exception, store_word, load_word,
2040         address_translation, load_memory, store_memory, cache_op,
2041         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2042         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2043         current instruction address - cia - argument.
2044         (sim_read, sim_write): Call address_translation directly.
2045         (sim_engine_run): Rename variable vaddr to cia.
2046         (signal_exception): Pass cia to sim_monitor
2047
2048         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2049         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2050         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2051
2052         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2053         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2054         SIM_ASSERT.
2055
2056         * interp.c (signal_exception): Pass restart address to
2057         sim_engine_restart.
2058
2059         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2060         idecode.o): Add dependency.
2061
2062         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2063         Delete definitions
2064         (DELAY_SLOT): Update NIA not PC with branch address.
2065         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2066
2067         * mips.igen: Use CIA not PC in branch calculations.
2068         (illegal): Call SignalException.
2069         (BEQ, ADDIU): Fix assembler.
2070
2071 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2072
2073         * m16.igen (JALX): Was missing.
2074
2075         * configure.in (enable-sim-igen): New configuration option.
2076         * configure: Re-generate.
2077
2078         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2079
2080         * interp.c (load_memory, store_memory): Delete parameter RAW.
2081         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2082         bypassing {load,store}_memory.
2083
2084         * sim-main.h (ByteSwapMem): Delete definition.
2085
2086         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2087
2088         * interp.c (sim_do_command, sim_commands): Delete mips specific
2089         commands.  Handled by module sim-options.
2090
2091         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2092         (WITH_MODULO_MEMORY): Define.
2093
2094         * interp.c (sim_info): Delete code printing memory size.
2095
2096         * interp.c (mips_size): Nee sim_size, delete function.
2097         (power2): Delete.
2098         (monitor, monitor_base, monitor_size): Delete global variables.
2099         (sim_open, sim_close): Delete code creating monitor and other
2100         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2101         manage memory regions.
2102         (load_memory, store_memory): Use sim-core for memory model.
2103
2104         * interp.c (address_translation): Delete all memory map code
2105         except line forcing 32 bit addresses.
2106
2107 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2108
2109         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2110         trace options.
2111
2112         * interp.c (logfh, logfile): Delete globals.
2113         (sim_open, sim_close): Delete code opening & closing log file.
2114         (mips_option_handler): Delete -l and -n options.
2115         (OPTION mips_options): Ditto.
2116
2117         * interp.c (OPTION mips_options): Rename option trace to dinero.
2118         (mips_option_handler): Update.
2119
2120 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2121
2122         * interp.c (fetch_str): New function.
2123         (sim_monitor): Rewrite using sim_read & sim_write.
2124         (sim_open): Check magic number.
2125         (sim_open): Write monitor vectors into memory using sim_write.
2126         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2127         (sim_read, sim_write): Simplify - transfer data one byte at a
2128         time.
2129         (load_memory, store_memory): Clarify meaning of parameter RAW.
2130
2131         * sim-main.h (isHOST): Defete definition.
2132         (isTARGET): Mark as depreciated.
2133         (address_translation): Delete parameter HOST.
2134
2135         * interp.c (address_translation): Delete parameter HOST.
2136
2137 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2138
2139         * mips.igen:
2140
2141         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2142         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2143
2144 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2145
2146         * mips.igen: Add model filter field to records.
2147
2148 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2149
2150         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2151
2152         interp.c (sim_engine_run): Do not compile function sim_engine_run
2153         when WITH_IGEN == 1.
2154
2155         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2156         target architecture.
2157
2158         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2159         igen. Replace with configuration variables sim_igen_flags /
2160         sim_m16_flags.
2161
2162         * m16.igen: New file.  Copy mips16 insns here.
2163         * mips.igen: From here.
2164
2165 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2166
2167         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2168         to top.
2169         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2170
2171 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2172
2173         * gencode.c (build_instruction): Follow sim_write's lead in using
2174         BigEndianMem instead of !ByteSwapMem.
2175
2176 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2177
2178         * configure.in (sim_gen): Dependent on target, select type of
2179         generator.  Always select old style generator.
2180
2181         configure: Re-generate.
2182
2183         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2184         targets.
2185         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2186         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2187         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2188         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2189         SIM_@sim_gen@_*, set by autoconf.
2190
2191 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2192
2193         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2194
2195         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2196         CURRENT_FLOATING_POINT instead.
2197
2198         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2199         (address_translation): Raise exception InstructionFetch when
2200         translation fails and isINSTRUCTION.
2201
2202         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2203         sim_engine_run): Change type of of vaddr and paddr to
2204         address_word.
2205         (address_translation, prefetch, load_memory, store_memory,
2206         cache_op): Change type of vAddr and pAddr to address_word.
2207
2208         * gencode.c (build_instruction): Change type of vaddr and paddr to
2209         address_word.
2210
2211 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2212
2213         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2214         macro to obtain result of ALU op.
2215
2216 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2217
2218         * interp.c (sim_info): Call profile_print.
2219
2220 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2221
2222         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2223
2224         * sim-main.h (WITH_PROFILE): Do not define, defined in
2225         common/sim-config.h.  Use sim-profile module.
2226         (simPROFILE): Delete defintion.
2227
2228         * interp.c (PROFILE): Delete definition.
2229         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2230         (sim_close): Delete code writing profile histogram.
2231         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2232         Delete.
2233         (sim_engine_run): Delete code profiling the PC.
2234
2235 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2236
2237         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2238
2239         * interp.c (sim_monitor): Make register pointers of type
2240         unsigned_word*.
2241
2242         * sim-main.h: Make registers of type unsigned_word not
2243         signed_word.
2244
2245 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2246
2247         * interp.c (sync_operation): Rename from SyncOperation, make
2248         global, add SD argument.
2249         (prefetch): Rename from Prefetch, make global, add SD argument.
2250         (decode_coproc): Make global.
2251
2252         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2253
2254         * gencode.c (build_instruction): Generate DecodeCoproc not
2255         decode_coproc calls.
2256
2257         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2258         (SizeFGR): Move to sim-main.h
2259         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2260         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2261         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2262         sim-main.h.
2263         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2264         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2265         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2266         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2267         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2268         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2269
2270         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2271         exception.
2272         (sim-alu.h): Include.
2273         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2274         (sim_cia): Typedef to instruction_address.
2275
2276 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2277
2278         * Makefile.in (interp.o): Rename generated file engine.c to
2279         oengine.c.
2280
2281         * interp.c: Update.
2282
2283 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2284
2285         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2286
2287 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2288
2289         * gencode.c (build_instruction): For "FPSQRT", output correct
2290         number of arguments to Recip.
2291
2292 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2293
2294         * Makefile.in (interp.o): Depends on sim-main.h
2295
2296         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2297
2298         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2299         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2300         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2301         STATE, DSSTATE): Define
2302         (GPR, FGRIDX, ..): Define.
2303
2304         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2305         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2306         (GPR, FGRIDX, ...): Delete macros.
2307
2308         * interp.c: Update names to match defines from sim-main.h
2309
2310 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2311
2312         * interp.c (sim_monitor): Add SD argument.
2313         (sim_warning): Delete.  Replace calls with calls to
2314         sim_io_eprintf.
2315         (sim_error): Delete. Replace calls with sim_io_error.
2316         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2317         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2318         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2319         argument.
2320         (mips_size): Rename from sim_size. Add SD argument.
2321
2322         * interp.c (simulator): Delete global variable.
2323         (callback): Delete global variable.
2324         (mips_option_handler, sim_open, sim_write, sim_read,
2325         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2326         sim_size,sim_monitor): Use sim_io_* not callback->*.
2327         (sim_open): ZALLOC simulator struct.
2328         (PROFILE): Do not define.
2329
2330 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2331
2332         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2333         support.h with corresponding code.
2334
2335         * sim-main.h (word64, uword64), support.h: Move definition to
2336         sim-main.h.
2337         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2338
2339         * support.h: Delete
2340         * Makefile.in: Update dependencies
2341         * interp.c: Do not include.
2342
2343 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2344
2345         * interp.c (address_translation, load_memory, store_memory,
2346         cache_op): Rename to from AddressTranslation et.al., make global,
2347         add SD argument
2348
2349         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2350         CacheOp): Define.
2351
2352         * interp.c (SignalException): Rename to signal_exception, make
2353         global.
2354
2355         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2356
2357         * sim-main.h (SignalException, SignalExceptionInterrupt,
2358         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2359         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2360         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2361         Define.
2362
2363         * interp.c, support.h: Use.
2364
2365 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2366
2367         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2368         to value_fpr / store_fpr. Add SD argument.
2369         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2370         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2371
2372         * sim-main.h (ValueFPR, StoreFPR): Define.
2373
2374 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2375
2376         * interp.c (sim_engine_run): Check consistency between configure
2377         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2378         and HASFPU.
2379
2380         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2381         (mips_fpu): Configure WITH_FLOATING_POINT.
2382         (mips_endian): Configure WITH_TARGET_ENDIAN.
2383         * configure: Update.
2384
2385 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2386
2387         * configure: Regenerated to track ../common/aclocal.m4 changes.
2388
2389 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2390
2391         * configure: Regenerated.
2392
2393 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2394
2395         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2396
2397 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2398
2399         * gencode.c (print_igen_insn_models): Assume certain architectures
2400         include all mips* instructions.
2401         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2402         instruction.
2403
2404         * Makefile.in (tmp.igen): Add target. Generate igen input from
2405         gencode file.
2406
2407         * gencode.c (FEATURE_IGEN): Define.
2408         (main): Add --igen option.  Generate output in igen format.
2409         (process_instructions): Format output according to igen option.
2410         (print_igen_insn_format): New function.
2411         (print_igen_insn_models): New function.
2412         (process_instructions): Only issue warnings and ignore
2413         instructions when no FEATURE_IGEN.
2414
2415 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2416
2417         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2418         MIPS targets.
2419
2420 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2421
2422         * configure: Regenerated to track ../common/aclocal.m4 changes.
2423
2424 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2425
2426         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2427         SIM_RESERVED_BITS): Delete, moved to common.
2428         (SIM_EXTRA_CFLAGS): Update.
2429
2430 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2431
2432         * configure.in: Configure non-strict memory alignment.
2433         * configure: Regenerated to track ../common/aclocal.m4 changes.
2434
2435 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2436
2437         * configure: Regenerated to track ../common/aclocal.m4 changes.
2438
2439 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2440
2441         * gencode.c (SDBBP,DERET): Added (3900) insns.
2442         (RFE): Turn on for 3900.
2443         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2444         (dsstate): Made global.
2445         (SUBTARGET_R3900): Added.
2446         (CANCELDELAYSLOT): New.
2447         (SignalException): Ignore SystemCall rather than ignore and
2448         terminate.  Add DebugBreakPoint handling.
2449         (decode_coproc): New insns RFE, DERET; and new registers Debug
2450         and DEPC protected by SUBTARGET_R3900.
2451         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2452         bits explicitly.
2453         * Makefile.in,configure.in: Add mips subtarget option.
2454         * configure: Update.
2455
2456 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2457
2458         * gencode.c: Add r3900 (tx39).
2459
2460
2461 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2462
2463         * gencode.c (build_instruction): Don't need to subtract 4 for
2464         JALR, just 2.
2465
2466 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2467
2468         * interp.c: Correct some HASFPU problems.
2469
2470 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2471
2472         * configure: Regenerated to track ../common/aclocal.m4 changes.
2473
2474 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2475
2476         * interp.c (mips_options): Fix samples option short form, should
2477         be `x'.
2478
2479 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2480
2481         * interp.c (sim_info): Enable info code.  Was just returning.
2482
2483 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2484
2485         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2486         MFC0.
2487
2488 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2489
2490         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2491         constants.
2492         (build_instruction): Ditto for LL.
2493
2494 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2495
2496         * configure: Regenerated to track ../common/aclocal.m4 changes.
2497
2498 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2499
2500         * configure: Regenerated to track ../common/aclocal.m4 changes.
2501         * config.in: Ditto.
2502
2503 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2504
2505         * interp.c (sim_open): Add call to sim_analyze_program, update
2506         call to sim_config.
2507
2508 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2509
2510         * interp.c (sim_kill): Delete.
2511         (sim_create_inferior): Add ABFD argument. Set PC from same.
2512         (sim_load): Move code initializing trap handlers from here.
2513         (sim_open): To here.
2514         (sim_load): Delete, use sim-hload.c.
2515
2516         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2517
2518 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2519
2520         * configure: Regenerated to track ../common/aclocal.m4 changes.
2521         * config.in: Ditto.
2522
2523 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2524
2525         * interp.c (sim_open): Add ABFD argument.
2526         (sim_load): Move call to sim_config from here.
2527         (sim_open): To here.  Check return status.
2528
2529 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2530
2531         * gencode.c (build_instruction): Two arg MADD should
2532         not assign result to $0.
2533
2534 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2535
2536         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2537         * sim/mips/configure.in: Regenerate.
2538
2539 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2540
2541         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2542         signed8, unsigned8 et.al. types.
2543
2544         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2545         hosts when selecting subreg.
2546
2547 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2548
2549         * interp.c (sim_engine_run): Reset the ZERO register to zero
2550         regardless of FEATURE_WARN_ZERO.
2551         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2552
2553 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2554
2555         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2556         (SignalException): For BreakPoints ignore any mode bits and just
2557         save the PC.
2558         (SignalException): Always set the CAUSE register.
2559
2560 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2561
2562         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2563         exception has been taken.
2564
2565         * interp.c: Implement the ERET and mt/f sr instructions.
2566
2567 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2568
2569         * interp.c (SignalException): Don't bother restarting an
2570         interrupt.
2571
2572 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2573
2574         * interp.c (SignalException): Really take an interrupt.
2575         (interrupt_event): Only deliver interrupts when enabled.
2576
2577 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2578
2579         * interp.c (sim_info): Only print info when verbose.
2580         (sim_info) Use sim_io_printf for output.
2581
2582 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2583
2584         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2585         mips architectures.
2586
2587 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2588
2589         * interp.c (sim_do_command): Check for common commands if a
2590         simulator specific command fails.
2591
2592 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2593
2594         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2595         and simBE when DEBUG is defined.
2596
2597 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2598
2599         * interp.c (interrupt_event): New function.  Pass exception event
2600         onto exception handler.
2601
2602         * configure.in: Check for stdlib.h.
2603         * configure: Regenerate.
2604
2605         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2606         variable declaration.
2607         (build_instruction): Initialize memval1.
2608         (build_instruction): Add UNUSED attribute to byte, bigend,
2609         reverse.
2610         (build_operands): Ditto.
2611
2612         * interp.c: Fix GCC warnings.
2613         (sim_get_quit_code): Delete.
2614
2615         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2616         * Makefile.in: Ditto.
2617         * configure: Re-generate.
2618
2619         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2620
2621 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2622
2623         * interp.c (mips_option_handler): New function parse argumes using
2624         sim-options.
2625         (myname): Replace with STATE_MY_NAME.
2626         (sim_open): Delete check for host endianness - performed by
2627         sim_config.
2628         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2629         (sim_open): Move much of the initialization from here.
2630         (sim_load): To here.  After the image has been loaded and
2631         endianness set.
2632         (sim_open): Move ColdReset from here.
2633         (sim_create_inferior): To here.
2634         (sim_open): Make FP check less dependant on host endianness.
2635
2636         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2637         run.
2638         * interp.c (sim_set_callbacks): Delete.
2639
2640         * interp.c (membank, membank_base, membank_size): Replace with
2641         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2642         (sim_open): Remove call to callback->init. gdb/run do this.
2643
2644         * interp.c: Update
2645
2646         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2647
2648         * interp.c (big_endian_p): Delete, replaced by
2649         current_target_byte_order.
2650
2651 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2652
2653         * interp.c (host_read_long, host_read_word, host_swap_word,
2654         host_swap_long): Delete. Using common sim-endian.
2655         (sim_fetch_register, sim_store_register): Use H2T.
2656         (pipeline_ticks): Delete.  Handled by sim-events.
2657         (sim_info): Update.
2658         (sim_engine_run): Update.
2659
2660 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2661
2662         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2663         reason from here.
2664         (SignalException): To here. Signal using sim_engine_halt.
2665         (sim_stop_reason): Delete, moved to common.
2666
2667 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2668
2669         * interp.c (sim_open): Add callback argument.
2670         (sim_set_callbacks): Delete SIM_DESC argument.
2671         (sim_size): Ditto.
2672
2673 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2674
2675         * Makefile.in (SIM_OBJS): Add common modules.
2676
2677         * interp.c (sim_set_callbacks): Also set SD callback.
2678         (set_endianness, xfer_*, swap_*): Delete.
2679         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2680         Change to functions using sim-endian macros.
2681         (control_c, sim_stop): Delete, use common version.
2682         (simulate): Convert into.
2683         (sim_engine_run): This function.
2684         (sim_resume): Delete.
2685
2686         * interp.c (simulation): New variable - the simulator object.
2687         (sim_kind): Delete global - merged into simulation.
2688         (sim_load): Cleanup.  Move PC assignment from here.
2689         (sim_create_inferior): To here.
2690
2691         * sim-main.h: New file.
2692         * interp.c (sim-main.h): Include.
2693
2694 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2695
2696         * configure: Regenerated to track ../common/aclocal.m4 changes.
2697
2698 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2699
2700         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2701
2702 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2703
2704         * gencode.c (build_instruction): DIV instructions: check
2705         for division by zero and integer overflow before using
2706         host's division operation.
2707
2708 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2709
2710         * Makefile.in (SIM_OBJS): Add sim-load.o.
2711         * interp.c: #include bfd.h.
2712         (target_byte_order): Delete.
2713         (sim_kind, myname, big_endian_p): New static locals.
2714         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2715         after argument parsing.  Recognize -E arg, set endianness accordingly.
2716         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2717         load file into simulator.  Set PC from bfd.
2718         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2719         (set_endianness): Use big_endian_p instead of target_byte_order.
2720
2721 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2722
2723         * interp.c (sim_size): Delete prototype - conflicts with
2724         definition in remote-sim.h.  Correct definition.
2725
2726 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2727
2728         * configure: Regenerated to track ../common/aclocal.m4 changes.
2729         * config.in: Ditto.
2730
2731 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2732
2733         * interp.c (sim_open): New arg `kind'.
2734
2735         * configure: Regenerated to track ../common/aclocal.m4 changes.
2736
2737 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2738
2739         * configure: Regenerated to track ../common/aclocal.m4 changes.
2740
2741 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2742
2743         * interp.c (sim_open): Set optind to 0 before calling getopt.
2744
2745 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2746
2747         * configure: Regenerated to track ../common/aclocal.m4 changes.
2748
2749 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2750
2751         * interp.c : Replace uses of pr_addr with pr_uword64
2752         where the bit length is always 64 independent of SIM_ADDR.
2753         (pr_uword64) : added.
2754
2755 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2756
2757         * configure: Re-generate.
2758
2759 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2760
2761         * configure: Regenerate to track ../common/aclocal.m4 changes.
2762
2763 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2764
2765         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2766         in argv form.
2767         (other sim_*): New SIM_DESC argument.
2768
2769 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2770
2771         * interp.c: Fix printing of addresses for non-64-bit targets.
2772         (pr_addr): Add function to print address based on size.
2773
2774 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2775
2776         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2777
2778 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2779
2780         * gencode.c (build_mips16_operands): Correct computation of base
2781         address for extended PC relative instruction.
2782
2783 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2784
2785         * interp.c (mips16_entry): Add support for floating point cases.
2786         (SignalException): Pass floating point cases to mips16_entry.
2787         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2788         registers.
2789         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2790         or fmt_word.
2791         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2792         and then set the state to fmt_uninterpreted.
2793         (COP_SW): Temporarily set the state to fmt_word while calling
2794         ValueFPR.
2795
2796 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2797
2798         * gencode.c (build_instruction): The high order may be set in the
2799         comparison flags at any ISA level, not just ISA 4.
2800
2801 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2802
2803         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2804         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2805         * configure.in: sinclude ../common/aclocal.m4.
2806         * configure: Regenerated.
2807
2808 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2809
2810         * configure: Rebuild after change to aclocal.m4.
2811
2812 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2813
2814         * configure configure.in Makefile.in:  Update to new configure
2815         scheme which is more compatible with WinGDB builds.
2816         * configure.in:  Improve comment on how to run autoconf.
2817         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2818         * Makefile.in:  Use autoconf substitution to install common
2819         makefile fragment.
2820
2821 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2822
2823         * gencode.c (build_instruction): Use BigEndianCPU instead of
2824         ByteSwapMem.
2825
2826 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2827
2828         * interp.c (sim_monitor): Make output to stdout visible in
2829         wingdb's I/O log window.
2830
2831 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2832
2833         * support.h: Undo previous change to SIGTRAP
2834         and SIGQUIT values.
2835
2836 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2837
2838         * interp.c (store_word, load_word): New static functions.
2839         (mips16_entry): New static function.
2840         (SignalException): Look for mips16 entry and exit instructions.
2841         (simulate): Use the correct index when setting fpr_state after
2842         doing a pending move.
2843
2844 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2845
2846         * interp.c: Fix byte-swapping code throughout to work on
2847         both little- and big-endian hosts.
2848
2849 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2850
2851         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2852         with gdb/config/i386/xm-windows.h.
2853
2854 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2855
2856         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2857         that messes up arithmetic shifts.
2858
2859 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2860
2861         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2862         SIGTRAP and SIGQUIT for _WIN32.
2863
2864 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2865
2866         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2867         force a 64 bit multiplication.
2868         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2869         destination register is 0, since that is the default mips16 nop
2870         instruction.
2871
2872 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2873
2874         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2875         (build_endian_shift): Don't check proc64.
2876         (build_instruction): Always set memval to uword64.  Cast op2 to
2877         uword64 when shifting it left in memory instructions.  Always use
2878         the same code for stores--don't special case proc64.
2879
2880         * gencode.c (build_mips16_operands): Fix base PC value for PC
2881         relative operands.
2882         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2883         jal instruction.
2884         * interp.c (simJALDELAYSLOT): Define.
2885         (JALDELAYSLOT): Define.
2886         (INDELAYSLOT, INJALDELAYSLOT): Define.
2887         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2888
2889 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2890
2891         * interp.c (sim_open): add flush_cache as a PMON routine
2892         (sim_monitor): handle flush_cache by ignoring it
2893
2894 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2895
2896         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2897         BigEndianMem.
2898         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2899         (BigEndianMem): Rename to ByteSwapMem and change sense.
2900         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2901         BigEndianMem references to !ByteSwapMem.
2902         (set_endianness): New function, with prototype.
2903         (sim_open): Call set_endianness.
2904         (sim_info): Use simBE instead of BigEndianMem.
2905         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2906         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2907         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2908         ifdefs, keeping the prototype declaration.
2909         (swap_word): Rewrite correctly.
2910         (ColdReset): Delete references to CONFIG.  Delete endianness related
2911         code; moved to set_endianness.
2912
2913 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2914
2915         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2916         * interp.c (CHECKHILO): Define away.
2917         (simSIGINT): New macro.
2918         (membank_size): Increase from 1MB to 2MB.
2919         (control_c): New function.
2920         (sim_resume): Rename parameter signal to signal_number.  Add local
2921         variable prev.  Call signal before and after simulate.
2922         (sim_stop_reason): Add simSIGINT support.
2923         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2924         functions always.
2925         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2926         if logfh is NULL.
2927         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2928         a call to sim_warning.
2929
2930 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2931
2932         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2933         16 bit instructions.
2934
2935 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2936
2937         Add support for mips16 (16 bit MIPS implementation):
2938         * gencode.c (inst_type): Add mips16 instruction encoding types.
2939         (GETDATASIZEINSN): Define.
2940         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2941         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2942         mtlo.
2943         (MIPS16_DECODE): New table, for mips16 instructions.
2944         (bitmap_val): New static function.
2945         (struct mips16_op): Define.
2946         (mips16_op_table): New table, for mips16 operands.
2947         (build_mips16_operands): New static function.
2948         (process_instructions): If PC is odd, decode a mips16
2949         instruction.  Break out instruction handling into new
2950         build_instruction function.
2951         (build_instruction): New static function, broken out of
2952         process_instructions.  Check modifiers rather than flags for SHIFT
2953         bit count and m[ft]{hi,lo} direction.
2954         (usage): Pass program name to fprintf.
2955         (main): Remove unused variable this_option_optind.  Change
2956         ``*loptarg++'' to ``loptarg++''.
2957         (my_strtoul): Parenthesize && within ||.
2958         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2959         (simulate): If PC is odd, fetch a 16 bit instruction, and
2960         increment PC by 2 rather than 4.
2961         * configure.in: Add case for mips16*-*-*.
2962         * configure: Rebuild.
2963
2964 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2965
2966         * interp.c: Allow -t to enable tracing in standalone simulator.
2967         Fix garbage output in trace file and error messages.
2968
2969 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2970
2971         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2972         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2973         * configure.in: Simplify using macros in ../common/aclocal.m4.
2974         * configure: Regenerated.
2975         * tconfig.in: New file.
2976
2977 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
2978
2979         * interp.c: Fix bugs in 64-bit port.
2980         Use ansi function declarations for msvc compiler.
2981         Initialize and test file pointer in trace code.
2982         Prevent duplicate definition of LAST_EMED_REGNUM.
2983
2984 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
2985
2986         * interp.c (xfer_big_long): Prevent unwanted sign extension.
2987
2988 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
2989
2990         * interp.c (SignalException): Check for explicit terminating
2991         breakpoint value.
2992         * gencode.c: Pass instruction value through SignalException()
2993         calls for Trap, Breakpoint and Syscall.
2994
2995 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
2996
2997         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2998         only used on those hosts that provide it.
2999         * configure.in: Add sqrt() to list of functions to be checked for.
3000         * config.in: Re-generated.
3001         * configure: Re-generated.
3002
3003 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3004
3005         * gencode.c (process_instructions): Call build_endian_shift when
3006         expanding STORE RIGHT, to fix swr.
3007         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3008         clear the high bits.
3009         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3010         Fix float to int conversions to produce signed values.
3011
3012 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3013
3014         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3015         (process_instructions): Correct handling of nor instruction.
3016         Correct shift count for 32 bit shift instructions. Correct sign
3017         extension for arithmetic shifts to not shift the number of bits in
3018         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3019         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3020         Fix madd.
3021         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3022         It's OK to have a mult follow a mult.  What's not OK is to have a
3023         mult follow an mfhi.
3024         (Convert): Comment out incorrect rounding code.
3025
3026 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3027
3028         * interp.c (sim_monitor): Improved monitor printf
3029         simulation. Tidied up simulator warnings, and added "--log" option
3030         for directing warning message output.
3031         * gencode.c: Use sim_warning() rather than WARNING macro.
3032
3033 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3034
3035         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3036         getopt1.o, rather than on gencode.c.  Link objects together.
3037         Don't link against -liberty.
3038         (gencode.o, getopt.o, getopt1.o): New targets.
3039         * gencode.c: Include <ctype.h> and "ansidecl.h".
3040         (AND): Undefine after including "ansidecl.h".
3041         (ULONG_MAX): Define if not defined.
3042         (OP_*): Don't define macros; now defined in opcode/mips.h.
3043         (main): Call my_strtoul rather than strtoul.
3044         (my_strtoul): New static function.
3045
3046 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3047
3048         * gencode.c (process_instructions):  Generate word64 and uword64
3049         instead of `long long' and `unsigned long long' data types.
3050         * interp.c:  #include sysdep.h to get signals, and define default
3051         for SIGBUS.
3052         * (Convert):  Work around for Visual-C++ compiler bug with type
3053         conversion.
3054         * support.h:  Make things compile under Visual-C++ by using
3055         __int64 instead of `long long'.  Change many refs to long long
3056         into word64/uword64 typedefs.
3057
3058 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3059
3060         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3061         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3062         (docdir): Removed.
3063         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3064         (AC_PROG_INSTALL): Added.
3065         (AC_PROG_CC): Moved to before configure.host call.
3066         * configure: Rebuilt.
3067
3068 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3069
3070         * configure.in: Define @SIMCONF@ depending on mips target.
3071         * configure: Rebuild.
3072         * Makefile.in (run): Add @SIMCONF@ to control simulator
3073         construction.
3074         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3075         * interp.c: Remove some debugging, provide more detailed error
3076         messages, update memory accesses to use LOADDRMASK.
3077
3078 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3079
3080         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3081         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3082         stamp-h.
3083         * configure: Rebuild.
3084         * config.in: New file, generated by autoheader.
3085         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3086         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3087         HAVE_ANINT and HAVE_AINT, as appropriate.
3088         * Makefile.in (run): Use @LIBS@ rather than -lm.
3089         (interp.o): Depend upon config.h.
3090         (Makefile): Just rebuild Makefile.
3091         (clean): Remove stamp-h.
3092         (mostlyclean): Make the same as clean, not as distclean.
3093         (config.h, stamp-h): New targets.
3094
3095 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3096
3097         * interp.c (ColdReset): Fix boolean test. Make all simulator
3098         globals static.
3099
3100 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3101
3102         * interp.c (xfer_direct_word, xfer_direct_long,
3103         swap_direct_word, swap_direct_long, xfer_big_word,
3104         xfer_big_long, xfer_little_word, xfer_little_long,
3105         swap_word,swap_long): Added.
3106         * interp.c (ColdReset): Provide function indirection to
3107         host<->simulated_target transfer routines.
3108         * interp.c (sim_store_register, sim_fetch_register): Updated to
3109         make use of indirected transfer routines.
3110
3111 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3112
3113         * gencode.c (process_instructions): Ensure FP ABS instruction
3114         recognised.
3115         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3116         system call support.
3117
3118 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3119
3120         * interp.c (sim_do_command): Complain if callback structure not
3121         initialised.
3122
3123 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3124
3125         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3126         support for Sun hosts.
3127         * Makefile.in (gencode): Ensure the host compiler and libraries
3128         used for cross-hosted build.
3129
3130 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3131
3132         * interp.c, gencode.c: Some more (TODO) tidying.
3133
3134 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3135
3136         * gencode.c, interp.c: Replaced explicit long long references with
3137         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3138         * support.h (SET64LO, SET64HI): Macros added.
3139
3140 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3141
3142         * configure: Regenerate with autoconf 2.7.
3143
3144 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3145
3146         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3147         * support.h: Remove superfluous "1" from #if.
3148         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3149
3150 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3151
3152         * interp.c (StoreFPR): Control UndefinedResult() call on
3153         WARN_RESULT manifest.
3154
3155 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3156
3157         * gencode.c: Tidied instruction decoding, and added FP instruction
3158         support.
3159
3160         * interp.c: Added dineroIII, and BSD profiling support. Also
3161         run-time FP handling.
3162
3163 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3164
3165         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3166         gencode.c, interp.c, support.h: created.